Random error calibration method with microfield exposure

Abstract

Methods for characterizing stochastic effects in the prototyping process include: selecting at least one prototyping feature of the circuit design layout, where at least one prototyping feature is identified as having a tendency toward stochastic error; creating a stochastic calibration layout comprising multiple instances of at least one prototyping feature; collecting measurement data from a prototyping device with multiple instances of at least one prototyping feature, the prototyping device being created from the stochastic calibration layout; and characterizing the stochastic effects of the prototyping process using the prototyping device on at least one prototyping feature based on measurement data from multiple instances of at least one prototyping feature.

Description

STOCHASTIC ERROR CALIBRATION METHOD WITH MICRO FIELD EXPOSURESCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority of US application 63 / 546,311 which was filed on 30 October 2023, and which is incorporated herein in its entirety by reference.TECHNICAL FIELD

[0002] The present disclosure relates generally to lithography characterization, and a method for characterizing stochastic effects in a lithography process.BACKGROUND

[0003] A lithographic projection apparatus can be used, for example, in the manufacture of integrated circuits (ICs). A patterning device (e.g., a mask) may contain or provide a pattern corresponding to an individual layer of the IC (“design layout”), and this pattern can be transferred onto a target portion (e.g. comprising one or more dies) on a substrate (e.g., silicon wafer) that has been coated with a layer of radiation-sensitive material (“resist”), by methods such as irradiating the target portion through the pattern on the patterning device. In general, a single substrate includes a plurality of adjacent target portions to which the pattern is transferred successively by the lithographic projection apparatus, one target portion at a time.

[0004] Prior to transferring the pattern from the patterning device to the substrate, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures (“post-exposure procedures”), such as a post-exposure bake (PEB), development, a hard bake and measurement / inspection of the transferred pattern. This array of procedures is used as a basis to make an individual layer of a device, e.g., an IC. The substrate may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish the individual layer of the device. If several layers are required in the device, then the whole procedure, or a variant thereof, is repeated for each layer. Eventually, a device will be present in each target portion on the substrate. These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc.

[0005] Thus, manufacturing devices, such as semiconductor devices, typically involves processing a substrate (e.g., a semiconductor wafer) using a number of fabrication processes to form various features and multiple layers of the devices. Such layers and features are typically manufactured and processed using, e.g., deposition, lithography, etch, chemical-mechanical polishing, and ion implantation. Multiple devices may be fabricated on a plurality of dies on a substrate and then separated into individual devices. This device manufacturing process may be considered a patterning process. A patterning process involves a patterning step, such as optical and / or nanoimprint lithography using apatterning device in a lithographic apparatus, to transfer a pattern on the patterning device to a substrate and typically, but optionally, involves one or more related pattern processing steps, such as resist development by a development apparatus, baking of the substrate using a bake tool, etching using the pattern using an etch apparatus, etc.

[0006] As noted, lithography is a central step in the manufacturing of devices such as ICs, where patterns formed on substrates define functional elements of the devices, such as microprocessors, memory chips, etc. Similar lithographic techniques are also used in the formation of flat panel displays, micro-electromechanical systems (MEMS) and other devices.

[0007] As semiconductor manufacturing processes continue to advance, the dimensions of functional elements have continually been reduced while the number of functional elements, such as transistors, per device has been steadily increasing over decades, following a trend commonly referred to as “Moore’s law”. At the current state of technology, layers of devices are manufactured using lithographic projection apparatuses that project a design layout onto a substrate using illumination from a deepultraviolet illumination source, creating individual functional elements having dimensions well below 100 nm, i.e., less than half the wavelength of the radiation from the illumination source (e.g., a 193 nm illumination source).

[0008] This process in which features with dimensions smaller than the classical resolution limit of a lithographic projection apparatus are printed, is commonly known as low-ki lithography, according to the resolution formula CD = kjxk / NA, where I is the wavelength of radiation employed (currently in most cases 248nm or 193nm), NA is the numerical aperture of projection optics in the lithographic projection apparatus, CD is the “critical dimension’ -generally the smallest feature size printed-and ki is an empirical resolution factor. In general, the smaller ki the more difficult it becomes to reproduce a pattern on the substrate that resembles the shape and dimensions planned by a designer in order to achieve particular electrical functionality and performance. To overcome these difficulties, sophisticated fine-tuning steps are applied to the lithographic projection apparatus, the design layout, or the patterning device. These include, for example, but not limited to, optimization of NA and optical coherence settings, customized illumination schemes, use of phase shifting patterning devices, modeling and optimizing to account for stochastic effects, optical proximity correction (OPC, sometimes also referred to as “optical and process correction”) in the design layout, or other methods generally defined as “resolution enhancement techniques” (RET). In order to account for stochastic effects an adequate number of repeating instance of a design may be characterized (e.g., measured) and design stochasticity determined. For random logic design or peripheral memory design or relatively low-repeat patterns or features, there may not be enough instances to collect metrology data, especially stochastic effect data, to ensure calibration and validation accuracy — such as calibration of a model, validation of a model, validation of a process, etc.SUMMARY

[0009] Embodiments of the present disclosure provide a method for generating a layout containing multiple instances of one or more pattern features selected for stochastic effect characterization. Embodiments provide methods for selecting one or more pattern features based on a stochastic model, generating a layout based on the one or more selected pattern features, fabricating a calibration wafer based on the layout, obtaining metrology data from the calibration wafer, and characterizing stochastic effects of the patterning process based on the obtained metrology data. Embodiments provide methods for stochastic model adjustment.

[0010] According to an embodiment, there is provided a method for characterizing stochastic effects in a patterning process comprising: selecting at least one pattern feature of a circuitry design layout, wherein the at least one pattern feature is identified as prone to stochastic error; generating a stochastic calibration layout comprising multiple instances of the at least one pattern feature; obtaining metrology data from a wafer that has been patterned with multiple instances of the at least one pattern feature, the wafer having been patterned by a patterning device generated from the stochastic calibration layout; and characterizing stochastic effects of a patterning process utilizing the patterning device on the at least one pattern feature based upon the metrology data from the multiple instances of the at least one pattern feature.

[0011] In an embodiment, the circuitry design layout comprises a random logic circuitry design layout and wherein the at least one pattern features comprises at least one random logic feature.

[0012] In an embodiment, the at least one pattern feature identified as prone to stochastic error comprises at least one pattern featured determined to have a stochastic error by a stochastic model.

[0013] In an embodiment, further comprising calibrating the stochastic model based on the characterized stochastic effects.

[0014] In an embodiment, calibrating the stochastic model comprises adjusting the stochastic model based on an average, median, mean, standard deviation, one or more higher order stochastic moments, one or more distributions, or combination thereof of the obtained metrology data.

[0015] In an embodiment, the at least one pattern feature identified as prone to stochastic error comprises at least one pattern feature determined to have stochastic error based on failure analysis, feature size, similarity to previously fabricated features, or a combination thereof.

[0016] In an embodiment, further comprising adjusting the circuitry design layout or the patterning process based on the characterized stochastic effects.

[0017] In an embodiment, further comprising determining stochastic effects of the patterning process on the circuitry design layout based on the stochastic effects of the patterning process on the at least one pattern feature.

[0018] In an embodiment, determining stochastic effects of the patterning process on the circuitry design layout comprises generalizing the stochastic effects of the patterning process on the at least one pattern feature to additional features of the circuitry design layout.

[0019] In an embodiment, the wafer that has been patterned comprises a wafer patterned by a plurality of exposures by micro field exposure to contain multiple areas each containing the multiple instances of the at least one pattern feature and wherein generating the stochastic calibration layout further comprises configuring one or more recipes to pattern the wafer by the plurality of exposures.

[0020] In an embodiment, an area of the micro field exposure is on the order of 10 pm by 10 pm.

[0021] In an embodiment, the patterning device comprises a patterning device to pattern a wafer by a plurality of exposures to contain multiple areas each containing the multiple instances of the at least one pattern feature.

[0022] In an embodiment, generating the layout for the patterning device further comprises generating one or more recipes for a patterning apparatus to undertake the patterning process using the patterning device.

[0023] In an embodiment, the one or more recipes vary in at least one of dose, focus, or a combination thereof.

[0024] In an embodiment, the wafer that has been patterned with the multiple instances of the at least one pattern feature comprises a focus exposure matrix (FEM) wafer, various regions of the FEM wafer containing the multiple instances of the at least one pattern feature.

[0025] In an embodiment, obtaining metrology data comprises: obtaining scanning electron microscopy (SEM) images of the multiple instances of the at least one pattern feature; measuring at least one of a first dimension and placement of the multiple instances of the at least one pattern feature; determining a distribution of the measured at least one of a first dimension and placement of the multiple instances of the at least on pattern feature, and wherein determining stochasticity of the multiple instances of the at least one pattern feature in the obtained SEM images comprises characterizing the stochasticity of the distribution.

[0026] In an embodiment, the obtained metrology data comprises at least one of critical dimension (CD), overlay, edge placement error (EPE), failure number, failure rate, feature area, or a combination thereof.

[0027] In an embodiment, selecting the at least one pattern feature comprises: obtaining predicted stochastic errors for multiple features of the circuitry design layout; ranking each of the multiple features based on their corresponding predicted stochastic errors; and selecting as the at least one pattern feature one or more of the multiple features based on the ranking.

[0028] In an embodiment,, further comprising selecting an additional one or more of the multiple features as the at least one pattern features based on the ranking.

[0029] In an embodiment, the patterning process is a lithography process, resist process, etch process, or combination thereof.

[0030] In an embodiment, the stochastic model is a model of stochastic error.

[0031] In an embodiment, obtaining metrology data comprises obtaining metrology data for on the order of 300,000 instances of the at least one pattern feature.

[0032] In an embodiment, characterizing stochastic effect comprises characterizing stochastic effects to one the order of a part per billion failure rate for the at least one pattern feature, the at least one pattern feature comprising a non-repeating pattern feature.

[0033] In an embodiment, the circuitry design layout comprises random logic patterns.

[0034] According to another embodiment, one or more non-transitory, machine-readable medium having instruction thereon is provided, the instructions when executed by a processor being configured to perform the method of any other embodiment.

[0035] According to an embodiment, a system is provided comprising: a scanner configured to perform a patterning process for a circuitry design layout; at least one scanner recipe for the patterning process for the circuitry design layout; a processor; and one or more non-transitory, machine -readable medium having instruction thereon, the instructions when executed by a processor being configured to: select at least one pattern feature with a stochastic error from the circuitry design layout; generate a stochastic calibration layout and at least one calibration scanner recipe to pattern a wafer to containing multiple instances of the at least one pattern feature; and operate the scanner based on the at least one calibration scanner recipe and the stochastic calibration layout to generate a patterned wafer containing multiple instances of the at least one pattern feature.

[0036] In an embodiment, the at least one calibration scanner recipe comprises multiple scanner recipes which vary in at least one of dose and focus and wherein the patterned wafer comprises a focus exposure matrix (FEM) wafer, various regions of the FEM wafer containing the multiple instances of the at least one pattern feature.

[0037] In an embodiment, further comprising a scanning electron microscope (SEM) configured to obtain SEM images of the multiple instances of the at least one pattern feature, the processor being further configured to: determine stochastics effects of the at least one calibration scanner recipe on the at least one pattern feature from the SEM images of the multiple instances of the at least one pattern feature, wherein the at least one calibration scanner recipe is generated based on the at least one scanner recipe for the patterning process.

[0038] In an embodiment, the circuitry design layout is a random logic design layout and wherein the at least one pattern feature comprises a non-repeating pattern feature.BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate one or more embodiments and, together with the description, explain these embodiments. Embodiments of the invention will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbols indicate corresponding parts, and in which:

[0040] Figure 1 illustrates a block diagram of various subsystems of a lithographic projection apparatus, according to an embodiment.

[0041] Figure 2 illustrates an exemplary flow chart for simulating lithography in a lithographic projection apparatus, according to an embodiment.

[0042] Figure 3 depicts a schematic representation of holistic lithography, representing a cooperation between three technologies to optimize semiconductor manufacturing, according to an embodiment.

[0043] Figure 4 depicts a schematic representation of pattern selection for stochastic error characterization, according to an embodiment.

[0044] Figure 5 depicts a schematic representation of generation of a wafer containing multiple instances of selected pattern features, according to an embodiment.

[0045] Figures 6A-6B depict graphs relating stochastic effects for full field and micro field exposures, according to an embodiment.

[0046] Figure 7 is a flowchart illustrating a method for characterization of stochastic effects in a patterning process, according to an embodiment.

[0047] Figure 8 is a block diagram of an example computer system, according to an embodiment of the present disclosure.DETAILED DESCRIPTION

[0048] Embodiments of the present disclosure are described in detail with reference to the drawings, which are provided as illustrative examples of the disclosure so as to enable those skilled in the art to practice the disclosure. Notably, the figures and examples below are not meant to limit the scope of the present disclosure to a single embodiment, but other embodiments are possible by way of interchange of some or all of the described or illustrated elements. Moreover, where certain elements of the present disclosure can be partially or fully implemented using known components, only those portions of such known components that are necessary for an understanding of the present disclosure will be described, and detailed descriptions of other portions of such known components will be omitted so as not to obscure the disclosure. Embodiments described as being implemented in software should not be limited thereto, but can include embodiments implemented in hardware, or combinations of software and hardware, and vice-versa, as will be apparent to those skilled in the art, unless otherwise specified herein. In the present specification, an embodiment showing a singular component should not be considered limiting; rather, the disclosure is intended to encompass other embodiments including a plurality of the same component, and vice-versa, unless explicitly stated otherwise herein. Moreover, applicants do not intend for any term in the specification or claims to be ascribed an uncommon or special meaning unless explicitly set forth as such. Further, the present disclosure encompasses present and future known equivalents to the known components referred to herein by way of illustration.

[0049] Although specific reference may be made in this text to the manufacture of ICs, it should be explicitly understood that the description herein has many other possible applications. For example, it may be employed in the manufacture of integrated optical systems, guidance and detection patterns for magnetic domain memories, liquid-crystal display panels, thin-film magnetic heads, etc. The skilledartisan will appreciate that, in the context of such alternative applications, any use of the terms “wafer” or “die” in this text should be considered as interchangeable with the more general terms “substrate” and “target portion”, respectively.

[0050] A patterning device can comprise, or can form, one or more design layouts. The design layout can be generated utilizing CAD (computer-aided design) programs. This process is often referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional design layouts / patterning devices. These rules are set based processing and design limitations. For example, design rules define the space tolerance between devices (such as gates, capacitors, etc.) or interconnect lines, to ensure that the devices or lines do not interact with one another in an undesirable way. One or more of the design rule limitations may be referred to as a “critical dimension” (CD). A critical dimension of a device can be defined as the smallest width of a line or hole, or the smallest space between two lines or two holes. Thus, the CD regulates the overall size and density of the designed device. One of the goals in device fabrication is to faithfully reproduce the original design intent on the substrate (via the patterning device).

[0051] The term “mask”, “mask pattern,” or “patterning device” as employed in this text may be broadly interpreted as referring to a generic patterning device or pattern for use on or with a generic patterning device that can be used to endow an incoming radiation beam with a patterned cross-section, corresponding to a pattern that is to be created in a target portion of the substrate. Besides the classic mask (transmissive or reflective; binary, phase-shifting, hybrid, etc.), examples of other such patterning devices include a programmable mirror array. An example of such a device is a matrix-addressable surface having a viscoelastic control layer and a reflective surface. The basic principle behind such an apparatus is that (for example) addressed areas of the reflective surface reflect incident radiation as diffracted radiation, whereas unaddressed areas reflect incident radiation as undiffracted radiation. Using an appropriate filter, the said undiffracted radiation can be filtered out of the reflected beam, leaving only the diffracted radiation behind; in this manner, the beam becomes patterned according to the addressing pattern of the matrix-addressable surface. The required matrix addressing can be performed using suitable electronic means. Examples of other such patterning devices also include a programmable LCD array. An example of such a construction is given in U.S. Patent No. 5,229,872, which is incorporated herein by reference.

[0052] Figure 1 illustrates a block diagram of various subsystems of a lithographic projection apparatus 10A, according to an embodiment of the present disclosure. Major components are a radiation source 12A, which may be a deep-ultraviolet excimer laser source or other type of source including an extreme ultra violet (EUV) source (the lithographic projection apparatus itself need not have the radiation source), illumination optics which, e.g., define the partial coherence (denoted as sigma) and which may include optics 14A, 16Aa and 16Ab that shape radiation from the source 12A; a patterning device (or mask) 18 A; and transmission optics 16Ac that project an image of the patterning device pattern onto a substrate plane 22A.

[0053] A pupil 20A can be included with transmission optics 16Ac. In some embodiments, there can be one or more pupils before and / or after mask 18 A. As described in further detail herein, pupil 20A can provide patterning of the light that ultimately reaches substrate plane 22A. An adjustable filter or aperture at the pupil plane of the projection optics may restrict the range of beam angles that impinge on the substrate plane 22A, where the largest possible angle defines the numerical aperture of the projection optics NA= n sin(0max), wherein n is the refractive index of the media between the substrate and the last element of the projection optics, and 0maxis the largest angle of the beam exiting from the projection optics that can still impinge on the substrate plane 22A.

[0054] In a lithographic projection apparatus, a source provides illumination (i.e., radiation) to a patterning device and projection optics direct and shape the illumination, via the patterning device, onto a substrate. This is not to disclaim that the source does not itself provide patterning, directing, or shaping to the radiation or that patterning, directing, or shaping does not occur between the source and the projection optics. The projection optics may include at least some of the components 14A, 16Aa, 16Ab and 16Ac. An aerial image (Al) is the radiation intensity distribution at substrate level. A resist model can be used to calculate the resist image from the aerial image, an example of which can be found in U.S. Patent Application Publication No. US 2009-0157630, the disclosure of which is hereby incorporated by reference in its entirety. The resist model is related to properties of the resist layer (e.g., effects of chemical processes which occur during exposure, post-exposure bake (PEB) and development). Optical properties of the lithographic projection apparatus (e.g., properties of the illumination, the patterning device and the projection optics) dictate the aerial image and can be defined in an optical model. Since the patterning device used in the lithographic projection apparatus can be changed, it is desirable to separate the optical properties of the patterning device from the optical properties of the rest of the lithographic projection apparatus including at least the source and the projection optics. Details of techniques and models used to transform a design layout into various lithographic images (e.g., an aerial image, a resist image, etc.), apply OPC using those techniques and models and evaluate performance (e.g., in terms of process window) are described in U.S. Patent Application Publication Nos. US 2008-0301620, 2007-0050749, 2007-0031745, 2008-0309897, 2010- 0162197, and 2010-0180251, the disclosure of each which is hereby incorporated by reference in its entirety.

[0055] Figure 2 illustrates an exemplary flow chart for simulating lithography in a lithographic projection apparatus, according to an embodiment of the present disclosure. Source model 31 represents optical characteristics (including radiation intensity distribution and / or phase distribution) of the source. Projection optics model 32 represents optical characteristics (including changes to the radiation intensity distribution and / or the phase distribution caused by the projection optics) of the projection optics. Design layout model 35 represents optical characteristics of a design layout (including changes to the radiation intensity distribution and / or the phase distribution caused by design layout 33), which is the representation of an arrangement of features on or formed by a patterning device. Aerial image36 can be simulated from design layout model 35, projection optics model 32, and design layout model 35. Resist image 38 can be simulated from aerial image 36 using resist model 37. Simulation of lithography can, for example, predict contours and CDs in the resist image.

[0056] More specifically, source model 31 can represent the optical characteristics of the source that include, but are not limited to, numerical aperture settings, illumination sigma (o) settings as well as any particular illumination shape (e.g., off-axis radiation sources such as annular, quadrupole, dipole, etc.). Projection optics model 32 can represent the optical characteristics of the projection optics, including aberration, distortion, one or more refractive indexes, one or more physical sizes, one or more physical dimensions, etc. Design layout model 35 can represent one or more physical properties of a physical patterning device, as described, for example, in U.S. Patent No. 7,587,704, which is incorporated by reference in its entirety. The objective of the simulation is to accurately predict, for example, edge placement, aerial image intensity slope and / or CD, which can then be compared against an intended design. The intended design is generally defined as a pre-OPC design layout which can be provided in a standardized digital file format such as GDSII or OASIS or another file format.

[0057] From this design layout, one or more portions may be identified, which are referred to as “clips”. In an embodiment, a set of clips is extracted, which represents the complicated patterns in the design layout (typically about 50 to 1000 clips, although any number of clips may be used). These patterns or clips represent small portions (i.e., circuits, cells or patterns) of the design and more specifically, the clips typically represent small portions for which particular attention and / or verification is needed. In other words, clips may be the portions of the design layout, or may be similar or have a similar behavior of portions of the design layout, where one or more critical features are identified either by experience (including clips provided by a customer), by trial and error, or by running a full-chip simulation. Clips may contain one or more test patterns or gauge patterns.

[0058] An initial larger set of clips may be provided a priori by a customer based on one or more known critical feature areas in a design layout which require particular image optimization. Alternatively, in another embodiment, an initial larger set of clips may be extracted from the entire design layout by using some kind of automated (such as machine vision) or manual algorithm that identifies the one or more critical feature areas.

[0059] In a lithographic projection apparatus, as an example, a cost function may be expressed as Equation 1, below:where (z1;z2, ••• , zN) are N design variables or values thereof. fp(z1, z2, --- , zN) can be a function of the design variables (z1;z2, • • • , zw) such as a difference between an actual value and an intended valueof a characteristic for a set of values of the design variables of (z1;z2, --- , zN). wpis a weight constant associated with fp(z-[, z2, -" zN). For example, the characteristic may be a position of an edge of a pattern, measured at a given point on the edge. Different fp(z1;z2, • • • , zw) may have different weight wp. For example, if a particular edge has a narrow range of permitted positions, the weight wpfor the fp(z^, z2, ••• , zN) representing the difference between the actual position and the intended position of the edge may be given a higher value. fp(z1, z2, --- , zN') can also be a function of an interlayer characteristic, which is in turn a function of the design variables (z1;z2, ■■■ , zN') . Of course, CF(z1, z2, ••• , zw) is not limited to the form in Eq. 1. CF(z1, z2, --- , zw) can be in any other suitable form.

[0060] The cost function may represent any one or more suitable characteristics of the lithographic projection apparatus, lithographic process or the substrate, for instance, focus, CD, image shift, pattern placement error, image distortion, image rotation, stochastic variation, throughput, local CD variation, process window, an interlayer characteristic, or a combination thereof. In one embodiment, the design variables (z1;z2, • • • , zN) comprise one or more selected from dose, global bias of the patterning device, and / or shape of illumination. Since it is the resist image that often dictates the pattern on a substrate, the cost function may include a function that represents one or more characteristics of the resist image. For example, fpz1, z2, --- , zN) can be simply a distance between a point in the resist image to an intended position of that point (i.e., edge placement error EPEp(z1, z2, ••• , zw). The design variables can include any adjustable parameter such as an adjustable parameter of the source, the patterning device, the projection optics, dose, focus, etc.

[0061] The lithographic apparatus may include components collectively called a “wavefront manipulator” that can be used to adjust the shape of a wavefront and intensity distribution and / or phase shift of a radiation beam. In an embodiment, the lithographic apparatus can adjust a wavefront and intensity distribution at any location along an optical path of the lithographic projection apparatus, such as before the patterning device, near a pupil plane, near an image plane, and / or near a focal plane. The wavefront manipulator can be used to correct or compensate for certain distortions of the wavefront and intensity distribution and / or phase shift caused by, for example, the source, the patterning device, temperature variation in the lithographic projection apparatus, thermal expansion of components of the lithographic projection apparatus, etc. Adjusting the wavefront and intensity distribution and / or phase shift can change values of the characteristics represented by the cost function. Such changes can be simulated from a model or actually measured. The design variables can include parameters of the wavefront manipulator.

[0062] The design variables may have constraints, which can be expressed as (z1;z2, ■■■ , zN') G Z, where Z is a set of possible values of the design variables. One possible constraint on the design variables may be imposed by a desired throughput of the lithographic projection apparatus. Without such a constraint imposed by the desired throughput, the optimization may yield a set of values of thedesign variables that are unrealistic. For example, if the dose is a design variable, without such a constraint, the optimization may yield a dose value that makes the throughput economically impossible. However, the usefulness of constraints should not be interpreted as a necessity. For example, the throughput may be affected by the pupil fill ratio. For some illumination designs, a low pupil fill ratio may discard radiation, leading to lower throughput. Throughput may also be affected by the resist chemistry. Slower resist (e.g., a resist that requires higher amount of radiation to be properly exposed) leads to lower throughput.

[0063] As used herein, the term “process model” means a model that includes one or more models that simulate a patterning process. For example, a process model can include any combination of: an optical model (e.g., that models a lens system / proj ection system used to deliver light in a lithography process and may include modelling the final optical image of light that goes onto a photoresist), a resist model (e.g., that models physical effects of the resist, such as chemical effects due to the light), an optical proximity correction (OPC) model (e.g., that can be used to make masks or reticles and may include sub-resolution resist features (SRAFs), etc.).

[0064] As used herein, the term “concurrently” means that two or more things are occurring at approximately, but not necessarily exactly, at the same time. For example, varying a pupil design concurrently with a mask pattern can mean making a small modification to a pupil design, then making a small adjustment to a mask pattern, and then another modification to the pupil design, and so on. However, the present disclosure contemplates that in some parallel processing applications, concurrency can refer to operations occurring at the same time, or having some overlapping in time.

[0065] The present disclosure provides apparatuses, methods and computer program products which, among other things, relate to modifying or optimizing features of a lithography apparatus (e.g., scanner) in order to increase performance and manufacturing efficiency. The features that can be modified can include an optical spectrum of light used in the lithography process, a mask, a pupil, etc. Any combination of these features (and possibly others) can be implemented in order to improve, for example, a depth of focus, a process window, a contrast, or the like, of a lithography apparatus. In some embodiments, modification of one feature affects the other features. In this way, to achieve the desired improvements, multiple features can be concurrently modified / varied, as described below.

[0066] Figure 3 depicts a schematic representation of holistic lithography, representing a cooperation between three technologies to optimize semiconductor manufacturing. Typically, the patterning process in a lithographic apparatus LA is one of the most critical steps in the processing which requires high accuracy of dimensioning and placement of structures on the substrate W (Figure 1). To ensure this high accuracy, three systems (in this example) may be combined in a so called “holistic” control environment as schematically depicted in Figure 3. One of these systems is the lithographic apparatus LA which is (virtually) connected to a metrology apparatus (e.g., a metrology tool) MT (a second system), and to a computer system CL (a third system). A “holistic” environment may be configured to optimize the cooperation between these three systems to enhance the overall process window andprovide tight control loops to ensure that the patterning performed by the lithographic apparatus LA stays within a process window. The process window defines a range of process parameters (e.g., dose, focus, overlay) within which a specific manufacturing process yields a defined result (e.g., a functional semiconductor device) - typically within which the process parameters in the lithographic process or patterning process are allowed to vary.

[0067] The computer system CL may use (part of) the design layout to be patterned to predict which resolution enhancement techniques to use and to perform computational lithography simulations and calculations to determine which mask layout and lithographic apparatus settings achieve the largest overall process window of the patterning process (depicted in Figure 2 by the double arrow in the first scale SCI). Typically, the resolution enhancement techniques are arranged to match the patterning possibilities of the lithographic apparatus LA. The computer system CL may also be used to detect where within the process window the lithographic apparatus LA is currently operating (e.g., using input from the metrology tool MT) to predict whether defects may be present due to, for example, sub-optimal processing (depicted in Figure 2 by the arrow pointing “0” in the second scale SC2).

[0068] The metrology apparatus (tool) MT may provide input to the computer system CL to enable accurate simulations and predictions, and may provide feedback to the lithographic apparatus LA to identify possible drifts, e.g., in a calibration status of the lithographic apparatus LA (depicted in Figure 3 by the multiple arrows in the third scale SC3).

[0069] In lithographic processes, it is desirable to make frequent measurements of the structures created, e.g., for process control and verification. Different types of metrology tools MT for making such measurements are known, including scanning electron microscopes or various forms of optical metrology tool, image based or scatterometery-based metrology tools. Image analysis on images obtained from optical metrology tools and scanning electron microscopes can be used to measure various dimensions (e.g., CD, overlay, edge placement error (EPE) etc.) and detect defects for the structures.

[0070] Figure 4 depicts an exemplary schematic representation of pattern selection for stochastic error characterization, according to an embodiment. According to an embodiment of the present disclosure, one or more pattern features may be selected from a design layout, including based on a predicted stochastic error, and used to generate a stochastic calibration layout. The calibration layout may contain multiple instances of the one or more pattern features and may be used to pattern a calibration wafer which may yield metrology results able to characterize the stochastic effects on the one or more pattern features at up to a part per billion level. Stochastic effects, such as variable photon shot noise, may cause random variations in lithography processes, which may be especially evident in EUV and other high photon energy regimes where total number of photons may be low. Stochastic effects may be difficult to eliminate — such as due to their random nature, quantum effects, etc. — but may have quantifiable and qualifiable effects on patterning processes. Stochastic effects may be modeled by one or more model, such as a post lithography stochastic model, a post etch stochastic model, a failuremodel, etc. Models which include stochastic effects may be based on physical principles (or experimental results, etc.), but may operate more accurately when calibrated or validated against a specific process. Calibration of a model may include adjustment of one or more parameter of the model, such as fitting of stochastic noise distribution used in the model to a measured stochastic distribution for the process. Validation of a model may include determination of whether or not the model represents (e.g., accurately predicts) effects for a process. Herein, it should be understood that embodiments described in reference to “calibration” may instead be performed in reference to “validation”. For example, a model may be calibrated based on measured stochastic effects and it may then be determined if the calibrated model accurately represents the measured stochastic effects (e.g., the model may be validated) or vice versa. Accurate characterization (e.g., measurement and modeling) of stochastic effects (e.g., stochastic variations in edge placement, edge placement error, stochastic edge placement error, missing features (e.g., line breaks, missing contacts), merged features (e.g., kissing contacts), etc.), even without reduction of such stochastic effects, may allow for design layouts and patterning recipes to be designed (or redesigned) to minimize overall impact of stochastic effects on chip quality. Stochastic effects may be particularly difficult to measure for non-repeating patterns, such as isolated patterns, random logic designs, etc., which may not have enough identical instances of a given pattern features in a field of view (FOV) of a metrology tool (such as a scanning electron microscope (SEM)) to accurately determine a standard deviation (or other higher order (e.g., greater than second degree) moments), average, distribution, etc. for the probability of a stochastic effect causing a given error in fabrication. Stochastic effects for non-repeating patterns may be characterized (e.g., statistically) by using the same methods used to characterize stochastic effects for repeating patterns. Stochastic effects for non-repeating patterns may be harder to model than stochastic effects for repeating patterns, because the characterization of stochastic effects has greater error for patterns with fewer (or less than a threshold of) instances. Likewise, stochastic effect models for non-repeating patterns may need to be calibrated by using measured stochastic effects, which may be harder to obtain or less accurate as previously explained. For example, 300,000 repeats of a feature may be required (e.g., statistically) to characterize a stochastic effect well enough to provide (e.g., measure or model) a part per billion (PPB) level of defect probability accuracy.

[0071] Herein, a pattern refers to an arrangement of multiple features — where features may be two- dimensional or three-dimensional features having a shape and a size. A wafer may comprise multiple repeats of identical patterns (for example, multiple substantially identical chips). The wafer or a chip within the wafer may contain one or more irregular (e.g., non-repeating) patterns, including chips which are substantially different from one another. Each chip (or wafer area) may contain various features arranged in pattern, at least some of which may be irregular (that is, substantially non-repeating) patterns or features. Irregular features may be features for which the wafer or chip may contain fewer than a statistically significant number of repeats, such as only one instance, 10s of repeats, 100s of repeats, 1000s of repeats, etc. Irregular features on the wafer or chip may be imaged (such as during thelithography process), but the number of repeats on the wafer or chip (or at a specific dose or focus) may be insufficient for accurate statistical analysis of stochastic effects.

[0072] The example area 410 (e.g., of design layout of a wafer or chip) is provided for explicative purposes only. The example area 410 may include regions of periodic patterns (such as the region 412 with periodic contact holes) and regions of irregular patterns (such as the region 414 with irregularly shaped and spaced features which may, for example, correspond to random logic features). The example area 410 may include regions of isolated features, such as isolated feature 416. The example area 410 may be a chip, for a portion of a chip, etc. From the example area 410, features or parts of features may be selected for generating a stochastic calibration layout. The selected features may be selected based on a stochastic model operating on the design layout, based on defect analysis from either fabricated chips or a defect model based on the design layout, based on criticality of the features (e.g., critical features such as features with a CD may be selected with or without knowledge of stochastic effects on them), etc. The features may be selected from the features of the example area 410 based on any appropriate method. Regular features (e.g., the region 412), including regular features which may have large stochastic effects according to a stochastic model, may be excluded from selection for the stochastic calibration layout — such as in cases where enough instances of the regular features are present in the design layout for measurement of stochastic effect on those regular features in a wafer or chip fabricated based on the design layout itself.

[0073] A stochastic model 430 may be constructed to predict the stochastic effects on portions of the example area 410 (such as based on an input of the design layout corresponding to the example area 410). The stochastic model 430 may be a stochastic edge placement error (SEPE) model. The stochastic model 430 may be a stochastic error model. The stochastic model 430 may be a CD model which includes stochastic effects. The stochastic model 430 may be a model which include optical effects (e.g., photon shot noise), which include stochasticity. The stochastic model 430 may be a model which includes process variation effects (e.g., critical ionization in photoresist development) which include stochasticity. The stochastic model 430 may be any appropriate model which includes prediction of stochastic effects, where stochastic effects may include variation in average, mean, standard deviation, distribution, etc. of feature size, feature area, feature roughness, feature placement, feature failure, etc. The stochastic model 430 may include a physical model, such as based on optical stochasticity (for example, photon shot noise). The stochastic model 430 may be calibrated to measure of a stochastic effect in a fabricated wafer, including first calibrated to a measure of stochasticity in repeating patterns and then calibrated to a measure of stochasticity in irregular patterns. The stochastic model 430 may include a machine learning model, such as a model trained to predict hotspots in design layouts

[0074] The stochastic model 430 may operate on portions of the design layout corresponding to the example area 410. The stochastic model 430 may output stochastic effect estimates (e.g., predictions) for features of a design layout, regions of a design layout, etc., such as a heat map of feature location, a histogram, etc. The stochastic model 430 may estimate stochasticity based on multiple output predictedwafer patterns, such as by running multiple simulations and compiling stochastic differences between various outputs. The stochastic model 430 may directly output stochastic information (e.g., SEPE, stochastic CD variation, CD distribution, etc.) for the design layout.

[0075] The design layout (or portions thereof) may be fed into the stochastic model 430, which may select regions (e.g., regions 420, 422, 424) of the example area 410 as “hotspots”. Herein, “hotspots” may be areas of a pattern for which stochastic effects may cause defects, such as feature placement error, feature size error, feature roughness, etc. Hotspots may include a feature, such as an isolated feature. Hotspots may include a region of a feature. Hotspots may include multiple features, including features which may have a merging failure mode (e.g., a failure caused by insufficient separation). Hotspots may include a feature and a location, where stochastic effects may cause misplacement of the feature. Hotspots may include features and spacing, where stochastic effects may cause incorrect spacing of the features. The stochastic model 430 may additionally or instead operate on regions of a design layout, such as regions which are preselected from the example area 410. For example, the stochastic model 430 may select, from the example area 410, the regions 420, 422, and 424 as regions which contain one or more features which have a high stochastic error (e.g., high probability of stochastic error).

[0076] The stochastic model 430 may associate each of the regions upon which it operates with a stochastic error score. The stochastic error score may be a predicted measure of stochastic effects, such as SEPE. The stochastic error score may be an absolute or relative measure of stochastic effects (e.g., stochastic error). The stochastic model 430 may output a ranking of the regions (e.g., of the example area 410) based on their stochastic error scores. For example, the stochastic model 430 may rank the regions 420, 422, 424 and may output a ranking where the region 424 has the highest stochastic error score, the region 420 has a second highest stochastic error score, and the region 422 has the third highest stochastic error score. The stochastic model 430 may rank substantially all features of a design layout, such as corresponding to the example area 410. The stochastic model 430 may rank substantially all features of the example area 410 with a stochastic error score higher than a threshold and may not rank features of the example area 410 with stochastic error scores lower than a threshold. For example, the region 412 with regular features may have a stochastic error score lower than a threshold and may not be ranked by the stochastic model 430.

[0077] The stochastic model 430 may predict a stochastic effect for each pixel (or voxel) of a region. For example, the region 424 may have a predicted SEPE as output by the stochastic model 430. The SEPE evaluated along the cross-sectional line 432 is displayed in graph 440. The graph 440 depicts probability of edge placement at each point along the line 432 as the curve 442. The probability of edge placement may include probabilities which account for missing features, merged features, etc. The SEPE (or any other appropriate measure of a stochastic effect) may be characterized by one or more curve fitting (such as by Gaussian curves 446 and 448), by mean, median, mode, average, etc. (such asby curve mode 444), by full width half max (FWHM) (e.g., FWHM 445), or any other appropriate stochastic distribution characterization method.

[0078] Instead of or in addition to the stochastic model 430, features may be selected by defect analysis, such as failure analysis (e.g., yield analysis), based on either wafers fabricated from the design layout or wafers previously fabricated from similar design layouts. For example, features may be selected based on expected stochastic effects or rankings from previous versions of the design layout (e.g., a design layout for similar features, such as random memory, in a different device, at a previous node, fabricated on a different machine type, etc.). Hotspots may be identified through defect analysis and such features selected for inclusion in the calibration layout. Hotspots may be manually selected, such as by users (based on user knowledge of previous design hotspots, based on knowledge of criticality of various features, based on features which are different from previously fabricated features and which may therefore have unknown stochastic effects, etc.) Hereinafter reference to the stochastic model should be taken to include alternate feature selection methods, including methods which do not include a model.

[0079] Once the regions of the example area 410 are ranked by the stochastic model or another appropriate method, selected features (and spacings) 450 may be determined. The features and spacings of the hotspot may be preserved, in part or in full. For example, the features of the region 424 (e.g., as depicted in black) may be conserved, while features of the example area 410 to which the features of the region 424 correspond (e.g., features 418 and 419) may not be conserved. In some embodiments, intermediate features (e.g., hashed features 452 and 454) may be generated which contain the features of the region 424. The selected features and spacings 450 may then be reproduced many times, such as on a calibration wafer containing an example area 460. The selected features and spacings 450 may be patterned using a calibration patterning device (e.g., mask). The calibration patterning device may contain patterns similar to selected regions of the patterning device used to generate the example area 410.

[0080] Figure 5 depicts a schematic representation of generation of a wafer containing multiple instances of selected pattern features, according to an embodiment. According to an embodiment of the present disclosure, the wafer (e.g., a calibration wafer 500) with multiple instances of one or more features is generated in order to perform stochastic effect characterization for the one or more features. The calibration wafer 500 may be fabricated based on design layout containing multiple repeats of the one or more features. The calibration wafer 500 may be fabricated by micro field exposure, massive micro field exposure, etc.

[0081] Once one or more features are selected, such as as-previously described in reference to Figure 4, a design layout for the calibration wafer 500 may be generated. The design layout may be a lithography mask design layout. The design layout may be any appropriate design layout. The design layout may be any appropriate size and may correspond to any appropriate exposure size. The exposure size may be a conventional exposure size (e.g., approximately 26 by 32 mm2in exposure field size).The exposure size may be a micro field exposure size (e.g., approximately 1 by 1 mm2in exposure field size). The design layout may include multiple groups of one or more features for stochastic effect characterization. For example, the design layout (and calibration wafer) may include features from the region 424 and features from the region 420 of Figure 4.

[0082] The calibration wafer 500 may be a focus exposure matrix (FEM) calibration wafer. For example, the calibration wafer 500 may be divided into a set of regions corresponding to values in the x and y directions (e.g., x values -6 to 6 on x-axis 502 and y values -6 to 6 on y-axis 504). Each of the regions may also correspond to a different value of dose (measured in percentage along column 508) and focus (measured in nm along row 506). Each of the regions of the calibration wafer 500 may have a consistent value of dose and focus within the region, but may vary in at least one of dose or focus from others of the regions of the calibration wafer 500. Stochastic effects may vary based on dose and focus. In order to characterize a stochastic effect to a part per billion level, up to 300,000 measurements may be needed at each dose and focus. In order to generate this number of instances of the selected features, each region of the calibration wafer 500 may be further divided.

[0083] An example region 510 of the calibration wafer is depicted. The example region 510 may have a substantially consistent dose and focus. The example region 510 may be patterned (e.g., exposed) by one or more exposures, such as multiple exposures with substantially the same dose and focus. The example region 510 may correspond to a conventional exposure field size of approximately 26 by 32 mm2. The example region 510 may be created by one or more exposure of a conventional exposure field size, where each exposure of conventional exposure field size may be an exposure of a corresponding patterning device (e.g., lithography mask). The example region 510 may correspond to multiple micro field exposure field sizes of approximately 1 by 1 mm2. The example region 510 may be created by multiple (e.g., massively multiple) exposures of a micro field exposure field size, where each exposure of the micro field exposure field size may be an exposure of a corresponding micro field patterning device (e.g., lithography mask). The example region 510 may be made up of N by M micro fields 520, where each micro field 520 may be between 1 mm and 100 pm in dimensions. A conventional exposure field size may be divided into approximately 85,800 (or M x N) micro fields 520. In some embodiments, a conventional exposure may be used, with a conventional exposure field size, but the area of the conventional exposure field size may be subdivided as will be explained for the micro fields 520, below.

[0084] Each micro field 520 may be further divided into m by n subfields 530. Each of the subfields 530 may contain one or more features for stochastic effect characterization. The subfields 530 may have dimensions on the order of 10 pm by 10 pm. The example region 510 may therefore contain M*N*m*n total instances of the selected one or more features. The number of subfields 530 which may be contained within a micro field 520 may depend on the size of the selected one or more features. Likewise, the number of features micro fields 520 which may be included in the example region 510 may depend on the number and size of the subfields 530. In some embodiments, the micro fields 520of the example region 510 may contain the same selected one or more features. In some embodiments, various micro fields 520 of the example region 510 may contain different sets of selected one or more features, such as some micro fields 520 may contain a first selected feature while other micro fields may contain a second selected feature. The subfields 530 may contain features selected from a production wafer based on predicted stochastic errors, as previously described.

[0085] The calibration wafer 500 may have a pattern which is generated by any appropriate method, such as previously described in reference to Figure 4. The calibration wafer 500 may be patterned by a patterning process using conventional exposure, micro field exposure, massive micro field exposure (e.g., large numbers of micro field exposures), etc. The calibration wafer 500 may be patterned by a patterning device (e.g., lithography mask). The patterning device corresponding to the calibration wafer 500 may be generated based on the desired pattern for the calibration wafer 500 (e.g., the multiple instances of the selected one or more features). The patterning device may be generated based on a pattern (e.g., design layout) corresponding to a production wafer (e.g., the wafer 400 of Figure 4) from which the one or more features are selected.

[0086] For example, the subfields 530 may contain features 532, 534, and 536. A patterning device corresponding to the calibration wafer 500 may contain features 542, 544, and 546, which generate the features 532, 534, and 536, respectively, when used in a patterning process by conventional or micro field exposure. The calibration wafer 500 may correspond to a patterning device which contains multiple instances of a design layout 540 corresponding to the subfields 530.

[0087] Figures 6A-6B depict graphs relating stochastic effects for full field and micro field exposures, according to an embodiment. According to an embodiment of the present disclosure, stochastic effects measured on a calibration wafer fabricated through micro field exposure may be approximately the same as stochastic effects measured on a production wafer on which the calibration wafer is based, to within a fitting factor. The relationship between stochastic effects in features fabricated by micro field exposure and by conventional field exposure may be linear.

[0088] Figure 6A depicts a graph of feature area along y axis 604 as a function of position in an image where the feature area is determined (along x axis 602). Line 610 represents average feature area as a function of position, while line 612 and 614 represent the bounds of the first standard deviation for the average feature area, for micro field exposure. Line 620 represents average feature area as a function of position, while line 622 and 624 represent the bounds of the first standard deviation for the average feature area, for full field exposure. Line 610 and 620 exhibit the same trend as a function of position, relatively similar standard deviations, and approximately linearly related average feature area.

[0089] Figure 6B depicts a histogram of feature area (along x-axis 652) and number of instances of features with a given feature area (along y-axis 654). Line 660 represents the distribution of feature size for a micro field exposure, while line 670 represents the distribution of feature size for a full field exposure. The distribution of the feature size is relatively similar for each type of exposure, withdifferent center points. This is consistent with a linear relationship between feature size in micro field and full field exposures, with substantially no alteration of the stochastic distribution of feature size.

[0090] Based on a calibration wafer produced by micro field exposure, stochastic effects may be determined. A stochastic model may be adjusted (e.g., calibrated) based on measurement of features in the calibration wafer, such as by SEM imaging, template matching, contour matching, etc.

[0091] Figure 7 is a flowchart illustrating a method for characterization of stochastic effects in a patterning process, according to an embodiment. According to an embodiment of the present disclosure, a stochastic effect on one or more feature may be characterized by generating a layout containing multiple instances of the one or more feature, obtaining metrology data measuring physical dimensions of the multiple instances of the one or more features in a fabricated wafer generated based on the layout, and statistically analyzing the metrology data. Each of these operations is described in detail below. The operations of method 700 presented below are intended to be illustrative. In some embodiments, method 700 may be accomplished with one or more additional operations not described, and / or without one or more of the operations discussed. Additionally, the order in which the operations of method 700 are illustrated in Figure 7 and described below is not intended to be limiting. In some embodiments, one or more portions of method 700 may be implemented (e.g., by simulation, modeling, etc.) in one or more processing devices (e.g., one or more processors). The one or more processing devices may include one or more devices executing some or all of the operations of method 700 in response to instructions stored electronically on an electronic storage medium. The one or more processing devices may include one or more devices configured through hardware, firmware, and / or software to be specifically designed for execution of one or more of the operations of method 700, for example.

[0092] At an operation 702, one or more features of a pattern are selected. The one or more features may be selected from a periodic or non-periodic pattern. The one or more features may be multiple features and a separation between the features. The one or more features may be a feature with a size and shape. The one or more features may be an isolated feature. The one or more features may be selected based on a stochastic model, which may be an OPC verification. The stochastic model may be a calibrated or uncalibrated stochastic model. The stochastic model may be any appropriate stochastic model, as previously described. The one or more features may be selected as “hotspots” from a larger pattern. The one or more features may be selected based on a stochastic error score. The one or more features may be selected based on a ranking of features of a pattern according to a stochastic error score.

[0093] At an operation 704, a layout is generated based on the selected one or more features. The layout may be a design layout. The layout may be or be converted to a mask design layout. The layout may be a layout for a patterning device. The layout may be a layout for conventional exposure. The layout may be a layout for micro field exposure. The layout may correspond to a focus exposure matrix or part of a focus exposure matrix, as previously described. The layout may contain multiple micro field exposure layouts. The layout may be a micro field exposure layout. The layout may containmultiple instances of the selected one or more features. The layout may be a mask pattern configured to generate multiple instances of the selected one or more features.

[0094] In one or more embodiments, one or more recipes for fabrication of the layout may be generated. The one or more recipes may be generated based on the layout generated based on the selected one or more features. The one or more recipes may be micro exposure recipes. The one or more recipes may be based on a recipe for a design layout from which the one or more features are selected. For example, the layout may be generated based on the selected one or more features from the design layout and one or more recipes may be generated based on a recipe corresponding to the design layout — e.g., the one or more recipes may be identical to the recipe corresponding to the design layout, may have different exposure areas, may have different dose, focus, etc. when compared to the recipe corresponding to the design layout. The one or more recipes may be specific to a fabrication device, for example, a recipe for a lithography apparatus (e.g., scanner). The one or more recipes may vary, including for multiple instances of the same layout. For example, the one or more recipes may vary in focus, dose, etc. A set of recipes may be generated to fabricated a FEM wafer, where the set of recipes may vary in focus, dose, etc. The one or more recipes may correspond to a specific exposure time, area, dose, etc.

[0095] A calibration wafer may be fabricated based on the layout. The layout may include or correspond to a recipe for generation of the calibration wafer (e.g., a lithography recipe). The calibration wafer may be fabricated based on one or more generated recipes. The layout may correspond to a recipe for conventional exposure, such as if the layout is a layout for conventional exposure. The layout may correspond to multiple recipes for micro field exposure, such as if the layout is a layout for micro field exposure. The recipe may have multiple settings, such as for each focus and dose of the focus exposure matrix. The calibration wafer may be fabricated based on the layout and the recipe(s) corresponding to the layout.

[0096] At an operation 706, metrology data is obtained from the calibration wafer patterned using the layout. The metrology data may be optical metrology data (e.g., images). The metrology data may be scanning electron microscopy (SEM) images. The metrology data may include data on placement, size, roughness, separation distance, CD, etc. for substantially all instances of the selected one or more features on the calibration wafer. The metrology data may be obtained from the images by template matching, contour matching, edge placement gauges, or any other appropriate image processing. The metrology data may be obtained in one or more fields of view (FOV). The metrology data may be batched for each exposure condition (e.g., of the focus exposure matrix). The metrology data may be any metrology data which varies due at least in part to stochastic effects.

[0097] At an operation 708, stochastic effects of the patterning process on the selected one or more features are characterized. The stochastic effects of the patterning process may be the stochastic effects of the patterning process used to fabricate the calibration wafer. The patterning process may be a measured patterning process, which may or may not be substantially identical to any patterning processinput into a stochastic model. That is, the stochastic effects of the performed patterning process may be different from the stochastic effects of an ideal patterning process, including due to non-idealities in the patterning process.

[0098] The stochastic effects may be characterized in any appropriate manner. For example, a stochastic effect may cause a distribution in one or more feature characteristics (e.g., distance, size, length, area, etc.). The stochastic effect may be characterized by characterizing the distribution, such as by determining a norm, mean, median, model, midpoint, etc. The distribution may be characterized by determination of a standard deviation, range, FWHM, measure of variability, etc. The distribution may be curve fit, such as to a Gaussian, Lorentzian, etc. curve which may match the distribution. The distribution may be described by a histogram. The distribution may be a symmetric or asymmetric distribution.

[0099] The characterized stochastic effect may be adjusted, such as linearly, by a parameter which relates the distribution of feature characteristics for micro field exposure to the distribution of feature characteristics in conventional field exposure. The characterized stochastic effects may be used qualitatively, such as to determine if a new feature arrangement is better than a previous feature arrangement. The characterized stochastic effects may be used to adjust a stochastic model, including the stochastic model used to select the one or more features.

[0100] As described above, method 700 (and / or the other methods and systems described herein) is configured for characterizing stochastic effects of a patterning process.

[0101] Figure 8 is a diagram of an example computer system CS that may be used for one or more of the operations described herein, according to an embodiment of the present disclosure. Computer system CS includes a bus BS or other communication mechanism for communicating information, and a processor PRO (or multiple processors) coupled with bus BS for processing information. Computer system CS also includes a main memory MM, such as a random-access memory (RAM) or other dynamic storage device, coupled to bus BS for storing information and instructions to be executed by processor PRO. Main memory MM also may be used for storing temporary variables or other intermediate information during execution of instructions by processor PRO. Computer system CS further includes a read only memory (ROM) ROM or other static storage device coupled to bus BS for storing static information and instructions for processor PRO. A storage device SD, such as a magnetic disk or optical disk, is provided and coupled to bus BS for storing information and instructions.

[0102] Computer system CS may be coupled via bus BS to a display DS, such as a cathode ray tube (CRT) or flat panel or touch panel display for displaying information to a computer user. An input device ID, including alphanumeric and other keys, is coupled to bus BS for communicating information and command selections to processor PRO. Another type of user input device is cursor control CC, such as a mouse, a trackball, or cursor direction keys for communicating direction information and command selections to processor PRO and for controlling cursor movement on display DS. This input device typically has two degrees of freedom in two axes, a first axis (e.g., x) and a second axis (e.g., y),that allows the device to specify positions in a plane. A touch panel (screen) display may also be used as an input device.

[0103] In some embodiments, portions of one or more methods described herein may be performed by computer system CS in response to processor PRO executing one or more sequences of one or more instructions contained in main memory MM. Such instructions may be read into main memory MM from another computer-readable medium, such as storage device SD. Execution of the sequences of instructions included in main memory MM causes processor PRO to perform the process steps (operations) described herein. One or more processors in a multi-processing arrangement may also be employed to execute the sequences of instructions contained in main memory MM. In some embodiments, hard-wired circuitry may be used in place of or in combination with software instructions. Thus, the description herein is not limited to any specific combination of hardware circuitry and software.

[0104] The term “computer-readable medium” and / or “machine readable medium” as used herein refers to any medium that participates in providing instructions to processor PRO for execution. Such a medium may take many forms, including but not limited to, non-volatile media, volatile media, and transmission media. Non-volatile media include, for example, optical or magnetic disks, such as storage device SD. Volatile media include dynamic memory, such as main memory MM. Transmission media include coaxial cables, copper wire and fiber optics, including the wires that comprise bus BS. Transmission media can also take the form of acoustic or light waves, such as those generated during radio frequency (RF) and infrared (IR) data communications. Computer-readable media can be non- transitory, for example, a floppy disk, a flexible disk, hard disk, magnetic tape, any other magnetic medium, a CD-ROM, DVD, any other optical medium, punch cards, paper tape, any other physical medium with patterns of holes, a RAM, a PROM, and EPROM, a FLASH-EPROM, any other memory chip or cartridge. Non-transitory computer readable media can have instructions recorded thereon. The instructions, when executed by a computer, can implement any of the operations described herein. Transitory computer-readable media can include a carrier wave or other propagating electromagnetic signal, for example.

[0105] Various forms of computer readable media may be involved in carrying one or more sequences of one or more instructions to processor PRO for execution. For example, the instructions may initially be borne on a magnetic disk of a remote computer. The remote computer can load the instructions into its dynamic memory and send the instructions over a telephone line using a modem. A modem local to computer system CS can receive the data on the telephone line and use an infrared transmitter to convert the data to an infrared signal. An infrared detector coupled to bus BS can receive the data carried in the infrared signal and place the data on bus BS. Bus BS carries the data to main memory MM, from which processor PRO retrieves and executes the instructions. The instructions received by main memory MM may optionally be stored on storage device SD either before or after execution by processor PRO.

[0106] Computer system CS may also include a communication interface CI coupled to bus BS. Communication interface CI provides a two-way data communication coupling to a network link NDL that is connected to a local network LAN. For example, communication interface CI may be an integrated services digital network (ISDN) card or a modem to provide a data communication connection to a corresponding type of telephone line. As another example, communication interface CI may be a local area network (LAN) card to provide a data communication connection to a compatible LAN. Wireless links may also be implemented. In any such implementation, communication interface CI sends and receives electrical, electromagnetic, or optical signals that carry digital data streams representing various types of information.

[0107] Network link NDL typically provides data communication through one or more networks to other data devices. For example, network link NDL may provide a connection through local network LAN to a host computer HC. This can include data communication services provided through the worldwide packet data communication network, now commonly referred to as the “Internet” INT. Local network LAN (Internet) may use electrical, electromagnetic, or optical signals that carry digital data streams. The signals through the various networks and the signals on network data link NDL and through communication interface CI, which carry the digital data to and from computer system CS, are exemplary forms of carrier waves transporting the information.

[0108] Computer system CS can send messages and receive data, including program code, through the network(s), network data link NDL, and communication interface CL In the Internet example, host computer HC might transmit a requested code for an application program through Internet INT, network data link NDL, local network LAN, and communication interface CL One such downloaded application may provide all or part of a method described herein, for example. The received code may be executed by processor PRO as it is received, and / or stored in storage device SD, or other non-volatile storage for later execution. In this manner, computer system CS may obtain application code in the form of a carrier wave.

[0109] Embodiments of the present disclosure can be further described by the following clauses.1. A method for characterizing stochastic effects in a patterning process comprising: selecting at least one pattern feature of a circuitry design layout, wherein the at least one pattern feature is identified as prone to stochastic error; generating a stochastic calibration layout comprising multiple instances of the at least one pattern feature; obtaining metrology data from a wafer that has been patterned with multiple instances of the at least one pattern feature, the wafer having been patterned by a patterning device generated from the stochastic calibration layout; and characterizing stochastic effects of a patterning process utilizing the patterning device on the at least one pattern feature based upon the metrology data from the multiple instances of the at least one pattern feature.2. The method of clause 1 , wherein the circuitry design layout comprises a random logic circuitry design layout and wherein the at least one pattern features comprises at least one random logic feature.3. The method of clause 1 , wherein the at least one pattern feature identified as prone to stochastic error comprises at least one pattern featured determined to have a stochastic error by a stochastic model.4. The method of clause 3, further comprising calibrating the stochastic model based on the characterized stochastic effects.5. The method of clause 4, wherein calibrating the stochastic model comprises adjusting the stochastic model based on an average, median, mean, standard deviation, one or more higher order stochastic moment, one or more distributions, or combination thereof of the obtained metrology data.6. The method of clause 1 , wherein the at least one pattern feature identified as prone to stochastic error comprises at least one pattern feature determined to have stochastic error based on failure analysis, feature size, similarity to previously fabricated features, or a combination thereof.7. The method of clause 1, further comprising adjusting the circuitry design layout or the patterning process based on the characterized stochastic effects.8. The method of clause 1, further comprising determining stochastic effects of the patterning process on the circuitry design layout based on the stochastic effects of the patterning process on the at least one pattern feature.9. The method of clause 8, wherein determining stochastic effects of the patterning process on the circuitry design layout comprises generalizing the stochastic effects of the patterning process on the at least one pattern feature to additional features of the circuitry design layout.10. The method of clause 1 , wherein the wafer that has been patterned comprises a wafer patterned by a plurality of exposures by micro field exposure to contain multiple areas each containing the multiple instances of the at least one pattern feature and wherein generating the stochastic calibration layout further comprises configuring one or more recipes to pattern the wafer by the plurality of exposures.11. The method of clause 10, wherein an area of the micro field exposure is on the order of 10 pm by 10 pm.12. The method of clause 1, wherein the patterning device comprises a patterning device to pattern a wafer by a plurality of exposures to contain multiple areas each containing the multiple instances of the at least one pattern feature.13. The method of clause 1 or 12, wherein generating the layout for the patterning device further comprises generating one or more recipes for a patterning apparatus to undertake the patterning process using the patterning device.14. The method of clause 13, wherein the one or more recipes vary in at least one of dose, focus, or a combination thereof.15. The method of clause 13, wherein the wafer that has been patterned with the multiple instances of the at least one pattern feature comprises a focus exposure matrix (FEM) wafer, various regions of the FEM wafer containing the multiple instances of the at least one pattern feature.16. The method of clause 1, wherein obtaining metrology data comprises: obtaining scanning electron microscopy (SEM) images of the multiple instances of the at least one pattern feature; measuring at least one of a first dimension and placement of the multiple instances of the at least one pattern feature; determining a distribution of the measured at least one of a first dimension and placement of the multiple instances of the at least on pattern feature, and wherein determining stochasticity of the multiple instances of the at least one pattern feature in the obtained SEM images comprises characterizing the stochasticity of the distribution.17. The method of clause 1, wherein the obtained metrology data comprises at least one of critical dimension (CD), overlay, edge placement error (EPE), failure number, failure rate, feature area, or a combination thereof.18. The method of clause 1, wherein selecting the at least one pattern feature comprises: obtaining predicted stochastic errors for multiple features of the circuitry design layout; ranking each of the multiple features based on their corresponding predicted stochastic errors; and selecting as the at least one pattern feature one or more of the multiple features based on the ranking.19. The method of clause 18, further comprising selecting an additional one or more of the multiple features as the at least one pattern features based on the ranking.20. The method of clause 1, wherein the patterning process is a lithography process, resist process, etch process, or combination thereof.21. The method of clause 3, wherein the stochastic model is a model of stochastic error.22. The method of clause 1 , wherein obtaining metrology data comprises obtaining metrology data for on the order of 300,000 instances of the at least one pattern feature.23. The method of clause 1, wherein characterizing stochastic effect comprises characterizing stochastic effects to one the order of a part per billion failure rate for the at least one pattern feature, the at least one pattern feature comprising a non-repeating pattern feature.24. The method of clause 1, wherein the circuitry design layout comprises random logic patterns.25. One or more non-transitory, machine-readable medium having instruction thereon, the instructions when executed by a processor being configured to perform the method of any one of clauses 1 to 24.26. A system comprising: a scanner configured to perform a patterning process for a circuitry design layout;at least one scanner recipe for the patterning process for the circuitry design layout; a processor; and one or more non-transitory, machine -readable medium having instruction thereon, the instructions when executed by a processor being configured to: select at least one pattern feature with a stochastic error from the circuitry design layout; generate a stochastic calibration layout and at least one calibration scanner recipe to pattern a wafer to containing multiple instances of the at least one pattern feature; and operate the scanner based on the at least one calibration scanner recipe and the stochastic calibration layout to generate a patterned wafer containing multiple instances of the at least one pattern feature.27. The system of clause 26, wherein the at least one calibration scanner recipe comprises multiple scanner recipes which vary in at least one of dose and focus and wherein the patterned wafer comprises a focus exposure matrix (FEM) wafer, various regions of the FEM wafer containing the multiple instances of the at least one pattern feature.28. The system of clause 26, further comprising a scanning electron microscope (SEM) configured to obtain SEM images of the multiple instances of the at least one pattern feature, the processor being further configured to: determine stochastics effects of the at least one calibration scanner recipe on the at least one pattern feature from the SEM images of the multiple instances of the at least one pattern feature, wherein the at least one calibration scanner recipe is generated based on the at least one scanner recipe for the patterning process.29. The system of clause 26, wherein the circuitry design layout is a random logic design layout and wherein the at least one pattern feature comprises a non-repeating pattern feature.

[0110] While the concepts disclosed herein may be used for manufacturing with a substrate such as a silicon wafer, it shall be understood that the disclosed concepts may be used with any type of manufacturing system (e.g., those used for manufacturing on substrates other than silicon wafers).

[0111] In addition, the combination and sub-combinations of disclosed elements may comprise separate embodiments. For example, one or more of the operations described above may be included in separate embodiments, or they may be included together in the same embodiment.

[0112] The descriptions above are intended to be illustrative, not limiting. Thus, it will be apparent to one skilled in the art that modifications may be made as described without departing from the scope of the claims set out below.

Claims

WHAT IS CLAIMED IS:

1. A method for characterizing stochastic effects in a patterning process comprising: selecting at least one pattern feature of a circuitry design layout, wherein the at least one pattern feature is identified as prone to stochastic error; generating a stochastic calibration layout comprising multiple instances of the at least one pattern feature; obtaining metrology data from a wafer that has been patterned with multiple instances of the at least one pattern feature, the wafer having been patterned by a patterning device generated from the stochastic calibration layout; and characterizing stochastic effects of a patterning process utilizing the patterning device on the at least one pattern feature based upon the metrology data from the multiple instances of the at least one pattern feature.

2. The method of claim 1 , wherein the circuitry design layout comprises a random logic circuitry design layout and wherein the at least one pattern features comprises at least one random logic feature, and wherein the at least one pattern feature identified as prone to stochastic error comprises at least one pattern featured determined to have a stochastic error by a stochastic model.

3. The method of claim 2, further comprising calibrating the stochastic model based on the characterized stochastic effects.

4. The method of claim 3, wherein calibrating the stochastic model comprises adjusting the stochastic model based on an average, median, mean, standard deviation, one or more higher order stochastic moment, one or more distributions, or combination thereof of the obtained metrology data.

5. The method of claim 1, wherein the at least one pattern feature identified as prone to stochastic error comprises at least one pattern feature determined to have stochastic error based on failure analysis, feature size, similarity to previously fabricated features, or a combination thereof, and further comprising determining stochastic effects of the patterning process on the circuitry design layout based on the stochastic effects of the patterning process on the at least one pattern feature.

6. The method of claim 5, wherein determining stochastic effects of the patterning process on the circuitry design layout comprises generalizing the stochastic effects of the patterning process on the at least one pattern feature to additional features of the circuitry design layout.

7. The method of claim 1, wherein the wafer that has been patterned comprises a wafer patterned by a plurality of exposures by micro field exposure to contain multiple areas each containing the multiple instances of the at least one pattern feature and wherein generating the stochastic calibration layout further comprises configuring one or more recipes to pattern the wafer by the plurality of exposures.

8. The method of claim 7, wherein an area of the micro field exposure is on the order of 10 pm by 10 pm.

9. The method of claim 1, wherein the patterning device comprises a patterning device to pattern a wafer by a plurality of exposures to contain multiple areas each containing the multiple instances of the at least one pattern feature.

10. The method of claim 1, wherein generating the layout for the patterning device further comprises generating one or more recipes for a patterning apparatus to undertake the patterning process using the patterning device, wherein the one or more recipes vary in at least one of dose, focus, or a combination thereof.

11. The method of claim 10, wherein the wafer that has been patterned with the multiple instances of the at least one pattern feature comprises a focus exposure matrix (FEM) wafer, various regions of the FEM wafer containing the multiple instances of the at least one pattern feature.

12. The method of claim 1, wherein obtaining metrology data comprises: obtaining scanning electron microscopy (SEM) images of the multiple instances of the at least one pattern feature; measuring at least one of a first dimension and placement of the multiple instances of the at least one pattern feature; determining a distribution of the measured at least one of a first dimension and placement of the multiple instances of the at least on pattern feature, and wherein determining stochasticity of the multiple instances of the at least one pattern feature in the obtained SEM images comprises characterizing the stochasticity of the distribution.

13. The method of claim 1, wherein the patterning process is a lithography process, resist process, etch process, or combination thereof, and wherein the obtained metrology data comprises at least one of critical dimension (CD), overlay, edge placement error (EPE), failure number, failure rate, feature area, or a combination thereof.

14. The method of claim 1, wherein selecting the at least one pattern feature comprises: obtaining predicted stochastic errors for multiple features of the circuitry design layout; ranking each of the multiple features based on their corresponding predicted stochastic errors; and selecting as the at least one pattern feature one or more of the multiple features based on the ranking.

15. The method of claim 14, further comprising selecting an additional one or more of the multiple features as the at least one pattern features based on the ranking.

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