Display platforms and display devices

Abstract

The invention relates to a display base (40) and a display device, the display base consisting of: first area and second area with gate control circuit (20), gate control circuit (20) consisting of: several shift registers, at least one shift register stage consisting of: pre-processing circuit and control output circuit, control output circuit consisting of: N control output auxiliary circuits, the nth control output auxiliary circuit is electrically connected to the nth control signal output terminal, in at least one display frame, the start time of the control signal output from the nth control signal output terminal is later than the start time of the control signal output from at least one of the first control signal output terminals to the (n-1)th control signal output terminal, and the area of ​​the nth control output auxiliary circuit is larger than the area of ​​at least one of the first control output auxiliary circuits to the (n-1)th control output auxiliary circuit.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and particularly to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, the present disclosure provides a display substrate comprising: a first region and a second region, wherein the first region is provided with an array-arranged pixel driving circuit, and the second region is provided with a gate driving circuit, wherein the gate driving circuit is configured to provide a driving signal to the pixel driving circuit, wherein the gate driving circuit comprises: a plurality of shift registers, wherein at least one shift register comprises: a preamplifier circuit and a driving output circuit, wherein the preamplifier circuit is electrically connected to a signal input terminal, a reset signal terminal, and a cascade output signal terminal, respectively; the driving output circuit is electrically connected to N driving output signal terminals, respectively; the signal input terminal of the at least one shift register is electrically connected to the cascade output signal terminal of the at least one shift register, and the reset signal terminal of the at least one shift register is electrically connected to the cascade output signal terminal of the at least one shift register.

[0006] The drive output circuit includes: N drive output sub-circuits, the nth drive output sub-circuit being electrically connected to the nth drive output signal terminal, and in at least one display frame, a start time of a drive signal output by the Nth drive output signal terminal being later than a start time of a drive signal output by at least one of the first drive signal terminal to the N-1th drive output signal terminal, where N>2, 1≤n≤N;

[0007] The area of ​​the Nth driver output sub-circuit is larger than the area of ​​at least one of the first to N-1th driver output sub-circuits.

[0008] In an exemplary embodiment, the present invention comprises: a substrate and a driving structure layer disposed on the substrate, wherein the gate driving circuit and the pixel driving circuit are located in the driving structure layer, wherein the driving structure layer comprises: a semiconductor layer, a first conductive layer, and a second conductive layer sequentially stacked on the substrate, and at least one driving output sub-circuit comprises: an output transistor, a noise reduction transistor, and an output capacitor, wherein the transistor comprises: an active pattern, a gate electrode, a first electrode, and a second electrode, and the capacitor comprises: a first electrode plate and a second electrode plate;

[0009] The semiconductor layer includes at least: an active pattern of an output transistor located in at least one driver output sub-circuit and an active pattern of a noise reduction transistor;

[0010] The first conductive layer includes at least: a first plate of an output capacitor located at at least one driver output sub-circuit;

[0011] The second conductive layer includes at least a second plate of an output capacitor located at at least one drive output sub-circuit, a gate electrode, a first electrode, a second electrode of an output transistor, and a gate electrode, a first electrode, and a second electrode of a noise reduction transistor.

[0012] In an exemplary embodiment, an area of ​​an output transistor in the Nth driver output sub-circuit is larger than an area of ​​an output transistor of at least one of the first driver output sub-circuit to the N-1th driver output sub-circuit, and an area of ​​an output capacitor in the Nth driver output sub-circuit is equal to an area of ​​an output capacitor of at least one of the first driver output sub-circuit to the N-1th driver output sub-circuit.

[0013] In an exemplary embodiment, a width-to-length ratio of a channel region of an active pattern of an output transistor in the Nth driver output sub-circuit is greater than a width-to-length ratio of a channel region of an active pattern of an output transistor in at least one driver output sub-circuit from the first driver output sub-circuit to the N-1th driver output sub-circuit.

[0014] In an exemplary embodiment, a width-to-length ratio of a channel region of an active pattern of an output transistor in a first driver output sub-circuit is greater than a width-to-length ratio of a channel region of an active pattern of an output transistor in at least one of a second driver output sub-circuit to an N-1th driver output sub-circuit.

[0015] In an exemplary embodiment, width-to-length ratios of channel regions of the output transistors in at least two of the second to N−1th driver output sub-circuits are equal.

[0016] In an exemplary embodiment, an area of ​​an output capacitor in the Nth driver output sub-circuit is greater than an area of ​​an output capacitor of at least one of the first driver output sub-circuit to the N-1th driver output sub-circuit, and an area of ​​an output transistor in the Nth driver output sub-circuit is equal to an area of ​​an output transistor of at least one of the first driver output sub-circuit to the N-1th driver output sub-circuit.

[0017] In an exemplary embodiment, in at least one drive output sub-circuit, at least a portion of the gate electrode of the output transistor is a ring structure, at least a portion of the first pole of the output transistor is a ring structure, the gate electrode of the output transistor surrounds the first pole of the output transistor, and the second pole of the output transistor is arranged on at least one side of the gate electrode of the output transistor.

[0018] In an exemplary embodiment, in at least one driver output sub-circuit, the output capacitor is located on a side of the output transistor close to the second center line, and the noise reduction transistor is located on a side of the output transistor close to the first center line. The first center line is the center line of the area occupied by the driver output circuit extending along the first direction, and the second center line is the center line of the area occupied by the driver output circuit extending along the second direction.

[0019] In an exemplary embodiment, N=4, the output device in the first driver output subcircuit and the output device in the second driver output subcircuit are symmetrically arranged with respect to the second centerline, the output device in the second driver output subcircuit and the output device in the third driver output subcircuit are symmetrically arranged with respect to the first centerline, the output capacitor in the fourth driver output subcircuit and the output capacitor in the third driver output subcircuit are symmetrically arranged with respect to the second centerline, at least a portion of the output transistors in the fourth driver output subcircuit and the output transistors in the third driver output subcircuit are symmetrically arranged with respect to the second centerline, the output capacitor in the fourth driver output subcircuit and the output capacitor in the first driver output subcircuit are symmetrically arranged with respect to the first centerline, and at least a portion of the output transistors in the fourth driver output subcircuit and the output transistors in the first driver output subcircuit are symmetrically arranged with respect to the first centerline, the output devices include: output transistors and output capacitors, the first centerline is a centerline of an area occupied by the driver output circuit extending along the first direction, and the second centerline is a centerline of an area occupied by the driver output circuit extending along the second direction;

[0020] The noise reduction transistor of the first driver output sub-circuit and the noise reduction transistor of the second driver output sub-circuit are located on a side of the output device of the first driver output sub-circuit close to the first center line, and the noise reduction transistor of the second driver output sub-circuit is located on a side of the noise reduction transistor of the first driver output sub-circuit close to the first center line. The noise reduction transistor of the third driver output sub-circuit and the noise reduction transistor of the fourth driver output sub-circuit are located on a side of the output device of the third driver output sub-circuit close to the first center line, and the noise reduction transistor of the third driver output sub-circuit is located on a side of the noise reduction transistor of the fourth driver output sub-circuit close to the first center line.

[0021] The noise reduction transistor of the first driver output sub-circuit and the noise reduction transistor of the fourth driver output sub-circuit are asymmetrically arranged relative to the first center line, and the noise reduction transistor of the second driver output sub-circuit and the noise reduction transistor of the third driver output sub-circuit are asymmetrically arranged relative to the first center line.

[0022] In an exemplary embodiment, the region where the driving output circuit is located is divided into a first region and a second region by the second center line;

[0023] The output device of the first driver output sub-circuit and the output device of the fourth driver output sub-circuit are located in the first area, and the output device of the second driver output sub-circuit and the output device of the third driver output sub-circuit are located in the second area;

[0024] The noise reduction transistor of at least one of the first to fourth driver output sub-circuits is located in a first region and a second region, and an area of ​​the noise reduction transistor located in the first region is smaller than an area of ​​the noise reduction transistor located in the second region;

[0025] The areas of the noise reduction transistors of the first driver output sub-circuit and the second driver output sub-circuit in the first region are larger than the areas of the noise reduction transistors of the third driver output sub-circuit and the fourth driver output sub-circuit in the first region, and the areas of the noise reduction transistors of the first driver output sub-circuit and the second driver output sub-circuit in the second region are smaller than the areas of the noise reduction transistors of the third driver output sub-circuit and the fourth driver output sub-circuit in the second region.

[0026] In an exemplary embodiment, the active pattern of the output transistor of the fourth driver output sub-circuit includes: at least one first active pattern and at least one second active pattern, wherein a length of the first active pattern along the second direction is greater than a length of the second active pattern along the second direction;

[0027] The first active pattern includes: a first active portion and a second active portion, the first active portion and the second active portion have the same length along the first direction, and the second active portion is located on a side of the first active portion close to the first center line;

[0028] The first active portion and the second active pattern of the active pattern of the output transistor of the fourth driver output sub-circuit are symmetrically arranged with at least a portion of the active pattern of the output transistor of the first driver output sub-circuit relative to the first center line, and the first active portion and the second active pattern of the active pattern of the output transistor of the fourth driver output sub-circuit are symmetrically arranged with at least a portion of the active pattern of the output transistor of the third driver output sub-circuit relative to the second center line.

[0029] In an exemplary embodiment, the first electrode of the output transistor of the fourth drive output sub-circuit includes: a first electrode portion and a second electrode portion spaced apart;

[0030] The first electrode portion of the output transistor of the fourth driver output sub-circuit is symmetrically arranged with respect to the first electrode of the output transistor of the first driver output sub-circuit with respect to the first center line, and the first electrode portion of the output transistor of the fourth driver output sub-circuit is symmetrically arranged with respect to the first electrode of the output transistor of the third driver output sub-circuit;

[0031] The first electrode portion and the second electrode portion include a closed loop structure, an orthographic projection of the first electrode portion on the substrate at least partially overlaps with an orthographic projection of the first active portion and the second active pattern on the substrate, and an orthographic projection of the second electrode portion on the substrate at least partially overlaps with an orthographic projection of the second active portion on the substrate;

[0032] An area of ​​the first electrode portion is larger than an area of ​​the second electrode portion.

[0033] In an exemplary embodiment, the gate electrode of the output transistor of the fourth driver output sub-circuit includes: a first gate electrode portion and a second gate electrode portion connected to each other;

[0034] The first gate electrode portion of the gate electrode of the output transistor of the fourth driver output sub-circuit is symmetrically arranged with respect to the gate electrode of the output transistor of the first driver output sub-circuit with respect to the first center line, and the first gate electrode portion of the gate electrode of the output transistor of the fourth driver output sub-circuit is symmetrically arranged with respect to the gate electrode of the output transistor of the third driver output sub-circuit with respect to the second center line;

[0035] The first gate electrode portion and the second gate electrode portion comprise a closed loop structure, wherein an orthographic projection of the first gate electrode portion on the substrate at least partially overlaps with an orthographic projection of the first active portion and the second active pattern on the substrate, and an orthographic projection of the second gate electrode portion on the substrate at least partially overlaps with an orthographic projection of the second active portion on the substrate; the first gate electrode portion surrounds the first electrode portion, and the second gate electrode portion surrounds the second electrode portion;

[0036] An area of ​​the first gate electrode portion is larger than an area of ​​the second gate electrode portion.

[0037] In an exemplary embodiment, a virtual straight line extending in the first direction and passing through the noise reduction transistor of the fourth driver output sub-circuit passes through the output transistor of the fourth driver output sub-circuit.

[0038] In an exemplary embodiment, the second region further includes: output connection lines, the output connection lines including: first to fourth output connection lines; the first driver output sub-circuit is connected to the first output connection line, the second driver output sub-circuit is connected to the second output connection line, the third driver output sub-circuit is connected to the third output connection line, and the fourth driver output sub-circuit is connected to the fourth output connection line;

[0039] The first output connection line and the second output connection line are located between the output transistor of the first driver output sub-circuit and the noise reduction transistor of the first driver output sub-circuit, and the third output connection line and the fourth output connection line are located between the output transistor of the fourth driver output sub-circuit and the noise reduction transistor of the fourth driver output sub-circuit;

[0040] The first output connection line and the second output connection line extend along a first direction, the third output connection line and the fourth output connection line are zigzag-line shaped and at least partially extend along the first direction, and the output connection lines are located in the second conductive layer.

[0041] In an exemplary embodiment, at least one of the third and fourth output connection lines includes: a first output connection portion, a second output connection portion, and a third output connection portion; the first output connection portion and the third output connection portion extend along a first direction, the second output connection portion extends along a second direction, and the second output connection portion is electrically connected to the first and third output connection portions, respectively.

[0042] In an exemplary embodiment, N=4, the first to third driver output subcircuits include: one output capacitor, and the fourth driver output subcircuit includes: two output capacitors;

[0043] The output devices in the first drive output subcircuit and the output devices in the second drive output subcircuit are symmetrically arranged with respect to the second center line, the output devices in the second drive output subcircuit and the output devices in the third drive output subcircuit are symmetrically arranged with respect to the first center line, the output devices in the fourth drive output subcircuit and the output devices in the first drive output subcircuit are symmetrically arranged with respect to the first center line, the output devices in the first to third drive output subcircuits include: output transistors and output capacitors, the output devices in the fourth drive output subcircuit include: output transistors and one of the output capacitors, the first center line is the center line of the area occupied by the drive output circuit extending along the first direction, and the second center line is the center line of the area occupied by the drive output circuit extending along the second direction;

[0044] The noise reduction transistor of the first driver output sub-circuit and the noise reduction transistor of the second driver output sub-circuit are located on a side of the output device of the first driver output sub-circuit close to the first center line, and the noise reduction transistor of the second driver output sub-circuit is located on a side of the noise reduction transistor of the first driver output sub-circuit close to the first center line. The noise reduction transistor of the third driver output sub-circuit and the noise reduction transistor of the fourth driver output sub-circuit are located on a side of the output device of the third driver output sub-circuit close to the first center line, and the noise reduction transistor of the third driver output sub-circuit is located on a side of the noise reduction transistor of the fourth driver output sub-circuit close to the first center line. Another output capacitor of the fourth driver output sub-circuit is located on a side of the output device of the fourth driver output sub-circuit close to the first center line.

[0045] The noise reduction transistor of the first driver output sub-circuit and the noise reduction transistor of the fourth driver output sub-circuit are symmetrically arranged relative to the first center line, and the noise reduction transistor of the second driver output sub-circuit and the noise reduction transistor of the third driver output sub-circuit are symmetrically arranged relative to the first center line.

[0046] In an exemplary embodiment, the region where the driving output circuit is located is divided into a first region and a second region by the second center line;

[0047] The output device of the first driver output sub-circuit, the output device of the fourth driver output sub-circuit, and another output capacitor are located in a first area, and the output device of the second driver output sub-circuit and the output device of the third driver output sub-circuit are located in a second area;

[0048] The noise reduction transistor of at least one of the first to fourth driver output sub-circuits is located in the first region and the second region, and the area of ​​the noise reduction transistor located in the first region is smaller than the area of ​​the noise reduction transistor located in the second region.

[0049] In an exemplary embodiment, an area of ​​the noise reduction transistor located in the second region is in a range of 1 to 3 times an area of ​​the noise reduction transistor located in the first region.

[0050] In an exemplary embodiment, the second region further includes: output connection lines, the output connection lines including: first to fourth output connection lines; the first driver output sub-circuit is connected to the first output connection line, the second driver output sub-circuit is connected to the second output connection line, the third driver output sub-circuit is connected to the third output connection line, and the fourth driver output sub-circuit is connected to the fourth output connection line;

[0051] The output connection line extends along a first direction, the first output connection line and the second output connection line are located between the output device of the first driver output sub-circuit and the noise reduction transistor of the first driver output sub-circuit, the third output connection line and the fourth output connection line are located between the output device of the fourth driver output sub-circuit and the noise reduction transistor of the fourth driver output sub-circuit, and another output capacitor of the fourth driver output sub-circuit and the noise reduction transistor are located on the same side of the third output connection line and the fourth output connection line;

[0052] The first output connection line and the second output connection line are located in the second conductive layer.

[0053] In an exemplary embodiment, at least one of the third and fourth output connection lines includes: a first output connection portion, a second output connection portion, and a third output connection portion; the first output connection portion, the second output connection portion, and the third output connection portion extend along a first direction, and the second output connection portion is electrically connected to the first and third output connection portions, respectively;

[0054] The first output connection portion and the third output connection portion are located in the second conductive layer, and the second output connection portion is located in the first conductive layer.

[0055] In an exemplary embodiment, the first area is provided with at least one first signal line and at least one second signal line, the pixel driving circuit is electrically connected to the first signal line and the second signal line, respectively, the first signal line at least partially extends along the first direction, and the second signal line at least partially extends along the second direction;

[0056] The first signal line at least includes: a scan signal line, the second signal line at least includes: a first power line, a sensing signal line and a data signal line, and at least one driving output sub-circuit in the shift register is electrically connected to at least one first signal line;

[0057] The first signal line is located in a first conductive layer, and the second signal line is located in a second conductive layer.

[0058] In an exemplary embodiment, the at least one scan signal line includes: a plurality of signal connection lines and a plurality of signal overlapping lines; the plurality of signal connection lines and the plurality of signal overlapping lines are alternately arranged along the first direction;

[0059] The signal connection lines are arranged along a first direction, and the orthographic projection of the signal overlapping line on the substrate overlaps with the orthographic projection of at least one second signal line on the substrate by at least a line point;

[0060] The line width of the signal connection line of the scanning signal line connected to at least one driving output sub-circuit from the first driving output sub-circuit to the N-1th driving output sub-circuit in at least one stage of the shift register is smaller than the line width of the signal connection line of the scanning signal line connected to the Nth driving output sub-circuit.

[0061] In an exemplary embodiment, for at least one stage of shift register, a line width of a signal connection line of a scanning signal line connected to the Nth driving output sub-circuit is in a range of 1.5 times to 2 times a line width of a signal connection line of a scanning signal line connected to at least one driving output sub-circuit from the first driving output sub-circuit to the N-1th driving output sub-circuit.

[0062] In an exemplary embodiment, for at least one stage of the shift register, the signal overlapping lines of the scanning signal lines connected from the first driving output sub-circuit to the Nth driving output sub-circuit are in a ring structure;

[0063] For at least one scanning signal line, the length of the signal overlapping line along the first direction is greater than the line width of at least one second signal line, and the length of the signal overlapping line along the second direction is greater than the line width of the signal connection line.

[0064] In an exemplary embodiment, for at least one stage of the shift register, a signal overlap line of a scanning signal line connected to at least one of the first driving output sub-circuit to the N-1th driving output sub-circuit is a ring structure;

[0065] For the scan signal lines connected to the first drive output sub-circuit to the N-1th drive output sub-circuit, the length of the signal overlapping line along the first direction is greater than the line width of at least one second signal line, and the length of the signal overlapping line along the second direction is greater than the line width of the signal connection line;

[0066] The signal overlapping lines of the scanning signal lines connected to the Nth driving output sub-circuit extend along a first direction, and at least one boundary is arc-shaped. The average line width of the signal overlapping lines of the scanning signal lines connected to the Nth driving output sub-circuit is smaller than the line width of the signal connection lines of the scanning signal lines connected to the Nth driving output sub-circuit.

[0067] In a second aspect, the present disclosure further provides a display substrate, comprising: a first area and a second area, wherein the first area is provided with an array-arranged pixel driving circuit, and the second area is provided with a gate driving circuit, wherein the gate driving circuit is configured to provide a driving signal to the pixel driving circuit, and the gate driving circuit comprises: a plurality of shift registers, wherein at least one shift register comprises: a preamplifier circuit and a driving output circuit, wherein the preamplifier circuit is electrically connected to a signal input terminal, a reset signal terminal, and a cascade output signal terminal, respectively; the driving output circuit is electrically connected to N output clock signal terminals, respectively; the signal input terminal of the at least one shift register is electrically connected to the cascade output signal terminal of the at least one shift register, and the reset signal terminal of the at least one shift register is electrically connected to the cascade output signal terminal of the at least one shift register.

[0068] The drive output circuit includes: N drive output sub-circuits, the nth drive output sub-circuit being electrically connected to the nth output clock signal terminal;

[0069] The second region is provided with M*N output clock signal lines, at least one output clock signal line extends at least partially along the second direction and is located on a side of the driver output circuit away from the first region, and the first output clock signal terminal to the Nth output clock signal terminal of the at least one stage shift register are electrically connected to the N output clock signal lines respectively, where M≥2;

[0070] For at least one stage of shift register, the line width of the output clock signal line connected to the Nth output clock signal terminal is greater than the line width of the output clock signal line connected to at least one output clock signal terminal from the first output clock signal terminal to the N-1th output clock signal terminal.

[0071] In an exemplary embodiment, the invention further includes: a substrate and a driving structure layer disposed on the substrate, wherein the gate driving circuit and the pixel driving circuit are located in the driving structure layer, and the driving structure layer includes: a semiconductor layer, a first conductive layer, and a second conductive layer sequentially stacked on the substrate;

[0072] The output clock signal line is located in the second conductive layer.

[0073] In an exemplary embodiment, the nth output clock signal terminal of the at least one stage shift register is electrically connected to one of the nth output clock signal line, the N+nth output clock signal line, and the (M-1)*N+nth output clock signal line;

[0074] The n-th output clock signal terminals of adjacent M-stage shift registers are connected to different output clock signal lines.

[0075] In an exemplary embodiment, at least one output clock signal line is provided with a via;

[0076] The length of a via in an output clock signal line connected to at least one of the first output clock signal terminal to the N-1th output clock signal terminal of the at least one stage of the shift register along the first direction is shorter than the length of a via in an output clock signal line connected to the Nth output clock signal terminal of the at least one stage of the shift register along the first direction;

[0077] A via-related distance of an output clock signal line connected to at least one of the first output clock signal terminal and the N-1th output clock signal terminal of the at least one shift register is equal to a via-related distance of an output clock signal line connected to the Nth output clock signal terminal of the at least one shift register, wherein the via-related distance is a distance between a boundary of the output clock signal line and a boundary of the via of the output clock signal line.

[0078] In an exemplary embodiment, the second region further includes: a plurality of clock connection lines, the clock connection lines including: a first clock connection line to an Nth clock connection line, the clock connection lines being located in the first conductive layer;

[0079] At least one shift register is electrically connected to the nth output clock signal line through the nth clock connection line, and the orthographic projection of at least one clock connection line on the substrate at least partially overlaps with the orthographic projection of the via hole of at least one output clock signal line on the substrate.

[0080] In an exemplary embodiment, the second region further includes: a data unit, the data unit being electrically connected to output clock signal lines connected to N driver output sub-circuits of at least one stage of the shift register, and configured to provide a first clock signal to the output clock signal lines connected to the second to N-1 driver output sub-circuits of the at least one stage of the shift register, and to provide a second clock signal to the output clock signal line connected to the N-th driver output sub-circuit, wherein the first clock signal includes a first rising edge and a first falling edge, and the second clock signal includes a second rising edge, a third rising edge, and a second falling edge;

[0081] During a time period where the first rising edge is located, the voltage of the first clock signal rises from the second voltage to the first voltage; and during a time period where the first falling edge is located, the voltage of the first clock signal falls from the first voltage to the second voltage.

[0082] During the time period of the second rising edge, the voltage of the second clock signal rises from the third voltage to the second voltage; during the time period of the third rising edge, the voltage of the second clock signal rises from the second voltage to the first voltage; and during the time period of the second falling edge, the voltage of the second clock signal falls from the first voltage to the third voltage.

[0083] The first voltage is a positive voltage, the second voltage and the third voltage are negative voltages, and an absolute value of the second voltage is smaller than an absolute value of the third voltage.

[0084] In an exemplary embodiment, the data unit is further configured to provide a third clock signal to an output clock signal line connected to a first driver output sub-circuit of at least one stage of the shift register, the third clock signal including: a fourth rising edge, a third falling edge, and a fourth falling edge;

[0085] During the time period of the fourth rising edge, the voltage of the third clock signal rises from the second voltage to the fourth voltage; during the time period of the third falling edge, the voltage of the third clock signal drops from the fourth voltage to the first voltage; and during the time period of the fourth falling edge, the voltage of the third clock signal drops from the first voltage to the second voltage.

[0086] The first voltage and the fourth voltage are positive voltages, the second voltage is a negative voltage, and the fourth voltage is greater than the first voltage.

[0087] In an exemplary embodiment, the second region further includes: a data unit, the data unit being electrically connected to output clock signal lines connected to N driver output sub-circuits of at least one stage of the shift register, and configured to provide a fourth clock signal to the output clock signal lines connected to the second to N-1th driver output sub-circuits of the at least one stage of the shift register, and to provide a fifth clock signal to the output clock signal line connected to the Nth driver output sub-circuit;

[0088] The duration of the time period in which the falling edge of the fifth clock signal is located is less than half the duration of the time period in which the falling edge of the fourth clock signal is located.

[0089] In an exemplary embodiment, the data unit is further configured to provide a sixth clock signal to an output clock signal line connected to a first driver output sub-circuit of at least one stage of the shift register;

[0090] The duration of the time period in which the rising edge of the sixth clock signal is located is less than half the duration of the time period in which the rising edge of the fourth clock signal is located.

[0091] In a third aspect, the present disclosure further provides a display device, comprising: the above-mentioned display substrate.

[0092] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0093] Summary of the Figures

[0094] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0095] FIG1 is a schematic structural diagram of a display device;

[0096] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0097] FIG3 is a schematic diagram of a planar structure of another display substrate;

[0098] FIG4 is a schematic diagram of a planar structure of another display substrate;

[0099] FIG5 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0100] FIG6 is a schematic structural diagram of a shift register;

[0101] FIG7 is an equivalent circuit diagram of a shift register;

[0102] FIG8 is a timing diagram of the operation of the shift register provided in FIG7 ;

[0103] FIG9 is a first structural diagram of a drive output circuit provided in an embodiment of the present disclosure;

[0104] FIG10 is a second structural diagram of a drive output circuit provided in an embodiment of the present disclosure;

[0105] FIG11 is a schematic diagram of part of the film layer in FIG10;

[0106] FIG12 is a schematic diagram showing a partial structure of the first region of the display substrate;

[0107] FIG13 is a second schematic diagram showing a partial structure of the first region of the display substrate;

[0108] FIG14 is a schematic diagram of a portion of a second area of ​​a display device;

[0109] FIG15 is a signal diagram of a first clock signal;

[0110] FIG16 is a signal diagram of a second clock signal;

[0111] FIG17 is a signal diagram of a third clock signal;

[0112] FIG18 is a schematic diagram of the semiconductor layer pattern in FIG9 ;

[0113] FIG19 is a schematic diagram of a semiconductor layer pattern in FIG10 ;

[0114] FIG20 is a schematic diagram of the first conductive layer pattern in FIG9 ;

[0115] FIG21 is a schematic diagram of FIG9 after forming a first conductive layer pattern;

[0116] FIG22 is a schematic diagram of the first conductive layer pattern in FIG10 ;

[0117] FIG23 is a schematic diagram of FIG10 after forming a first conductive layer pattern;

[0118] FIG24 is a schematic diagram of FIG9 after forming a second insulating layer;

[0119] FIG25 is a schematic diagram of FIG10 after forming a second insulating layer;

[0120] FIG26 is a schematic diagram of the second conductive layer pattern in FIG9 ;

[0121] FIG27 is a schematic diagram of FIG9 after forming a second conductive layer pattern;

[0122] FIG28 is a schematic diagram of the second conductive layer pattern in FIG10 ;

[0123] FIG. 29 is a schematic diagram of FIG. 10 after forming a second conductive layer pattern.

[0124] Details

[0125] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0126] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0127] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0128] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0129] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0130] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0131] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0132] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0133] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0134] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0135] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0136] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0137] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0138] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include: a timing controller (not shown in the figure) located in the non-display area 1, a data driving circuit 30 and a gate driving circuit 20, and the display device also includes: a display substrate 40. The timing controller is connected to the data driving circuit 30 and the gate driving circuit 20, respectively. The data driving circuit 30 is connected to a plurality of data signal lines DL, respectively. The gate driving circuit 20 is connected to a plurality of scan signal lines GL, respectively. The display substrate may include: a pixel array. The pixel array may include a plurality of sub-pixels 410. At least one sub-pixel 410 may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit. The pixel driving circuit may be connected to the scan signal line and the data signal line, respectively.

[0139] In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals suitable for the specifications of the data driving circuit 30 to the data driving circuit 30, and can provide clock signals, scan start signals, etc. suitable for the specifications of the gate driving circuit 20 to the gate driving circuit 20.

[0140] In an exemplary embodiment, the data drive circuit 30 may generate a data voltage to be provided to the data signal line DL using a grayscale value and a control signal received from a timing controller. For example, the data drive circuit 30 may sample the grayscale value using a clock signal and apply a data voltage corresponding to the grayscale value to the data signal line D on a pixel row basis. The gate drive circuit 20 may generate a scan signal to be provided to the scan signal line GL by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the gate drive circuit 20 may sequentially provide a scan signal having an on-level pulse to the scan signal line GL. For example, the gate drive circuit 20 may be configured in the form of a shift register and may generate a scan signal by sequentially transmitting a scan start signal provided in the form of an on-level pulse to the next stage circuit under the control of a clock signal.

[0141] Figure 2 is a schematic diagram of the planar structure of a display substrate, Figure 3 is a schematic diagram of the planar structure of another display substrate, and Figure 4 is a schematic diagram of the planar structure of yet another display substrate. As shown in Figures 2 to 4, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first subpixel P1 that emits a first color light, a second subpixel P2 that emits a second color light, and a third subpixel P3 that emits a third color light. The first subpixel P1, the second subpixel P2, and the third subpixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to a scan signal line and a data signal line. The pixel driving circuits are configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the light-emitting device. The light-emitting devices in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to the pixel driving circuit of the subpixel in which they are located. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the subpixel in which they are located.

[0142] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) emitting red light, the second subpixel P2 may be a blue subpixel (B) emitting blue light, and the third subpixel P3 may be a green subpixel (G) emitting green light.

[0143] In exemplary embodiments, the shape of the sub-pixels may be rectangular, diamond, pentagonal, or hexagonal.

[0144] In an exemplary embodiment, a pixel unit may include three sub-pixels, which may be arranged horizontally, vertically, or in a herringbone pattern, without limitation in this disclosure. FIG2 illustrates an example of a pixel unit in which three sub-pixels are arranged horizontally. FIG3 illustrates an example of a pixel unit in which three sub-pixels are arranged in a herringbone pattern.

[0145] In other exemplary embodiments, a pixel unit may include four sub-pixels, which may be arranged horizontally, vertically, or in a square pattern, etc., which is not limited in this disclosure. FIG4 illustrates an example in which four sub-pixels in a pixel unit are arranged in a square pattern to form a GGRB pixel arrangement.

[0146] In example embodiments, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure.

[0147] Figure 5 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in Figure 5, the pixel driving circuit has a 3T1C structure and can include three transistors (a switching transistor QTFT, a sensing transistor STFT, and a driving transistor DTFT), a capacitor C, and six signal lines (a data signal line Data, a first scanning signal line G1, a second scanning signal line G2, a sensing signal line Sense, a first power line VDD, and a second power line VSS).

[0148] In an exemplary embodiment, the gate electrode of the switching transistor QTFT is coupled to the first scanning signal line G1, the first electrode of the switching transistor QTFT is coupled to the data signal line Data, and the second electrode of the switching transistor QTFT is coupled to the gate electrode of the driving transistor DTFT. The switching transistor QTFT is used to receive the data signal transmitted by the data signal line Data under the control of the first scanning signal line G1, so that the gate electrode of the driving transistor DTFT receives the data signal.

[0149] In an exemplary embodiment, the gate electrode of the driving transistor DTFT is coupled to the second electrode of the switching transistor QTFT, the first electrode of the driving transistor DTFT is coupled to the first power line VDD, the second electrode of the driving transistor DTFT is coupled to the first electrode of the light-emitting device L, and the driving transistor DTFT is used to generate a corresponding driving current at the second electrode under the control of the data signal received by its gate electrode.

[0150] In an exemplary embodiment, the gate electrode of the sensing transistor STFT is coupled to the second scanning signal line G2, the first electrode of the sensing transistor STFT is coupled to the sensing signal line Sense, the second electrode of the sensing transistor STFT is coupled to the second electrode of the driving transistor DTFT, and the sensing transistor STFT is used to extract the threshold voltage Vth and mobility of the driving transistor DTFT in response to the sensing timing to compensate for the threshold voltage Vth.

[0151] In an exemplary embodiment, the first electrode of the light-emitting device L is coupled to the second electrode of the driving transistor DTFT, the second electrode of the light-emitting device is coupled to the second power line VSS, and the light-emitting device L is configured to emit light of corresponding brightness in response to the driving current of the second electrode of the driving transistor DTFT.

[0152] In an exemplary embodiment, a first electrode of the capacitor C is coupled to the gate electrode of the driving transistor DTFT, a second electrode of the capacitor C is coupled to the second electrode of the sensing transistor STFT, and the capacitor C is used to store the potential of the gate electrode of the driving transistor DTFT.

[0153] In an exemplary embodiment, the operation process of the pixel driving circuit includes: when the signal of the first scanning signal line G1 is a valid level signal, the switching transistor QTFT is turned on, and the data voltage Vdata provided by the data signal line Data is stored in the capacitor C via the switching transistor QTFT, thereby controlling the driving transistor T2 to generate a driving current to drive the light-emitting device L to emit light. In addition, when the signal of the second scanning signal line G2 is a valid level signal, the sensing transistor STFT is turned on, and the sensing transistor STFT responds to the sensing timing to extract the threshold voltage Vth and mobility of the driving transistor DTFT.

[0154] In some exemplary embodiments, the switching transistor QTFT, the sensing transistor STFT, and the driving transistor DTFT may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the difficulty of the display substrate process, and improve the product yield. In some possible implementations, the switching transistor QTFT, the sensing transistor STFT, and the driving transistor DTFT may include P-type transistors and N-type transistors.

[0155] In an exemplary embodiment, the first scan signal line G1 and the second scan signal line G2 may be the same signal line. That is, the pixel driving circuit can simultaneously drive the light-emitting device L to emit light while also extracting the threshold voltage Vth and mobility of the driving transistor DTFT. The display substrate can externally compensate the pixel driving circuit based on the threshold voltage Vth and mobility of the driving transistor DTFT.

[0156] In an exemplary embodiment, the first scan signal line G1 and the second scan signal line G2 may extend along a first direction, while the data signal line Data, the first power line VDD, and the sense signal line Sense extend along a second direction. The first direction intersects the second direction. Exemplarily, the angle between the first direction and the second direction is approximately 70 to 90 degrees. The first direction and the second direction may lie in the same plane. For example, the first direction may be a row direction, and the second direction may be a column direction.

[0157] In an exemplary embodiment, the light-emitting device may include any one of an organic light-emitting diode (OLED), a quantum dot light-emitting diode, and an inorganic light-emitting diode. For example, the light-emitting device L may be a micron-sized light-emitting device, such as a micro light-emitting diode (Micro LED), a sub-millimeter light-emitting diode (Mini LED), or a micro organic light-emitting diode (Micro OLED), etc., and the present disclosure is not limited to this. For example, taking the light-emitting device L as an organic light-emitting diode (OLED) as an example, the light-emitting device may include: a stacked first electrode (e.g., as an anode), an organic light-emitting layer, and a second electrode (e.g., as a cathode).

[0158] In an exemplary embodiment, the organic light-emitting layer may include an emissive layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be a common layer connected together, and the emissive layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0159] In an exemplary embodiment, the gate drive circuit is electrically connected to a plurality of first signal lines and is configured to provide drive signals to the first signal lines. The first signal lines include scan signal lines. The scan signal lines may be at least one of first scan signal lines and second scan signal lines.

[0160] In an exemplary embodiment, the gate drive circuit includes a plurality of cascaded shift registers. At least one shift register stage can be electrically connected to at least one first signal line. FIG6 is a schematic diagram of the shift register structure. As shown in FIG6, at least one shift register stage can include a preamplifier circuit and N drive output sub-circuits. FIG6 is illustrative using N=4 as an example.

[0161] In an exemplary embodiment, as shown in FIG6 , the front-end circuit is electrically connected to the first signal input terminal INPUT1, the second signal input terminal INPUT2, the detection input terminal OE, the first clock signal terminal CKA, the second clock signal terminal CKD, the reset signal terminal RST, the total reset signal terminal TRST, the DC high-level power supply terminal VDD1, the AC high-level power supply terminal VDD2, the first low-level power supply terminal VGL1, the cascade signal input terminal CR, the pull-up node PU, and the pull-down node PD, and is configured to be connected to the first signal input terminal INPUT2, the detection input terminal OE, the first clock signal terminal C Under the control of the signals of KA, the first signal input terminal INPUT1, the reset signal terminal RST and the total reset signal terminal TRST, the signal of the first clock signal terminal CKA, the DC high-level power supply terminal VDD1 or the first low-level power supply terminal VGL1 is provided to the pull-up node PU; under the control of the signal of the AC high-level power supply terminal VDD2 and the pull-up node PU, the signal of the AC high-level power supply terminal VDD2 or the first low-level power supply terminal VGL1 is provided to the pull-down node PD; under the control of the signal of the pull-up node PU, the signal of the second clock power supply terminal CKD is provided to the cascade signal input terminal CR.

[0162] In an exemplary embodiment, the nth driver output sub-circuit is electrically connected to the pull-up node PU, the pull-down node PD, the nth output clock signal terminal CKEn, the nth driver output signal terminal OUTn, and the second low-level power supply terminal VGL2, respectively, and is configured to provide the signal of the nth output clock signal terminal CKEn to the nth driver output signal terminal OUTn under the control of the signal of the pull-up node PU, or to provide the signal of the second low-level power supply terminal VGL2 to the nth driver output signal terminal OUTn under the control of the signal of the pull-down node PD.

[0163] In an exemplary embodiment, at least one shift register stage is electrically connected to at least one first signal line. Any of the first drive signal output terminals OUT1 through the Nth drive signal output terminal OUTN in the at least one shift register stage is electrically connected to the at least one first signal line. Specifically, the nth drive signal output terminal OUTn in the at least one shift register stage is electrically connected to the at least one first signal line connected to the at least one shift register stage. In other words, the present disclosure implements driving of multiple rows of sub-pixels by a shift register by providing multiple drive output sub-circuits.

[0164] Figure 7 is an equivalent circuit diagram of a shift register. As shown in Figure 7, the preamp circuit includes a first pull-up sub-circuit, which is configured to provide a signal from the first clock signal terminal CKA to a pull-up node PU under the control of signals from the detection signal terminal OE, the second signal input terminal INPUT2, and the first clock signal terminal CKA. Exemplarily, the first pull-up sub-circuit may include first through third transistors M1, M3, and a first capacitor C1. Among them, the gate electrode of the first transistor M1 is electrically connected to the detection signal terminal OE, the first electrode of the first transistor M1 is electrically connected to the second signal input terminal INPUT2, the second electrode of the first transistor M1 is electrically connected to the first node H, the gate electrode of the second transistor M2 is electrically connected to the first node H, the first electrode of the second transistor M2 is electrically connected to the first clock signal terminal CKA, the second electrode of the second transistor M2 is electrically connected to the second node N, the gate electrode of the third transistor M3 is electrically connected to the first clock signal terminal CKA, the first electrode of the third transistor M3 is electrically connected to the second node N, the second electrode of the third transistor M3 is electrically connected to the pull-up node PU, the first end of the first capacitor C1 is electrically connected to the first low-level power supply terminal VGL1, and the second end of the first capacitor C1 is electrically connected to the first node H.

[0165] In an exemplary embodiment, the first pull-up sub-circuit may pull up the potential of the signal of the pull-up node PU during the sensing phase.

[0166] In an exemplary embodiment, as shown in FIG7 , the front-end circuit may further include a second pull-up sub-circuit configured to provide a signal from the DC high-level signal terminal VDD1 to the pull-up node PU under control of a signal from the first signal input terminal INPUT1. Exemplarily, the second pull-up sub-circuit may include a fourth transistor M4. A gate electrode of the fourth transistor M4 is electrically connected to the first signal input terminal INPUT1, a first electrode of the fourth transistor M4 is electrically connected to the DC high-level signal terminal VDD1, and a second electrode of the fourth transistor M4 is electrically connected to the pull-up node PU.

[0167] In an exemplary embodiment, the second pull-up sub-circuit may pull up the potential of the signal of the pull-up node PU in the display phase.

[0168] In an exemplary embodiment, as shown in FIG7 , the front-end circuit may further include: a cascade output subcircuit. The cascade output subcircuit is configured to provide a signal of the second clock signal terminal CKD to the cascade signal output terminal CR under the control of the signal of the pull-up node PU. Exemplarily, the cascade output subcircuit may include: a fifth transistor M5 and a second capacitor C2. The gate electrode of the fifth transistor M5 is electrically connected to the pull-up node PU, the first electrode of the fifth transistor M5 is electrically connected to the second clock signal terminal CKD, the second electrode of the fifth transistor M5 is electrically connected to the cascade signal output terminal CR, the first end of the second capacitor C2 is electrically connected to the pull-up node PU, and the second end of the second capacitor C2 is electrically connected to the cascade signal output terminal CR.

[0169] In an exemplary embodiment, the cascade output sub-circuit may provide a cascade signal to the first signal input terminal INPUT1 of the next stage shift register.

[0170] In an exemplary embodiment, as shown in FIG7 , the front-end circuit may further include a noise reduction sub-circuit. The noise reduction sub-circuit is configured to provide a signal from the AC high-level power supply terminal VDD2 to the pull-down node PD under control of a signal from the AC high-level power supply terminal VDD2, and to provide a signal from the first low-level power supply terminal VGL1 to the pull-up node PU and the cascade output signal terminal CR under control of a signal from the pull-down node PD. Exemplarily, the noise reduction sub-circuit may include sixth through ninth transistors M6 through M9. Among them, the gate electrode and the first electrode of the sixth transistor M6 are electrically connected to the AC high-level power supply terminal VDD2, the second electrode of the sixth transistor M6 is electrically connected to the pull-down node PD, the gate electrode of the seventh transistor M7 is electrically connected to the pull-up node PU, the first electrode of the seventh transistor M7 is electrically connected to the first low-level power supply terminal VGL1, the second electrode of the seventh transistor M7 is electrically connected to the pull-down node PD, the gate electrode of the eighth transistor M8 is electrically connected to the pull-down node PD, the first electrode of the eighth transistor M8 is electrically connected to the pull-up node PU, the second electrode of the eighth transistor M8 is electrically connected to the first low-level power supply terminal VGL1, the gate electrode of the ninth transistor M9 is electrically connected to the pull-down node PD, the first electrode of the ninth transistor M9 is electrically connected to the cascade signal output terminal CR, and the second electrode of the ninth transistor M9 is electrically connected to the first low-level power supply terminal VGL1.

[0171] In an exemplary embodiment, the noise reduction sub-circuit can reduce the noise of the shift register after the shift register outputs, thereby improving the reliability of the shift register.

[0172] In an exemplary embodiment, as shown in FIG7 , the preamplifier circuit may further include a reset subcircuit. The reset subcircuit is configured to provide a signal from the first low-level power supply terminal VGL1 to the pull-up node PU under the control of signals from the reset signal terminal RST and the total reset signal terminal TRST. Exemplarily, the reset subcircuit may include a tenth transistor M10 and an eleventh transistor M11. The gate electrode of the tenth transistor M10 is electrically connected to the reset signal terminal RST, the first electrode of the tenth transistor M10 is electrically connected to the first low-level power supply terminal VGL1, the second electrode of the tenth transistor M10 is electrically connected to the pull-up node PU, the gate electrode of the eleventh transistor M11 is electrically connected to the total reset signal terminal TRST, the first electrode of the eleventh transistor M11 is electrically connected to the first low-level power supply terminal VGL1, and the second electrode of the eleventh transistor M11 is electrically connected to the pull-up node PU.

[0173] In an exemplary embodiment, as shown in FIG7 , the first driver output sub-circuit may include: a first output transistor M51, a first noise reduction transistor M61, and a first output capacitor OC1. The gate electrode of the first output transistor M51 is electrically connected to the pull-up node PU, the first electrode of the first output transistor M51 is electrically connected to the first output clock signal terminal CKE1, the second electrode of the first output transistor M51 is electrically connected to the first driver output signal terminal OUT1, the gate electrode of the first noise reduction transistor M61 is electrically connected to the pull-down node PD, the first electrode of the first noise reduction transistor M61 is electrically connected to the second low-level power supply terminal VGL2, the second electrode of the first noise reduction transistor M61 is electrically connected to the first driver output signal terminal OUT1, the first plate OC1-1 of the first output capacitor OC1 is electrically connected to the first driver output signal terminal OUT1, and the second plate OC1-2 of the first output capacitor C1 is electrically connected to the pull-up node PU.

[0174] In an exemplary embodiment, as shown in FIG7 , the second driver output sub-circuit may include: a second output transistor M52, a second noise reduction transistor M62, and a second output capacitor OC2. The gate electrode of the second output transistor M52 is electrically connected to the pull-up node PU, the first electrode of the second output transistor M52 is electrically connected to the second output clock signal terminal CKE2, the second electrode of the second output transistor M52 is electrically connected to the second driver output signal terminal OUT2, the gate electrode of the second noise reduction transistor M62 is electrically connected to the pull-down node PD, the first electrode of the second noise reduction transistor M62 is electrically connected to the second low-level power supply terminal VGL2, the second electrode of the second noise reduction transistor M62 is electrically connected to the second driver output signal terminal OUT2, the first plate OC2-1 of the second output capacitor OC2 is electrically connected to the second driver output signal terminal OUT2, and the second plate OC2-2 of the second output capacitor C2 is electrically connected to the pull-up node PU.

[0175] In an exemplary embodiment, as shown in FIG7 , the third driver output sub-circuit may include: a third output transistor M53, a third noise reduction transistor M63, and a third output capacitor OC3. The gate electrode of the third output transistor M53 is electrically connected to the pull-up node PU, the first electrode of the third output transistor M53 is electrically connected to the third output clock signal terminal CKE3, the second electrode of the third output transistor M53 is electrically connected to the third driver output signal terminal OUT3, the gate electrode of the third noise reduction transistor M63 is electrically connected to the pull-down node PD, the first electrode of the third noise reduction transistor M63 is electrically connected to the second low-level power supply terminal VGL2, the first electrode of the third noise reduction transistor M63 is electrically connected to the third driver output signal terminal OUT3, the first plate OC3-1 of the third output capacitor OC3 is electrically connected to the third driver output signal terminal OUT3, and the second plate OC3-2 of the third output capacitor C3 is electrically connected to the pull-up node PU.

[0176] In an exemplary embodiment, as shown in FIG7 , the fourth driver output sub-circuit may include: a fourth output transistor M54, a fourth noise reduction transistor M64, and a fourth output capacitor OC4. The gate electrode of the fourth output transistor M54 is electrically connected to the pull-up node PU, the first electrode of the fourth output transistor M54 is electrically connected to the fourth output clock signal terminal CKE4, the second electrode of the fourth output transistor M54 is electrically connected to the fourth driver output signal terminal OUT4, the gate electrode of the fourth noise reduction transistor M64 is electrically connected to the pull-down node PD, the first electrode of the fourth noise reduction transistor M64 is electrically connected to the second low-level power supply terminal VGL2, the first electrode of the fourth noise reduction transistor M64 is electrically connected to the fourth driver output signal terminal OUT4, the first plate OC4-1 of the fourth output capacitor OC4 is electrically connected to the fourth driver output signal terminal OUT4, and the second plate OC4-2 of the fourth output capacitor C4 is electrically connected to the pull-up node PU.

[0177] In some exemplary embodiments, the first to eleventh transistors M1 to M11, the first to fourth output transistors M51 to M54, and the first to fourth noise reduction transistors M61 to M64 can be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the difficulty of manufacturing the display substrate, and improve the product yield. Figure 7 illustrates an example in which the first to eleventh transistors M1 to M11, the first to fourth output transistors M51 to M54, and the first to fourth noise reduction transistors M61 to M64 are all N-type transistors.

[0178] In an exemplary embodiment, the signal at any one of the first clock signal terminal CKA, the second clock signal terminal CKD, and the first output clock signal terminal CKE1 through the fourth output clock signal terminal CKE4 is a square wave signal that repeats high and low voltages. For example, the second clock signal terminal CKD and the first output clock signal terminal CKE1 through the fourth output clock signal terminal CKE4 may have the same period and may be configured as phase-shifted signals. Here, the signal at the second clock signal terminal CKE2 may be phase-shifted by half a period compared to the signal at the first clock signal terminal CKE1. The signal at the third clock signal terminal CKE3 may be phase-shifted by half a period compared to the signal at the second clock signal terminal CKE2. The signal at the fourth clock signal terminal CKE4 may be phase-shifted by half a period compared to the signal at the third clock signal terminal CKE3. The high voltage period in each period of the signal at at least one of the first output clock signal terminal CKE1 through the fourth output clock signal terminal CKE4 may be set to be longer than the low voltage period.

[0179] In an exemplary embodiment, the signal of the first low-level power supply terminal VGL1 is a DC signal and is continuously a low-level signal.

[0180] In an exemplary embodiment, the signal of the second low-level power supply terminal VGL2 is a DC signal and is continuously a low-level signal. The absolute value of the voltage of the signal of the second low-level power supply terminal VGL2 is greater than the absolute value of the voltage of the signal of the first low-level power supply terminal VGL1.

[0181] In an exemplary embodiment, the signal of the DC high-level power supply terminal VDD1 is a DC signal and is continuously a high-level signal.

[0182] In an exemplary embodiment, the signal of the AC high-level power supply terminal VDD2 is an AC signal, and the signal is a high-level signal in a partial time period and a low-level signal in a partial time period.

[0183] In an exemplary embodiment, the first capacitor C1, the second capacitor C2, and any of the capacitors in all the driver output subcircuits can be capacitor devices manufactured by a process. For example, the capacitor device can be realized by making a special capacitor electrode, and the multiple capacitor electrodes of the capacitor can be realized by a metal layer, a semiconductor layer (such as doped polysilicon), etc. Alternatively, the first capacitor C1, the second capacitor C2, and any of the capacitors in all the driver output subcircuits can be parasitic capacitances between multiple devices, and can be realized by the transistor itself and other devices and circuits. The connection method of the first capacitor C1, the second capacitor C2, and any of the capacitors in all the driver output subcircuits includes but is not limited to the method described above, and can be other applicable connection methods, and the level of the corresponding node can be stored. Here, the exemplary embodiment of the present disclosure is not limited to this.

[0184] In an exemplary embodiment, the shift register's operating process includes: a display phase and a sensing phase. During the display phase, the second pull-up sub-circuit provides a signal to the pull-up node PU, and during the sensing phase, the first pull-up sub-circuit provides a signal to the pull-up node PU. FIG8 is an operating timing diagram of the shift register provided in FIG7 . As shown in FIG8 , the shift register's operating process during the display phase may include:

[0185] In the first phase S1, the input phase, the signal at the first signal input terminal INPUT1 is a high-level signal, and the signals at the second clock signal terminal CKD and the first to fourth output clock signal terminals CKE1 to CKE4 are low-level signals. The signal at the first signal input terminal INPUT1 is a high-level signal, the fourth transistor M4 is turned on, the signal at the DC high-level power supply terminal VDD1 is written to the pull-up node PU, and the signal at the pull-up node PU is a high-level signal. The fifth transistor M5 and the first to fourth drive output transistors M51 to M54 are turned on, and the signals at the second clock signal terminal CKD and the first to fourth output clock signal terminals CKE1 to CKE4 are written to the cascade signal output terminal CR and the first to fourth drive signal output terminals OUT1 to OUT4, respectively. The cascade signal output terminal CR and the first to fourth drive signal output terminals OUT1 to OUT4 do not output.

[0186] In the second stage S2, the first output stage, the signal at the first output clock signal terminal CKE1 is a high-level signal, and the signals at the second output clock signal terminals CKE2 to the fourth output clock signal terminals CKE4 are low-level signals. The signal at the pull-up node PU remains high-level due to the action of the second capacitor C2 and the first output capacitors OC1 to the fourth output capacitors OC4. The first drive output transistors M51 to the fourth drive output transistors M54 are turned on, and the high-level signal at the first output clock signal terminal CKE1 is written to the first drive signal output terminal OUT1. In this stage, the first drive signal output terminal OUT1 outputs a drive signal.

[0187] In the third stage S3, the second output stage, the signal at the second output clock signal terminal CKE2 is a high-level signal, while the signals at the first output clock signal terminal CKE1, the third output clock signal terminal CKE3, and the fourth output clock signal terminal CKE4 are low-level signals. The signal at the pull-up node PU remains high-level due to the action of the second capacitor C2 and the first to fourth output capacitors OC1 to OC4. The first to fourth drive output transistors M51 to M54 are turned on, and the high-level signal at the second output clock signal terminal CKE2 is written to the second drive signal output terminal OUT2. In this stage, the second drive signal output terminal OUT2 outputs the drive signal.

[0188] In the fourth stage S4, the third output stage, the signal at the third output clock signal terminal CKE3 is a high-level signal, while the signals at the first output clock signal terminal CKE1, the second output clock signal terminal CKE2, and the fourth output clock signal terminal CKE4 are low-level signals. The signal at the pull-up node PU remains high-level due to the action of the second capacitor C2 and the first to fourth output capacitors OC1 to OC4. The first to fourth drive output transistors M51 to M54 are turned on, and the high-level signal at the third output clock signal terminal CKE3 is written to the third drive signal output terminal OUT3. In this stage, the third drive signal output terminal OUT3 outputs a drive signal.

[0189] In the fifth stage S5, the fourth output stage, the signal at the fourth output clock signal terminal CKE4 is a high-level signal, and the signals at the first output clock signal terminal CKE1 to the third output clock signal terminal CKE3 are low-level signals. The signal at the pull-up node PU remains high-level due to the action of the second capacitor C2 and the first output capacitor OC1 to the fourth output capacitor OC4. The first drive output transistor M51 to the fourth drive output transistor M54 are turned on, and the high-level signal at the fourth output clock signal terminal CKE4 is written to the fourth drive signal output terminal OUT4. In this stage, the fourth drive signal output terminal OUT4 outputs a drive signal.

[0190] In an exemplary embodiment, time periods of driving signals output by adjacent output stages overlap.

[0191] The time period from the second stage S2 to the fifth stage S5 may be referred to as a display driving pulse output period.

[0192] In an exemplary embodiment, the second clock signal terminal CKD may be a high-level signal in one of the second stage S2 to the fifth stage S5 , so that the cascade signal output terminal CR outputs the cascade signal.

[0193] In an exemplary embodiment, after the display drive pulse output period, the operation process of the shift register may further include a reset phase. During the reset phase, the signal at the reset signal terminal RST of at least one stage of the shift register is a high-level signal, the tenth transistor M10 is turned on, the signal at the pull-up node PU is pulled low by the signal at the first low-level power supply terminal VGL1, the fifth transistor M5 and the first to fourth output transistors M51 to M54 are turned off, and the signals at the first to fourth drive output signal terminals OUT1 to OUT4 are not affected by the signals at the first to fourth output clock signal terminals CKE1 to CKE4.

[0194] In an exemplary embodiment, after the display driving pulse output period, the operation process of the shift register may further include: a noise reduction stage. In the noise reduction stage, when the signal of the AC high-level power supply terminal VDD2 is a high-level signal, the sixth transistor M6 is turned on, the signal of the pull-down node PD is pulled high, the eighth transistor M8, the ninth transistor M9, and the first to fourth noise reduction transistors M61 to M62 are turned on, the signals of the pull-up node PU and the cascade output signal terminal CR are pulled low by the signal of the first low-level power supply terminal VGL1, and the signals of the first to fourth drive output signal terminals OUT1 to OUT4 are pulled low by the signal of the second low-level power supply terminal VGL2, thereby reducing the noise of the shift register.

[0195] In an exemplary embodiment, when the shift register is in the sensing phase, in the input phase, the signals of the detection signal terminal OE, the second signal input terminal INPUT2, and the first clock signal terminal CKA are high-level signals, the first transistor M3, the second transistor M2, and the third transistor M3 are turned on, and the signals of the first node H, the second node N, and the pull-up node PU are high-level signals.

[0196] As shown in Figure 8, when the first drive signal output terminal OUT1 of at least one stage of the shift register outputs a drive signal, that is, in the first output stage, the potential of the signal of the pull-up node PU rises from the second potential V2 to the third potential V3, and then rises from the third potential V3 to the fourth potential V4. Due to the continuous increase in the potential of the signal of the pull-up node PU, the drive signal output by the first drive signal output terminal OUT1 has a relatively obvious rising edge. This rising edge will affect the conduction time of some transistors (such as switching transistors or sensing transistors) in the pixel driving circuit, thereby affecting the display screen.

[0197] As shown in FIG8 , when the second drive signal output terminal OUT2 and the third drive signal output terminal OUT3 of at least one stage of the shift register output drive signals, that is, in the second output stage and the third output stage, the potential of the signal at the pull-up node PU remains substantially unchanged at the fourth potential V4. The reason why the potential of the signal at the pull-up node PU remains substantially unchanged at the fourth potential V4 in the second output stage is that when the second drive signal output terminal OUT2 outputs the drive signal, the potential of the signal at the pull-up node PU is pulled up by the drive signal output by the second drive signal output terminal OUT2 under the action of the second output capacitor OC2. However, at this time, the potential of the drive signal output by the first drive signal output terminal OUT1 begins to decrease. Under the action of the first output capacitor OC1, the potential of the signal at the pull-up node PU is pulled down by the drive signal output by the first drive signal output terminal OUT1. Therefore, the potential of the signal at the pull-up node PU remains unchanged in the second output stage under the action of the first output capacitor OC1 and the second output capacitor OC2. Similarly, the reason why the potential of the signal of the pull-up node PU remains basically unchanged at the level of the fourth potential V4 in the third output stage is that when the drive signal is output by the third drive signal output terminal OUT3, under the action of the third output capacitor OC3, the potential of the signal of the pull-up node PU will be pulled up by the drive signal output by the third drive signal output terminal OUT3. However, at this time, the potential of the drive signal output by the second drive signal output terminal OUT2 begins to decrease. Under the action of the second output capacitor OC2, the potential of the signal of the pull-up node PU will be pulled down by the drive signal output by the second drive signal output terminal OUT2. Therefore, the potential of the signal of the pull-up node PU remains unchanged in the third output stage under the action of the second output capacitor OC2 and the third output capacitor OC3.

[0198] As shown in FIG8 , when the fourth drive signal output terminal OUT4 of at least one shift register outputs a drive signal, that is, in the fourth output stage, the potential of the signal at the pull-up node PU decreases from the fourth potential V4 to the third potential V3. In the second half of the fourth output stage, the potential of the drive signal output by the fourth noise reduction transistor M54 begins to decrease. Under the action of the fourth output capacitor OC4, the potential of the signal at the pull-up node PU further decreases. Because no drive signal is output after the fourth drive signal output terminal OUT4 in at least one shift register unit, that is, there is no drive output sub-circuit that can increase the potential of the signal at the pull-up node PU, the potential of the pull-up node PU decreases from the fourth potential V4 to the third potential V3, and then from the third potential V3 to the second potential V2. Therefore, the drive signal output by the fourth drive signal output terminal OUT4 (also the drive signal output by the last drive signal output terminal in the shift register) has a longer falling edge. This longer falling edge affects the conduction duration of some transistors (e.g., switching transistors or sensing transistors) in the pixel driving circuit. To summarize, since the signal of the pull-up node in the shift register in the display substrate changes during the output stage, the drive signals provided by the shift register to the pixel drive circuits of different rows connected to it are also different. In particular, the brightness of the sub-pixel connected to the last drive output sub-circuit of the shift register is darker than the brightness of the sub-pixels connected to the remaining drive output sub-circuits, causing horizontal stripes to appear on the display substrate, resulting in uneven display of the display substrate and affecting the display effect of the display substrate.

[0199] FIG9 is a first structural diagram of a driving output circuit provided in an embodiment of the present disclosure, and FIG10 is a second structural diagram of a driving output circuit provided in an embodiment of the present disclosure. The display substrate provided in an embodiment of the present disclosure may include: a first area and a second area, the first area being provided with an array-arranged pixel driving circuit, the second area being provided with a gate driving circuit, the gate driving circuit being configured to provide a driving signal to the pixel driving circuit, the gate driving circuit including: a plurality of shift registers, at least one shift register including: a pre-circuit and a driving output circuit, the pre-circuit being electrically connected to a signal input terminal, a reset signal terminal and a cascade output signal terminal, respectively, the driving output circuit being electrically connected to N driving output signal terminals, the signal input terminal of at least one shift register being electrically connected to the cascade output signal terminal of at least one shift register, and the reset signal terminal of at least one shift register being electrically connected to the cascade output signal terminal of at least one shift register.

[0200] In an exemplary embodiment, the pixel driving circuit is the pixel driving circuit provided in FIG. 5 , and the shift register is the shift register provided in FIG. 7 .

[0201] In an exemplary embodiment, as shown in Figures 9 and 10, a drive output circuit includes N drive output sub-circuits, with the nth drive output sub-circuit electrically connected to the nth drive output signal terminal. During at least one display frame, the start time of the drive signal output by the Nth drive output signal terminal is later than the start time of the drive signal output by at least one of the first to the N-1th drive output signal terminals, where N > 2 and 1 ≤ n ≤ N. Figures 9 and 10 are illustrated using N = 4 as an example. Exemplarily, the start time of the drive signal output by the nth drive output signal terminal is later than the start time of the drive signal output by the (n-1)th drive output signal terminal, i.e., the start time of the drive signal output by the second drive output signal terminal is later than the start time of the drive signal output by the first drive output signal terminal, the start time of the drive signal output by the third drive output signal terminal is later than the start time of the drive signal output by the second drive output signal terminal, and the start time of the drive signal output by the fourth drive output signal terminal is later than the start time of the drive signal output by the third drive output signal terminal.

[0202] In an exemplary embodiment, as shown in Figures 9 and 10, the area of ​​the Nth driver output sub-circuit is larger than the area of ​​at least one of the first to N-1th driver output sub-circuits. For example, the first driver output sub-circuit includes a first output transistor M51, a first output capacitor OC1, and a first noise reduction transistor M61; the second driver output sub-circuit includes a second output transistor M52, a second output capacitor OC2, and a second noise reduction transistor M62; the third driver output sub-circuit includes a third output transistor M53, a third output capacitor OC3, and a third noise reduction transistor M63; and the fourth driver output sub-circuit includes a fourth output transistor M54, a fourth output capacitor OC4, and a fourth noise reduction transistor M64.

[0203] The present disclosure improves the driving capability of the Nth drive output subcircuit by setting the area of ​​the Nth drive output subcircuit that outputs the drive signal the latest to be larger than the area of ​​at least one drive output subcircuit from the first drive output subcircuit to the N-1th drive output subcircuit, thereby reducing the duration of the time period in which the falling edge of the drive signal output by the Nth drive output subcircuit occurs, improving the horizontal stripe phenomenon of the display substrate, and enhancing the display effect of the display substrate.

[0204] In an exemplary embodiment, a display substrate may include: a base and a driving structure layer disposed on the base, wherein a gate driving circuit and a pixel driving circuit are located in the driving structure layer, the driving structure layer including: a semiconductor layer, a first conductive layer, and a second conductive layer sequentially stacked on the base, at least one driving output sub-circuit including: an output transistor, a noise reduction transistor, and an output capacitor, the transistor including: an active pattern, a gate electrode, a first electrode, and a second electrode, and the capacitor including: a first electrode plate and a second electrode plate;

[0205] The semiconductor layer includes at least: an active pattern of an output transistor and an active pattern of a noise reduction transistor located in at least one driver output sub-circuit;

[0206] The first conductive layer includes at least: a second plate of an output capacitor located at at least one driver output sub-circuit;

[0207] The second conductive layer includes at least a first plate of an output capacitor located in at least one driver output subcircuit, a gate electrode, a first pole and a second pole of an output transistor, and a gate electrode, a first pole and a second pole of a noise reduction transistor.

[0208] In an exemplary embodiment, as shown in FIG10 , the area of ​​the output transistors in the Nth driver output sub-circuit is larger than the area of ​​the output transistors in at least one of the first through N-1th driver output sub-circuits, and the area of ​​the output capacitors in the Nth driver output sub-circuit is equal to the area of ​​the output capacitors in at least one of the first through N-1th driver output sub-circuits. For example, the area of ​​the fourth output transistor M54 is larger than the area of ​​at least one of the first through third output transistors M51 through M53, and the area of ​​the fourth output capacitor OC4 is equal to the area of ​​at least one of the first through third output capacitors OC1 through OC3.

[0209] In an exemplary embodiment, the width-to-length ratio of the channel region of the active pattern of the output transistor in the Nth driver output sub-circuit is greater than the width-to-length ratio of the channel region of the active pattern of the output transistor in at least one of the first through N-1th driver output sub-circuits, thereby increasing the drive capability of the output transistor in the Nth driver output sub-circuit. Exemplarily, the width-to-length ratio of the channel region of the active pattern of the fourth output transistor M54 is greater than the width-to-length ratio of the channel region of the active pattern of at least one of the first through third output transistors M51 through M53.

[0210] In an exemplary embodiment, the width-to-length ratio of the channel region of the active pattern of the output transistor in the first driver output sub-circuit is greater than the width-to-length ratio of the channel region of the active pattern of the output transistor in at least one of the second to N-1th driver output sub-circuits. Exemplarily, the width-to-length ratio of the channel region of the active pattern of the first output transistor M51 is greater than the width-to-length ratio of the channel region of the active pattern of the second and third output transistors M52 and M53.

[0211] In an exemplary embodiment, the width-to-length ratios of the channel regions of the active patterns of the output transistors in at least two of the second through N-1th driver output sub-circuits are equal, ensuring consistent driving capabilities across the second through N-1th driver output sub-circuits and ensuring display uniformity across the display substrate. For example, the width-to-length ratio of the channel region of the active pattern of the second output transistor M52 is equal to the width-to-length ratio of the channel region of the active pattern of the third output transistor M53.

[0212] In an exemplary embodiment, as shown in Figures 9 and 10, in at least one driver output sub-circuit, at least a portion of the gate electrode of the output transistor is a ring structure, at least a portion of the first electrode of the output transistor is a ring structure, the gate electrode of the output transistor surrounds the first electrode of the output transistor, and the second electrode of the output transistor is disposed on at least one side of the gate electrode of the output transistor. For example, at least a portion of the gate electrode 512 of the first output transistor is a ring structure, at least a portion of the first electrode 513 of the first output transistor is a ring structure, the gate electrode 512 of the first output transistor surrounds the first electrode 513 of the first output transistor, and the second electrode 514 of the first output transistor is disposed on at least one side of the gate electrode 512 of the first output transistor. At least a portion of the gate electrode 522 of the second output transistor is a ring structure, at least a portion of the first electrode 523 of the second output transistor is a ring structure, the gate electrode 522 of the second output transistor surrounds the first electrode 523 of the second output transistor, and the second electrode 524 of the second output transistor is disposed on at least one side of the gate electrode 522 of the second output transistor. On one side, at least a portion of the gate electrode 532 of the third output transistor is a ring structure, at least a portion of the first pole 533 of the third output transistor is a ring structure, the gate electrode 532 of the third output transistor surrounds the first pole 533 of the third output transistor, and the second pole 534 of the third output transistor is arranged on at least one side of the gate electrode 532 of the third output transistor. At least a portion of the gate electrode 542 of the fourth output transistor is a ring structure, at least a portion of the first pole 543 of the fourth output transistor is a ring structure, the gate electrode 542 of the fourth output transistor surrounds the first pole 543 of the fourth output transistor, and the second pole 544 of the fourth output transistor is arranged on at least one side of the gate electrode 542 of the fourth output transistor.

[0213] In an exemplary embodiment, as shown in Figures 9 and 10, in at least one driver output sub-circuit, the output capacitor is located on a side of the output transistor close to the second center line O2, and the noise reduction transistor is located on a side of the output transistor close to the first center line O1. The first center line O1 is the center line of the area occupied by the driver output circuit extending along the first direction D1, and the second center line O2 is the center line of the area occupied by the driver output circuit extending along the second direction D2. Illustratively, the first output capacitor OC1 is located on a side of the first output transistor M51 close to the second center line O2, the first noise reduction transistor M61 is located on a side of the first output transistor M51 close to the first center line O1, the second output capacitor OC2 is located on a side of the second output transistor M52 close to the second center line O2, the second noise reduction transistor M62 is located on a side of the second output transistor M52 close to the first center line O1, the third output capacitor OC3 is located on a side of the third output transistor M53 close to the second center line O2, the third noise reduction transistor M63 is located on a side of the third output transistor M53 close to the first center line O1, the fourth output capacitor OC4 is located on a side of the fourth output transistor M54 close to the second center line O2, and the fourth noise reduction transistor M64 is located on a side of the fourth output transistor M54 close to the first center line O1.

[0214] In an exemplary embodiment, as shown in FIG10 , N=4, the output device in the first driver output sub-circuit (i.e., the first output transistor M51 and the first output capacitor OC1) and the output device in the second driver output sub-circuit (i.e., the second output transistor M52 and the second output capacitor OC2) are symmetrically arranged with respect to the second center line O2, the output device in the second driver output sub-circuit (i.e., the second output transistor M52 and the second output capacitor OC2) and the output device in the third driver output sub-circuit (i.e., the third output transistor M53 and the third output capacitor OC3) are symmetrically arranged with respect to the first center line O1, and the output capacitor in the fourth driver output sub-circuit (i.e., the fourth output capacitor OC4) and the output capacitor in the third driver output sub-circuit (i.e., the fourth output capacitor OC5) are symmetrically arranged with respect to the first center line O1. The third output capacitor OC3) is symmetrically arranged with respect to the second center line O2, at least a portion of the output transistor in the fourth driver output sub-circuit (that is, the fourth output transistor M54) and the output transistor in the third driver output sub-circuit (that is, the third output transistor M53) are symmetrically arranged with respect to the second center line O2, the output capacitor in the fourth driver output sub-circuit (that is, the fourth output capacitor OC4) and the output capacitor in the first driver output sub-circuit (that is, the first output capacitor OC1) are symmetrically arranged with respect to the first center line O1, and at least a portion of the output transistor in the fourth driver output sub-circuit (that is, the fourth output transistor M54) and the output transistor in the first driver output sub-circuit (that is, the first output transistor M51) are symmetrically arranged with respect to the first center line O1.

[0215] In an exemplary embodiment, as shown in FIG10 , the noise reduction transistor of the first driver output sub-circuit (i.e., the first noise reduction transistor M61) and the noise reduction transistor of the second driver output sub-circuit (i.e., the second noise reduction transistor M62) are located on the side of the output device of the first driver output sub-circuit (i.e., the first output transistor M51 and the first output capacitor OC1) close to the first center line O1, and the noise reduction transistor of the second driver output sub-circuit (i.e., the second noise reduction transistor M62) is located on the side of the noise reduction transistor of the first driver output sub-circuit (i.e., the first noise reduction transistor M61) close to the second center line O1. On one side of the center line O1, the noise reduction transistor of the third driver output sub-circuit (i.e., the third noise reduction transistor M63) and the noise reduction transistor of the fourth driver output sub-circuit (i.e., the fourth noise reduction transistor M64) are located on a side of the output device of the third driver output sub-circuit (i.e., the third output transistor M53 and the third output capacitor OC3) close to the first center line O1, and the noise reduction transistor of the third driver output sub-circuit (i.e., the third noise reduction transistor M63) is located on a side of the noise reduction transistor of the fourth driver output sub-circuit (i.e., the fourth noise reduction transistor M64) close to the first center line O1.

[0216] In an exemplary embodiment, as shown in FIG10 , the noise reduction transistor of the first driver output sub-circuit (i.e., the first noise reduction transistor M61) and the noise reduction transistor of the fourth driver output sub-circuit (i.e., the fourth noise reduction transistor M64) are asymmetrically arranged relative to the first center line O1, and the noise reduction transistor of the second driver output sub-circuit (i.e., the second noise reduction transistor M62) and the noise reduction transistor of the third driver output sub-circuit (i.e., the third noise reduction transistor M63) are asymmetrically arranged relative to the first center line O1.

[0217] In an exemplary embodiment, as shown in FIG10 , the region where the driver output circuit is located is divided by a second center line O2 into a first region R1 and a second region R2. The output devices of the first driver output sub-circuit (i.e., the first output transistor M51 and the first output capacitor OC1) and the output devices of the fourth driver output sub-circuit (i.e., the fourth output transistor M54 and the fourth output capacitor OC4) are located in the first region R1, while the output devices of the second driver output sub-circuit (i.e., the second output transistor M52 and the second output capacitor OC2) and the output devices of the third driver output sub-circuit (i.e., the third output transistor M53 and the third output capacitor OC3) are located in the second region R2.

[0218] In an exemplary embodiment, as shown in FIG10 , the noise reduction transistors of at least one of the first to fourth driver output sub-circuits (i.e., at least one of the first, second, third, and fourth noise reduction transistors M61, M62, M63, and M64) are located in a first region R1 and a second region R2, and the area of ​​the noise reduction transistors located in the first region R1 is smaller than the area of ​​the noise reduction transistors located in the second region R2. For example, the area of ​​the first noise reduction transistor M61 located in the first region R1 is smaller than the area of ​​the first noise reduction transistor M61 located in the second region R2, the area of ​​the second noise reduction transistor M62 located in the first region R1 is smaller than the area of ​​the second noise reduction transistor M62 located in the second region R2, the area of ​​the third noise reduction transistor M63 located in the first region R1 is smaller than the area of ​​the third noise reduction transistor M63 located in the second region R2, and the area of ​​the fourth noise reduction transistor M64 located in the first region R1 is smaller than the area of ​​the fourth noise reduction transistor M64 located in the second region R2.

[0219] In an exemplary embodiment, as shown in FIG10 , the areas of the noise reduction transistors of the first driver output sub-circuit and the second driver output sub-circuit (i.e., the first noise reduction transistor M61 and the second noise reduction transistor M62) within the first region R1 are larger than the areas of the noise reduction transistors of the third driver output sub-circuit and the fourth driver output sub-circuit (i.e., the third noise reduction transistor M63 and the fourth noise reduction transistor M64) within the first region R1, and the areas of the noise reduction transistors of the first driver output sub-circuit and the second driver output sub-circuit (i.e., the first noise reduction transistor M61 and the second noise reduction transistor M62) within the second region R2 are smaller than the areas of the noise reduction transistors of the third driver output sub-circuit and the fourth driver output sub-circuit (i.e., the third noise reduction transistor M63 and the fourth noise reduction transistor M64) within the second region R2.

[0220] In an exemplary embodiment, FIG11 is a partial schematic diagram of the film layers in FIG10. As shown in FIG11, the active pattern 541 of the output transistor of the fourth driver output sub-circuit (i.e., the fourth output transistor M54) includes at least one first active pattern 5411 and at least one second active pattern 5412, wherein the length of the first active pattern 5411 along the second direction D2 is greater than the length of the second active pattern 5412 along the second direction D2.

[0221] In an exemplary embodiment, as shown in FIG. 11 , the first active pattern 5411 includes a first active portion 5411A and a second active portion 5411B, the first active portion 5411A and the second active pattern 5412 having the same length along the first direction D1 , and the second active portion 5411B is located on a side of the first active portion 5411A closer to the first center line O1 .

[0222] In an exemplary embodiment, as shown in FIG11 , the first active portion and the second active pattern of the active pattern of the output transistor of the fourth driver output sub-circuit (i.e., the fourth output transistor M54) are symmetrically arranged with at least a portion of the active pattern 511 of the output transistor of the first driver output sub-circuit (i.e., the first output transistor M51) relative to the first center line O1, and the first active portion and the second active pattern of the active pattern of the output transistor of the fourth driver output sub-circuit (i.e., the fourth output transistor M54) are symmetrically arranged with the active pattern 531 of the output transistor of the third driver output sub-circuit (i.e., the third output transistor M53) relative to the second center line O2. The active pattern 511 of the first output transistor and the active pattern 521 of the second output transistor are symmetrically arranged with respect to the second center line O2, and the active pattern 521 of the second output transistor and the active pattern 531 of the third output transistor are symmetrically arranged with respect to the first center line O1.

[0223] In an exemplary embodiment, as shown in FIG10 , the first electrode 543 of the output transistor of the fourth driver output sub-circuit (i.e., the fourth output transistor M54) includes a first electrode portion 543A and a second electrode portion 543B spaced apart from each other. The first electrode portion 543A of the output transistor of the fourth driver output sub-circuit (i.e., the fourth output transistor M54) is symmetrically arranged with respect to the first center line O1 with respect to the first electrode 513 of the output transistor of the first driver output sub-circuit (i.e., the first output transistor M51), and the first electrode portion 543A of the output transistor of the fourth driver output sub-circuit (i.e., the fourth output transistor M54) is symmetrically arranged with respect to the first electrode 533 of the output transistor of the third driver output sub-circuit (i.e., the third output transistor M53).

[0224] In an exemplary embodiment, as shown in Figures 10 and 11, the first electrode portion 543A and the second electrode portion 543B include: a closed loop structure, the orthographic projection of the first electrode portion 543A on the substrate at least partially overlaps with the orthographic projection of the first active portion 5411A and the second active pattern 5412 on the substrate, and the orthographic projection of the second electrode portion 543B on the substrate at least partially overlaps with the orthographic projection of the second active portion 5411B on the substrate.

[0225] In an exemplary embodiment, as shown in FIG. 10 , the area of ​​the first electrode portion 543A is greater than the area of ​​the second electrode portion 543B.

[0226] In an exemplary embodiment, as shown in FIG10 , the gate electrode 542 of the output transistor of the fourth driver output sub-circuit (i.e., the fourth output transistor M54) includes a first gate electrode portion 542A and a second gate electrode portion 542B connected to each other. The first gate electrode portion 542A of the gate electrode of the output transistor of the fourth driver output sub-circuit is symmetrically arranged with the gate electrode 512 of the output transistor of the first driver output sub-circuit (i.e., the first output transistor) relative to the first centerline O1. The first gate electrode portion 542A of the gate electrode 542 of the output transistor of the fourth driver output sub-circuit (i.e., the fourth output transistor M54) is symmetrically arranged with the gate electrode 532 of the output transistor of the third driver output sub-circuit (i.e., the third output transistor M53) relative to the second centerline O2. The gate electrode 512 of the first output transistor is symmetrically arranged with the gate electrode 522 of the second output transistor relative to the second centerline O2. The gate electrode 522 of the second output transistor is symmetrically arranged with the gate electrode 532 of the third output transistor relative to the first centerline O1.

[0227] In an exemplary embodiment, in combination with Figures 10 and 12, the first gate electrode portion 542A and the second gate electrode portion 542B include: a closed loop structure, the orthographic projection of the first gate electrode portion 542A on the substrate at least partially overlaps with the orthographic projection of the first active portion 5411A and the second active pattern 5412 on the substrate, and the orthographic projection of the second gate electrode portion 542B on the substrate at least partially overlaps with the orthographic projection of the second active portion 5411B on the substrate; the first gate electrode portion 542A surrounds the first electrode portion 543A, and the second gate electrode portion 542B surrounds the second electrode portion 543B.

[0228] In an exemplary embodiment, as shown in FIG. 10 , the area of ​​the first gate electrode portion 542A is greater than the area of ​​the second gate electrode portion 542B.

[0229] In an exemplary embodiment, as shown in FIG10 , a virtual straight line extending along the first direction D1 and passing through the noise reduction transistor of the fourth driver output sub-circuit (i.e., the fourth noise reduction transistor M64) passes through the output transistor of the fourth driver output sub-circuit (i.e., the fourth output transistor M54). Furthermore, the virtual straight line extending along the first direction D1 and passing through the noise reduction transistor of the fourth driver output sub-circuit (i.e., the fourth noise reduction transistor M64) passes through the second gate electrode portion 542B and the second electrode portion 543B.

[0230] In an exemplary embodiment, as shown in FIG10 , the second region may further include output connection lines. The output connection lines may include first to fourth output connection lines OUTL1 to OUTL4; a first driver output sub-circuit connected to the first output connection line OUTL1, a second driver output sub-circuit connected to the second output connection line OUTL2, a third driver output sub-circuit connected to the third output connection line OUTL3, and a fourth driver output sub-circuit connected to the fourth output connection line OUTL4.

[0231] In an exemplary embodiment, as shown in Figure 10, the first output connection line OUTL1 and the second output connection line OUTL2 are located between the output transistor of the first drive output sub-circuit (that is, the first output transistor M51) and the noise reduction transistor of the first drive output sub-circuit (that is, the first noise reduction transistor M61), and the third output connection line OUTL3 and the fourth output connection line OUTL4 are located between the output transistor of the fourth drive output sub-circuit (that is, the fourth output transistor M54) and the noise reduction transistor of the fourth drive output sub-circuit (that is, the fourth noise reduction transistor M64).

[0232] In an exemplary embodiment, as shown in FIG. 10 , the output connection line is located in the second conductive layer.

[0233] In an exemplary embodiment, as shown in FIG. 10 , the first and second output connection lines OUTL1 and OUTL2 extend in a first direction D1 , and the third and fourth output connection lines OUTL3 and OUTL4 are zigzag-line shaped and at least partially extend in the first direction D1 .

[0234] In an exemplary embodiment, as shown in FIG10 , the third output connection line OUTL3 includes a first output connection portion OUTL3A, a second output connection portion OUTL3B, and a third output connection portion OUTL3C. The first output connection portion OUTL3A and the third output connection portion OUTL3C extend along a first direction D1, and the second output connection portion OUTL3B extends along a second direction D2. The second output connection portion OUTL3B is electrically connected to the first output connection portion OUTL3A and the third output connection portion OUTL3C, respectively.

[0235] In an exemplary embodiment, as shown in Figure 10, the fourth output connection line OUTL4 includes: a first output connection portion OUTL4A, a second output connection portion OUTL4B and a third output connection portion OUTL4C; the first output connection portion OUTL4A and the third output connection portion OUTL4C extend along the first direction D1, the second output connection portion OUTL4B extends along the second direction D2, and the second output connection portion OUTL4B is electrically connected to the first output connection portion OUTL4A and the third output connection portion OUTL4C, respectively.

[0236] In an exemplary embodiment, as shown in FIG9 , the area of ​​the output capacitor in the Nth driver output subcircuit is greater than the area of ​​the output capacitor of at least one of the first through N-1th driver output subcircuits, and the area of ​​the output transistor in the Nth driver output subcircuit is equal to the area of ​​the output transistor of at least one of the first through N-1th driver output subcircuits. Exemplarily, the area of ​​the fourth output capacitor OC4 is greater than the area of ​​at least one of the first through third output capacitors OC1 through OC3, and the area of ​​the fourth output transistor M54 is equal to the area of ​​at least one of the first through third output transistors M51 through M53.

[0237] In an exemplary embodiment, as shown in FIG9 , N=4, the first to third driver output sub-circuits include one output capacitor, and the fourth driver output sub-circuit includes two output capacitors. The output devices in the first driver output sub-circuit (i.e., the first output transistor M51 and the first output capacitor OC1) and the output devices in the second driver output sub-circuit (i.e., the second output transistor M52 and the second output capacitor OC2) are symmetrically arranged with respect to the second center line O2. The output devices in the second driver output sub-circuit (i.e., the second output transistor M52 and the second output capacitor OC2) and the output devices in the third driver output sub-circuit (i.e., the third output transistor M53 and the third output capacitor OC3) are symmetrically arranged with respect to the first center line O1. The output devices in the fourth driver output sub-circuit (i.e., the fourth output transistor M54 and one of the fourth output capacitors OC4) and the output devices in the third driver output sub-circuit (i.e., the third output transistor M53 and the third output capacitor OC3) are symmetrically arranged with respect to the second center line O2. The output devices in the fourth driver output sub-circuit (i.e., the fourth output transistor M54 and one of the fourth output capacitors OC4) and the output devices in the first driver output sub-circuit (i.e., the first output transistor M51 and the first output capacitor OC1) are symmetrically arranged with respect to the first center line O1.

[0238] In an exemplary embodiment, as shown in FIG9 , the noise reduction transistor of the first driver output sub-circuit (i.e., the first noise reduction transistor M61) and the noise reduction transistor of the second driver output sub-circuit (i.e., the second noise reduction transistor M62) are located on the side of the output device of the first driver output sub-circuit (i.e., the first output transistor M51 and the first output capacitor OC1) close to the first center line O1, and the noise reduction transistor of the second driver output sub-circuit (i.e., the second noise reduction transistor M62) is located on the side of the noise reduction transistor of the first driver output sub-circuit (i.e., the first noise reduction transistor M61) close to the first center line O1, and the noise reduction transistor of the third driver output sub-circuit (i.e., the third noise reduction transistor M63) and the third driver output sub-circuit (i.e., the third noise reduction transistor M64) are located on the side of the output device of the first driver output sub-circuit (i.e., the first output transistor M51 and the first output capacitor OC1) close to the first center line O1. The noise reduction transistors of the four drive output sub-circuits (i.e., the fourth noise reduction transistor M64) are located on a side of the output device of the third drive output sub-circuit (i.e., the third output transistor M53 and the third output capacitor OC3) close to the first center line O1, and the noise reduction transistor of the third drive output sub-circuit (i.e., the third noise reduction transistor M63) is located on a side of the noise reduction transistor of the fourth drive output sub-circuit (i.e., the fourth noise reduction transistor M64) close to the first center line O1, and another output capacitor OC4 of the fourth drive output sub-circuit is located on a side of the output device of the fourth drive output sub-circuit (i.e., the fourth output transistor M54 and one of the fourth output capacitors OC4) close to the first center line O1.

[0239] In an exemplary embodiment, as shown in FIG9 , the noise reduction transistor of the first driver output sub-circuit (i.e., the first noise reduction transistor M61) and the noise reduction transistor of the fourth driver output sub-circuit (i.e., the second noise reduction transistor M62) are symmetrically arranged relative to the first center line O1, and the noise reduction transistor of the second driver output sub-circuit (i.e., the second noise reduction transistor M62) and the noise reduction transistor of the third driver output sub-circuit (i.e., the third noise reduction transistor M63) are symmetrically arranged relative to the first center line O1.

[0240] In an exemplary embodiment, as shown in FIG9 , the region where the driver output circuit is located is divided by a second center line O2 into a first region R1 and a second region R2. The output device of the first driver output sub-circuit (i.e., the first output transistor M51 and the first output capacitor OC1) and the output device of the fourth driver output sub-circuit (i.e., the fourth output transistor M54 and one of the output capacitors OC4) and the other output capacitor OC4 are located in the first region R1, while the output device of the second driver output sub-circuit (i.e., the second output transistor M52 and the second output capacitor OC2) and the output device of the third driver output sub-circuit (i.e., the third output transistor M53 and the third output capacitor OC3) are located in the second region R2.

[0241] In an exemplary embodiment, as shown in FIG9 , the noise reduction transistors of at least one of the first to fourth driver output sub-circuits are located in the first region R1 and the second region R2, and the area of ​​the noise reduction transistor located in the first region R1 is smaller than the area of ​​the noise reduction transistor located in the second region R2. That is, the area of ​​the first noise reduction transistor M61 located in the first region R1 is smaller than the area of ​​the first noise reduction transistor M61 located in the second region R2, the area of ​​the second noise reduction transistor M62 located in the first region R1 is smaller than the area of ​​the second noise reduction transistor M62 located in the second region R2, the area of ​​the third noise reduction transistor M63 located in the first region R1 is smaller than the area of ​​the third noise reduction transistor M63 located in the second region R2, and the area of ​​the fourth noise reduction transistor M4 located in the first region R1 is smaller than the area of ​​the fourth noise reduction transistor M64 located in the second region R2.

[0242] In an exemplary embodiment, the area of ​​the noise reduction transistor located in the second region R2 is in a range of 1 to 3 times the area of ​​the noise reduction transistor located in the first region R1. For example, the area of ​​the noise reduction transistor located in the second region R2 may be twice the area of ​​the noise reduction transistor located in the first region R1.

[0243] In an exemplary embodiment, as shown in FIG9 , the second region further includes: output connection lines, the output connection lines including: first to fourth output connection lines OUTL1 to OUTL4; a first driver output sub-circuit connected to the first output connection line OUTL1, a second driver output sub-circuit connected to the second output connection line OUTL2, a third driver output sub-circuit connected to the third output connection line OUTL3, and a fourth driver output sub-circuit connected to the fourth output connection line OUTL4.

[0244] 9 , the output link lines extend along a first direction D1. Exemplarily, at least one of the first to fourth output link lines OUTL1 to OUTL4 extends along the first direction D1.

[0245] In an exemplary embodiment, as shown in Figure 9, the first output connection line OUTL1 and the second output connection line OUTL2 are located between the output device of the first drive output sub-circuit (that is, the first output transistor M51 and the first output capacitor OC1) and the noise reduction transistor of the first drive output sub-circuit (that is, the first noise reduction transistor M61), and the third output connection line OUTL3 and the fourth output connection line OUTL4 are located between the output device of the fourth drive output sub-circuit (that is, the fourth output transistor M54 and one of the output capacitors OC4) and the noise reduction transistor of the fourth drive output sub-circuit (that is, the fourth noise reduction transistor M64).

[0246] In an exemplary embodiment, as shown in FIG9 , another output capacitor (i.e., another fourth output capacitor OC4) of the fourth driver output sub-circuit and a noise reduction transistor (i.e., a fourth noise reduction transistor M64) are located on the same side of the third output connection line OUTL3 and the fourth output connection line OUTL4.

[0247] In an exemplary embodiment, as shown in FIG. 9 , the first and second output link lines OUTL1 and OUTL2 may be located at the second conductive layer.

[0248] In an exemplary embodiment, as shown in FIG9 , the third output connection line OUTL3 includes a first output connection portion OUTL3A, a second output connection portion OUTL3B, and a third output connection portion OUTL3C. The first output connection portion OUTL3A, the second output connection portion OUTL3B, and the third output connection portion OUTL3C extend along a first direction D1, and the second output connection portion OUTL3B is electrically connected to the first output connection portion OUTL3A and the third output connection portion OUTL3C, respectively. The first output connection portion OUTL3A and the third output connection portion OUTL3C may be located on the second conductive layer, and the second output connection portion OUTL3B may be located on the first conductive layer.

[0249] In an exemplary embodiment, as shown in FIG9 , the fourth output connection line OUTL4 includes a first output connection portion OUTL4A, a second output connection portion OUTL4B, and a third output connection portion OUTL4C. The first output connection portion OUTL4A, the second output connection portion OUTL4B, and the third output connection portion OUTL4C extend along a first direction D1, and the second output connection portion OUTL4B is electrically connected to the first output connection portion OUTL4A and the third output connection portion OUTL4C, respectively. The first output connection portion OUTL4A and the third output connection portion OUTL4C are located in the second conductive layer, while the second output connection portion OUTL4B is located in the first conductive layer.

[0250] In an exemplary embodiment, the configuration of the fourth driving output sub-circuit in FIG. 9 and FIG. 10 can avoid a large space occupied by the shift register, thereby improving the space utilization of the shift register.

[0251] In an exemplary embodiment, FIG12 is a schematic diagram of a partial structure within the first region of the display substrate, and FIG13 is a schematic diagram of a partial structure within the first region of the display substrate. As shown in FIG12 and FIG13 , the first region is provided with at least one first signal line and at least one second signal line. The pixel drive circuit is electrically connected to the first signal line and the second signal line, respectively. The first signal line extends at least partially along the first direction D1, and the second signal line extends at least partially along the second direction D2. The first signal line includes at least a scan signal line GL, and the second signal line includes at least a first power line VDD, a sense signal line Sense, and a data signal line Data. At least one drive output sub-circuit in the shift register is electrically connected to the at least one first signal line. FIG12 and FIG13 illustrate the example of N=4, with one drive signal output terminal connected to one scan signal line GL. GL(1) in Figures 12 and 13 is the scanning signal line connected to the first driving output sub-circuit of the first-level shift register, GL(2) is the scanning signal line connected to the second driving output sub-circuit of the first-level shift register, GL(3) is the scanning signal line connected to the third driving output sub-circuit of the first-level shift register, and GL(4) is the scanning signal line connected to the fourth driving output sub-circuit of the first-level shift register.

[0252] In an exemplary embodiment, the first signal line may be located in the first conductive layer, and the second signal line may be located in the second conductive layer. Alternatively, the first signal line and the second signal line may be located in other film layers, which is not limited in the present disclosure.

[0253] In an exemplary embodiment, as shown in FIG12 and FIG13 , at least one scan signal line GL includes a plurality of signal connection lines GLA and a plurality of signal overlapping lines GLB. The plurality of signal connection lines GLA and the plurality of signal overlapping lines GLB are alternately arranged along a first direction D1. The signal connection lines GLA are arranged along the first direction D1, and an orthographic projection of the signal overlapping lines GLB on the substrate overlaps an orthographic projection of at least one second signal line on the substrate by at least 10%.

[0254] In an exemplary embodiment, as shown in FIG12 and FIG13 , the line width of the signal connection line GLA of the scanning signal line GL connected to at least one of the first to N-1th driving output sub-circuits in at least one stage of the shift register is smaller than the line width of the signal connection line GLA of the scanning signal line GL connected to the Nth driving output sub-circuit. Exemplarily, the line width of the signal connection line GLA of the scanning signal lines GL(1) to GL(3) is smaller than the line width of the signal connection line GLA of the scanning signal line GL(4).

[0255] In an exemplary embodiment, as shown in FIG12 and FIG13 , for at least one stage of the shift register, the line width of the signal connection line GLA of the scanning signal line GL connected to the Nth driving output sub-circuit is within a range of 1.5 to 2 times the line width of the signal connection line GLA of the scanning signal line GL connected to at least one driving output sub-circuit from the first driving output sub-circuit to the N-1th driving output sub-circuit. Exemplarily, the line width of the signal connection line GLA of the scanning signal line GL(4) is 1.5 to 2 times the line width of the signal connection line GLA of the scanning signal lines GL(1) to GL(3).

[0256] In an exemplary embodiment, as shown in FIG12 , for at least one stage of the shift register, the signal overlap line GLB of the scanning signal line GL connected from the first drive output sub-circuit to the Nth drive output sub-circuit is a ring structure. For at least one scanning signal line GL, the length of the signal overlap line GLB along the first direction D1 is greater than the line width of at least one second signal line, and the length of the signal overlap line GLB along the second direction D2 is greater than the line width of the signal connection line GLA. Exemplarily, the signal overlap lines GLB of the scanning signal lines GL(1) to GL(4) are all ring structures. The fact that the signal overlap lines in the present disclosure are ring-shaped can reduce the area of ​​the overlapping region between the scanning signal line and the second signal line, reduce crosstalk between the signal lines, and improve the reliability of the display substrate.

[0257] In an exemplary embodiment, as shown in FIG13 , for at least one stage of the shift register, the signal overlap line GLB of the scanning signal line GL connected to at least one of the first through N-1th driver output subcircuits is a ring structure. For the scanning signal lines GL connected to the first through N-1th driver output subcircuits, the length of the signal overlap line GLB along the first direction D1 is greater than the line width of at least one second signal line, and the length of the signal overlap line GLB along the second direction D2 is greater than the line width of the signal connection line GLA. Exemplarily, the signal overlap lines GLB of the scanning signal lines GL(1) through GL(4) are all ring structures.

[0258] In an exemplary embodiment, as shown in FIG13 , a signal overlapping line GLB of the scan signal line GL connected to the Nth drive output sub-circuit extends along a first direction D1 and has at least one arc-shaped boundary. The average line width of the signal overlapping line GLB of the scan signal line GL connected to the Nth drive output sub-circuit is smaller than the line width of the signal connection line GLA of the scan signal line GL connected to the Nth drive output sub-circuit. Having an average line width of the signal overlapping line GLB of the scan signal line GL connected to the Nth drive output sub-circuit smaller than the line width of the signal connection line GLA of the scan signal line GL connected to the Nth drive output sub-circuit can reduce the resistance and capacitance loads of the scan signal line connected to the last drive output sub-circuit in the shift register, improve the display uniformity of the sub-pixels driven by the shift register, and enhance the reliability of the display substrate.

[0259] The arrangement of the scanning signal line GL connected to the Nth driving output sub-circuit in FIG12 and FIG13 can reduce the difference between the signals transmitted by the plurality of scanning signal lines connected to the shift register, and can improve the display uniformity of the display substrate.

[0260] In an exemplary embodiment, the driving output circuit is further electrically connected to N output clock signal terminals respectively, and the nth driving output sub-circuit is electrically connected to the nth output clock signal terminal.

[0261] The present disclosure also provides a display substrate, comprising: a first region and a second region, wherein the first region is provided with an array of pixel drive circuits, and the second region is provided with a gate drive circuit, the gate drive circuit being configured to provide a drive signal to the pixel drive circuit, the gate drive circuit comprising: a plurality of shift registers, at least one shift register comprising: a preamplifier circuit and a drive output circuit, the preamplifier circuit being electrically connected to a signal input terminal, a reset signal terminal, and a cascade output signal terminal, respectively; the drive output circuit being electrically connected to N output clock signal terminals, the signal input terminal of at least one shift register being electrically connected to the cascade output signal terminal of at least one shift register, and the reset signal terminal of at least one shift register being electrically connected to the cascade output signal terminal of at least one shift register. The drive output circuit comprises: N drive output sub-circuits, the nth drive output sub-circuit being electrically connected to the nth output clock signal terminal; FIG14 is a schematic diagram of a portion of the second region of a display device. As shown in FIG14 , the second region of the display substrate is provided with M*N output clock signal lines, at least one output clock signal line extending at least partially along a second direction D2 and located on a side of the drive output circuit away from the first region, where M≥2. FIG14 is described by taking M=3, N=4 as an example. FIG14 includes: a first output clock signal line CLKE1 to a twelfth output clock signal line CLKE12.

[0262] In an exemplary embodiment, the display substrate may further include a base and a driving structure layer disposed on the base, wherein the gate driving circuit and the pixel driving circuit are located in the driving structure layer, and the driving structure layer includes a semiconductor layer, a first conductive layer, and a second conductive layer sequentially stacked on the base. The output clock signal line may be located in the second conductive layer.

[0263] In an exemplary embodiment, as shown in FIG14 , the first to Nth output clock signal terminals of at least one stage of the shift register are electrically connected to N output clock signal lines, respectively. FIG14 illustrates the first output clock signal terminal being electrically connected to the ninth output clock signal line CLKE9, the second output clock signal terminal being electrically connected to the tenth output clock signal line CLKE10, the third output clock signal terminal being electrically connected to the eleventh output clock signal line CLKE11, and the fourth output clock signal terminal being electrically connected to the twelfth output clock signal line CLKE12.

[0264] In an exemplary embodiment, as shown in FIG14 , for at least one stage of the shift register, the line width of the output clock signal line connected to the Nth output clock signal terminal is greater than the line width of the output clock signal line connected to at least one of the first through N-1th output clock signal terminals. Exemplarily, the line width of the twelfth output clock signal line CLKE12 is greater than the line width of at least one of the ninth through eleventh output clock signal lines CLKE9 through CLKE11.

[0265] In an exemplary embodiment, the nth output clock signal terminal of at least one shift register is electrically connected to one of the nth output clock signal line, the N+nth output clock signal line, to the (M-1)*N+nth output clock signal line; the nth output clock signal terminal of the adjacent M-stage shift registers is connected to different output clock signal lines. For example, taking M=3 and N=4 as an example, each three-stage shift register is a repeating unit. For the first stage shift register in each three-stage shift register, the first output clock signal terminal is connected to the first output clock signal line CLKE1, the second output clock signal terminal is connected to the second output clock signal line CLKE2, the third output clock signal terminal is connected to the third output clock signal line CLKE3, and the fourth output clock signal terminal is connected to the fourth output clock signal line CLKE4. For the second stage shift register in each three-stage shift register, the first output clock signal terminal is connected to the fifth output clock signal line CLKE5, the second output clock signal terminal is connected to the fifth output clock signal line CLKE6, and the second output clock signal terminal is connected to the fifth output clock signal line CLKE7. The output clock signal terminal is connected to the sixth output clock signal line CLKE6, the third output clock signal terminal is connected to the seventh output clock signal line CLKE7, the fourth output clock signal terminal is connected to the eighth output clock signal line CLKE8, and for the third-stage shift register in each three-stage shift register, the first output clock signal terminal is connected to the ninth output clock signal line CLKE9, the second output clock signal terminal is connected to the tenth output clock signal line CLKE10, the third output clock signal terminal is connected to the eleventh output clock signal line CLKE11, and the fourth output clock signal terminal is connected to the twelfth output clock signal line CLKE12. Taking M=4 and N=4 as an example, every four-stage shift register is a repeating unit. For the first-stage shift register in every three-stage shift register, the first output clock signal terminal is connected to the first output clock signal line, the second output clock signal terminal is connected to the second output clock signal line, the third output clock signal terminal is connected to the third output clock signal line, and the fourth output clock signal terminal is connected to the fourth output clock signal line. For the second-stage shift register in every four-stage shift register, the first output clock signal terminal is connected to the fifth output clock signal line, the second output clock signal terminal is connected to the sixth output clock signal line, the third output clock signal terminal is connected to the seventh output clock signal line, and the fourth output clock signal terminal is connected to the eighth output clock signal line. For the third-stage shift register in every four-stage shift register, the first output clock signal terminal is connected to the th output clock signal line, the second output clock signal terminal is connected to the tenth output clock signal line, the third output clock signal terminal is connected to the eleventh output clock signal line, and the fourth output clock signal terminal is connected to the twelfth output clock signal line.For the fourth-stage shift register in every four-stage shift register, the first output clock signal terminal is connected to the thirteenth output clock signal line CLKE13, the second output clock signal terminal is connected to the fourteenth output clock signal line CLKE14, the third output clock signal terminal is connected to the fifteenth output clock signal line CLKE15, and the fourth output clock signal terminal is connected to the sixteenth output clock signal line CLKE16. In other words, the Nth driver output sub-circuit is electrically connected to an integer multiple of the Nth output signal line.

[0266] In an exemplary embodiment, as shown in FIG14 , at least one output clock signal line is provided with a via V. A length along the first direction D1 of the via in the output clock signal line connected to at least one of the first output clock signal terminal to the N-1th output clock signal terminal of the at least one stage of the shift register is shorter than a length along the first direction D1 of the via in the output clock signal line connected to the Nth output clock signal terminal of the at least one stage of the shift register.

[0267] In an exemplary embodiment, as shown in FIG14 , a via-related distance W1 of an output clock signal line connected to at least one of the first output clock signal terminal to the N-1th output clock signal terminal of the at least one shift register is equal to a via-related distance W2 of an output clock signal line connected to the Nth output clock signal terminal of the at least one shift register, wherein the via-related distance is a distance between a boundary of the output clock signal line and a boundary of a via of the output clock signal line.

[0268] In an exemplary embodiment, as shown in FIG14 , the second region further includes a plurality of clock connection lines, including a first clock connection line through an Nth clock connection line, and the clock connection lines are located in the first conductive layer. FIG14 illustrates an example where N=4 and the clock connection lines include a first clock connection line CL1 through a fourth clock connection line CL4.

[0269] In an exemplary embodiment, as shown in FIG14 , at least one stage of shift register is electrically connected to the nth output clock signal line through the nth clock connection line, and the orthographic projection of at least one clock connection line on the substrate at least partially overlaps with the orthographic projection of the via of at least one output clock signal line on the substrate.

[0270] In the present disclosure, W1=W2 can ensure that the overlapping area between each output clock signal line and any clock signal line is the same, so that the parasitic capacitance in the shift register can maintain good uniformity, thereby ensuring the reliability of the shift register.

[0271] In an exemplary embodiment, Figure 15 is a schematic diagram of a first clock signal, and Figure 16 is a schematic diagram of a second clock signal. As shown in Figures 15 and 16, the second region further includes a data unit electrically connected to output clock signal lines connected to N driver output sub-circuits of at least one shift register stage, configured to provide a first clock signal to the output clock signal lines connected to the second through N-1 driver output sub-circuits of the at least one shift register stage, and to provide a second clock signal to the output clock signal line connected to the N-th driver output sub-circuit, wherein the first clock signal includes a first rising edge and a first falling edge, and the second clock signal includes a second rising edge, a third rising edge, and a second falling edge.

[0272] In an exemplary embodiment, as shown in FIG15 , during the period of the first rising edge, the voltage of the first clock signal rises from the second voltage VL2 to the first voltage VL1 , and during the period of the first falling edge, the voltage of the first clock signal falls from the first voltage VL1 to the second voltage VL2 .

[0273] In an exemplary embodiment, as shown in FIG16 , in the time period where the second rising edge is located, the voltage of the second clock signal rises from the third voltage VL3 to the second voltage VL2, in the time period where the third rising edge is located, the voltage of the second clock signal rises from the second voltage VL2 to the first voltage VL1, and in the time period where the second falling edge is located, the voltage of the second clock signal falls from the first voltage VL1 to the third voltage VL3.

[0274] By setting the second clock signal as above, the present disclosure can achieve the rapid drop of the output drive signal of the Nth drive output sub-circuit to a lower potential, shorten the falling edge of the output drive signal of the Nth drive output sub-circuit, and thus achieve the uniformity of the multiple drive signals output by the shift register, thereby improving the reliability of the display substrate.

[0275] In an exemplary embodiment, the first voltage VL1 is a positive voltage, the second voltage VL2 and the third voltage VL3 are negative voltages, and the absolute value of the second voltage VL2 is smaller than the absolute value of the third voltage VL3. For example, the first voltage VL1 may be 24 volts, the second voltage VL2 may be -6 volts, and the third voltage VL3 may be -8 volts.

[0276] In an exemplary embodiment, FIG17 is a signal diagram of a third clock signal. As shown in FIG17 , the data unit is further configured to provide a third clock signal to an output clock signal line connected to the first driver output sub-circuit of at least one shift register stage. The third clock signal includes a fourth rising edge, a third falling edge, and a fourth falling edge. During the time period of the fourth rising edge, the voltage of the third clock signal rises from the second voltage VL2 to the fourth voltage VL4. During the time period of the third falling edge, the voltage of the third clock signal drops from the fourth voltage VL4 to the first voltage VL1. During the time period of the fourth falling edge, the voltage of the third clock signal drops from the first voltage VL1 to the second voltage VL2.

[0277] In an exemplary embodiment, the fourth voltage is a positive voltage and is greater than the first voltage. For example, the fourth voltage may be 26 volts.

[0278] By setting the third clock signal as above, the present disclosure can realize that the output drive signal of the first drive output sub-circuit rises quickly to a higher potential, shortens the rising edge of the output drive signal of the first drive output sub-circuit, and thereby realizes the uniformity of the multiple drive signals output by the shift register, thereby improving the reliability of the display substrate.

[0279] In an exemplary embodiment, the second region further includes a data unit electrically connected to output clock signal lines connected to N driver output sub-circuits of at least one shift register stage, and configured to provide a fourth clock signal to the output clock signal lines connected to the second to N-1 driver output sub-circuits of the at least one shift register stage, and to provide a fifth clock signal to the output clock signal line connected to the N-th driver output sub-circuit. The duration of a time period of a falling edge of the fifth clock signal is less than half the duration of a time period of a falling edge of the fourth clock signal.

[0280] By setting the fifth clock signal as above, the present disclosure can make the output drive signal of the Nth drive output sub-circuit fall quickly, shorten the falling edge of the output drive signal of the Nth drive output sub-circuit, and thus achieve the uniformity of the multiple drive signals output by the shift register, thereby improving the reliability of the display substrate.

[0281] In an exemplary embodiment, the data unit is further configured to provide a sixth clock signal to an output clock signal line connected to a first driver output sub-circuit of at least one stage of the shift register; the duration of a time period in which the rising edge of the sixth clock signal is located is less than half the duration of a time period in which the rising edge of the fourth clock signal is located.

[0282] By setting the sixth clock signal as above, the present disclosure can achieve a rapid rise in the output drive signal of the first drive output sub-circuit, shorten the rising edge of the output drive signal of the other first drive output sub-circuit, and thus achieve uniformity of the multiple drive signals output by the shift register, thereby improving the reliability of the display substrate.

[0283] In an exemplary embodiment, the display substrate may further include: a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate; and an encapsulation structure layer disposed on a side of the light-emitting structure layer away from the substrate. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited in this disclosure.

[0284] In exemplary embodiments, the substrate may be a flexible substrate, or may be a rigid substrate.

[0285] In an exemplary embodiment, the light-emitting structure layer may include an anode, a pixel definition layer, an organic light-emitting layer and a cathode. The anode is connected to the drain electrode of the driving transistor through a via, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of corresponding color under the drive of the anode and the cathode.

[0286] In an exemplary embodiment, the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0287] In an exemplary embodiment, the touch structure layer may include a first touch insulation layer arranged on the packaging structure layer, a first touch metal layer arranged on the first touch insulation layer, a second touch insulation layer covering the first touch metal layer, a second touch metal layer arranged on the second touch insulation layer, and a touch protection layer covering the second touch metal layer. The first touch metal layer may include a plurality of bridging electrodes, the second touch metal layer may include a plurality of first touch electrodes and second touch electrodes, and the first touch electrode or the second touch electrode may be connected to the bridging electrode through a via.

[0288] The following is an illustrative explanation using the preparation process of a display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be performed by any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed by any one or more of spraying, spin coating, and inkjet printing; and etching can be performed by any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate using a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer." If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0289] In an exemplary embodiment, a process of preparing a display substrate may include the following operations.

[0290] () Forming a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern may include: depositing a semiconductor thin film on a substrate, and patterning the semiconductor thin film through a patterning process to form a semiconductor layer pattern covering the substrate, as shown in Figures 18 and 19. Figure 18 is a schematic diagram of the semiconductor layer pattern in Figure 9, and Figure 19 is a schematic diagram of the semiconductor layer pattern in Figure 10.

[0291] In exemplary embodiments, as shown in FIG. 18 and FIG. 19 , the semiconductor layer pattern may include at least first to fourth output transistor active patterns 511 to 541 and first to fourth noise reduction transistor active patterns 611 to 641 .

[0292] In an exemplary embodiment, as shown in Figures 18 and 19, the active patterns 511 to 541 of the first to fourth output transistors are provided separately. The active pattern 611 of the first noise reduction transistor and the active pattern 621 of the second noise reduction transistor are integrally formed. The active pattern 631 of the third noise reduction transistor and the active pattern 641 of the fourth noise reduction transistor are integrally formed.

[0293] In an exemplary embodiment, as shown in FIG18 , the active pattern 511 of the first output transistor and the active pattern 521 of the second output transistor are symmetrically arranged with respect to the second center line O2, the active pattern 521 of the second output transistor and the active pattern 531 of the third output transistor are symmetrically arranged with respect to the first center line O1, the active pattern 511 of the first output transistor and the active pattern 541 of the fourth output transistor are symmetrically arranged with respect to the second center line O2, and the active pattern 531 of the third output transistor and the active pattern 541 of the fourth output transistor are symmetrically arranged with respect to the first center line O1. The active pattern 611 of the first noise reduction transistor and the active pattern 641 of the fourth output transistor are symmetrically arranged with respect to the first center line O1, and the active pattern 621 of the second noise reduction transistor and the active pattern 631 of the third output transistor are symmetrically arranged with respect to the first center line O1.

[0294] In an exemplary embodiment, as shown in FIG. 18 , a virtual straight line extending in the first direction D1 passing through the active pattern 631 of the third noise reduction transistor and the active pattern 641 of the fourth noise reduction transistor does not pass through the active pattern 641 of the fourth output transistor.

[0295] In an exemplary embodiment, as shown in FIG19 , the active pattern 511 of the first output transistor and the active pattern 521 of the second output transistor are symmetrically arranged relative to the second center line O2, the active pattern 521 of the second output transistor and the active pattern 531 of the third output transistor are symmetrically arranged relative to the first center line O1, portions of the active pattern 511 of the first output transistor and the active pattern 541 of the fourth output transistor are symmetrically arranged relative to the second center line O2, and the active pattern 531 of the third output transistor and the active pattern 541 of the fourth output transistor are symmetrically arranged relative to the first center line O1. The active pattern 611 of the first noise reduction transistor and the active pattern 641 of the fourth output transistor are asymmetrically arranged relative to the first center line O1, while the active pattern 621 of the second noise reduction transistor and the active pattern 631 of the third output transistor are asymmetrically arranged relative to the first center line O1.

[0296] In an exemplary embodiment, as shown in FIG. 19 , the area of ​​the active pattern 541 of the fourth output transistor is greater than the area of ​​at least one of the active patterns 511 to 531 of the first to third output transistors.

[0297] In an exemplary embodiment, as shown in FIG. 18 and FIG. 19 , the first to third output transistor active patterns 511 to 531 include a plurality of stripe structures extending along the second direction D2 , and the plurality of stripe structures are arranged along the first direction D1 .

[0298] In an exemplary embodiment, as shown in FIG. 19 , the length of a portion of the stripe structure in the active pattern 541 of the fourth output transistor is greater than the length of the stripe structure in the active patterns 511 to 531 of the first to third output transistors.

[0299] In an exemplary embodiment, as shown in FIG. 19 , a virtual straight line extending in the first direction D1 passing through the active pattern 631 of the third noise reduction transistor and the active pattern 641 of the fourth noise reduction transistor passes through the active pattern 541 of the fourth output transistor.

[0300] In an exemplary embodiment, as shown in Figures 18 and 19, the active patterns 611 through 641 of the first through fourth noise reduction transistors include a plurality of stripe structures extending along the second direction D2, and the plurality of stripe structures are arranged along the first direction D1. The length of the stripe structures in the active patterns 611 through 641 of the first through fourth noise reduction transistors is shorter than the length of the stripe structures in the active patterns 511 through 541 of the first through fourth output transistors.

[0301] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process to form a first insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the first insulating layer, as shown in Figures 20 to 23, Figure 20 is a schematic diagram of the first conductive layer pattern in Figure 9, Figure 21 is a schematic diagram of Figure 9 after the first conductive layer pattern is formed, Figure 22 is a schematic diagram of the first conductive layer pattern in Figure 10, and Figure 23 is a schematic diagram of Figure 10 after the first conductive layer pattern is formed. In an exemplary embodiment, the first conductive layer may be referred to as a gate metal (GATE) layer.

[0302] In an exemplary embodiment, as shown in Figures 20 to 23, the first conductive layer pattern in Figures 9 and 10 includes at least: the second plate OC1-2 of the first output capacitor to the second plate OC4-2 of the fourth output capacitor, the first clock connection line CL1 to the fourth clock connection line CL4, the first connection line L1, the second connection line L2, the third connection line L4, the fourth connection line L4, the sixth connection line L6, the seventh connection line L7, the eighth connection line L8, the ninth connection line L9 and the tenth connection line L10.

[0303] In an exemplary embodiment, as shown in FIG. 20 and FIG. 21 , the first conductive layer pattern provided in FIG. 9 further includes a fifth connection line L5 , a second output connection portion OUTL3B of a third output signal line, and a second output connection portion OUTL4B of a fourth output signal line.

[0304] In an exemplary embodiment, as shown in Figures 20 and 21, the first conductive layer pattern provided in Figure 9 includes one second plate OC1-2 of the first output capacitor, one second plate OC3-2 of the third output capacitor, and two second plates OC4-2 of the fourth output capacitor. The second plates OC1-2 of the first output capacitor and the second plates OC2-2 of the second output capacitor are symmetrically arranged relative to the second centerline O2. The second plates OC2-2 of the second output capacitor and the second plates OC3-2 of the third output capacitor are symmetrically arranged relative to the first centerline O1. The second plates OC3-2 of the third output capacitor and the second plates OC4-2 of one of the fourth output capacitors are symmetrically arranged relative to the second centerline O2. The second plates OC1-2 of the first output capacitor and the second plates OC4-2 of one of the fourth output capacitors are symmetrically arranged relative to the first centerline O1. The second plate OC4-2 of the other fourth output capacitor is located on the side of the second plate OC4-2 of one of the fourth output capacitors that is closer to the first centerline O1 and farther from the second centerline O2.

[0305] In an exemplary embodiment, as shown in Figures 20 and 21 , the second plate OC1-2 of the first output capacitor, the second plate OC3-2 of the third output capacitor, and the second plate OC4-2 of one of the fourth output capacitors are all shaped like a strip extending along the second direction D2. The second plate OC4-2 of the other fourth output capacitor is shaped like a strip extending along the first direction D1.

[0306] In an exemplary embodiment, as shown in Figures 22 and 23, the number of the second plate OC1-2 of the first output capacitor to the second plate OC3-2 of the fourth output capacitor in the first conductive layer pattern provided in Figure 10 is one. The second plate OC1-2 of the first output capacitor and the second plate OC2-2 of the second output capacitor are symmetrically arranged with respect to the second center line O2, the second plate OC2-2 of the second output capacitor and the second plate OC3-2 of the third output capacitor are symmetrically arranged with respect to the first center line O1, the second plate OC3-2 of the third output capacitor and the second plate OC4-2 of the fourth output capacitor are symmetrically arranged with respect to the second center line O2, and the second plate OC1-2 of the first output capacitor and the second plate OC4-2 of the fourth output capacitor are symmetrically arranged with respect to the first center line O1.

[0307] In an exemplary embodiment, as shown in FIG. 22 and FIG. 23 , the second plate OC1 - 2 of the first output capacitor to the second plate OC4 - 2 of the fourth output capacitor are all in the shape of a strip extending along the second direction D2 .

[0308] In an exemplary embodiment, as shown in Figures 20 to 23, the first to fourth clock connection lines CL1 to CL4 extend at least partially along the second direction D2. The first and second clock connection lines CL1 and CL2 are symmetrically arranged relative to the second center line O2, the third and second clock connection lines CL3 and CL2 are symmetrically arranged relative to the first center line O1, the first and fourth clock connection lines CL1 and CL4 are symmetrically arranged relative to the first center line O1, and the third and fourth clock connection lines CL3 and CL4 are symmetrically arranged relative to the second center line O2.

[0309] In an exemplary embodiment, as shown in FIG. 20 to FIG. 23 , at least one of the first to tenth connection lines L1 to L10 at least partially extends in the second direction D2 .

[0310] In an exemplary embodiment, as shown in Figures 20 to 23, the first to fourth connection lines L1 to L4 are located on one side of the first center line O1, the fifth to ninth connection lines L5 to L9 are located on the other side of the first center line O1, and the tenth connection line L10 is symmetrically arranged with respect to the first center line O1.

[0311] In an exemplary embodiment, as shown in Figures 20 to 23, the first connection line L1, the second connection line L2, the fifth connection line L5, the sixth connection line L6 and the seventh connection line are located on one side of the second center line O2, and the third connection line L3, the fourth connection line L4, the eighth connection line L8, the ninth connection line L9 and the tenth connection line L10 are located on the other side of the second center line O2.

[0312] In an exemplary embodiment, as shown in FIG. 20 to FIG. 23 , the third and eighth connection lines L3 and L8 are symmetrically disposed with respect to the first center line O1 , and the fourth and ninth connection lines L4 and L9 are symmetrically disposed with respect to the first center line O1 .

[0313] In an exemplary embodiment, as shown in Figures 20 and 21, the second connection line L2 and the sixth connection line L6 are symmetrically arranged with respect to the first center line O1. The orthographic projection of the sixth connection line L6 on the substrate does not overlap with the orthographic projections of the active patterns of the third and fourth noise reduction transistors on the substrate.

[0314] In an exemplary embodiment, as shown in Figures 22 and 23, the second connection line L2 and the sixth connection line L6 are asymmetrically arranged relative to the first center line O1. The orthographic projection of the sixth connection line L6 on the substrate overlaps with the orthographic projections of the active patterns of the third and fourth noise reduction transistors on the substrate.

[0315] In an exemplary embodiment, as shown in FIG. 20 and FIG. 21 , the second output connection portion OUTL3B of the third output signal line has a bar shape extending in the first direction D1 .

[0316] In an exemplary embodiment, as shown in FIG. 20 and FIG. 21 , the second output connection portion OUTL4B of the fourth output signal line has a bar shape extending in the first direction D1 .

[0317] In an exemplary embodiment, as shown in FIG. 20 and FIG. 21 , the second output connection portion OUTL3B of the third output signal line and the second output connection portion OUTL4B of the fourth output signal line are arranged along the second direction D2 and have the same length along the first direction D1 .

[0318] (3) Forming a second insulating layer pattern. In an exemplary embodiment, forming the second insulating layer pattern may include: depositing a second insulating film on the substrate on which the aforementioned pattern is formed, patterning the second insulating film using a patterning process to form a second insulating layer covering the first conductive layer, wherein the second insulating layer is provided with a plurality of vias, as shown in Figures 24 and 25. Figure 24 is a schematic diagram of Figure 9 after the second insulating layer is formed, and Figure 25 is a schematic diagram of Figure 10 after the second insulating layer is formed.

[0319] In an exemplary embodiment, as shown in FIG. 24 , the plurality of via holes in the second insulating layer in FIG. 9 includes first to twenty-ninth via holes V29 .

[0320] In an exemplary embodiment, as shown in FIG. 25 , the plurality of via holes in the second insulating layer in FIG. 10 include first to eleventh via holes V11 , fourteenth to twenty-first via holes V14 to V21 , and twenty-fifth to twenty-ninth via holes V25 to V29 .

[0321] In an exemplary embodiment, the orthographic projection of the first via V1 on the substrate is located within the range of the orthographic projection of the active pattern of the first output transistor on the substrate, the first insulating layer within the first via V1 is etched away to expose the surface of the active pattern of the first output transistor, and the first via V1 is configured to connect the first electrode and the second electrode of the subsequently formed first output transistor to the active pattern of the first output transistor through the via.

[0322] In an exemplary embodiment, the orthographic projection of the second via V2 on the substrate is located within the range of the orthographic projection of the active pattern of the second output transistor on the substrate, the first insulating layer in the second via V2 is etched away to expose the surface of the active pattern of the second output transistor, and the second via V2 is configured to connect the first electrode and the second electrode of the subsequently formed second output transistor to the active pattern of the second output transistor through the via.

[0323] In an exemplary embodiment, the orthographic projection of the third via V3 on the substrate is located within the range of the orthographic projection of the active pattern of the third output transistor on the substrate, the first insulating layer in the third via V3 is etched away to expose the surface of the active pattern of the third output transistor, and the third via V3 is configured to connect the first electrode and the second electrode of the subsequently formed third output transistor to the active pattern of the third output transistor through the via.

[0324] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is located within the range of the orthographic projection of the active pattern of the fourth output transistor on the substrate, the first insulating layer in the fourth via V4 is etched away to expose the surface of the active pattern of the fourth output transistor, and the fourth via V4 is configured to connect the first electrode and the second electrode of the subsequently formed fourth output transistor to the active pattern of the fourth output transistor through the via.

[0325] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the active pattern of the first noise reduction transistor on the substrate, the first insulating layer in the fifth via V5 is etched away to expose the surface of the active pattern of the first noise reduction transistor, and the fifth via V5 is configured to connect the first electrode and the second electrode of the subsequently formed first noise reduction transistor to the active pattern of the first noise reduction transistor through the via.

[0326] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the active pattern of the second noise reduction transistor on the substrate, the first insulating layer in the sixth via V6 is etched away to expose the surface of the active pattern of the second noise reduction transistor, and the sixth via V6 is configured to connect the first electrode and the second electrode of the subsequently formed second noise reduction transistor to the active pattern of the second noise reduction transistor through the via.

[0327] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the active pattern of the third noise reduction transistor on the substrate, the first insulating layer in the seventh via V7 is etched away, exposing the surface of the active pattern of the third noise reduction transistor, and the seventh via V7 is configured to connect the first electrode and the second electrode of the subsequently formed third noise reduction transistor to the active pattern of the third noise reduction transistor through the via.

[0328] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the active pattern of the fourth noise reduction transistor on the substrate, the first insulating layer in the eighth via V8 is etched away, exposing the surface of the active pattern of the fourth noise reduction transistor, and the eighth via V8 is configured to connect the first electrode and the second electrode of the subsequently formed fourth noise reduction transistor to the active pattern of the fourth noise reduction transistor through the via.

[0329] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the second plate of the first output capacitor on the substrate, the ninth via V9 exposes the surface of the second plate of the first output capacitor, and the ninth via V9 is configured to connect the second electrode of the subsequently formed first output transistor to the second plate of the first output capacitor through the via.

[0330] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the substrate is located within the range of the orthographic projection of the second plate of the second output capacitor on the substrate, the tenth via V10 exposes the surface of the second plate of the second output capacitor, and the tenth via V10 is configured to connect the second electrode of the subsequently formed second output transistor to the second plate of the second output capacitor through the via.

[0331] In an exemplary embodiment, the orthographic projection of the eleventh via V11 on the substrate is located within the range of the orthographic projection of the second plate of the third output capacitor on the substrate, the eleventh via V11 exposes the surface of the second plate of the third output capacitor, and the eleventh via V11 is configured to connect the second electrode of the subsequently formed third output transistor to the second plate of the third output capacitor through the via.

[0332] In an exemplary embodiment, in the display substrate provided in FIG9 , the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the second plate of one of the fourth output capacitors on the substrate, the twelfth via V12 exposes the surface of the second plate of one of the fourth output capacitors, and the twelfth via V12 is configured to connect the second electrode of the subsequently formed fourth output transistor to the second plate of one of the fourth output capacitors through the via.

[0333] In an exemplary embodiment, in the display substrate provided in FIG10 , the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the second plate of the fourth output capacitor on the substrate, the twelfth via V12 exposes the surface of the second plate of the fourth output capacitor, and the twelfth via V12 is configured to connect the second electrode of the subsequently formed fourth output transistor to the second plate of the fourth output capacitor through the via.

[0334] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 on the substrate is located within the range of the orthographic projection of the second plate of the other fourth output capacitor on the substrate, the thirteenth via V13 exposes the surface of the second plate of the other fourth output capacitor, and the thirteenth via V13 is configured to connect the second electrode of the subsequently formed fourth output transistor to the second plate of the other fourth output capacitor through the via.

[0335] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the first clock connection line on the substrate, the fourteenth via V14 exposes the surface of the first clock connection line, and the fourteenth via V14 is configured to connect the first electrode of the subsequently formed first output transistor to the first clock connection line through the via.

[0336] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is located within the range of the orthographic projection of the second clock connection line on the substrate, the fifteenth via V15 exposes the surface of the second clock connection line, and the fifteenth via V15 is configured to connect the first electrode of the subsequently formed second output transistor to the second clock connection line through the via.

[0337] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the third clock connection line on the substrate, the sixteenth via V16 exposes the surface of the third clock connection line, and the sixteenth via V16 is configured to connect the first electrode of the subsequently formed third output transistor to the third clock connection line through the via.

[0338] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 on the substrate is located within the range of the orthographic projection of the fourth clock connection line on the substrate, the seventeenth via V17 exposes the surface of the fourth clock connection line, and the seventeenth via V17 is configured to connect the first electrode of the subsequently formed fourth output transistor to the fourth clock connection line through the via.

[0339] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 on the substrate is located within the range of the orthographic projection of the first connecting line on the substrate, the eighteenth via V18 exposes the surface of the first connecting line, and the eighteenth via V18 is configured to connect the second electrode of the subsequently formed first output transistor and the first output signal line to the first connecting line through the via.

[0340] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 on the substrate is located within the range of the orthographic projection of the second connecting line on the substrate, the nineteenth via V19 exposes the surface of the second connecting line, and the nineteenth via V19 is configured to connect the gate electrode of the subsequently formed first noise reduction transistor and the gate electrode of the second noise reduction transistor to the second connecting line.

[0341] In an exemplary embodiment, the orthographic projection of the twentieth via V20 on the substrate is located within the range of the orthographic projection of the third connecting line on the substrate, the twentieth via V20 exposes the surface of the third connecting line, and the twentieth via V20 is configured to connect the gate electrode of the subsequently formed first noise reduction transistor and the gate electrode of the second noise reduction transistor to the third connecting line.

[0342] In an exemplary embodiment, the orthographic projection of the twenty-first via V21 on the substrate is located within the range of the orthographic projection of the fourth connecting line on the substrate, the twenty-first via V21 exposes the surface of the fourth connecting line, and the twenty-first via V21 is configured to connect the second electrode of the subsequently formed second output transistor and the first electrode of the second noise reduction transistor to the fourth connecting line.

[0343] In an exemplary embodiment, the orthographic projection of the twenty-second via V22 on the substrate is located within the range of the orthographic projection of the second output connection portion of the third output signal line on the substrate, the twenty-second via V22 exposes the surface of the second output connection portion of the third output signal line, and the twenty-second via V22 is configured to connect the subsequently formed first output connection portion and the third output connection portion of the third output signal line with the second output connection portion of the third output signal line.

[0344] In an exemplary embodiment, the orthographic projection of the twenty-third via V23 on the substrate is located within the range of the orthographic projection of the second output connection portion of the fourth output signal line on the substrate, the twenty-third via V23 exposes the surface of the second output connection portion of the fourth output signal line, and the twenty-third via V23 is configured to connect the subsequently formed first output connection portion and the third output connection portion of the fourth output signal line with the second output connection portion of the fourth output signal line.

[0345] In an exemplary embodiment, the orthographic projection of the twenty-fourth via V24 on the substrate is located within the range of the orthographic projection of the fifth connecting line on the substrate, the twenty-fourth via V24 exposes the surface of the fifth connecting line, and the twenty-fourth via V24 is configured to connect the gate electrode of the subsequently formed fourth output transistor (which is also the first plate of one of the fourth output capacitors) and the first plate of the other fourth output capacitor to the fifth connecting line.

[0346] In an exemplary embodiment, the orthographic projection of the twenty-fifth via V25 on the substrate is located within the range of the orthographic projection of the sixth connecting line on the substrate, the twenty-fifth via V25 exposes the surface of the sixth connecting line, and the twenty-fifth via V25 is configured to connect the gate electrode of the subsequently formed third noise reduction transistor and the gate electrode of the fourth noise reduction transistor to the sixth connecting line.

[0347] In an exemplary embodiment, the orthographic projection of the twenty-sixth via V26 in Figure 9 on the substrate is located within the range of the orthographic projection of the seventh connecting line on the substrate, the twenty-sixth via V26 exposes the surface of the seventh connecting line, and the twenty-sixth via V26 is configured to connect the second electrode of the subsequently formed fourth output transistor and the first output connection portion of the fourth output signal line to the seventh connecting line.

[0348] In an exemplary embodiment, the orthographic projection of the twenty-sixth via V26 in Figure 10 on the substrate is located within the range of the orthographic projection of the seventh connecting line on the substrate, the twenty-sixth via V26 exposes the surface of the seventh connecting line, and the twenty-sixth via V26 is configured to connect the second electrode of the subsequently formed fourth output transistor and the fourth output signal line to the seventh connecting line.

[0349] In an exemplary embodiment, the orthographic projection of the twenty-seventh via V27 on the substrate is located within the range of the orthographic projection of the eighth connecting line on the substrate, the twenty-seventh via V27 exposes the surface of the eighth connecting line, and the twenty-seventh via V27 is configured to connect the gate electrode of the subsequently formed third noise reduction transistor and the gate electrode of the fourth noise reduction transistor to the eighth connecting line.

[0350] In an exemplary embodiment, the orthographic projection of the twenty-eighth via V28 in Figure 9 on the substrate is located within the range of the orthographic projection of the ninth connecting line on the substrate, the twenty-eighth via V28 exposes the surface of the ninth connecting line, and the twenty-eighth via V28 is configured to connect the first electrode of the subsequently formed third noise reduction transistor and the first output connection portion of the third output signal line to the ninth connecting line.

[0351] In an exemplary embodiment, the orthographic projection of the twenty-eighth via V28 in Figure 10 on the substrate is located within the range of the orthographic projection of the ninth connecting line on the substrate, the twenty-eighth via V28 exposes the surface of the ninth connecting line, and the twenty-eighth via V28 is configured to connect the first electrode and the third output signal line of the subsequently formed third noise reduction transistor to the ninth connecting line.

[0352] In an exemplary embodiment, the orthographic projection of the twenty-ninth via V29 on the substrate is located within the range of the orthographic projection of the ninth connecting line on the substrate, the twenty-ninth via V29 exposes the surface of the ninth connecting line, and the twenty-ninth via V29 is configured to connect the gate electrode of the subsequently formed third output transistor (which is also the first plate of the third output capacitor) and the gate electrode of the second output transistor (which is also the first plate of the first output capacitor) to the ninth connecting line.

[0353] (4) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film through a patterning process, and forming a second conductive layer pattern disposed on the second insulating layer, as shown in Figures 26 to 29, wherein Figure 26 is a schematic diagram of the second conductive layer pattern in Figure 9, Figure 27 is a schematic diagram of Figure 9 after the second conductive layer pattern is formed, Figure 28 is a schematic diagram of the second conductive layer pattern in Figure 10, and Figure 29 is a schematic diagram of Figure 10 after the second conductive layer pattern is formed. In an exemplary embodiment, the second conductive layer may be referred to as a source-drain metal (SD) layer.

[0354] In an exemplary embodiment, as shown in Figures 26 to 29, the second conductive layer pattern includes at least: the gate electrode 512, the first pole 513 and the second pole 514 of the first output transistor to the gate electrode 542, the first pole 543 and the second pole 544 of the fourth output transistor, the gate electrode 612, the first pole 613 and the second pole 614 of the first noise reduction transistor to the gate electrode 642, the first pole 643 and the second pole 644 of the fourth noise reduction transistor, and the first plate OC1-1 of the first output capacitor to the first plate OC4-1 of the fourth output capacitor.

[0355] 26 and 27 , the second conductive layer pattern in FIG. 9 further includes at least first and third output connection portions OUTL3A and OUTL3C of a third output signal line and first and third output connection portions OUTL4A and OUTL4C of a fourth output signal line.

[0356] In an exemplary embodiment, as shown in FIG. 28 and FIG. 29 , the second conductive layer pattern in FIG. 10 further includes at least a third output signal line OUTL3 and a fourth output signal line OUTL4 .

[0357] In the exemplary embodiment, the gate electrode 512 of the first output transistor and the first plate OC1-1 of the first output capacitor in Figures 9 and 10 are integrally formed. The gate electrode 512 of the first output transistor has a ring-shaped structure, with the boundary extending along the second direction D2 forming a bow shape. The first plate OC1-1 of the first output capacitor has a strip shape extending along the second direction D2, with the boundary proximal to the gate electrode 512 forming a bow shape. There are two first plates OC1-1 of the first output capacitor, spaced apart.

[0358] In an exemplary embodiment, the first electrode 513 of the first output transistor in Figures 9 and 10 is disposed within the gate electrode 512 of the first output transistor and may be shaped like a "string." The first electrode 513 of the first output transistor is connected to the active pattern of the first output transistor via a first via and to the first clock connection line via a fourteenth via.

[0359] In the exemplary embodiment, the second electrode 514 of the first output transistor in Figures 9 and 10 is disposed on at least one side of the gate electrode 512 of the first output transistor, and the shape of the second electrode 514 of the first output transistor matches the shape of the gate electrode 512 of the first output transistor. The second electrode 514 of the first output transistor is connected to the active pattern of the first output transistor through a first via, to the first connection line through an eighteenth via, and to the second plate of the first output capacitor through a ninth via.

[0360] In the exemplary embodiment, the gate electrode 522 of the second output transistor and the first plate OC2-1 of the second output capacitor in Figures 9 and 10 are integrally formed. The gate electrode 522 of the second output transistor has a ring-shaped structure, with a boundary extending along the second direction D2 forming a bow shape. The first plate OC2-1 of the second output capacitor has a strip shape extending along the second direction D2, with a boundary proximal to the gate electrode 522 of the second output transistor forming a bow shape. There are two first plates OC2-1 of the second output capacitor, spaced apart. The gate electrode 522 of the second output transistor is connected to the ninth connection line via a twenty-ninth via.

[0361] In an exemplary embodiment, the first electrode 523 of the second output transistor in Figures 9 and 10 is disposed within the gate electrode 522 of the second output transistor and may be shaped like a string. The first electrode 523 of the second output transistor is connected to the active pattern of the second output transistor via a second via and to the second clock connection line via a fifteenth via.

[0362] In the exemplary embodiment, the second electrode 524 of the second output transistor and the second output signal line OUTL2 in Figures 9 and 10 are integrally structured. The second output signal line OUTL2 is linear, extending at least partially along the first direction D1. The second electrode 524 of the second output transistor is disposed on at least one side of the gate electrode 522 of the second output transistor, and the shape of the second electrode 524 of the second output transistor matches the shape of the gate electrode 522 of the second output transistor. The second electrode 524 of the second output transistor is connected to the active pattern of the second output transistor via a second via, connected to the second plate of the second output capacitor via a tenth via, and connected to the fourth connection line via a twenty-first via.

[0363] In the exemplary embodiment, the gate electrode 532 of the third output transistor and the first plate OC3-1 of the third output capacitor in Figures 9 and 10 are integrally formed. The gate electrode 532 of the third output transistor has a ring-shaped structure, with a boundary extending along the second direction D2 forming a bow shape. The first plate OC3-1 of the third output capacitor has a strip shape extending along the second direction D2, with a boundary proximal to the gate electrode 532 of the third output transistor forming a bow shape. There are two first plates OC3-1 of the third output capacitor, spaced apart. The gate electrode 532 of the third output transistor is connected to the ninth connection line via a twenty-ninth via.

[0364] In an exemplary embodiment, the first electrode 533 of the third output transistor in Figures 9 and 10 is disposed within the gate electrode 532 of the third output transistor and may be shaped like a string. The first electrode 533 of the third output transistor is connected to the active pattern of the third output transistor via a third via and to the third clock connection line via a sixteenth via.

[0365] In the exemplary embodiment shown in FIG9 , the second electrode 534 of the third output transistor is integrally formed with the first output connection portion OUTL3A of the third output signal line. The first output connection portion OUTL3A of the third output signal line OUTL3 is linear and extends at least partially along the first direction D1. The second electrode 534 of the third output transistor is disposed on at least one side of the gate electrode 532 of the third output transistor, and the shape of the second electrode 534 of the third output transistor matches the shape of the gate electrode 532 of the third output transistor. The second electrode 534 of the third output transistor is connected to the active pattern of the third output transistor via a third via, to the second plate of the third output capacitor via an eleventh via, to the second output connection portion of the third output signal line via a twenty-second via, and to the ninth connection line via a twenty-eighth via.

[0366] In the exemplary embodiment, in FIG10 , the second electrode 534 of the third output transistor is integrally formed with the third output signal line OUTL3. The third output signal line OUTL3 is linear, extending at least partially along the first direction D1. The second electrode 534 of the third output transistor is disposed on at least one side of the gate electrode 532 of the third output transistor, and the shape of the second electrode 534 of the third output transistor matches the shape of the gate electrode 532 of the third output transistor. The second electrode 534 of the third output transistor is connected to the active pattern of the third output transistor via a third via, and is also connected to the ninth connection line via a twenty-eighth via.

[0367] In the exemplary embodiment shown in FIG9 , the gate electrode 542 of the fourth output transistor and the first plate OC4-1 of one of the fourth output capacitors are integrally formed. The gate electrode 542 of the fourth output transistor has a ring-shaped structure, with its boundary extending along the second direction D2 forming a bow shape. The first plate OC4-1 of one of the fourth output capacitors has a strip shape extending along the second direction D2, with its boundary proximal to the gate electrode 542 forming a bow shape. There are two first plates OC-1 of the fourth output capacitors, spaced apart.

[0368] 9 , the first plate OC4 - 1 of another fourth output capacitor is in a strip shape extending along the first direction D1 and is connected to the gate electrode 542 of the fourth output transistor through a twenty-fourth via.

[0369] In the exemplary embodiment shown in FIG10 , the gate electrode 542 of the fourth output transistor and the first plate OC4-1 of the fourth output capacitor are integrally formed. The gate electrode 542 of the fourth output transistor has a ring-shaped structure, with its boundary extending along the second direction D2 forming a bow shape. One of the first plates OC4-1 of the fourth output capacitor is strip-shaped, extending along the second direction D2, and its boundary near the gate electrode 542 of the fourth output transistor forms a bow shape. There are two first plates OC-1 of the fourth output capacitor, spaced apart.

[0370] In an exemplary embodiment, the first electrode 543 of the fourth output transistor in Figures 9 and 10 is disposed within the gate electrode 542 of the fourth output transistor, and at least a portion thereof may be shaped like a string. The first electrode 543 of the fourth output transistor is connected to the active pattern of the fourth output transistor via a fourth via and to the fourth clock connection line via a seventeenth via.

[0371] In the exemplary embodiment, in FIG9 , the second electrode 544 of the fourth output transistor is disposed on at least one side of the gate electrode 542 of the fourth output transistor, and the shape of the second electrode 544 of the fourth output transistor matches the shape of the gate electrode 542 of the fourth output transistor. The second electrode 544 of the fourth output transistor is connected to the active pattern of the fourth output transistor via a fourth via, connected to the second plate of one of the fourth output capacitors via a twelfth via, connected to the second plate of the other fourth output capacitor via a thirteenth via, and connected to the seventh connection line via a twenty-sixth via.

[0372] In the exemplary embodiment, in FIG10 , the second electrode 544 of the fourth output transistor is disposed on at least one side of the gate electrode 542 of the fourth output transistor, and the shape of the second electrode 544 of the fourth output transistor matches the shape of the gate electrode 542 of the fourth output transistor. The second electrode 544 of the fourth output transistor is connected to the active pattern of the fourth output transistor through a fourth via, is connected to the second plate of the fourth output capacitor through a twelfth via, and is connected to the seventh connection line through a twenty-sixth via.

[0373] 9 and 10 , the gate electrode 612 of the first noise reduction transistor is in a strip shape extending along the first direction. The gate electrode 612 of the first noise reduction transistor is connected to the second connection line through the nineteenth via hole and to the third connection line through the twentieth via hole.

[0374] In an exemplary embodiment, the first electrode 613 of the first noise reduction transistor and the first output signal line OUTL1 in Figures 9 and 10 are integrally structured. The first output signal line OUTL1 is strip-shaped and extends along a first direction. The first electrode 613 of the first noise reduction transistor is connected to the active pattern of the first noise reduction transistor via a fifth via and is connected to the first connection line via an eighteenth via.

[0375] In an exemplary embodiment, the second electrode 614 of the first noise reduction transistor and the second electrode 624 of the second noise reduction transistor in Figures 9 and 10 are integrally formed. The integral structure of the second electrode 614 of the first noise reduction transistor and the second electrode 624 of the second noise reduction transistor includes a ring structure. The integral structure of the second electrode 614 of the first noise reduction transistor and the second electrode 624 of the second noise reduction transistor is connected to the active pattern of the first noise reduction transistor via a fifth via and to the active pattern of the second noise reduction transistor via a sixth via.

[0376] 9 and 10 , the gate electrode 622 of the second noise reduction transistor is in a strip shape extending along the first direction. The gate electrode 622 of the second noise reduction transistor is connected to the second connection line through the nineteenth via hole and to the third connection line through the twentieth via hole.

[0377] In the exemplary embodiment, the first electrode 623 of the second noise reduction transistor in Figures 9 and 10 is provided separately. The first electrode 623 of the second noise reduction transistor includes a ring structure. The first electrode 623 of the second noise reduction transistor is connected to the active pattern of the second noise reduction transistor through a sixth via hole and is connected to the fourth connection line through a twenty-first via hole.

[0378] 9 and 10 , the gate electrode 632 of the third noise reduction transistor is in a strip shape extending along the first direction. The gate electrode 632 of the third noise reduction transistor is connected to the sixth connection line through the twenty-fifth via hole and to the eighth connection line through the twenty-seventh via hole.

[0379] In an exemplary embodiment, the first electrode 633 of the third noise reduction transistor in FIG9 and FIG10 is separately provided as a whole. The first electrode 633 of the third noise reduction transistor is connected to the active pattern of the third noise reduction transistor through the seventh via hole and is connected to the ninth connection line through the twenty-eighth via hole.

[0380] In an exemplary embodiment, the second electrode 634 of the third noise reduction transistor and the second electrode 644 of the fourth noise reduction transistor in Figures 9 and 10 are integrally formed. The integral structure of the second electrode 634 of the third noise reduction transistor and the second electrode 644 of the fourth noise reduction transistor includes a ring structure. The integral structure of the second electrode 634 of the third noise reduction transistor and the second electrode 644 of the fourth noise reduction transistor is connected to the active pattern of the third noise reduction transistor via a seventh via and to the active pattern of the fourth noise reduction transistor via an eighth via.

[0381] 9 and 10 , the gate electrode 642 of the fourth noise reduction transistor is in a strip shape extending along the first direction. The gate electrode 642 of the fourth noise reduction transistor is connected to the sixth connection line through the twenty-fifth via hole and to the eighth connection line through the twenty-seventh via hole.

[0382] In an exemplary embodiment, in FIG9 , the first electrode 643 of the fourth noise reduction transistor and the first output connection portion OUTL4A of the fourth output signal line are integrally formed. This integral structure comprises a ring-shaped structure. The first electrode 643 of the fourth noise reduction transistor is connected to the active pattern of the fourth noise reduction transistor via an eighth via, to the second output connection portion of the fourth output signal line via a twenty-third via, and to the seventh connection line via a twenty-sixth via.

[0383] In an exemplary embodiment, in FIG10 , the first electrode 643 of the fourth noise reduction transistor and the fourth output signal line OUTL are integrally formed. The integral structure of the first electrode 643 of the fourth noise reduction transistor and the fourth output signal line OU4A comprises a ring structure. The first electrode 643 of the fourth noise reduction transistor is connected to the active pattern of the fourth noise reduction transistor via an eighth via.

[0384] In an exemplary embodiment, the third output connection portion OUTL3C of the third output signal line in FIG. 9 is shaped like a bar extending along the first direction D1 and is connected to the second output connection portion of the third output signal line through a twenty-second via hole.

[0385] In an exemplary embodiment, the third output connection portion OUTL3C of the fourth output signal line in FIG. 9 is shaped like a bar extending along the first direction D1 and is connected to the second output connection portion of the fourth output signal line through a twenty-third via hole.

[0386] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0387] In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The first and second flexible material layers may be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The first and second inorganic material layers may be made of silicon nitride (SiNx) or silicon oxide (SiOx) to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers. The semiconductor layer may be made of amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: first coating a layer of polyimide on a glass carrier, and forming a first flexible (PI1) layer after curing; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating the amorphous silicon layer with another layer of polyimide, and forming a second flexible (PI2) layer after curing; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the substrate.

[0388] In exemplary embodiments, the semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer, or may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0389] In an exemplary embodiment, the first conductive layer and the second conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo.

[0390] In an exemplary embodiment, the first insulating layer and the second insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer may be referred to as a gate insulating (GI) layer, and the second insulating layer may be referred to as an interlayer insulating (ILD) layer. The first planarizing layer and the second planarizing layer may be made of an organic material, such as a resin.

[0391] In an exemplary embodiment, after the driving structure layer is prepared, a light emitting structure layer is prepared on the driving structure layer. The preparation process of the light emitting structure layer may include the following operations.

[0392] Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the anode conductive film using a patterning process to form an anode conductive layer disposed on the driving structure layer, wherein the anode conductive layer includes at least a plurality of anode patterns.

[0393] In an exemplary embodiment, the anode conductive layer has a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0394] Forming a pixel definition layer pattern. In an exemplary embodiment, forming the pixel definition layer pattern may include coating a pixel definition film on the substrate having the aforementioned pattern formed thereon, and patterning the pixel definition film using a patterning process to form the pixel definition layer.

[0395] In an exemplary embodiment, the subsequent preparation process may include:

[0396] First, an organic light-emitting layer is formed by an evaporation or inkjet printing process, and then a cathode is formed on the organic light-emitting layer, and then an encapsulation structure layer is formed. The encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0397] The present disclosure also provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc., and the embodiments of the present invention are not limited thereto. In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as an OLED, a quantum dot display (QLED), a light-emitting diode display (Micro LED or Mini LED), or a quantum dot light-emitting diode display (QDLED), etc., and the present disclosure is not limited thereto.

[0398] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0399] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0400] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate, comprising: a first region and a second region, wherein the first region is provided with pixel driving circuits arranged in an array, the second region is provided with a gate driving circuit, the gate driving circuit is configured to provide driving signals to the pixel driving circuits, the gate driving circuit includes: a plurality of shift registers, at least one stage of shift register includes: a pre-stage circuit and a driving output circuit, the pre-stage circuit is electrically connected to a signal input terminal, a reset signal terminal and a cascaded output signal terminal respectively, the driving output circuit is electrically connected to N driving output signal terminals respectively, the signal input terminal of at least one stage of shift register is electrically connected to the cascaded output signal terminal of at least one stage of shift register, and the reset signal terminal of at least one stage of shift register is electrically connected to the cascaded output signal terminal of at least one stage of shift register, the driving output circuit includes: N driving output sub-circuits, the nth driving output sub-circuit is electrically connected to the nth driving output signal terminal, in at least one display frame, the start time of the driving signal output from the Nth driving output signal terminal is later than the start time of the driving signal output from at least one of the first driving signal terminal to the (N - 1)th driving output signal terminal, N>2, 1≤n≤N; the area of the Nth driving output sub-circuit is larger than the area of at least one of the first driving output sub-circuit to the (N - 1)th driving output sub-circuit.

2. The display substrate according to claim 1, comprising: a substrate and a driving structure layer provided on the substrate, the gate driving circuit and the pixel driving circuits are located in the driving structure layer, the driving structure layer includes: a semiconductor layer, a first conductive layer and a second conductive layer stacked in sequence on the substrate, at least one driving output sub-circuit includes: an output transistor, a noise reduction transistor and an output capacitor, the transistor includes: an active pattern, a gate electrode, a first pole and a second pole, and the capacitor includes: a first electrode plate and a second electrode plate; the semiconductor layer at least includes: the active patterns of the output transistor and the noise reduction transistor located in at least one driving output sub-circuit; the first conductive layer at least includes: the second electrode plate of the output capacitor located in at least one driving output sub-circuit; the second conductive layer at least includes; the first electrode plate of the output capacitor located in at least one driving output sub-circuit, the gate electrode, the first pole and the second pole of the output transistor, and the gate electrode, the first pole and the second pole of the noise reduction transistor.

3. The display substrate according to claim 2, wherein, the area of the output transistor in the Nth driving output sub-circuit is larger than the area of the output transistor in at least one of the first driving output sub-circuit to the (N - 1)th driving output sub-circuit, and the area of the output capacitor in the Nth driving output sub-circuit is equal to the area of the output capacitor in at least one of the first driving output sub-circuit to the (N - 1)th driving output sub-circuit.

4. The display substrate according to claim 2, wherein, The aspect ratio of the channel region of the active pattern of the output transistor in the Nth driving output sub-circuit is greater than the aspect ratio of the channel region of the active pattern of the output transistor in at least one of the driving output sub-circuits from the first driving output sub-circuit to the (N - 1)th driving output sub-circuit.

5. The display substrate according to claim 4, wherein, the aspect ratio of the channel region of the active pattern of the output transistor in the first driving output sub-circuit is greater than the aspect ratio of the channel region of the active pattern of the output transistor in at least one of the driving output sub-circuits from the second driving output sub-circuit to the (N - 1)th driving output sub-circuit.

6. The display substrate according to claim 4 or 5, wherein, the aspect ratios of the channel regions of the active patterns of the output transistors in at least two of the driving output sub-circuits from the second driving output sub-circuit to the (N - 1)th driving output sub-circuit are equal.

7. The display substrate according to claim 2, wherein, the area of the output capacitor in the Nth driving output sub-circuit is greater than the area of the output capacitor in at least one of the driving output sub-circuits from the first driving output sub-circuit to the (N - 1)th driving output sub-circuit, and the area of the output transistor in the Nth driving output sub-circuit is equal to the area of the output transistor in at least one of the driving output sub-circuits from the first driving output sub-circuit to the (N - 1)th driving output sub-circuit.

8. The display substrate according to claim 2, wherein, in at least one driving output sub-circuit, at least a part of the gate electrode of the output transistor is a ring structure, at least a part of the first pole of the output transistor is a ring structure, the gate electrode of the output transistor surrounds the first pole of the output transistor, and the second pole of the output transistor is disposed on at least one side of the gate electrode of the output transistor.

9. The display substrate according to claim 2, wherein, in at least one driving output sub-circuit, the output capacitor is located on the side of the output transistor close to the second midline, and the noise reduction transistor is located on the side of the output transistor close to the first midline, where the first midline is the midline extending in the first direction of the area occupied by the driving output circuit, and the second midline is the midline extending in the second direction of the area occupied by the driving output circuit.

10. The display substrate according to claim 3, wherein, N = 4. The output devices in the first drive output sub - circuit and the output devices in the second drive output sub - circuit are symmetrically arranged with respect to the second center line. The output devices in the second drive output sub - circuit and the output devices in the third drive output sub - circuit are symmetrically arranged with respect to the first center line. The output capacitors in the fourth drive output sub - circuit and the output capacitors in the third drive output sub - circuit are symmetrically arranged with respect to the second center line. At least part of the output transistors in the fourth drive output sub - circuit and the output transistors in the third drive output sub - circuit are symmetrically arranged with respect to the second center line. The output capacitors in the fourth drive output sub - circuit and the output capacitors in the first drive output sub - circuit are symmetrically arranged with respect to the first center line. At least part of the output transistors in the fourth drive output sub - circuit and the output transistors in the first drive output sub - circuit are symmetrically arranged with respect to the first center line. The output devices include: output transistors and output capacitors. The first center line is the center line extending along the first direction in the area occupied by the drive output circuit. The second center line is the center line extending along the second direction in the area occupied by the drive output circuit; The noise reduction transistors in the first drive output sub - circuit and the noise reduction transistors in the second drive output sub - circuit are located on the side of the output devices in the first drive output sub - circuit close to the first center line, and the noise reduction transistors in the second drive output sub - circuit are located on the side of the noise reduction transistors in the first drive output sub - circuit close to the first center line. The noise reduction transistors in the third drive output sub - circuit and the noise reduction transistors in the fourth drive output sub - circuit are located on the side of the output devices in the third drive output sub - circuit close to the first center line, and the noise reduction transistors in the third drive output sub - circuit are located on the side of the noise reduction transistors in the fourth drive output sub - circuit close to the first center line; The noise reduction transistors in the first drive output sub - circuit and the noise reduction transistors in the fourth drive output sub - circuit are asymmetrically arranged with respect to the first center line. The noise reduction transistors in the second drive output sub - circuit and the noise reduction transistors in the third drive output sub - circuit are asymmetrically arranged with respect to the first center line.

11. The display substrate according to claim 10, wherein, the area where the drive output circuit is located is divided into a first area and a second area by the second center line; the output devices of the first drive output sub - circuit and the output devices of the fourth drive output sub - circuit are located in the first area, and the output devices of the second drive output sub - circuit and the output devices of the third drive output sub - circuit are located in the second area; the noise reduction transistors of at least one of the first drive output sub - circuit to the fourth drive output sub - circuit are located in the first area and the second area, and the area of the noise reduction transistors located in the first area is smaller than the area of the noise reduction transistors located in the second area; The area of the noise reduction transistors of the first driving output sub - circuit and the second driving output sub - circuit in the first region is larger than the area of the noise reduction transistors of the third driving output sub - circuit and the fourth driving output sub - circuit in the first region, and the area of the noise reduction transistors of the first driving output sub - circuit and the second driving output sub - circuit in the second region is smaller than the area of the noise reduction transistors of the third driving output sub - circuit and the fourth driving output sub - circuit in the second region.

12. The display substrate according to claim 10, wherein, The active pattern of the output transistor of the fourth driving output sub - circuit includes: at least one first active pattern and at least one second active pattern, wherein the length of the first active pattern along the second direction is greater than the length of the second active pattern along the second direction; The first active pattern includes: a first active portion and a second active portion, the first active portion has the same length as the second active pattern along the first direction, and the second active portion is located on the side of the first active portion close to the first mid - line; At least a part of the first active portion of the active pattern of the output transistor of the fourth driving output sub - circuit and the second active pattern are symmetrically arranged with respect to the first mid - line with at least a part of the active pattern of the output transistor of the first driving output sub - circuit, and at least a part of the first active portion of the active pattern of the output transistor of the fourth driving output sub - circuit and the second active pattern are symmetrically arranged with respect to the second mid - line with at least a part of the active pattern of the output transistor of the third driving output sub - circuit.

13. The display substrate according to claim 12, wherein, The first pole of the output transistor of the fourth driving output sub - circuit includes: a first electrode portion and a second electrode portion arranged at intervals; The first electrode portion of the output transistor of the fourth driving output sub - circuit is symmetrically arranged with respect to the first mid - line with the first pole of the output transistor of the first driving output sub - circuit, and the first electrode portion of the output transistor of the fourth driving output sub - circuit is symmetrically arranged with the first pole of the output transistor of the third driving output sub - circuit; The first electrode portion and the second electrode portion include: a closed - loop structure, the positive projection of the first electrode portion on the substrate overlaps at least partially with the positive projections of the first active portion and the second active pattern on the substrate, and the positive projection of the second electrode portion on the substrate overlaps at least partially with the positive projection of the second active portion on the substrate; The area of the first electrode portion is larger than the area of the second electrode portion.

14. The display substrate according to claim 13, wherein, The gate electrode of the output transistor of the fourth driving output sub - circuit includes: a first gate electrode portion and a second gate electrode portion connected to each other; The first gate electrode portion of the gate electrode of the output transistor of the fourth driving output sub - circuit is symmetrically arranged with respect to the first mid - line with the gate electrode of the output transistor of the first driving output sub - circuit, and the first gate electrode portion of the gate electrode of the output transistor of the fourth driving output sub - circuit is symmetrically arranged with respect to the second mid - line with the gate electrode of the output transistor of the third driving output sub - circuit; The first gate electrode portion and the second gate electrode portion include: a closed-loop structure. The orthographic projection of the first gate electrode portion on the substrate at least partially overlaps with the orthographic projections of the first active portion and the second active pattern on the substrate. The orthographic projection of the second gate electrode portion on the substrate at least partially overlaps with the orthographic projection of the second active portion on the substrate. The first gate electrode portion surrounds the first electrode portion, and the second gate electrode portion surrounds the second electrode portion; The area of the first gate electrode portion is larger than the area of the second gate electrode portion.

15. The display substrate according to claim 10, wherein, A virtual straight line extending in the first direction through the noise reduction transistor of the fourth driving output sub-circuit passes through the output transistor of the fourth driving output sub-circuit.

16. The display substrate according to claim 10, wherein, The second region further includes: output connection lines, and the output connection lines include: first to fourth output connection lines; the first driving output sub-circuit is connected to the first output connection line, the second driving output sub-circuit is connected to the second output connection line, the third driving output sub-circuit is connected to the third output connection line, and the fourth driving output sub-circuit is connected to the fourth output connection line; The first output connection line and the second output connection line are located between the output transistor of the first driving output sub-circuit and the noise reduction transistor of the first driving output sub-circuit. The third output connection line and the fourth output connection line are located between the output transistor of the fourth driving output sub-circuit and the noise reduction transistor of the fourth driving output sub-circuit; The first output connection line and the second output connection line extend in the first direction. The third output connection line and the fourth output connection line are in a zigzag shape and at least partially extend in the first direction. The output connection lines are located in the second conductive layer.

17. The display substrate according to claim 16, wherein, At least one of the third output connection line and the fourth output connection line includes: a first output connection portion, a second output connection portion, and a third output connection portion; the first output connection portion and the third output connection portion extend in the first direction, the second output connection portion extends in the second direction, and the second output connection portion is electrically connected to the first output connection portion and the third output connection portion respectively.

18. The display substrate according to claim 7, wherein, N = 4. The first to third driving output sub-circuits include: one output capacitor, and the fourth driving output sub-circuit includes: two output capacitors; The output devices in the first driving output sub - circuit and the output devices in the second driving output sub - circuit are symmetrically arranged with respect to the second center line. The output devices in the second driving output sub - circuit and the output devices in the third driving output sub - circuit are symmetrically arranged with respect to the first center line. The output devices in the fourth driving output sub - circuit and the output devices in the third driving output sub - circuit are symmetrically arranged with respect to the second center line. The output devices in the fourth driving output sub - circuit and the output devices in the first driving output sub - circuit are symmetrically arranged with respect to the first center line. The output devices in the first driving output sub - circuit to the third driving output sub - circuit include: output transistors and output capacitors. The output devices in the fourth driving output sub - circuit include: output transistors and one of the output capacitors. The first center line is the center line extending along the first direction in the area occupied by the driving output circuit. The second center line is the center line extending along the second direction in the area occupied by the driving output circuit; The noise - reducing transistors in the first driving output sub - circuit and the noise - reducing transistors in the second driving output sub - circuit are located on the side of the output devices in the first driving output sub - circuit close to the first center line, and the noise - reducing transistors in the second driving output sub - circuit are located on the side of the noise - reducing transistors in the first driving output sub - circuit close to the first center line. The noise - reducing transistors in the third driving output sub - circuit and the noise - reducing transistors in the fourth driving output sub - circuit are located on the side of the output devices in the third driving output sub - circuit close to the first center line, and the noise - reducing transistors in the third driving output sub - circuit are located on the side of the noise - reducing transistors in the fourth driving output sub - circuit close to the first center line. The other output capacitor in the fourth driving output sub - circuit is located on the side of the output devices in the fourth driving output sub - circuit close to the first center line; The noise - reducing transistors in the first driving output sub - circuit and the noise - reducing transistors in the fourth driving output sub - circuit are symmetrically arranged with respect to the first center line. The noise - reducing transistors in the second driving output sub - circuit and the noise - reducing transistors in the third driving output sub - circuit are symmetrically arranged with respect to the first center line.

19. The display substrate according to claim 18, wherein, the area where the driving output circuit is located is divided into a first area and a second area by the second center line; the output devices of the first driving output sub - circuit, the output devices of the fourth driving output sub - circuit and the other output capacitor are located in the first area, and the output devices of the second driving output sub - circuit and the output devices of the third driving output sub - circuit are located in the second area; The noise - reducing transistors of at least one driving output sub - circuit among the first driving output sub - circuit to the fourth driving output sub - circuit are located in the first area and the second area, and the area of the noise - reducing transistors located in the first area is smaller than the area of the noise - reducing transistors located in the second area.

20. The display substrate according to claim 19, wherein, the area of the noise - reducing transistors located in the second area is in the range of 1 to 3 times the area of the noise - reducing transistors located in the first area.

21. The display substrate according to claim 18, wherein, The second region further includes: output connection lines, where the output connection lines include: a first output connection line to a fourth output connection line; a first driving output sub - circuit is connected to the first output connection line, a second driving output sub - circuit is connected to the second output connection line, a third driving output sub - circuit is connected to the third output connection line, and a fourth driving output sub - circuit is connected to the fourth output connection line; The output connection lines extend along a first direction. The first output connection line and the second output connection line are located between the output device of the first driving output sub - circuit and the noise reduction transistor of the first driving output sub - circuit. The third output connection line and the fourth output connection line are located between the output device of the fourth driving output sub - circuit and the noise reduction transistor of the fourth driving output sub - circuit. Another output capacitor of the fourth driving output sub - circuit and the noise reduction transistor are on the same side of the third output connection line and the fourth output connection line; The first output connection line and the second output connection line are located in the second conductive layer.

22. The display substrate according to claim 21, wherein, At least one of the third output connection line and the fourth output connection line includes: a first output connection portion, a second output connection portion, and a third output connection portion; the first output connection portion, the second output connection portion, and the third output connection portion extend along the first direction, and the second output connection portion is electrically connected to the first output connection portion and the third output connection portion respectively; The first output connection portion and the third output connection portion are located in the second conductive layer, and the second output connection portion is located in the first conductive layer.

23. The display substrate according to claim 2, wherein, The first region is provided with at least one first signal line and at least one second signal line. The pixel driving circuit is electrically connected to the first signal line and the second signal line respectively. The first signal line extends at least partially along the first direction, and the second signal line extends at least partially along the second direction; The first signal line at least includes: a scan signal line, and the second signal line at least includes: a first power line, a sensing signal line, and a data signal line. At least one driving output sub - circuit in the shift register is electrically connected to at least one first signal line; The first signal line is located in the first conductive layer, and the second signal line is located in the second conductive layer.

24. The display substrate according to claim 23, wherein, At least one first signal line includes: a plurality of signal connection lines and a plurality of signal overlapping lines; the plurality of signal connection lines and the plurality of signal overlapping lines are alternately arranged along the first direction; The signal connection lines are arranged along the first direction, and the positive projection of the signal overlapping lines on the substrate overlaps at least partially with the positive projection of at least one second signal line on the substrate; The line width of the signal connection lines of the first signal line connected to at least one of the first driving output sub - circuit to the (N - 1)th driving output sub - circuit in at least one stage of the shift register is smaller than the line width of the signal connection lines of the first signal line connected to the Nth driving output sub - circuit.

25. The display substrate according to claim 24, wherein, ​ For at least one stage of shift registers, the line width of the signal connection line of the first signal line connected in the Nth driving output sub-circuit is in the range of 1.5 to 2 times the line width of the signal connection line of the first signal line connected in at least one driving output sub-circuit among the first driving output sub-circuit to the (N - 1)th driving output sub-circuit.

26. The display substrate according to claim 24, wherein, For at least one stage of shift registers, the signal overlapping line of the first signal line connected in the first driving output sub-circuit to the Nth driving output sub-circuit is in a ring structure; For at least one first signal line, the length of the signal overlapping line in the first direction is greater than the line width of at least one second signal line, and the length of the signal overlapping line in the second direction is greater than the line width of the signal connection line.

27. The display substrate according to claim 24, wherein, For at least one stage of shift registers, the signal overlapping line of the first signal line connected in at least one driving output sub-circuit among the first driving output sub-circuit to the (N - 1)th driving output sub-circuit is in a ring structure; For the first signal line connected in the first driving output sub-circuit to the (N - 1)th driving output sub-circuit, the length of the signal overlapping line in the first direction is greater than the line width of at least one second signal line, and the length of the signal overlapping line in the second direction is greater than the line width of the signal connection line; The signal overlapping line of the first signal line connected in the Nth driving output sub-circuit extends in the first direction, and at least one boundary is in an arc shape, and the average line width of the signal overlapping line of the first signal line connected in the Nth driving output sub-circuit is less than the line width of the signal connection line of the first signal line connected in the Nth driving output sub-circuit.

28. A display substrate, comprising: A first region and a second region, the first region is provided with pixel driving circuits arranged in an array, the second region is provided with a gate driving circuit, the gate driving circuit is configured to provide driving signals to the pixel driving circuits, the gate driving circuit includes: a plurality of shift registers, at least one stage of shift registers includes: a pre-stage circuit and a driving output circuit, the pre-stage circuit is electrically connected to a signal input terminal, a reset signal terminal, and a cascaded output signal terminal respectively, the driving output circuit is electrically connected to N output clock signal terminals respectively, the signal input terminal of at least one stage of shift registers is electrically connected to the cascaded output signal terminal of at least one stage of shift registers, the reset signal terminal of at least one stage of shift registers is electrically connected to the cascaded output signal terminal of at least one stage of shift registers, The driving output circuit includes: N driving output sub-circuits, the nth driving output sub-circuit is electrically connected to the nth output clock signal terminal; The second region is provided with M * N output clock signal lines, at least one output clock signal line extends at least partially in the second direction and is located on the side of the driving output circuit away from the first region, the first output clock signal terminal to the Nth output clock signal terminal of at least one stage of shift registers are electrically connected to N output clock signal lines respectively, M ≥ 2; For at least one - stage shift register, the line width of the output clock signal line connected to the Nth output clock signal terminal is greater than the line width of at least one of the output clock signal lines connected to the first output clock signal terminal to the (N - 1)th output clock signal terminal.

29. The display substrate according to claim 28, further comprises: a substrate and a driving structure layer disposed on the substrate, the gate driving circuit and the pixel driving circuit are located in the driving structure layer, and the driving structure layer includes: a semiconductor layer, a first conductive layer, and a second conductive layer stacked in sequence on the substrate; The output clock signal line is located in the second conductive layer.

30. The display substrate according to claim 28, wherein, the nth output clock signal terminal of at least one - stage shift register is electrically connected to one of the nth output clock signal line, the (N + n)th output clock signal line to the ((M - 1)*N + n)th output clock signal line; The nth output clock signal terminals of adjacent M - stage shift registers are connected to different output clock signal lines.

31. The display substrate according to claim 28, wherein, at least one output clock signal line is provided with vias; the length of the via along the first direction in the output clock signal line connected to at least one of the first output clock signal terminal to the (N - 1)th output clock signal terminal of at least one - stage shift register is less than the length of the via along the first direction in the output clock signal line connected to the Nth output clock signal terminal of at least one - stage shift register; the via - related distance of the output clock signal line connected to at least one of the first output clock signal terminal to the (N - 1)th output clock signal terminal of at least one - stage shift register is equal to the via - related distance of the output clock signal line connected to the Nth output clock signal terminal of at least one - stage shift register, where the via - related distance is the distance between the boundary of the output clock signal line and the boundary of the via of the output clock signal line.

32. The display substrate according to claim 29, wherein, the second region further comprises: a plurality of clock connection lines, the clock connection lines include: a first clock connection line to an Nth clock connection line, and the clock connection lines are located in the first conductive layer; at least one - stage shift register is electrically connected to the connected nth output clock signal line through the nth clock connection line, and the orthographic projection of at least one clock connection line on the substrate at least partially overlaps with the orthographic projection of the via of at least one output clock signal line on the substrate.

33. The display substrate according to claim 28, wherein, The second region further includes: a data unit, electrically connected to output clock signal lines connected to N driving output sub-circuits of at least one stage of shift register, configured to provide a first clock signal to output clock signal lines connected to a second driving output sub-circuit to an (N - 1)-th driving output sub-circuit of at least one stage of shift register, and provide a second clock signal to an output clock signal line connected to the N-th driving output sub-circuit, the first clock signal including: a first rising edge and a first falling edge, the second clock signal including: a second rising edge, a third rising edge, and a second falling edge; In a time period where the first rising edge is located, the voltage of the first clock signal rises from a second voltage to a first voltage, and in a time period where the first falling edge is located, the voltage of the first clock signal falls from the first voltage to the second voltage; In a time period where the second rising edge is located, the voltage of the second clock signal rises from a third voltage to a second voltage, in a time period where the third rising edge is located, the voltage of the second clock signal rises from the second voltage to the first voltage, and in a time period where the second falling edge is located, the voltage of the second clock signal falls from the first voltage to the third voltage; The first voltage is a positive voltage, the second voltage and the third voltage are negative voltages, and an absolute value of the second voltage is less than an absolute value of the third voltage.

34. The display substrate according to claim 33, wherein, the data unit is further configured to provide a third clock signal to an output clock signal line connected to a first driving output sub-circuit of at least one stage of shift register, the third clock signal including: a fourth rising edge, a third falling edge, and a fourth falling edge; In a time period where the fourth rising edge is located, the voltage of the third clock signal rises from the second voltage to a fourth voltage, in a time period where the third falling edge is located, the voltage of the third clock signal falls from the fourth voltage to the first voltage, and in a time period where the fourth falling edge is located, the voltage of the third clock signal falls from the first voltage to the second voltage; The first voltage and the fourth voltage are positive voltages, the second voltage is a negative voltage, and the fourth voltage is greater than the first voltage.

35. The display substrate according to claim 28, wherein, The second region further includes: a data unit, electrically connected to output clock signal lines connected to N driving output sub-circuits of at least one stage of shift register, configured to provide a fourth clock signal to output clock signal lines connected to a second driving output sub-circuit to an (N - 1)-th driving output sub-circuit of at least one stage of shift register, and provide a fifth clock signal to an output clock signal line connected to the N-th driving output sub-circuit; A duration of a time period where a falling edge of the fifth clock signal is located is less than half of a duration of a time period where a falling edge of the fourth clock signal is located.

36. The display substrate according to claim 35, wherein, The data unit is further configured to provide a sixth clock signal to an output clock signal line connected to a first driving output sub-circuit of at least one stage of shift registers; The duration of the time period in which the rising edge of the sixth clock signal is located is less than half of the duration of the time period in which the rising edge of the fourth clock signal is located.

37. A display device, comprising: A display substrate according to any one of claims 1 to 36.

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