Vehicle and car display devices include this display device.

Abstract

The invention relates to a display device for vehicles, in a scheme comprising: a substrate; a photoluminescent component layer arranged on the substrate and comprising pixel electrodes, an organic film, and a common electrode; a pixel-determining film arranged on the substrate and comprising numerous openings exposing a portion of the pixel electrodes; a cladding layer arranged on the photoluminescent component layer; a metal oxide layer arranged on the cladding and overlapping the pixel-determining layer; a light-blocking layer arranged on the metal oxide layer and overlapping the metal oxide layer; and a color filter layer arranged on the light-blocking layer and the cladding layer.

Description

Vehicle display device and vehicle including same

[0001] The present invention relates to a vehicle display device and a vehicle including the same.

[0002] As the information society develops, the demand for display devices for displaying images is increasing in various forms. The display devices may be flat panel displays such as liquid crystal displays (LCDs), field emission displays (FEDs), and light emitting display panels (LEDs). The light emitting display devices may include organic light emitting display devices that include organic light emitting diodes (OLEDs) as light emitting elements, or light emitting diode display devices that include inorganic light emitting diodes (LEDs) as light emitting elements.

[0003] In vehicle display devices, a polarizing plate may be included to prevent outgassing of the organic film inside the display device due to external ultraviolet rays. The polarizing plate may be attached to the outside of the display device, but the manufacturing costs and time required for attaching the polarizing plate can reduce productivity. Therefore, research into vehicle display devices that can omit the polarizing plate is ongoing.

[0004] The problem to be solved by the present invention is to provide a vehicle display device capable of blocking ultraviolet rays without a polarizing plate, and a vehicle including the same.

[0005] The tasks of the present invention are not limited to the tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0006] According to one embodiment of the present invention for solving the above problem, a vehicle display device may include a substrate, a light-emitting element layer disposed on the substrate and including a pixel electrode, an organic film layer, and a common electrode, a pixel definition film disposed on the substrate and including a plurality of openings exposing a portion of the pixel electrode, an encapsulation layer disposed on the light-emitting element layer, a metal oxide layer disposed on the encapsulation layer and overlapping the pixel definition film, a light-shielding layer disposed on the metal oxide layer and overlapping the metal oxide layer, and a color filter layer disposed on the light-shielding layer and the encapsulation layer.

[0007] The metal oxide layer can be in contact with the upper surface of the sealing layer and the lower surface of the light-shielding layer.

[0008] The above metal oxide layer may include at least one selected from titanium oxide, zinc oxide, and tantalum oxide.

[0009] The thickness of the above metal oxide layer may be 10 to 10,000 nm.

[0010] The metal oxide layer may include a plurality of aperture holes overlapping the plurality of openings.

[0011] The size of the aperture hole of the metal oxide layer may be the same as the size of the aperture of the pixel defining film.

[0012] The size of the opening of the metal oxide layer may be larger than the size of the opening of the pixel defining film, and the width of the metal oxide layer may be smaller than the width of the pixel defining film.

[0013] The side of the metal oxide layer is positioned inside the side of the light-shielding layer, and the light-shielding layer can cover the upper surface and the side of the metal oxide layer.

[0014] The above light-shielding layer includes a plurality of holes overlapping the plurality of openings, and the size of the opening holes of the metal oxide layer may be larger than the size of the holes of the light-shielding layer.

[0015] The above light-shielding layer includes a plurality of holes overlapping the plurality of openings, and the size of the opening holes of the metal oxide layer may be smaller than the size of the holes of the light-shielding layer.

[0016] The side of the metal oxide layer protrudes outward from the side of the light-shielding layer, and the width of the metal oxide layer may be greater than the width of the light-shielding layer.

[0017] The above light-shielding layer includes a plurality of holes overlapping the plurality of openings, and the size of the opening holes of the metal oxide layer may be the same as the size of the holes of the light-shielding layer.

[0018] The side edges of the metal oxide layer can be aligned and matched with the side edges of the light-shielding layer.

[0019] The pixel defining film may include a plurality of pixel openings arranged between the pixel electrodes, and the light-blocking layer may include a plurality of pattern openings overlapping the plurality of pixel openings.

[0020] The side of the metal oxide layer is aligned with and coincides with the side of the pixel defining film, and the width of the metal oxide layer may be the same as the width of the pixel defining film.

[0021] In addition, according to one embodiment, a vehicle includes a dashboard and a vehicle display device disposed on the dashboard to display information, wherein the vehicle display device may include a substrate, a light-emitting element layer disposed on the substrate and including a pixel electrode, an organic film layer, and a common electrode, a pixel definition film disposed on the substrate and including a plurality of openings exposing a portion of the pixel electrode, an encapsulation layer disposed on the light-emitting element layer, a metal oxide layer disposed within the encapsulation layer and overlapping the pixel definition film, a light-shielding layer disposed on the encapsulation layer and overlapping the metal oxide layer, and a color filter layer disposed on the light-shielding layer and the encapsulation layer.

[0022] The above sealing layer may include a first sealing layer disposed on the light-emitting element layer, a second sealing layer disposed on the first sealing layer, and a third sealing layer disposed on the second sealing layer.

[0023] The metal oxide layer may be disposed between the second sealing layer and the third sealing layer.

[0024] The metal oxide layer may be disposed between the first sealing layer and the second sealing layer.

[0025] The above metal oxide layer may include at least one selected from titanium oxide, zinc oxide, and tantalum oxide.

[0026] Specific details of other embodiments are included in the detailed description and drawings.

[0027] According to one embodiment, a vehicle display device and a vehicle including the same can reduce light in the ultraviolet wavelength range incident from the outside from reaching a pixel defining film by disposing a metal oxide layer that absorbs light in the ultraviolet wavelength range between an encapsulating layer and a light-shielding layer. Accordingly, deterioration of an organic film layer and oxidation of a common electrode due to outgassing of the pixel defining film can be reduced, thereby reducing pixel shrinkage.

[0028] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects are included in this specification.

[0029] Figure 1 is a perspective view showing a display device according to one embodiment.

[0030] Fig. 2 is a cross-sectional view of the display device of Fig. 1 viewed from the side.

[0031] FIG. 3 is a plan view showing a display layer of a display device according to one embodiment.

[0032] FIG. 4 is a plan view showing a display area of ​​a display panel according to one embodiment.

[0033] Figure 5 is a plan view showing an enlarged view of area A of Figure 4.

[0034] Figure 6 is a cross-sectional view taken along line X1-X1' of Figure 5.

[0035] Figure 7 is a schematic diagram showing the incident path of external light.

[0036] Figure 8 is a plan view showing pixels according to another embodiment.

[0037] Figure 9 is a cross-sectional view taken along line X2-X2' of Figure 8.

[0038] Fig. 10 is a plan view showing pixels according to another embodiment.

[0039] Fig. 11 is a cross-sectional view taken along line X3-X3' of Fig. 10.

[0040] Fig. 12 is a cross-sectional view showing a display device according to another embodiment.

[0041] Fig. 13 is a cross-sectional view showing a display device according to another embodiment.

[0042] Fig. 14 is a cross-sectional view showing each light-emitting area of ​​a display device according to one embodiment.

[0043] Fig. 15 is a plan view showing each light-emitting area of ​​a display device according to one embodiment.

[0044] Fig. 16 is a cross-sectional view taken along line X4-X4' of Fig. 15.

[0045] Fig. 17 is a cross-sectional view showing a portion of a pixel opening of a display device according to one embodiment.

[0046] Fig. 18 is a schematic diagram of a case where a display device according to one embodiment is applied to a vehicle.

[0047] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0048] When an element or layer is referred to as "on" another element or layer, it includes both cases where it is directly above the other element or layer or where there is another layer or material intervening therebetween. Similarly, when an element or layer is referred to as "below," "left," and "right," it includes both cases where it is directly adjacent to the other element or where there is another layer or material intervening therebetween. Like reference numerals throughout the specification refer to like elements.

[0049] Although terms like "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it should be understood that a "first" component referred to below may also be a "second" component within the technical scope of the present invention.

[0050] Hereinafter, embodiments will be described with reference to the attached drawings.

[0051] Figure 1 is a perspective view showing a display device according to one embodiment.

[0052] Referring to FIG. 1, the display device (10) can display a moving image or a still image. The display device (10) may refer to any electronic device that provides a display screen. For example, the display device (10) may include a television, a laptop, a monitor, a billboard, an Internet of Things, a mobile phone, a smart phone, a tablet PC (Personal Computer), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an electronic book, a PMP (Portable Multimedia Player), a navigation system, a game console, a digital camera, a camcorder, a vehicle navigation system, a vehicle dashboard, etc. that provide a display screen. In the present specification, the display device (10) may be a vehicle display device that can be equipped in a vehicle, but is not limited thereto.

[0053] Examples of display devices (10) include inorganic light-emitting diode displays, organic light-emitting diode displays, quantum dot light-emitting diode displays, plasma displays, field emission displays, etc. Hereinafter, as an example of a display device, an organic light-emitting diode display is exemplified, but the present invention is not limited thereto, and if the same technical idea is applicable, it can be applied to other display devices.

[0054] The shape of the display device (10) can be modified in various ways. For example, the display device (10) can have a shape similar to a rectangle having a side in the first direction (DR1) and a side in the second direction (DR2). The corner where the side in the first direction (DR1) and the side in the second direction (DR2) meet can be formed to be rounded to have a curvature, but is not limited thereto and can also be formed at a right angle. The planar shape of the display device (10) is not limited to a rectangle and can be formed similarly to other polygons, circles, or ovals.

[0055] The display device (10) may include a display area (DA) and a non-display area (NDA). The display area (DA) is an area where a screen can be displayed, and the non-display area (NDA) is an area where a screen is not displayed. The display area (DA) may be referred to as an active area, and the non-display area (NDA) may also be referred to as an inactive area. The display area (DA) may generally occupy the center of the display device (10).

[0056] The display device (10) may include a display panel (100), a display driver (200), a circuit board (300), and a touch driver (400).

[0057] The display panel (100) may include a main area (MA) and a sub area (SBA).

[0058] The main area (MA) may include a display area (DA) including pixels that display an image, and a non-display area (NDA) arranged around the display area (DA). The display area (DA) may emit light from a plurality of light-emitting areas or a plurality of aperture areas. For example, the display panel (100) may include a pixel circuit including switching elements, a pixel definition film defining a light-emitting area or an aperture area, and a self-light emitting element.

[0059] For example, the self-luminous element may include, but is not limited to, at least one of an organic light emitting diode (OLED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro light emitting diode (Micro LED).

[0060] The non-display area (NDA) may be an area outside the display area (DA). The non-display area (NDA) may be defined as an edge area of ​​the main area (MA) of the display panel (100). The non-display area (NDA) may include a gate driver (not shown) that supplies gate signals to gate lines, and fan-out lines (not shown) that connect the display driver (200) and the display area (DA).

[0061] The sub-area (SBA) may be an area extending from one side of the main area (MA). The sub-area (SBA) may include a flexible material capable of bending, folding, rolling, etc. For example, when the sub-area (SBA) is bent, the sub-area (SBA) may overlap the main area (MA) in the thickness direction (third direction (DR3)). The sub-area (SBA) may include a display driver (200) and a pad portion connected to a circuit board (300). In another embodiment, the sub-area (SBA) may be omitted, and the display driver (200) and the pad portion may be disposed in the non-display area (NDA).

[0062] The display driver (200) can output signals and voltages for driving the display panel (100). The display driver (200) can supply data voltages to data lines. The display driver (200) can supply power voltage to a power line and supply a gate control signal to a gate driver. The display driver (200) can be formed as an integrated circuit (IC) and mounted on the display panel (100) using a COG (Chip on Glass) method, a COP (Chip on Plastic) method, or an ultrasonic bonding method. For example, the display driver (200) can be placed in the sub-area (SBA) and can overlap with the main area (MA) in the thickness direction by bending the sub-area (SBA). As another example, the display driver (200) can be mounted on a circuit board (300).

[0063] The circuit board (300) may be attached to the pad portion of the display panel (100) using an anisotropic conductive film (ACF). Lead lines of the circuit board (300) may be electrically connected to the pad portion of the display panel (100). The circuit board (300) may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0064] Fig. 2 is a cross-sectional view of the display device of Fig. 1 viewed from the side.

[0065] Referring to FIG. 2, the display panel (100) may include a display layer (DU) and a color filter layer (CFL). The display layer (DU) may include a substrate (SUB), a thin film transistor layer (TFTL), a light emitting element layer (EML), and an encapsulation layer (TFEL).

[0066] The substrate (SUB) may be a base substrate or a base member. The substrate (SUB) may be a flexible substrate capable of bending, folding, rolling, etc. For example, the substrate (SUB) may include a polymer resin such as polyimide (PI), but is not limited thereto. In other embodiments, the substrate (SUB) may include a glass material or a metal material.

[0067] A thin film transistor layer (TFTL) may be disposed on a substrate (SUB). The thin film transistor layer (TFTL) may include a plurality of thin film transistors constituting pixel circuits of pixels. The thin film transistor layer (TFTL) may further include gate lines, data lines, power lines, gate control lines, fan out lines connecting the display driver (200) and the data lines, and lead lines connecting the display driver (200) and the pad portion. Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when the gate driver is formed on one side of the non-display area (NDA) of the display panel (100), the gate driver may include thin film transistors.

[0068] A thin film transistor layer (TFTL) can be arranged in a display area (DA), a non-display area (NDA), and a sub-area (SBA). Thin film transistors, gate lines, data lines, and power lines of each pixel of the thin film transistor layer (TFTL) can be arranged in the display area (DA). Gate control lines and fan-out lines of the thin film transistor layer (TFTL) can be arranged in the non-display area (NDA). Lead lines of the thin film transistor layer (TFTL) can be arranged in the sub-area (SBA).

[0069] An emission layer (EML) may be disposed on a thin film transistor layer (TFTL). The emission layer (EML) may include a plurality of emission elements that emit light, including a first electrode, a second electrode, and an emission layer, and a pixel definition film that defines pixels. The plurality of emission elements of the emission layer (EML) may be disposed in a display area (DA).

[0070] In one embodiment, the light-emitting layer may be an organic light-emitting layer comprising an organic material. The light-emitting layer may include a hole transporting layer, an organic light-emitting layer, and an electron transporting layer. When the first electrode receives a voltage through a thin film transistor of the thin film transistor layer (TFTL) and the second electrode receives a cathode voltage, holes and electrons may move to the organic light-emitting layer through the hole transporting layer and the electron transporting layer, respectively, and combine with each other in the organic light-emitting layer to emit light.

[0071] In other embodiments, the light-emitting device may include a quantum dot light-emitting diode comprising a quantum dot light-emitting layer, an inorganic light-emitting diode comprising an inorganic semiconductor, or a micro light-emitting diode.

[0072] The encapsulation layer (TFEL) can cover the top and side surfaces of the light emitting element layer (EML) and protect the light emitting element layer (EML). The encapsulation layer (TFEL) can include at least one inorganic film and at least one organic film for encapsulating the light emitting element layer (EML).

[0073] A color filter layer (CFL) may be disposed on the encapsulation layer (TFEL). The color filter layer (CFL) may include a plurality of color filters corresponding to each of a plurality of light-emitting regions. Each of the color filters may selectively transmit light of a specific wavelength and block or absorb light of a different wavelength. The color filter layer (CFL) may absorb a portion of light entering from the outside of the display device (10) to reduce light reflected by external light. Therefore, the color filter layer (CFL) may prevent color distortion due to reflection of external light.

[0074] Since the color filter layer (CFL) is placed directly on the encapsulation layer (TFEL), the display device (10) may not require a separate substrate for the color filter layer (CFL). Accordingly, the thickness of the display device (10) may be relatively small.

[0075] FIG. 3 is a plan view showing a display layer of a display device according to one embodiment.

[0076] Referring to FIG. 3, the display layer (DU) may include a display area (DA) and a non-display area (NDA).

[0077] A display area (DA) may be arranged at the center of a display panel (100). A plurality of pixels (PX), a plurality of gate lines (GL), a plurality of data lines (DL), and a plurality of power lines (VL) may be arranged in the display area (DA). Each of the plurality of pixels (PX) may be defined as the smallest unit that emits light.

[0078] A plurality of gate lines (GL) can supply gate signals received from a gate driver (210) to a plurality of pixels (PX). The plurality of gate lines (GL) can extend in a first direction (DR1) and be spaced apart from each other in a second direction (DR2) intersecting the first direction (DR1).

[0079] A plurality of data lines (DL) can supply data voltages received from a display driver (200) to a plurality of pixels (PX). The plurality of data lines (DL) can extend in a second direction (DR2) and be spaced apart from each other in a first direction (DR1).

[0080] A plurality of power lines (VL) can supply a power voltage received from a display driver (200) to a plurality of pixels (PX). Here, the power voltage can be at least one of a driving voltage, an initialization voltage, a reference voltage, and a low-potential voltage. The plurality of power lines (VL) can extend in a second direction (DR2) and be spaced apart from each other in a first direction (DR1).

[0081] A non-display area (NDA) may surround a display area (DA). A gate driver (210), fan-out lines (FOL), and gate control lines (GCL) may be arranged in the non-display area (NDA). The gate driver (210) may generate a plurality of gate signals based on a gate control signal, and may sequentially supply the plurality of gate signals to a plurality of gate lines (GL) in a set order.

[0082] Fan out lines (FOL) can extend from the display driver (200) to the display area (DA). The fan out lines (FOL) can supply data voltages received from the display driver (200) to a plurality of data lines (DL).

[0083] A gate control line (GCL) can extend from the display driver (200) to the gate driver (210). The gate control line (GCL) can supply a gate control signal received from the display driver (200) to the gate driver (210).

[0084] The sub-area (SBA) may include a display driver (200), a pad area (PA), and first and second touch pad areas (TPA1, TPA2).

[0085] The display driver (200) can output signals and voltages for driving the display panel (100) to the fan out lines (FOL). The display driver (200) can supply a data voltage to the data line (DL) through the fan out lines (FOL). The data voltage can be supplied to a plurality of pixels (PX) and can control the brightness of the plurality of pixels (PX). The display driver (200) can supply a gate control signal to the gate driver (210) through the gate control line (GCL).

[0086] The pad area (PA) may be arranged at the edge of the sub area (SBA). The pad area (PA) may be electrically connected to the circuit board (300) using a material such as an anisotropic conductive film or a self-assembly anisotropic conductive paste (SAP). The pad area (PA) may include a plurality of display pad units (DP). The plurality of display pad units (DP) may be connected to a graphic system via the circuit board (300). The plurality of display pad units (DP) may be connected to the circuit board (300) to receive digital video data and supply the digital video data to the display driver (200).

[0087] FIG. 4 is a plan view showing a display area of ​​a display panel according to one embodiment.

[0088] Referring to FIG. 4, the display panel (100) may include a plurality of pixels (PX) arranged in a first direction (DR1) and a second direction (DR2). Each of the pixels (PX) may have a rectangular, square, or rhombus-shaped planar shape. For example, as illustrated in the drawing, each of the pixels (PX) may have a square-shaped planar shape. However, the present invention is not limited thereto, and may have various shapes such as polygons, circles, and ovals on a planar surface.

[0089] Some of the pixels (PX) may emit a first light, other of the pixels (PX) may emit a second light, and other of the pixels (PX) may emit a third light. Here, the first light may be light in a blue wavelength band, the second light may be light in a red wavelength band, and the third light may be light in a green wavelength band. The red wavelength band may be a wavelength band of about 600 nm to 750 nm, the green wavelength band may be a wavelength band of about 480 nm to 560 nm, and the blue wavelength band may be a wavelength band of about 370 nm to 460 nm, but the embodiments of the present specification are not limited thereto. In some embodiments, some of the pixels (PX) may emit white light.

[0090] Each of the pixels (PX) may include at least one of an organic light-emitting element including an organic material, an inorganic light-emitting element including an inorganic semiconductor, a quantum dot light-emitting element including a quantum dot light-emitting layer, and a micro light-emitting diode (micro LED) as a light-emitting element that emits light. Hereinafter, the description is centered on the case where each of the pixels (PX) includes an organic light-emitting element, but the present invention is not limited thereto.

[0091] Fig. 5 is a plan view showing an enlarged view of area A of Fig. 4. Fig. 6 is a cross-sectional view taken along line X1-X1' of Fig. 5. Fig. 7 is a schematic diagram showing the incident path of external light.

[0092] Referring to FIGS. 5 to 7 in conjunction with FIG. 2, a display panel (100) of a display device (10) may include a display layer (DU) and a color filter layer (CFL). The display layer (DU) may include a substrate (SUB), a thin film transistor layer (TFTL), a light emitting element layer (EML), and an encapsulation layer (TFEL). The display panel (100) may include a metal oxide layer (USL) on the encapsulation layer (TFEL), and may include a light-shielding layer (BM) disposed on the metal oxide layer (USL). Color filters (CF1, CF2, CF3) of the color filter layer (CFL) may be disposed on the light-shielding layer (BM).

[0093] The substrate (SUB) may be a base substrate or a base member. The substrate (SUB) may be a flexible substrate capable of bending, folding, rolling, etc. For example, the substrate (SUB) may include a polymer resin such as polyimide (PI), but is not limited thereto. In another example, the substrate (SUB) may include a glass material or a metal material.

[0094] A thin film transistor layer (TFTL) may include a first buffer layer (BF1), a lower metal layer (BML), a second buffer layer (BF2), a thin film transistor (TFT), a gate insulating layer (GI), a first interlayer insulating layer (ILD1), a capacitor electrode (CPE), a second interlayer insulating layer (ILD2), a first connection electrode (CNE1), a first passivation layer (PAS1), a second connection electrode (CNE2), and a second passivation layer (PAS2).

[0095] The first buffer layer (BF1) may be disposed on the substrate (SUB). The first buffer layer (BF1) may include an inorganic film capable of preventing the penetration of air or moisture. For example, the first buffer layer (BF1) may include a plurality of inorganic films alternately laminated.

[0096] A lower metal layer (BML) may be disposed on the first buffer layer (BF1). The lower metal layer (BML) may prevent light incident from below from entering the semiconductor layer (ACT) of the thin film transistor (TFT). The lower metal layer (BML) may be formed as a single layer or multiple layers made of, for example, one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0097] The second buffer layer (BF2) may cover the first buffer layer (BF1) and the lower metal layer (BML). The second buffer layer (BF2) may include an inorganic film capable of preventing the penetration of air or moisture. For example, the second buffer layer (BF2) may include a plurality of inorganic films alternately laminated.

[0098] A thin film transistor (TFT) may be disposed on the second buffer layer (BF2) and may constitute a pixel circuit of each of a plurality of pixels. For example, the thin film transistor (TFT) may be a driving transistor or a switching transistor of the pixel circuit. The thin film transistor (TFT) may include a semiconductor layer (ACT), a source electrode (SE), a drain electrode (DE), and a gate electrode (GE).

[0099] A semiconductor layer (ACT) may be disposed on a second buffer layer (BF2). The semiconductor layer (ACT) may overlap with the lower metal layer (BML) and the gate electrode (GE) in the thickness direction, and may be insulated from the gate electrode (GE) by a gate insulating layer (GI). A portion of the semiconductor layer (ACT) may be formed by conducting a material of the semiconductor layer (ACT) to form a source electrode (SE) and a drain electrode (DE).

[0100] The gate electrode (GE) may be disposed on the gate insulating layer (GI). The gate electrode (GE) may overlap the semiconductor layer (ACT) with the gate insulating layer (GI) interposed therebetween.

[0101] A gate insulating layer (GI) may be disposed on the semiconductor layer (ACT). For example, the gate insulating layer (GI) may cover the semiconductor layer (ACT) and the second buffer layer (BF2), and may insulate the semiconductor layer (ACT) from the gate electrode (GE). The gate insulating layer (GI) may include a contact hole through which the first connection electrode (CNE1) passes.

[0102] The first interlayer insulating layer (ILD1) may cover the gate electrode (GE) and the gate insulating layer (GI). The first interlayer insulating layer (ILD1) may include a contact hole through which the first connection electrode (CNE1) passes. The contact hole of the first interlayer insulating layer (ILD1) may be connected to the contact hole of the gate insulating layer (GI) and the contact hole of the second interlayer insulating layer (ILD2).

[0103] A capacitor electrode (CPE) may be disposed on a first interlayer insulating layer (ILD1). The capacitor electrode (CPE) may overlap with the gate electrode (GE) in the thickness direction. The capacitor electrode (CPE) and the gate electrode (GE) may form electrostatic capacitance.

[0104] The second interlayer insulating layer (ILD2) may cover the capacitor electrode (CPE) and the first interlayer insulating layer (ILD1). The second interlayer insulating layer (ILD2) may include a contact hole through which the first connection electrode (CNE1) passes. The contact hole of the second interlayer insulating layer (ILD2) may be connected to the contact hole of the first interlayer insulating layer (ILD1) and the contact hole of the gate insulating layer (GI).

[0105] A first connection electrode (CNE1) may be disposed on a second interlayer insulating layer (ILD2). The first connection electrode (CNE1) may electrically connect a drain electrode (DE) of a thin film transistor (TFT) to a second connection electrode (CNE2). The first connection electrode (CNE1) may be inserted into a contact hole formed in the second interlayer insulating layer (ILD2), the first interlayer insulating layer (ILD1), and the gate insulating layer (GI) to contact the drain electrode (DE) of the thin film transistor (TFT).

[0106] The first protective layer (PAS1) may cover the first connection electrode (CNE1) and the second interlayer insulating layer (ILD2). The first protective layer (PAS1) may protect the thin film transistor (TFT). The first protective layer (PAS1) may include a contact hole through which the second connection electrode (CNE2) passes.

[0107] The second connection electrode (CNE2) may be disposed on the first protective layer (PAS1). The second connection electrode (CNE2) may electrically connect the first connection electrode (CNE1) and the pixel electrode (AE) of the light emitting element (ED). The second connection electrode (CNE2) may be inserted into a contact hole formed in the first protective layer (PAS1) and may be brought into contact with the first connection electrode (CNE1).

[0108] The second protective layer (PAS2) may cover the second connection electrode (CNE2) and the first protective layer (PAS1). The second protective layer (PAS2) may include a contact hole through which the pixel electrode (AE) of the light-emitting element (ED) passes.

[0109] An emission layer (EML) may be disposed on a thin film transistor layer (TFTL). The emission layer (EML) may include an emission element (ED) and a pixel defining layer (PDL). The emission element (ED) may include a pixel electrode (AE), an organic layer (EL), and a common electrode (CE).

[0110] The pixel electrode (AE) may be disposed on the second passivation layer (PAS2). The pixel electrode (AE) may be disposed to overlap any one of the openings (OPE1, OPE2, OPE3) of the pixel defining layer (PDL). The pixel electrode (AE) may be electrically connected to the drain electrode (DE) of the thin film transistor (TFT) via the first and second connection electrodes (CNE1, CNE2).

[0111] The organic film layer (EL) may be disposed on the pixel electrode (AE). For example, the organic film layer (EL) may be an organic light-emitting layer made of an organic material, but is not limited thereto. When the organic film layer (EL) corresponds to an organic light-emitting layer, when a thin film transistor (TFT) applies a predetermined voltage to the pixel electrode (AE) of the light-emitting element (ED), and the common electrode (CE) of the light-emitting element (ED) receives the common voltage or cathode voltage, holes and electrons may move to the organic film layer (EL) through the hole transport layer and the electron transport layer, respectively, and the holes and electrons may combine with each other in the organic film layer (EL) to emit light.

[0112] The common electrode (CE) may be disposed on the organic film layer (EL). For example, the common electrode (CE) may be implemented in the form of an electrode common to all pixels, without being differentiated for each pixel. The common electrode (CE) may be disposed on the organic film layer (EL) in the first to third emission areas (EA1, EA2, EA3), and may be disposed on the pixel defining layer (PDL) in an area excluding the first to third emission areas (EA1, EA2, EA3).

[0113] The common electrode (CE) can receive a common voltage or a low-potential voltage. When the pixel electrode (AE) receives a voltage corresponding to the data voltage and the common electrode (CE) receives a low-potential voltage, a potential difference is formed between the pixel electrode (AE) and the common electrode (CE), causing the organic light emitting layer (EL) to emit light.

[0114] A pixel defining layer (PDL) may be disposed on a second passivation layer (PAS2) and a portion of a pixel electrode (AE) including a plurality of openings (OPE1, OPE2, OPE3). The pixel defining layer (PDL) may include a first opening (OPE1), a second opening (OPE2), and a third opening (OPE3), and each of the openings (OPE1, OPE2, OPE3) may expose a portion of the pixel electrode (AE).

[0115] Each of the openings (OPE1, OPE2, OPE3) of the pixel defining layer (PDL) can define first to third light emitting areas (EA1, EA2, EA3). For example, the first light emitting area (EA1) can be defined by the first opening (OPE1) of the pixel defining layer (PDL), the second light emitting area (EA2) can be defined by the second opening (OPE2) of the pixel defining layer (PDL), and the third light emitting area (EA3) can be defined by the third opening (OPE3) of the pixel defining layer (PDL).

[0116] In an exemplary embodiment, the areas or sizes of the first to third light-emitting areas (EA1, EA2, EA3) may be the same. In another exemplary embodiment, the areas or sizes of the first to third light-emitting areas (EA1, EA2, EA3) may be different. For example, the area of ​​the first light-emitting area (EA1) may be larger than the areas of each of the second light-emitting area (EA2) and the third light-emitting area (EA3), and the area of ​​the second light-emitting area (EA2) may be larger than the area of ​​the third light-emitting area (EA3). The areas of the light-emitting areas (EA1, EA2, EA3) may vary depending on the sizes of the openings (OPE1, OPE2, OPE3) formed in the pixel defining layer (PDL). Depending on the area of ​​the light-emitting area (EA1, EA2, EA3), the intensity of light emitted from the light-emitting area (EA1, EA2, EA3) can vary, and the color of the screen displayed on the display device (10) can be controlled by adjusting the area of ​​the light-emitting area (EA1, EA2, EA3).

[0117] A pixel defining layer (PDL) can separate and insulate pixel electrodes (AE) of each of a plurality of light emitting elements (ED). The pixel defining layer (PDL) can include a light absorbing material to prevent light reflection. For example, the pixel defining layer (PDL) can include a polyimide (PI)-based binder and a pigment containing a mixture of red, green, and blue. Alternatively, the pixel defining layer (PDL) can include a cardo-based binder resin and a mixture of a lactam black pigment and a blue pigment. Alternatively, the pixel defining layer (PDL) can include carbon black.

[0118] The encapsulation layer (TFEL) is disposed on the common electrode (CE) and can cover a plurality of light-emitting elements (ED). The encapsulation layer (TFEL) can include at least one inorganic film to prevent oxygen or moisture from penetrating the light-emitting element layer (EML). The encapsulation layer (TFEL) can include at least one organic film to protect the light-emitting element layer (EML) from foreign substances such as dust.

[0119] In an exemplary embodiment, the encapsulation layer (TFEL) may include a first encapsulation layer (TFE1), a second encapsulation layer (TFE2), and a third encapsulation layer (TFE3). The first encapsulation layer (TFE1) and the third encapsulation layer (TFE3) may be inorganic encapsulation layers, and the second encapsulation layer (TFE2) disposed therebetween may be an organic encapsulation layer.

[0120] The first encapsulating layer (TFE1) and the third encapsulating layer (TFE3) may each include one or more inorganic insulators. The inorganic insulators may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0121] The second encapsulating layer (TFE2) may include a polymer-based material. Examples of polymer-based materials include acrylic resins, epoxy resins, polyimides, and polyethylene. For example, the organic encapsulating layer (320) may include an acrylic resin, such as polymethyl methacrylate or polyacrylic acid. The second encapsulating layer (TFE2) may be formed by curing a monomer or applying a polymer.

[0122] A light-shielding layer (BM) may be disposed on the encapsulation layer (TFEL). The light-shielding layer (BM) may include a plurality of holes (OPT1, OPT2, OPT3) arranged to overlap the light-emitting areas (EA1, EA2, EA3). For example, a first hole (OPT1) may be arranged to overlap the first light-emitting area (EA1) or the first opening (OPE1). A second hole (OPT2) may be arranged to overlap the second light-emitting area (EA2) or the second opening (OPE2), and a third hole (OPT3) may be arranged to overlap the third light-emitting area (EA3) or the third opening (OPE3). The area or size of each of the holes (OPT1, OPT2, OPT3) may be larger than the area or size of the openings (OPE1, OPE2, OPE3) of the pixel defining layer (PDL). As the holes (OPT1, OPT2, OPT3) of the light-shielding layer (BM) are formed larger than the openings (OPE1, OPE2, OPE3) of the pixel defining layer (PDL), the light emitted from the light-emitting areas (EA1, EA2, EA3) can be viewed by the user not only from the front but also from the side of the display device (10).

[0123] The light-shielding layer (BM) may include a light-absorbing material. For example, the light-shielding layer (BM) may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, but is not limited thereto. The light-shielding layer (BM) may improve the color reproducibility of the display device (10) by preventing visible light from penetrating between the first to third light-emitting areas (EA1, EA2, and EA3) and causing color mixing.

[0124] The color filters (CF1, CF2, CF3) of the color filter layer (CFL) may be arranged on the light-shielding layer (BM). Different color filters (CF1, CF2, CF3) may be arranged to correspond to different light-emitting areas (EA1, EA2, EA3) or openings (OPE1, OPE2, OPE3), and holes (OPT1, OPT2, OPT3) of the light-shielding layer (BM), respectively. The color filters (CF1, CF2, CF3) may include a first color filter (CF1), a second color filter (CF2), and a third color filter (CF3) arranged to correspond to different light-emitting areas (EA1, EA2, EA3), respectively. For example, a first color filter (CF1) may be arranged to correspond to a first light-emitting area (EA1), a second color filter (CF2) may be arranged to correspond to a second light-emitting area (EA2), and a third color filter (CF3) may be arranged to correspond to a third light-emitting area (EA3). In addition, the first color filter (CF1) may be arranged in a first hole (OPT1) of a light-shielding layer (BM), the second color filter (CF2) may be arranged in a second hole (OPT2) of the light-shielding layer (BM), and the third color filter (CF3) may be arranged in a third hole (OPT3) of the light-shielding layer (BM). Each of the color filters (CF1, CF2, CF3) may be arranged to have a larger area in a plan view than the holes (OPT1, OPT2, OPT3) of the light-shielding layer (BM), and some of them may be arranged directly on the light-shielding layer (BM).

[0125] The color filters (CF1, CF2, CF3) may include a colorant such as a dye or pigment that absorbs light of a wavelength other than light of a specific wavelength, and may be arranged to correspond to the color of light emitted from the light-emitting areas (EA1, EA2, EA3). For example, the first color filter (CF1) may be arranged to overlap the first light-emitting area (EA1) and may be a blue color filter that transmits only blue first light. The second color filter (CF2) may be arranged to overlap the second light-emitting area (EA2) and may be a red color filter that transmits only red second light, and the third color filter (CF3) may be arranged to overlap the third light-emitting area (EA3) and may be a green color filter that transmits only green third light.

[0126] The planarization layer (OC) may be disposed on the color filters (CF1, CF2, CF3) to planarize the upper portions of the color filters (CF1, CF2, CF3). The planarization layer (OC) may be a colorless, light-transmitting layer that does not have a color in the visible light band. For example, the planarization layer (OC) may include a colorless, light-transmitting organic material such as an acrylic resin.

[0127] According to one embodiment, the color filters (CF1, CF2, CF3) of the display device (10) may be arranged to overlap with other adjacent color filters (CF1, CF2, CF3) on the light-shielding layer (BM). The color filters (CF1, CF2, CF3) arranged on the light-shielding layer (BM) may be arranged such that two adjacent color filters (CF1, CF2, CF3) completely cover the light-shielding layer (BM). Two adjacent color filters (CF1, CF2, CF3) may be arranged to partially overlap each other on the light-shielding layer (BM). The overlapping of the color filters (CF1, CF2, CF3) can reduce external light reflection by the light-shielding layer (BM), and the overlapping arrangement of the color filters (CF1, CF2, CF3) can be designed to further reduce the external light reflection.

[0128] The display device (10) may be arranged so that the first color filter (CF1) and the second color filter (CF2), which are adjacent to each other, overlap each other on the light-shielding layer (BM), and the second color filter (CF2) and the third color filter (CF3) may also be arranged so as to overlap each other on the light-shielding layer (BM). In the case of the first color filter (CF1) and the third color filter (CF3), which are adjacent to each other, they may also be arranged so as to overlap each other on the light-shielding layer (BM).

[0129] According to one embodiment, a metal oxide layer (USL) may be disposed between an encapsulation layer (TFEL) and a light-shielding layer (BM). The metal oxide layer (USL) may block (e.g., reflect or absorb) light in an ultraviolet wavelength band incident from the outside. When a pixel defining layer (PDL) disposed on an light-emitting element layer (EML) is exposed to light in an ultraviolet wavelength band, outgassing may occur through a chemical reaction. Since the pixel defining layer (PDL) is in direct contact with the pixel electrode (AE), the organic film layer (EL), and the common electrode (CE), a gas generated from the pixel defining layer (PDL) may directly affect the organic film layer (EL) and the common electrode (CE). For example, a gas emitted from the pixel defining layer (PDL) may deteriorate the organic film layer (EL) and oxidize the common electrode (CE). As a result, a pixel shrinkage problem may occur in which the area of ​​each light-emitting area (EA1, EA2, EA3) is reduced.

[0130] In one embodiment, by placing a metal oxide layer (USL) capable of blocking light in the ultraviolet wavelength band between the encapsulation layer (TFEL) and the light-shielding layer (BM), outgassing of the pixel defining layer (PDL) can be prevented, thereby reducing pixel shrinkage.

[0131] The metal oxide layer (USL) may be directly disposed on the encapsulation layer (TFEL). The lower surface of the metal oxide layer (USL) is in contact with the upper surface of the encapsulation layer (TFEL), and may, for example, be in direct contact with the upper surface of the third encapsulation layer (TFE3) of the encapsulation layer (TFEL). In addition, the metal oxide layer (USL) may be directly disposed on the lower surface of the light-shielding layer (BM). The upper surface of the metal oxide layer (USL) may be in direct contact with the lower surface of the light-shielding layer (BM). When the metal oxide layer (USL) is disposed under the light-shielding layer (BM), light incident from the outside can be reflected by the metal oxide layer (USL) and absorbed by the light-shielding layer (BM). Accordingly, it is possible to prevent visibility from being reduced due to reflection of external light.

[0132] The metal oxide layer (USL) can block (e.g., reflect or absorb) light in the ultraviolet wavelength band incident from the outside. The metal oxide layer (USL) can include a metal oxide capable of blocking light in the ultraviolet wavelength band. For example, the metal oxide layer (USL) can include at least one of titanium oxide, zinc oxide, and tantalum oxide. The metal oxide layer (USL) can have a thickness of 10 to 10,000 nm to effectively block light in the ultraviolet wavelength band. Here, when the thickness of the metal oxide layer (USL) is 10 nm or more, the blocking characteristic of light in the ultraviolet wavelength band is excellent, and when the thickness of the metal oxide layer (USL) is 10,000 nm or less, the blocking rate of light in the visible wavelength band can be prevented from increasing.

[0133] The metal oxide layer (USL) may include a plurality of aperture holes (OPU1, OPU2, OPU3) arranged to overlap the light-emitting areas (EA1, EA2, EA3). For example, the first aperture hole (OPU1) may be arranged to overlap the first light-emitting area (EA1) or the first opening (OPE1). The second aperture hole (OPU2) may be arranged to overlap the second light-emitting area (EA2) or the second opening (OPE2), and the third aperture hole (OPU3) may be arranged to overlap the third light-emitting area (EA3) or the third opening (OPE3).

[0134] The area or size of the plurality of aperture holes (OPU1, OPU2, OPU3) of the metal oxide layer (USL) may be the same as the area or size of the light-emitting area (EA1, EA2, EA3) or the plurality of openings (OPE1, OPE2, OPE3). For example, the area or size of the first aperture hole (OPU1) may be the same as the area or size of the first light-emitting area (EA1) or the first opening (OPE1), the area or size of the second aperture hole (OPU2) may be the same as the area or size of the second light-emitting area (EA2) or the second opening (OPE2), and the area or size of the third aperture hole (OPU3) may be the same as the area or size of the third light-emitting area (EA3) or the third opening (OPE3).

[0135] The side of the metal oxide layer (USL) may be aligned with and coincide with the side of the pixel defining layer (PDL). For example, the side of the metal oxide layer (USL) in contact with the first aperture (OPU1) may be aligned with and coincide with the side of the pixel defining layer (PDL) in contact with the first opening (OPE1). In addition, the side of the metal oxide layer (USL) in contact with the second aperture (OPU2) may be aligned with and coincide with the side of the pixel defining layer (PDL) in contact with the second opening (OPE2), and the side of the metal oxide layer (USL) in contact with the third aperture (OPU3) may be aligned with and coincide with the side of the pixel defining layer (PDL) in contact with the third opening (OPE3).

[0136] The width (W1) of the metal oxide layer (USL) may be the same as the width (W2) of the pixel defining layer (PDL). The width (W1) of the metal oxide layer (USL) may refer to the distance between the first aperture hole (OPU1) and the second aperture hole (OPU2), or between the second aperture hole (OPU2) and the third aperture hole (OPU3), or between the third aperture hole (OPU3) and the first aperture hole (OPU1). In addition, the width (W2) of the pixel defining layer (PDL) may refer to the distance between the first opening (OPE1) and the second opening (OPE2), or between the second opening (OPE2) and the third opening (OPE3), or between the third opening (OPE3) and the first opening (OPE1). For example, the width (W1) of the metal oxide layer (USL) between the first aperture hole (OPU1) and the second aperture hole (OPU2) may be the same as the width (W2) of the pixel defining layer (PDL) between the first opening (OPE1) and the second opening (OPE2). In addition, the width (W1) of the metal oxide layer (USL) between the second aperture hole (OPU2) and the third aperture hole (OPU3) may be the same as the width (W2) of the pixel defining layer (PDL) between the second opening (OPE2) and the third opening (OPE3), and the width (W1) of the metal oxide layer (USL) between the third aperture hole (OPU3) and the first aperture hole (OPU1) may be the same as the width (W2) of the pixel defining layer (PDL) between the third opening (OPE3) and the first opening (OPE1).

[0137] The area or size of the plurality of aperture holes (OPU1, OPU2, OPU3) of the metal oxide layer (USL) may be smaller than the area or size of the plurality of holes (OPT1, OPT2, OPT3) of the light-shielding layer (BM). For example, the area or size of the first aperture hole (OPU1) may be smaller than the area or size of the first hole (OPT1), the area or size of the second aperture hole (OPU2) may be smaller than the area or size of the second hole (OPT2), and the area or size of the third aperture hole (OPU3) may be smaller than the area or size of the third hole (OPT3).

[0138] The side of the metal oxide layer (USL) may protrude outwardly relative to the side of the light-shielding layer (BM). For example, the side of the metal oxide layer (USL) in contact with the first opening hole (OPU1) may protrude outwardly relative to the side of the light-shielding layer (BM) in contact with the first hole (OPT1). In addition, the side of the metal oxide layer (USL) in contact with the second opening hole (OPU2) may protrude outwardly relative to the side of the light-shielding layer (BM) in contact with the second hole (OPT2), and the side of the metal oxide layer (USL) in contact with the third opening hole (OPU3) may protrude outwardly relative to the side of the light-shielding layer (BM) in contact with the third hole (OPT3).

[0139] The width (W1) of the metal oxide layer (USL) may be greater than the width (W3) of the light-shielding layer (BM). The width (W3) of the light-shielding layer (BM) may refer to the distance between the first hole (OPT1) and the second hole (OPT2), or between the second hole (OPT2) and the third hole (OPT3), or between the third hole (OPT3) and the first hole (OPT1). For example, the width (W1) of the metal oxide layer (USL) between the first aperture hole (OPU1) and the second aperture hole (OPU2) may be greater than the width (W3) of the light-shielding layer (BM) between the first hole (OPT1) and the second hole (OPT2). Additionally, the width (W1) of the metal oxide layer (USL) between the second aperture hole (OPU2) and the third aperture hole (OPU3) may be greater than the width (W3) of the light-shielding layer (BM) between the second hole (OPT2) and the third hole (OPT3), and the width (W1) of the metal oxide layer (USL) between the third aperture hole (OPU3) and the first aperture hole (OPU1) may be greater than the width (W3) of the light-shielding layer (BM) between the third hole (OPT3) and the first hole (OPT1).

[0140] As described above, the display device (10) according to one embodiment can block light in the ultraviolet wavelength range incident from the outside from reaching the pixel defining layer (PDL) by arranging a metal oxide layer (USL) that absorbs light in the ultraviolet wavelength range between the encapsulating layer (TFE) and the light-shielding layer (BM). Accordingly, deterioration of the organic film layer (EL) and oxidation of the common electrode (CE) due to outgassing of the pixel defining layer (PDL) can be prevented, thereby preventing pixel shrinkage.

[0141] Fig. 8 is a plan view showing pixels according to another embodiment. Fig. 9 is a cross-sectional view taken along line X2-X2' of Fig. 8.

[0142] Referring to FIGS. 8 and 9, the present embodiment differs from the embodiments of FIGS. 5 to 7 described above in that the width (W1) of the metal oxide layer (USL) is equal to the width (W3) of the light-shielding layer (BM) and is smaller than the width (W2) of the pixel defining film (PDL). Hereinafter, descriptions overlapping with the above-described embodiments will be omitted and the differences will be described.

[0143] The area or size of the plurality of aperture holes (OPU1, OPU2, OPU3) of the metal oxide layer (USL) may be larger than the area or size of the light-emitting area (EA1, EA2, EA3) or the plurality of openings (OPE1, OPE2, OPE3). For example, the area or size of the first aperture hole (OPU1) may be larger than the area or size of the first light-emitting area (EA1) or the first opening (OPE1), the area or size of the second aperture hole (OPU2) may be larger than the area or size of the second light-emitting area (EA2) or the second opening (OPE2), and the area or size of the third aperture hole (OPU3) may be larger than the area or size of the third light-emitting area (EA3) or the third opening (OPE3).

[0144] The side of the metal oxide layer (USL) may be arranged inside the side of the pixel defining layer (PDL). For example, the side of the metal oxide layer (USL) in contact with the first aperture (OPU1) may be arranged inside the side of the pixel defining layer (PDL) in contact with the first opening (OPE1). In addition, the side of the metal oxide layer (USL) in contact with the second aperture (OPU2) may be arranged inside the side of the pixel defining layer (PDL) in contact with the second opening (OPE2), and the side of the metal oxide layer (USL) in contact with the third aperture (OPU3) may be arranged inside the side of the pixel defining layer (PDL) in contact with the third opening (OPE3).

[0145] The width (W1) of the metal oxide layer (USL) may be smaller than the width (W2) of the pixel defining layer (PDL). For example, the width (W1) of the metal oxide layer (USL) between the first aperture hole (OPU1) and the second aperture hole (OPU2) may be smaller than the width (W2) of the pixel defining layer (PDL) between the first opening (OPE1) and the second opening (OPE2). Additionally, the width (W1) of the metal oxide layer (USL) between the second aperture (OPU2) and the third aperture (OPU3) may be smaller than the width (W2) of the pixel defining layer (PDL) between the second aperture (OPE2) and the third aperture (OPE3), and the width (W1) of the metal oxide layer (USL) between the third aperture (OPU3) and the first aperture (OPU1) may be smaller than the width (W2) of the pixel defining layer (PDL) between the third aperture (OPE3) and the first aperture (OPE1).

[0146] The area or size of the plurality of aperture holes (OPU1, OPU2, OPU3) of the metal oxide layer (USL) may be the same as the area or size of the plurality of holes (OPT1, OPT2, OPT3) of the light-shielding layer (BM). For example, the area or size of the first aperture hole (OPU1) may be the same as the area or size of the first hole (OPT1), the area or size of the second aperture hole (OPU2) may be the same as the area or size of the second hole (OPT2), and the area or size of the third aperture hole (OPU3) may be the same as the area or size of the third hole (OPT3).

[0147] The side edge of the metal oxide layer (USL) may be aligned and matched with the side edge of the light-shielding layer (BM). For example, the side edge of the metal oxide layer (USL) in contact with the first opening hole (OPU1) may be aligned and matched with the side edge of the light-shielding layer (BM) in contact with the first hole (OPT1). In addition, the side edge of the metal oxide layer (USL) in contact with the second opening hole (OPU2) may be aligned and matched with the side edge of the light-shielding layer (BM) in contact with the second hole (OPT2), and the side edge of the metal oxide layer (USL) in contact with the third opening hole (OPU3) may be aligned and matched with the side edge of the light-shielding layer (BM) in contact with the third hole (OPT3).

[0148] The width (W1) of the metal oxide layer (USL) may be the same as the width (W3) of the light-shielding layer (BM). For example, the width (W1) of the metal oxide layer (USL) between the first aperture hole (OPU1) and the second aperture hole (OPU2) may be the same as the width (W3) of the light-shielding layer (BM) between the first hole (OPT1) and the second hole (OPT2). Additionally, the width (W1) of the metal oxide layer (USL) between the second aperture hole (OPU2) and the third aperture hole (OPU3) may be the same as the width (W3) of the light-shielding layer (BM) between the second hole (OPT2) and the third hole (OPT3), and the width (W1) of the metal oxide layer (USL) between the third aperture hole (OPU3) and the first aperture hole (OPU1) may be the same as the width (W3) of the light-shielding layer (BM) between the third hole (OPT3) and the first hole (OPT1).

[0149] As described above, the display device (10) according to one embodiment can reduce light in the ultraviolet wavelength range incident from the outside from reaching the pixel defining layer (PDL) by arranging a metal oxide layer (USL) that absorbs light in the ultraviolet wavelength range between the encapsulating layer (TFE) and the light-shielding layer (BM). Accordingly, deterioration of the organic film layer (EL) and oxidation of the common electrode (CE) due to outgassing of the pixel defining layer (PDL) can be reduced, thereby reducing the pixel shrinkage phenomenon.

[0150] Fig. 10 is a plan view showing pixels according to another embodiment. Fig. 11 is a cross-sectional view taken along line X3-X3' of Fig. 10.

[0151] Referring to FIGS. 10 and 11, the present embodiment differs from the embodiments of FIGS. 5 to 9 described above in that the width (W1) of the metal oxide layer (USL) is smaller than the width (W3) of the light-shielding layer (BM) and the width (W2) of the pixel defining film (PDL). Hereinafter, descriptions overlapping with the above-described embodiments will be omitted and the differences will be described.

[0152] The metal oxide layer (USL) may be disposed between the encapsulation layer (TFE) and the light-shielding layer (BM). The metal oxide layer (USL) may be disposed between the third encapsulation layer (TFE3) of the encapsulation layer (TFEL) and the light-shielding layer (BM). The light-shielding layer (BM) may cover the metal oxide layer (USL). For example, the light-shielding layer (BM) may be in direct contact with the upper surface and side edges of the metal oxide layer (USL).

[0153] The area or size of the plurality of aperture holes (OPU1, OPU2, OPU3) of the metal oxide layer (USL) may be larger than the area or size of the light-emitting area (EA1, EA2, EA3) or the plurality of openings (OPE1, OPE2, OPE3). For example, the area or size of the first aperture hole (OPU1) may be larger than the area or size of the first light-emitting area (EA1) or the first opening (OPE1), the area or size of the second aperture hole (OPU2) may be larger than the area or size of the second light-emitting area (EA2) or the second opening (OPE2), and the area or size of the third aperture hole (OPU3) may be larger than the area or size of the third light-emitting area (EA3) or the third opening (OPE3).

[0154] The side of the metal oxide layer (USL) may be arranged inside the side of the pixel defining layer (PDL). For example, the side of the metal oxide layer (USL) in contact with the first aperture (OPU1) may be arranged inside the side of the pixel defining layer (PDL) in contact with the first opening (OPE1). In addition, the side of the metal oxide layer (USL) in contact with the second aperture (OPU2) may be arranged inside the side of the pixel defining layer (PDL) in contact with the second opening (OPE2), and the side of the metal oxide layer (USL) in contact with the third aperture (OPU3) may be arranged inside the side of the pixel defining layer (PDL) in contact with the third opening (OPE3).

[0155] The width (W1) of the metal oxide layer (USL) may be smaller than the width (W2) of the pixel defining layer (PDL). For example, the width (W1) of the metal oxide layer (USL) between the first aperture hole (OPU1) and the second aperture hole (OPU2) may be smaller than the width (W2) of the pixel defining layer (PDL) between the first opening (OPE1) and the second opening (OPE2). Additionally, the width (W1) of the metal oxide layer (USL) between the second aperture (OPU2) and the third aperture (OPU3) may be smaller than the width (W2) of the pixel defining layer (PDL) between the second aperture (OPE2) and the third aperture (OPE3), and the width (W1) of the metal oxide layer (USL) between the third aperture (OPU3) and the first aperture (OPU1) may be smaller than the width (W2) of the pixel defining layer (PDL) between the third aperture (OPE3) and the first aperture (OPE1).

[0156] The area or size of the plurality of aperture holes (OPU1, OPU2, OPU3) of the metal oxide layer (USL) may be larger than the area or size of the plurality of holes (OPT1, OPT2, OPT3) of the light-shielding layer (BM). For example, the area or size of the first aperture hole (OPU1) may be larger than the area or size of the first hole (OPT1), the area or size of the second aperture hole (OPU2) may be larger than the area or size of the second hole (OPT2), and the area or size of the third aperture hole (OPU3) may be larger than the area or size of the third hole (OPT3).

[0157] The side of the metal oxide layer (USL) may be arranged inside the side of the light-shielding layer (BM). For example, the side of the metal oxide layer (USL) in contact with the first opening hole (OPU1) may be arranged inside the side of the light-shielding layer (BM) in contact with the first hole (OPT1). In addition, the side of the metal oxide layer (USL) in contact with the second opening hole (OPU2) may be arranged inside the side of the light-shielding layer (BM) in contact with the second hole (OPT2), and the side of the metal oxide layer (USL) in contact with the third opening hole (OPU3) may be arranged inside the side of the light-shielding layer (BM) in contact with the third hole (OPT3).

[0158] The width (W1) of the metal oxide layer (USL) may be smaller than the width (W3) of the light-shielding layer (BM). For example, the width (W1) of the metal oxide layer (USL) between the first aperture hole (OPU1) and the second aperture hole (OPU2) may be smaller than the width (W3) of the light-shielding layer (BM) between the first hole (OPT1) and the second hole (OPT2). Additionally, the width (W1) of the metal oxide layer (USL) between the second aperture hole (OPU2) and the third aperture hole (OPU3) may be smaller than the width (W3) of the light-shielding layer (BM) between the second hole (OPT2) and the third hole (OPT3), and the width (W1) of the metal oxide layer (USL) between the third aperture hole (OPU3) and the first aperture hole (OPU1) may be smaller than the width (W3) of the light-shielding layer (BM) between the third hole (OPT3) and the first hole (OPT1).

[0159] As described above, the display device (10) according to one embodiment can reduce light in the ultraviolet wavelength range incident from the outside from reaching the pixel defining layer (PDL) by arranging a metal oxide layer (USL) that absorbs light in the ultraviolet wavelength range between the encapsulating layer (TFE) and the light-shielding layer (BM). Accordingly, deterioration of the organic film layer (EL) and oxidation of the common electrode (CE) due to outgassing of the pixel defining layer (PDL) can be reduced, thereby reducing the pixel shrinkage phenomenon.

[0160] Fig. 12 is a cross-sectional view showing a display device according to another embodiment.

[0161] Referring to FIG. 12, there is a difference from the embodiments of FIGS. 5 to 11 described above in that the metal oxide layer (USL) is positioned between the second encapsulating layer (TFE2) and the third encapsulating layer (TFE3) of the encapsulating layer (TFE). Hereinafter, descriptions overlapping with the above-described embodiments will be omitted and the differences will be described.

[0162] The metal oxide layer (USL) may be disposed within the encapsulation layer (TFE). Specifically, the metal oxide layer (USL) may be disposed between the second encapsulation layer (TFE2) and the third encapsulation layer (TFE3) of the encapsulation layer (TFE). For example, the metal oxide layer (USL) may be disposed directly on the upper surface of the second encapsulation layer (TFE2) and covered by the third encapsulation layer (TFE3). That is, the third encapsulation layer (TFE3) may cover the metal oxide layer (USL).

[0163] In one embodiment, the metal oxide layer (USL) may be disposed under the third encapsulation layer (TFE3) and adjacent to the pixel defining layer (PDL). That is, by disposing the metal oxide layer (USL) adjacent to the pixel defining layer (PDL), the incident angle of light in the ultraviolet wavelength band incident from the outside can be reduced, thereby reducing the amount of light incident on the pixel defining layer (PDL).

[0164] The metal oxide layer (USL) may overlap with the pixel defining layer (PDL) and may overlap with the light-shielding layer (BM). The metal oxide layer (USL) may include a plurality of aperture holes (OPU1, OPU2, OPU3). As described in FIGS. 5 and 6, the areas or sizes of the plurality of aperture holes (OPU1, OPU2, OPU3) of the metal oxide layer (USL) may be the same as the areas or sizes of the light-emitting areas (EA1, EA2, EA3) or the plurality of openings (OPE1, OPE2, OPE3). In addition, the side edges of the metal oxide layer (USL) may be mutually aligned and matched with the side edges of the pixel defining layer (PDL). The areas or sizes of the plurality of aperture holes (OPU1, OPU2, OPU3) of the metal oxide layer (USL) may be smaller than the areas or sizes of the plurality of holes (OPT1, OPT2, OPT3) of the light-shielding layer (BM).

[0165] Fig. 13 is a cross-sectional view showing a display device according to another embodiment.

[0166] Referring to FIG. 13, there is a difference from the embodiments of FIGS. 5 to 12 described above in that the metal oxide layer (USL) is positioned between the first encapsulating layer (TFE1) and the second encapsulating layer (TFE2) of the encapsulating layer (TFE). Hereinafter, descriptions overlapping with the above-described embodiments will be omitted and the differences will be described.

[0167] The metal oxide layer (USL) may be disposed within the encapsulation layer (TFE). Specifically, the metal oxide layer (USL) may be disposed between the first encapsulation layer (TFE1) and the second encapsulation layer (TFE2) of the encapsulation layer (TFE). For example, the metal oxide layer (USL) may be disposed directly on the upper surface of the first encapsulation layer (TFE1) and covered by the second encapsulation layer (TFE2). That is, the second encapsulation layer (TFE2) may cover the metal oxide layer (USL).

[0168] In one embodiment, the metal oxide layer (USL) may be disposed under the second encapsulation layer (TFE2) and adjacent to the pixel defining layer (PDL). That is, by disposing the metal oxide layer (USL) adjacent to the pixel defining layer (PDL), the incident angle of light in the ultraviolet wavelength band incident from the outside can be reduced, thereby reducing the amount of light incident on the pixel defining layer (PDL).

[0169] The metal oxide layer (USL) may overlap with the pixel defining layer (PDL) and may overlap with the light-shielding layer (BM). The metal oxide layer (USL) may include a plurality of aperture holes (OPU1, OPU2, OPU3). As described in FIGS. 5 and 6, the areas or sizes of the plurality of aperture holes (OPU1, OPU2, OPU3) of the metal oxide layer (USL) may be the same as the areas or sizes of the light-emitting areas (EA1, EA2, EA3) or the plurality of openings (OPE1, OPE2, OPE3). In addition, the side edges of the metal oxide layer (USL) may be mutually aligned and matched with the side edges of the pixel defining layer (PDL). The areas or sizes of the plurality of aperture holes (OPU1, OPU2, OPU3) of the metal oxide layer (USL) may be smaller than the areas or sizes of the plurality of holes (OPT1, OPT2, OPT3) of the light-shielding layer (BM).

[0170] Fig. 14 is a cross-sectional view showing each light-emitting area of ​​a display device according to one embodiment. Fig. 15 is a plan view showing each light-emitting area of ​​a display device according to one embodiment. Fig. 16 is a cross-sectional view taken along line X4-X4' of Fig. 15. Fig. 17 is a cross-sectional view showing a portion of a pixel opening of a display device according to one embodiment.

[0171] In FIG. 16, the lower light-emitting layers (OLE1, OLE2, OLE3) and the upper light-emitting layers (OLE1', OLE2', OLE3') are represented as one layer by the drawing symbol 'OLE', and the common layers formed continuously in each light-emitting area (EA1, EA2, EA3), such as the hole injection layer (HIL), the first hole transport layer (HTL1), the first electron transport layer (ETL1), the charge generation layer (CGL), the second hole transport layer (HTL2), the buffer layer (BUL), and the second electron transport layer (ETL2), are represented as one layer by the drawing symbol 'COL'. In addition, in FIG. 17, the hole injection layer (HIL) and the first hole transport layer (HTL1) are depicted as one layer, the first electron transport layer (ETL1), the charge generation layer (CGL), and the second hole transport layer (HTL2) are depicted as one layer, and the buffer layer (BUL) and the second electron transport layer (ETL2) are depicted as one layer.

[0172] Referring to FIGS. 14 to 17, the present embodiment is different from the embodiments of FIGS. 5 to 13 described above in that pattern openings (OPX1, OPX2, OPX3) of a metal oxide layer (USL) are arranged on pixel openings (POP1, POP2, POP3) arranged on a pixel defining layer (PDL) and a second protective layer (PAS2). Hereinafter, descriptions overlapping with the above-described embodiments will be omitted and the differences will be described.

[0173] Referring to FIG. 14, light emitting elements (ED1, ED2, ED3) are arranged in the first light emitting area (EA1), the second light emitting area (EA2), and the third light emitting area (EA3), respectively, and each light emitting element (ED1, ED2, ED3) may include a pixel electrode (AE), an organic film layer (EL), and a common electrode (CE).

[0174] The organic film layer (ORL) may be formed in a structure in which a plurality of light-emitting layers are overlapped, for example, in a tandem structure. The organic film layer (ORL) may include a first stack (ST1) including lower light-emitting layers (OLE1, OLE2, OLE3), a second stack (ST2) positioned on the first stack (ST1) and including upper light-emitting layers (OLE1', OLE2', OLE3'), and a charge generation layer (CGL) positioned between the first stack (ST1) and the second stack (ST2). The first stack (ST1) and the second stack (ST2) may be positioned to overlap each other.

[0175] The lower light-emitting layers (OLE1, OLE2, OLE3) and the upper light-emitting layers (OLE1', OLE2', OLE3') can be arranged to overlap each other.

[0176] The first lower light-emitting layer (OLE1) and the first upper light-emitting layer (OLE1') can emit light of a first color, for example, blue light. The second lower light-emitting layer (OLE2) and the second upper light-emitting layer (OLE2') can emit light of a second color, for example, red light. The third lower light-emitting layer (OLE3) and the third upper light-emitting layer (OLE3') can emit light of a third color, for example, green light. That is, the light ultimately emitted from the organic film layer (ORL) can be blue light in the first light-emitting area (LA1), red light in the second light-emitting area (LA2), and green light in the third light-emitting area (LA3).

[0177] In some embodiments, the first lower light-emitting layer (OLE1) and the first upper light-emitting layer (OLE1') that emit blue light may each include a host and a dopant. The host is not particularly limited as long as it is a commonly used substance, but for example, Alq3(tris(8-hydroxyquinolino)aluminum), CBP(4,4'-bis(N-carbazolyl)-1,1'-biphenyl), PVK(poly(n-vinylcabazole)), ADN(9,10-di(naphthalene-2-yl)anthracene), TCTA(4,4',4''-Tris(carbazol-9-yl)-triphenylamine), TPBi(1,3,5-tris(N-phenylbenzimidazole-2-yl)benzene), TBADN(3-tert-butyl-9,10-di(naphth-2-yl)anthracene), DSA(distyrylarylene), CDBP(4,4'-bis(9-carbazolyl)-2,2"-dimethyl-biphenyl), MADN (2-Methyl-9,10-bis(naphthalen-2-yl)anthracene) can be used.

[0178] In addition, the first lower light-emitting layer (OLE1) and the first upper light-emitting layer (OLE1') that emit blue light may include a fluorescent material including any one selected from the group consisting of, for example, spiro-DPVBi, spiro-6P, distyryl-benzene (DSB), distyryl-arylene (DSA), polyfluorene (PFO) polymers, and poly(p-phenylene vinylene) polymers. As another example, the first lower light-emitting layer (OLE1) and the first upper light-emitting layer (OLE1') that emit blue light may include a phosphorescent material including an organometallic complex such as (4,6-F2ppy)2Irpic.

[0179] In some embodiments, the second lower light-emitting layer (OLE2) and the second upper light-emitting layer (OLE2') that emit red light may be formed of a phosphorescent material that includes a host material comprising CBP (carbazole biphenyl) or mCP (1,3-bis(carbazol-9-yl)), and a dopant that includes at least one selected from the group consisting of PIQIr(acac)(bis(1-phenylisoquinoline)acetylacetonate iridium), PQIr(acac)(bis(1-phenylquinoline)acetylacetonate iridium), PQIr(tris(1-phenylquinoline)iridium), and PtOEP(octaethylporphyrin platinum), or alternatively, may be formed of a fluorescent material that includes PBD:Eu(DBM)3(Phen) or Perylene, but is not limited thereto.

[0180] In some embodiments, the third lower light-emitting layer (OLE3) and the third upper light-emitting layer (OLE3') that emit green light may include a host material comprising CBP or mCP, and may be formed of a phosphorescent material including a dopant material comprising Ir(ppy)3(fac tris(2-phenylpyridine)iridium), or alternatively, may be formed of a fluorescent material including Alq3(tris(8-hydroxyquinolino)aluminum), but is not limited thereto.

[0181] A charge generation layer (CGL) may be disposed between the first stack (ST1) and the second stack (ST2). The charge generation layer (CGL) may serve to inject charges into each light-emitting layer. The charge generation layer (CGL) may serve to control a charge balance between the first stack (ST1) and the second stack (ST2). The charge generation layer (CGL) may include an n-type charge generation layer (CGL1) and a p-type charge generation layer (CGL2). The p-type charge generation layer (CGL2) may be disposed on the n-type charge generation layer (CGL1) and may be located between the n-type charge generation layer (CGL1) and the second stack (ST2).

[0182] The charge generation layer (CGL) may have a structure in which an n-type charge generation layer (CGL1) and a p-type charge generation layer (CGL2) are joined to each other. The n-type charge generation layer (CGL1) may be arranged closer to the pixel electrode (AE) among the pixel electrode (AE) and the common electrode (CE). The p-type charge generation layer (CGL2) is arranged closer to the common electrode (CE) among the pixel electrode (AE) and the common electrode (CE). The n-type charge generation layer (CGL1) supplies electrons to the lower emitting layers (OLE1, OLE2, OLE3) adjacent to the pixel electrodes (AE1, AE2, AE3), and the p-type charge generation layer (CGL2) supplies holes to the upper emitting layers (OLE1', OLE2', OLE3') included in the second stack (ST2). By placing a charge generation layer (CGL) between the first stack (ST1) and the second stack (ST2) to provide charges to each of the light-emitting layers, the light-emitting efficiency can be increased and the driving voltage can be lowered.

[0183] The first stack (ST1) is disposed on the first pixel electrode (AE1), the second pixel electrode (AE2), and the third pixel electrode (AE3), and may further include a first hole transport layer (HTL1), a first electron block layer (EBL1), and a first electron transport layer (ETL1).

[0184] The first hole transport layer (HTL1) may be disposed on each of the first pixel electrode (AE1), the second pixel electrode (AE2), and the third pixel electrode (AE3). The first hole transport layer (HTL1) serves to facilitate the transport of holes and may include a hole transport material. The hole transport material may include, but is not limited to, carbazole derivatives such as N-phenylcarbazole and polyvinylcarbazole, fluorene derivatives, triphenylamine derivatives such as TPD (N,N'-bis(3-methylphenyl)-N,N'-diphenyl-[1,1-biphenyl]-4,4'-diamine), TCTA (4,4',4"-tris(N-carbazolyl)triphenylamine), NPB (N,N'-di(1-naphthyl)-N,N'-diphenylbenzidine), TAPC (4,4'-Cyclohexylidene bis[N,N-bis(4-methylphenyl)benzenamine]), etc.

[0185] The first electron block layer (EBL1) may be positioned on the first hole transport layer (HTL1) and may be positioned between the first hole transport layer (HTL1) and the lower light-emitting layers (OLE1, OLE2, OLE3). The first electron block layer (EB1) may include a hole transport material and a metal or a metal compound to prevent electrons generated in the lower light-emitting layers (OLE1, OLE2, OLE3) from flowing into the first hole transport layer (HTL1). In some embodiments, the first hole transport layer (HTL1) and the first electron block layer (EBL1) described above may also be formed as a single layer in which the respective materials are mixed.

[0186] The first electron transport layer (ETL1) may be disposed on the lower emitting layers (OLE1, OLE2, OLE3) and may be disposed between the charge generation layer (CGL) and the lower emitting layers (OLE1, OLE2, OLE3). In some embodiments, the first electron transport layer (ETL1) is Alq3 (Tris(8-hydroxyquinolinato)aluminum), TPBi (1,3,5-Tri(1-phenyl-1H-benzo[d]imidazol-2-yl)phenyl), BCP (2,9-Dimethyl-4,7-diphenyl-1,10-phenanthroline), Bphen(4,7-Diphenyl-1,10-phenanthroline), TAZ(3-(4-Biphenylyl)-4-phenyl-5-tert-butylphenyl-1,2,4-triazole), NTAZ(4-(Naphthalen-1-yl)-3,5-diphenyl-4H-1,2,4-triazole), tBu-PBD (2-(4-Biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole), It may include an electron transport material such as BAlq (Bis(2-methyl-8-quinolinolato-N1,O8)-(1,1'-Biphenyl-4-olato)aluminum), Bebq2 (berylliumbis(benzoquinolin-10-olate), ADN (9,10-di(naphthalene-2-yl)anthracene), and mixtures thereof. However, the present invention is not limited to the type of the electron transport material.

[0187] The second stack (ST2) may be disposed on the charge generation layer (CGL) and may further include a second hole transport layer (HTL2), a second electron block layer (EBL2), a buffer layer (BUL), and a second electron transport layer (ETL2).

[0188] The second hole transport layer (HTL2) may be positioned on the charge generation layer (CGL). The second hole transport layer (HTL2) may be formed of the same material as the first hole transport layer (HTL1), or may include one or more materials selected from the materials exemplified as materials included in the first hole transport layer (HTL1). The second hole transport layer (HTL2) may be formed of a single layer or may be formed of multiple layers.

[0189] The second electron block layer (EBL2) may be positioned on the second hole transport layer (HTL2) and may be arranged between the second hole transport layer (HTL2) and the upper light-emitting layers (OLE1', OLE2', OLE3'). The second electron block layer (EBL2) may be made of the same material and the same structure as the first electron block layer (EBL1), or may include one or more materials selected from the materials exemplified as the materials included in the first electron block layer (EBL1).

[0190] The second electron transport layer (ETL2) may be disposed on the upper light-emitting layers (OLE1', OLE2', OLE3') and may be disposed between the upper light-emitting layers (OLE1', OLE2', OLE3') and the common electrode (CE). The second electron transport layer (ETL2) may be formed of the same material and the same structure as the first electron transport layer (ETL1), or may include one or more materials selected from the materials exemplified as the materials included in the first electron transport layer (ETL1). The second electron transport layer (ETL2) may be formed of a single layer or may be formed of a plurality of layers.

[0191] A buffer layer (BUL) may be disposed between the upper light-emitting layers (OLE1', OLE2', OLE3') and the second electron transport layer (ETL2). The buffer layer (BUL) may prevent holes from flowing from the upper light-emitting layers (OLE1', OLE2', OLE3') to the common electrode (CE). The buffer layer (BUL) may include, but is not limited to, materials having hole properties, for example, a hole transport layer material.

[0192] Although not shown in the drawing, a hole injection layer may be further disposed between the first stack (ST1) and the first pixel electrode (AE1), the second pixel electrode (AE2), and the third pixel electrode (AE3), and between the second stack (ST2) and the charge generation layer (CGL1). The hole injection layer may serve to inject holes more smoothly into the lower light-emitting layers (OLE1, OLE2, OLE3) and the upper light-emitting layers (OLE1', OLE2', OLE3'). In some embodiments, the hole injection layer may be formed of, but is not limited to, one or more selected from the group consisting of cupper phthalocyanine (CuPc), poly(3,4)-ethylenedioxythiophene (PEDOT), polyaniline (PANI), and N,N-dinaphthyl-N,N'-diphenyl benzidine (NPD).

[0193] In addition, although not shown in the drawing, an electron injection layer may be further positioned between the second electron transport layer (ETL2) and the common electrode (CE), and between the charge generation layer (CGL) and the first stack (ST1). The electron injection layer serves to facilitate the injection of electrons, and may be formed of, but is not limited to, Alq3 (tris(8-hydroxyquinolino)aluminum), PBD, TAZ, spiro-PBD, BAlq, or SAlq. In addition, the electron injection layer may be a metal halide compound, and may be formed of, but is not limited to, one or more selected from the group consisting of, for example, MgF2, LiF, NaF, KF, RbF, CsF, FrF, LiI, NaI, KI, RbI, CsI, FrI, and CaF2. In addition, the electron injection layer may include a lanthanide material such as Yb, Sm, or Eu. Alternatively, the electron injection layer may simultaneously include a metal halide material and a lanthanide material, such as RbI:Yb, KI:Yb, etc. When the electron injection layer includes both a metal halide material and a lanthanide material, the electron injection layer may be formed by co-deposition of the metal halide material and the lanthanide material.

[0194] In the above-described Fig. 14, the charge generation layer (CGL) may be a common layer that is continuously arranged and extends to a plurality of light-emitting areas (EA1, EA2, EA3). For example, in Fig. 14, the charge generation layer (CGL) may be a common layer that is continuously arranged in the first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3). The charge generation layer (CGL) may play a role in generating and transferring electrons and holes that contribute to actual light emission. When the charge generation layer (CGL) is a common layer, a leakage current may be generated in which charges (electrons and holes) generated in an adjacent light-emitting area are transferred to the adjacent light-emitting area. In this case, light emission due to the leakage current may occur in an light-emitting area that should not emit light, resulting in color mixing or undesired gradation.

[0195] In this embodiment, pixel openings (POP1, POP2, POP3) that can increase the movement path of charges by partially short-circuiting the charge generation layer (CGL) between each light-emitting area (EA1, EA2, EA3) are formed to reduce leakage current, and unnecessary metal oxide layers (USL) can be omitted by forming pattern openings (OPX1, OPX2, OPX3) in the metal oxide layer (USL).

[0196] As illustrated in FIGS. 15 to 17, the second protective layer (PAS2) and the pixel defining layer (PDL) may include a plurality of pixel openings (POP1, POP2, POP3). The plurality of pixel openings (POP1, POP2, POP3) may be arranged between the first to third light-emitting areas (EA1, EA2, EA3) and may be arranged so as not to overlap with the first to third light-emitting areas (EA1, EA2, EA3). The plurality of pixel openings (POP1, POP2, POP3) may be arranged so as to overlap with the light-blocking layer (BM). In the present embodiment, the plurality of pixel openings (POP1, POP2, POP3) are illustrated as being arranged between each of the first to third light-emitting areas (EA1, EA2, EA3), but this is not limited thereto, and some may be omitted. The plurality of pixel apertures (POP1, POP2, POP3) may include a first pixel aperture (POP1) positioned between a first light-emitting area (EA1) and a second light-emitting area (EA2), a second pixel aperture (POP2) positioned between a second light-emitting area (EA2) and a third light-emitting area (EA3), and a third pixel aperture (POP3) positioned between a third light-emitting area (EA3) and the first light-emitting area (EA1).

[0197] In the plurality of pixel openings (POP1, POP2, POP3), common layers of the organic film layer (EL) can be separated. The pixel defining layer (PDL) and the second passivation layer (PAS2) are layers made of organic materials and can be formed to have a very thick thickness compared to layers made of inorganic materials. For example, the pixel defining layer (PDL) and the second passivation layer (PAS2) can be formed to have a thickness of about several micrometers. The side edges of the plurality of pixel openings (POP1, POP2, POP3) formed in the pixel defining layer (PDL) and the second passivation layer (PAS2) are formed to have a very large taper, so that common layers made of very thin thicknesses, such as a hole injection layer (HIL), a first hole transport layer (HTL1), a first electron transport layer (ETL1), a charge generation layer (CGL), a second hole transport layer (HTL2), a buffer layer (BUL), and a second electron transport layer (ETL2), can be separated. Accordingly, by separating the common layers in multiple pixel apertures (POP1, POP2, POP3), leakage current in which charges (electrons and holes) generated in adjacent light-emitting regions are transferred to adjacent light-emitting regions can be reduced.

[0198] A light-shielding layer (BM) may be disposed on the encapsulation layer (TFEL). The light-shielding layer (BM) may include a plurality of pattern openings (OPX1, OPX2, OPX3) arranged to overlap a plurality of pixel openings (POP1, POP2, POP3). The plurality of pattern openings (OPX1, OPX2, OPX3) may be arranged between each of the light-emitting areas (EA1, EA2, EA3) and may be arranged to overlap the light-shielding layer (BM). For example, a first pattern opening (OPX1) may be arranged to overlap a first pixel opening (POP1). A second pattern opening (OPX2) may be arranged to overlap a second pixel opening (POP2), and a third pattern opening (OPX3) may be arranged to overlap a third pixel opening (POP3).

[0199] The area or size of each pattern opening (OPX1, OPX2, OPX3) may be the same as the area or size of each pixel opening (POP1, POP2, POP3). For example, the area or size of the first pattern opening (OPX1) may be the same as the area or size of the first pixel opening (POP1), the area or size of the second pattern opening (OPX2) may be the same as the area or size of the second pixel opening (POP2), and the area or size of the third pattern opening (OPX3) may be the same as the area or size of the third pixel opening (POP3).

[0200] In some embodiments, the area or size of each pattern opening (OPX1, OPX2, OPX3) may be larger than the area or size of each pixel opening (POP1, POP2, POP3). Furthermore, in some embodiments, the area or size of each pattern opening (OPX1, OPX2, OPX3) may be smaller than the area or size of each pixel opening (POP1, POP2, POP3).

[0201] As described above, the display device (10) according to one embodiment can reduce leakage current by forming pixel openings (POP1, POP2, POP3) formed in the pixel defining film (PDL) and the second passivation layer (PAS2) between the respective light-emitting areas (EA1, EA2, EA3). In addition, by forming pattern openings (OPX1, OPX2, OPX3) of the metal oxide layer (USL) overlapping the pixel openings (POP1, POP2, POP3), unnecessary metal oxide layers (USL) can be omitted.

[0202] Fig. 18 is a schematic diagram of a case where a display device according to one embodiment is applied to a vehicle.

[0203] Referring to FIG. 18, a display device (10) according to one embodiment may be, for example, a display device applied to a vehicle. The vehicle may include a body forming the exterior of the vehicle and an interior space defined by the body. The body may include a windshield (W) that protects the driver and passengers from the outside and provides the driver with a field of vision. The display device (10), as illustrated in FIG. 18, may be provided in the interior space.

[0204] In one embodiment, the display device (10) may be placed on a dashboard provided in the interior space. For example, the display device (10) may be placed on the dashboard in front of the driver's seat to provide the driver with speed information, etc., placed on the dashboard in front of the passenger seat to provide the passenger with entertainment information, etc., or placed in the center of the dashboard to provide map information, etc. FIG. 18 exemplarily illustrates a display device (10) placed on the dashboard in front of the driver's seat and a driver viewing the display screen of the display device (10). The driver can recognize (or view) the display screen of the display device (10) through light (LGT1) emitted from the display device (10) toward the driver.

[0205] The display device (10) may be exposed to light (UV) in the ultraviolet wavelength band from the outside or inside of the vehicle. As shown in FIGS. 5 to 17 described above, the display device (10) includes a metal oxide layer (USL) overlapping the pixel defining film (PDL), thereby blocking light (UV) in the ultraviolet wavelength band incident from the outside from entering the pixel defining film (PDL). Accordingly, deterioration of the organic film layer (EL) and oxidation of the common electrode (CE) due to outgassing of the pixel defining film (PDL) can be reduced, thereby reducing the pixel shrinkage phenomenon.

[0206] Although embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

Claims

1. Substrate; A light-emitting element layer disposed on the substrate and including a pixel electrode, an organic film layer, and a common electrode; A pixel defining film disposed on the substrate and including a plurality of openings exposing a portion of the pixel electrode; An encapsulating layer disposed on the light emitting element layer; A metal oxide layer disposed on the above encapsulating layer and overlapping the pixel defining film; A light-shielding layer disposed on the metal oxide layer and overlapping the metal oxide layer; and A vehicle display device including a color filter layer disposed on the above light-shielding layer and the above sealing layer.

2. In paragraph 1, A vehicle display device in which the metal oxide layer is in contact with the upper surface of the sealing layer and the lower surface of the light-shielding layer.

3. In paragraph 1, A vehicle display device, wherein the metal oxide layer comprises at least one selected from titanium oxide, zinc oxide, and tantalum oxide.

4. In paragraph 1, A vehicle display device wherein the thickness of the metal oxide layer is 10 to 10,000 nm.

5. In paragraph 1, A vehicle display device, wherein the metal oxide layer includes a plurality of aperture holes overlapping the plurality of openings.

6. In paragraph 5, A vehicle display device in which the size of the opening of the metal oxide layer is the same as the size of the opening of the pixel defining film.

7. In paragraph 5, A vehicle display device wherein the size of the opening of the metal oxide layer is larger than the size of the opening of the pixel defining film, and the width of the metal oxide layer is smaller than the width of the pixel defining film.

8. In paragraph 7, A vehicle display device in which the side of the metal oxide layer is positioned closer to the side of the light-shielding layer, and the light-shielding layer covers the upper surface and the side of the metal oxide layer.

9. In paragraph 7, The above-mentioned shading layer includes a plurality of holes overlapping the plurality of openings, A vehicle display device in which the size of the opening of the metal oxide layer is larger than the size of the hole of the light-shielding layer.

10. In paragraph 5, The above-mentioned shading layer includes a plurality of holes overlapping the plurality of openings, A vehicle display device in which the size of the opening of the metal oxide layer is smaller than the size of the hole of the light-shielding layer.

11. In Article 10, A vehicle display device, wherein the side of the metal oxide layer protrudes outward more than the side of the light-shielding layer, and the width of the metal oxide layer is larger than the width of the light-shielding layer.

12. In paragraph 5, The above-mentioned shading layer includes a plurality of holes overlapping the plurality of openings, A vehicle display device wherein the size of the opening of the metal oxide layer is the same as the size of the hole of the light shielding layer.

13. In paragraph 12, A vehicle display device in which the side of the metal oxide layer is mutually aligned and coincides with the side of the light-shielding layer.

14. In paragraph 1, A vehicle display device wherein the pixel defining film includes a plurality of pixel openings arranged between the pixel electrodes, and the light shielding layer includes a plurality of pattern openings overlapping the plurality of pixel openings.

15. In paragraph 1, A vehicle display device, wherein the side edges of the metal oxide layer are mutually aligned and coincide with the side edges of the pixel defining film, and the width of the metal oxide layer is the same as the width of the pixel defining film.

16. A vehicle including a dashboard and a vehicle display device arranged on the dashboard to display information, The above vehicle display device, substrate; A light-emitting element layer disposed on the substrate and including a pixel electrode, an organic film layer, and a common electrode; A pixel defining film disposed on the substrate and including a plurality of openings exposing a portion of the pixel electrode; An encapsulating layer disposed on the light emitting element layer; A metal oxide layer disposed within the encapsulating layer and overlapping the pixel defining film; A light-shielding layer disposed on the above sealing layer and overlapping the metal oxide layer; and A vehicle comprising a color filter layer disposed on the above light-shielding layer and the above sealing layer.

17. In paragraph 16, A vehicle in which the sealing layer includes a first sealing layer disposed on the light-emitting element layer, a second sealing layer disposed on the first sealing layer, and a third sealing layer disposed on the second sealing layer.

18. In paragraph 17, A vehicle in which the metal oxide layer is disposed between the second sealing layer and the third sealing layer.

19. In paragraph 17, A vehicle in which the metal oxide layer is disposed between the first sealing layer and the second sealing layer.

20. In paragraph 16, A vehicle wherein the metal oxide layer comprises at least one selected from titanium oxide, zinc oxide, and tantalum oxide.

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