DISPLAY PANELS AND DISPLAY EQUIPMENT

Abstract

The invention relates to a display panel and display device. The display panel comprises: a second display area; multiple sub-pixels, located within the second display area, each pixel in the multiple sub-pixels comprising a luminous detail and a pixel circuit supplying control current to the luminous detail; a first power line, configured to supply the first voltage signal to the pixel circuit, the first power line comprising fifth and sixth conductors, each wire in the multiple fifth conductors extending along the first direction, multiple fifth conductors spaced apart along the second direction, and each wire in the multiple sixth conductors extending along the second direction, multiple sixth conductors spaced apart along the first direction, multiple fifth and sixth conductors placed in different layers. Thanks to the display panel, the grid structure of the first power line can be more stable, and the voltage drop on the first power line is reduced, so that the brightness uniformity of the display panel is better.

Description

Display panel and display device

[0001] This disclosure claims priority to Chinese Patent Application No. 202010621890.3, filed on June 30, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] At least one embodiment of this disclosure relates to a display panel and a display device. Background Technology

[0003] Under-display camera designs typically include high pixel density (Pixels Per Inch, PPI) areas and low PPI areas. However, the light transmittance of low PPI areas in typical display panels is low, which is not conducive to improving the display effect of the camera in the imaging area.

[0004] Summary of the Invention

[0005] This disclosure provides at least one embodiment of a display panel, comprising: a first display area; a second display area, at least located on one side of the first display area; a plurality of sub-pixels located in the first display area and the second display area, wherein the density of the sub-pixels in the first display area is less than the density of the sub-pixels in the second display area, each sub-pixel including a pixel circuit; a plurality of pixel groups located in the first display area, at least one of the plurality of pixel groups including at least two sub-pixels; and a first power line configured to provide a first voltage signal to the pixel circuit, the first power line including a plurality of first conductors and a plurality of second conductors, the plurality of first conductors extending from the second display area to the first display area and electrically connected to the plurality of pixel groups, the plurality of second conductors located in the first display area and between adjacent first conductors, the plurality of second conductors extending along a first direction, adjacent second conductors being spaced apart from each other along the first direction, the plurality of second conductors being electrically connected to the plurality of pixel groups; at least one of the plurality of first conductors including a first sub-trace extending along the first direction and a second sub-trace extending along a second direction, the first direction and the second direction intersecting, the second sub-trace being electrically connected to at least one of the plurality of second conductors.

[0006] For example, in a display panel provided in at least one embodiment of this disclosure, the at least two sub-pixels include a first sub-pixel and a second sub-pixel, the first sub-pixel and the second sub-pixel are arranged along the first direction, at least one of the plurality of second wires is electrically connected to the first sub-pixel and the second sub-pixel, and the second sub-trace is located on a different layer from the plurality of second wires.

[0007] For example, in a display panel provided in at least one embodiment of this disclosure, the sub-pixel further includes a light-emitting element, the pixel circuit includes a first transistor, a second transistor and a storage capacitor, the first transistor is connected to the second transistor, the second transistor is connected to the light-emitting element, the first transistor includes a first active portion and a second active portion, and the first active portion and the second active portion are connected through a conductive portion.

[0008] For example, in a display panel provided in at least one embodiment of this disclosure, the second conductor further includes a connecting arm, the connecting arm and the conductive portion of a sub-pixel in the pixel group that overlaps with the second conductor are spaced apart from each other in a third direction and partially overlap in the third direction, the third direction being perpendicular to the first direction and perpendicular to the second direction.

[0009] For example, in a display panel provided in at least one embodiment of this disclosure, the connecting arm has a C-shaped shape.

[0010] For example, in a display panel provided in at least one embodiment of this disclosure, the plurality of pixel groups include a plurality of first pixel groups and a plurality of second pixel groups arranged at intervals, and adjacent first pixel groups and second pixel groups are connected by a plurality of traces.

[0011] For example, a display panel provided in at least one embodiment of this disclosure further includes connecting wires, wherein at least two of the plurality of traces between adjacent first pixel groups and second pixel groups have their orthographic projections on the substrate falling within the orthographic projection of the connecting wires on the substrate.

[0012] For example, in a display panel provided in at least one embodiment of this disclosure, there are multiple gaps between the plurality of traces, and at least one of the multiple gaps has its orthographic projection on the substrate at least partially overlapping with the orthographic projection of the connecting wire on the substrate.

[0013] For example, in a display panel provided in at least one embodiment of this disclosure, the pixel circuit includes a first reset signal line, a second reset signal line, a gate line, a light emission control signal line, and an initialization signal line to provide the pixel circuit with a first reset signal, a second reset signal, a gate scan signal, a light emission control signal, and an initialization signal, respectively; the plurality of traces are selected from at least two of the first reset signal line, the second reset signal line, the gate line, the light emission control signal line, the initialization signal line, and the first conductor.

[0014] For example, in a display panel provided in at least one embodiment of this disclosure, the connecting wire has a stop, the stop is disposed on the same layer as the connecting wire and integrally formed; the sub-pixel further includes a light-emitting element, the pixel circuit includes a first transistor, a second transistor and a storage capacitor, the first transistor is connected to the second transistor and the storage capacitor respectively, the second transistor is connected to the light-emitting element, the first transistor includes a first active part and a second active part, the first active part and the second active part are connected through a conductive part; the stop and the conductive part of a pixel unit in the pixel group that overlaps with the first wire are spaced apart from each other in the third direction and partially overlap in the third direction.

[0015] For example, in a display panel provided in at least one embodiment of this disclosure, at least a portion of the orthographic projection of the connecting wire on the substrate is located between the orthographic projections of the adjacent first pixel group and second pixel group on the substrate.

[0016] For example, in a display panel provided in at least one embodiment of this disclosure, the first reset signal line, the second reset signal line, the gate line, the light emission control signal line, the initialization signal line, and the second conductor of the first pixel group are respectively connected to the first reset signal line, the second reset signal line, the gate line, the light emission control signal line, the initialization signal line, and the second conductor of the second pixel group through the plurality of traces.

[0017] For example, in a display panel provided in at least one embodiment of this disclosure, the connecting wire and the second wire are located on the same layer and integrally formed; or the connecting wire and the initialization signal line are located on the same layer and integrally formed; or the connecting wire and the first wire are located on the same layer.

[0018] For example, in a display panel provided in at least one embodiment of this disclosure, the at least two sub-pixels further include a third sub-pixel and a fourth sub-pixel. The third sub-pixel and the fourth sub-pixel are arranged along the first direction and located on one side of the first sub-pixel and the second sub-pixel along the second direction. The third sub-pixel and the fourth sub-pixel are electrically connected to another of the plurality of second conductors, and the second sub-line is electrically connected to at least one of the plurality of second conductors.

[0019] For example, in a display panel provided in at least one embodiment of this disclosure, the second sub-trace has a stop block located on a different layer from the second sub-trace and connected by a via. The stop block and the conductive portion of a pixel unit in the pixel group that overlaps with the first conductor are spaced apart from each other in the third direction and partially overlap in the third direction.

[0020] For example, in a display panel provided in at least one embodiment of this disclosure, the first direction is perpendicular to the second direction.

[0021] For example, in a display panel provided in at least one embodiment of this disclosure, the plurality of second wires are arranged sequentially along the first direction.

[0022] For example, in a display panel provided in at least one embodiment of this disclosure, the adjacent second wires are not directly connected.

[0023] For example, in a display panel provided in at least one embodiment of this disclosure, the first wire and the second wire are connected through a through-hole penetrating the insulating layer.

[0024] For example, in a display panel provided in at least one embodiment of this disclosure, the first power line further includes a third conductor and a fourth conductor. The third conductor extends along the second direction, extends from the second display area to the first display area, and the second conductor is electrically connected to the third conductor. The fourth conductor extends along the second direction, is electrically connected to the second conductor, and the length of the fourth conductor in the second direction is less than or equal to the length of the third conductor in the second direction.

[0025] For example, a display panel provided in at least one embodiment of this disclosure includes a plurality of fourth conductors located between adjacent third conductors, the plurality of fourth conductors being arranged sequentially along the second direction, and adjacent fourth conductors being spaced apart from each other in the second direction.

[0026] For example, in a display panel provided in at least one embodiment of this disclosure, the first conductor and the third conductor are located on the same layer, and the fourth conductor and the third conductor are located on the same layer.

[0027] For example, in a display panel provided in at least one embodiment of this disclosure, the first display area includes a plurality of light-transmitting areas located between adjacent pixel groups.

[0028] For example, in a display panel provided in at least one embodiment of this disclosure, the plurality of pixel groups and the traces connected to adjacent pixel groups surround the plurality of light-transmitting areas.

[0029] At least one embodiment of this disclosure also provides a display device, including the display panel provided in any embodiment of this disclosure.

[0030] For example, the display device provided in at least one embodiment of this disclosure further includes a sensor; the sensor is disposed on one side of the display panel, and the orthographic projection of the sensor on the substrate at least partially overlaps with the first display area. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0032] Figures 1A to 1C are schematic diagrams of display panels provided in some embodiments of this disclosure;

[0033] Figure 2 is a schematic diagram of the second display area of ​​a display panel provided in at least one embodiment of the present disclosure;

[0034] Figure 3 is a schematic diagram of the first display area of ​​a display panel provided in at least one embodiment of the present disclosure;

[0035] Figure 4 is a schematic diagram of a sub-pixel in a display panel and a signal line that provides a signal to the sub-pixel according to at least one embodiment of the present disclosure;

[0036] Figure 5 is a schematic diagram of a display panel provided in at least one embodiment of the present disclosure;

[0037] Figures 6A to 6F are diagrams of a pixel circuit and its stacked structure provided in some embodiments of this disclosure;

[0038] Figure 7 is a schematic diagram of a display panel provided in at least one embodiment of the present disclosure;

[0039] Figure 8A is an enlarged schematic diagram of region A11 shown in Figure 7;

[0040] Figure 8B is an enlarged schematic diagram of region A12 shown in Figure 7;

[0041] Figure 8C is a plan view of the semiconductor pattern of the display panel shown in Figure 7;

[0042] Figure 9 is a plan view of the first conductive pattern layer of the display panel shown in Figure 7;

[0043] Figure 10 is a plan view of the second conductive pattern layer of the display panel shown in Figure 7;

[0044] Figure 11 is a plan view of the third conductive pattern layer of the display panel shown in Figure 7;

[0045] Figure 12 is a plan view of another display panel provided in at least one embodiment of the present disclosure;

[0046] Figure 13 is an enlarged schematic diagram of region A21 shown in Figure 12;

[0047] Figure 14 is a plan view of the semiconductor pattern of the display panel shown in Figure 12;

[0048] Figure 15 is a plan view of the first conductive pattern layer of the display panel shown in Figure 12;

[0049] Figure 16 is a plan view of the second conductive pattern layer of the display panel shown in Figure 12;

[0050] Figure 17 is a plan view of the third conductive pattern layer of the display panel shown in Figure 12;

[0051] Figure 18 is a schematic diagram of another display panel provided in at least one embodiment of the present disclosure;

[0052] Figure 19 is a plan view of the semiconductor pattern of the display panel shown in Figure 18;

[0053] Figure 20 is a plan view of the first conductive pattern layer of the display panel shown in Figure 18;

[0054] Figure 21 is a plan view of the second conductive pattern layer of the display panel shown in Figure 18;

[0055] Figure 22 is a plan view of the third conductive pattern layer of the display panel shown in Figure 18;

[0056] Figure 23 is a cross-sectional schematic diagram of the pixel circuit of a display panel provided in at least one embodiment of the present disclosure;

[0057] Figure 24 is a cross-sectional schematic diagram of a display panel provided in at least one embodiment of the present disclosure; and

[0058] Figure 25 is a schematic diagram of a display device provided in at least one embodiment of the present disclosure. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0060] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0061] Because of people's love for selfies, a front-facing camera is necessary. However, the front-facing camera and sensors take up some space. Currently, methods for placing the front-facing camera include: using a notch or waterdrop screen; or using an AA hole (Active Area), where a hole is cut out within the AA area to house the camera and sensors. However, neither of these methods can achieve the desired full-screen display. Therefore, we chose to use under-display camera technology. By changing the pixel density to increase the screen's aperture ratio, we placed the camera under the screen, thus preserving the integrity of the overall screen display.

[0062] To achieve a borderless, full-screen design, under-display camera technology is necessary, which requires increasing the aperture ratio of the display panel. Therefore, given these requirements, figuring out how to arrange the display panel structure to ensure optimal display quality becomes a critical issue that needs to be addressed.

[0063] This disclosure provides at least one embodiment of a display panel, comprising: a first display area; a second display area, at least located on one side of the first display area; a plurality of sub-pixels, located in the first and second display areas, wherein the density of sub-pixels in the first display area is less than the density of sub-pixels in the second display area, and each sub-pixel includes a pixel circuit; a plurality of pixel groups, located in the first display area, at least one of the plurality of pixel groups including at least two sub-pixels; and a first power line configured to provide a first voltage signal to the pixel circuit, the first power line including a plurality of first conductors and a plurality of second conductors, the plurality of first conductors extending from the second display area to the first display area and electrically connecting the plurality of pixel groups, the plurality of second conductors located in the first display area and between adjacent first conductors, the plurality of second conductors extending along a first direction, adjacent second conductors being spaced apart from each other along the first direction, and the plurality of second conductors electrically connecting the plurality of pixel groups; at least one of the plurality of first conductors including a first sub-line extending along the first direction and a second sub-line extending along a second direction, the first and second directions intersecting, and the second sub-line electrically connecting at least one of the plurality of second conductors.

[0064] The display panel provided in this embodiment can make the mesh structure of the first power line more stable and reduce the voltage drop on the first power line, so as to make the brightness uniformity of the display panel better and thus improve the display effect of the camera in the imaging area.

[0065] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0066] In conventional display panels, the first power line uses a mesh structure in both high and low PPI areas. To make the mesh structure of the first power line more stable and reduce the voltage drop on the first power line, thereby improving the brightness uniformity of the display panel and thus enhancing the display effect of the camera in the imaging area, the display panel provided in the embodiments of this disclosure optimizes the signal lines in the low PPI area. For example, the embodiments of this disclosure optimize the horizontal and vertical arrangement of the wires in the mesh first power line.

[0067] Figures 1A to 1C are schematic diagrams of display panels provided in some embodiments of the present disclosure. As shown in Figures 1A to 1C, the display panel includes a first display area R1 and a second display area R2. The first display area R1 is a low pixel density (Pixels Per Inch, PPI) area, and the second display area R2 is a high PPI area. The first display area R1 is a partially light-transmitting area. As shown in Figures 1A to 1C, the second display area R2 is located at least on one side of the first display area R1. The display panel shown in Figures 1A and 1B also includes a third area R3. A sensor, such as a camera, can be disposed in the first display area R1 (as shown in Figure 1C), or disposed in the first display area R1 and the third area R3 (as shown in Figures 1A and 1B). The third area R3 shown in Figures 1A and 1B can be a punch-hole area, that is, the material at the location corresponding to the third area R3 is removed to form a through hole. The sensor can receive ambient light. Taking a sensor as an example, an under-display camera can be implemented, allowing the primary display area corresponding to the sensor to display the image normally when the screen is in normal use. However, when the camera is taking a picture, the primary display area can allow ambient light to pass through, supporting normal use. For example, the sensor can be placed on the non-display side of the display panel. The sensor can also be called an under-display device.

[0068] Figure 1A also shows multiple gate lines 113 and multiple data lines 313. The multiple gate lines 113 include a first gate line GL1, and the multiple data lines 313 include a first data line DL1. The first gate line GL1 extends from the second display area R2 to the first display area R1. The first data line DL1 extends from the first display area R1 to the second display area R2. In embodiments of this disclosure, the extension of a component from the first display area R1 to the second display area R2 can be understood as the component being located in both the first and second display areas R1, or conversely, as the component extending from the second display area R2 to the first display area R1. For clarity, Figure 1A schematically shows several gate lines 113 and several data lines 313; the number of gate lines 113 and data lines 313 can be determined as needed. The multiple gate lines 113 and multiple data lines 313 intersect each other and are insulated from one another.

[0069] Figure 2 is a schematic diagram of the second display area of ​​a display panel provided in at least one embodiment of the present disclosure. Figure 3 is a schematic diagram of the first display area of ​​a display panel provided in at least one embodiment of the present disclosure. As shown in Figures 2 and 3, the display panel includes a plurality of sub-pixels P0, and the plurality of sub-pixels P0 includes a first sub-pixel 101, a second sub-pixel 102, a third sub-pixel 103, and a fourth sub-pixel 104. For example, the display panel includes a plurality of pixel groups P1 located in the first display area R1, and at least one pixel group P1 in the plurality of pixel groups P1 includes at least two sub-pixels. For example, in some examples, a pixel group P1 may include four sub-pixels. For instance, as shown in Figure 3, a first sub-pixel 101, a second sub-pixel 102, a third sub-pixel 103, and a fourth sub-pixel 104 constitute a pixel group P1. In other examples, a pixel group P1 may include two sub-pixels. For instance, as shown in Figure 5, a first sub-pixel 101 and a second sub-pixel 102 constitute a pixel group P1. A pixel group P1 may also include three sub-pixels (as shown in Figure 18). The embodiments disclosed herein are not limited to this. For example, a pixel group P1 is a repeating unit arranged in an array in the second display area R2. As shown in Figure 3, in the first display area R1, a pixel group P1 is also called a pixel island P1. The following embodiments are the same and will not be repeated. The first display area R1 includes multiple light-transmitting areas R0; the light-transmitting areas R0 are located between adjacent pixel islands P1. The light-transmitting areas R0 can transmit ambient light. For example, the light-transmitting region R0 may include a substrate and a transparent insulating layer on the substrate. The light-transmitting region R0 does not have a light-blocking structure, for example, it does not have metal traces. For example, the light-transmitting region R0 is located within the area enclosed by four adjacent pixel islands P1, but it is not limited thereto. For example, as shown in Figure 3, the adjacent pixel islands P1 are spaced apart.

[0070] For example, the length of each of the multiple light-transmitting regions R0 is approximately the same as the length of a sub-pixel. For example, pixel groups and traces connecting adjacent pixel groups surround the multiple light-transmitting regions R0.

[0071] For example, in the example shown in Figure 7, a pixel island may also include two sub-pixels, such as a first sub-pixel 101 and a second sub-pixel 102, where the first sub-pixel 101 is a red sub-pixel and the second sub-pixel 102 is a green sub-pixel; for example, in the embodiment shown in Figure 18, a pixel island P1 may also include three sub-pixels, such as a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103, where the first sub-pixel 101 is a red sub-pixel, the second sub-pixel 102 is a green sub-pixel, and the third sub-pixel 103 is a red sub-pixel. Pixel 103 is a blue subpixel. For example, these three subpixels are located in a row. For example, in the example shown in Figure 12, a pixel island may also include four subpixels, such as a first subpixel 101, a second subpixel 102, a third subpixel 103, and a fourth subpixel 104. For example, the first subpixel 101 is a red subpixel, the second subpixel 102 is a green subpixel, the third subpixel 103 is a blue subpixel, and the fourth subpixel 104 is a green subpixel. In other embodiments, the pixel group may also use pixel units of other colors. Of course, in other embodiments, the arrangement of multiple subpixels P0 in the display panel is not limited to that shown in Figures 2 and 3. The embodiments of this disclosure do not limit this.

[0072] Referring to Figures 2 and 3, multiple sub-pixels P0 are located in the first display area R1 and the second display area R2. The pixel density of the first display area R1 is less than the pixel density of the second display area R2. In other words, the sub-pixel density of the first display area R1 is less than the sub-pixel density of the second display area R2. The pixel density in the first display area R1 shown in Figure 3 is one-quarter of the pixel density in the second display area R2. That is, the sub-pixel density in the first display area R1 shown in Figure 3 is one-quarter of the sub-pixel density in the second display area R2. The arrangement of the light-transmitting area R0 and pixel units within the first display area R1 is not limited to that shown in Figure 3 and can be set as needed. For example, in other embodiments, the sub-pixel density in the first display area R1 is one-half, one-third, one-sixth, or one-eighth of the sub-pixel density in the second display area R2, etc., other values ​​different from one-quarter. The embodiments of this disclosure do not limit this.

[0073] For example, as shown in Figures 1A and 3, the display panel also includes gate lines 113 and data lines 313. Gate lines 113 and data lines 313 are insulated from each other. Each gate line 113 connects to a row of sub-pixels, and each data line 313 connects to a column of sub-pixels. For example, gate lines 113 are configured to provide scan signals to a row of sub-pixels.

[0074] For example, as shown in Figures 1A and 3, data line 313 includes a first data line DL1. The first data line DL1 is located at least in a first display area R1. For example, the first data line DL1 extends from the first display area R1 to a second display area R2.

[0075] For example, as shown in Figures 1A and 3, the gate line includes a first gate line GL1, which extends from the second display area R2 to the first display area R1. As shown in Figure 3, the light-transmitting area R0 is enclosed by two adjacent first gate lines GL1 and two adjacent first data lines DL1, but is not limited thereto.

[0076] Figure 4 is a schematic diagram of a sub-pixel in a display panel according to an embodiment of the present disclosure and the signal lines that provide signals to the sub-pixel. As shown in Figure 4, the display panel includes: a plurality of sub-pixels P0, each sub-pixel P0 including a light-emitting element EMC and a pixel circuit 10 that provides driving current to the light-emitting element EMC. The light-emitting element EMC may be an electroluminescent element, for example, an organic electroluminescent element, such as an organic light-emitting diode (OLED).

[0077] As shown in Figure 4, the display panel also includes an initialization signal line 210, an illumination control signal line 110, a data line 313, a first power line 311, and a second power line 312. For example, the gate line 113 is configured to provide a scan signal SCAN to the pixel circuit 10. The illumination control signal line 110 is configured to provide an illumination control signal EM to the sub-pixel P0. The data line 313 is configured to provide a data signal DATA to the pixel circuit 10. The first power line 311 is configured to provide a constant first voltage signal ELVDD to the pixel circuit 10. The second power line 312 is configured to provide a constant second voltage signal ELVSS to the pixel circuit 10, and the first voltage signal ELVDD is greater than the second voltage signal ELVSS. The initialization signal line 210 is configured to provide an initialization signal Vint to the pixel circuit 10. The initialization signal Vint is a constant voltage signal, the magnitude of which may be, for example, between the first voltage signal ELVDD and the second voltage signal ELVSS, but is not limited thereto. For example, the initialization signal Vint may be less than or equal to the second voltage signal ELVSS. For example, under the control of signals such as the scan signal SCAN, data signal DATA, initialization signal Vint, first voltage signal ELVDD, second voltage signal ELVSS, and light emission control signal EM, the pixel circuit 10 outputs a driving current to drive the light-emitting element EMC to emit light. As shown in Figure 4, the light-emitting element EMC includes a pixel electrode E1 and a common electrode E2. The pixel electrode E1 is connected to the pixel circuit 10, and the common electrode E2 is connected to the second power supply line 312.

[0078] Figure 5 is a schematic diagram of a display panel provided in some embodiments of this disclosure. It should be noted that Figure 5 illustrates a pixel island P1 comprising two sub-pixels as an example. Each pixel island P1 may also include three or four sub-pixels, and their specific connection relationships are similar, which will not be repeated here. The embodiments of this disclosure do not limit this.

[0079] As shown in Figure 5, the first power line 311 includes multiple first conductors L1 and multiple second conductors L2. For example, the first power line 311 may also include multiple third conductors L3. For example, the first conductors L1 extend from the second display area R2 to the first display area R1 and are electrically connected to multiple pixel groups (i.e., pixel islands) P1. The multiple second conductors L2 are located in the first display area R1 and are located between adjacent first conductors L1. Each second conductor L2 extends along a first direction D1, and the multiple second conductors L2 are electrically connected to multiple pixel groups P1. For example, the third conductors L3 are at least located in the first display area R1. For example, the third conductors L3 extend from the second display area R2 to the first display area R1. The third conductors L3 extend along a second direction D2. The first direction D1 intersects the second direction D2, and adjacent second conductors L2 are spaced apart from each other along the first direction D1. Adjacent second conductors L2 are connected to each other through first conductors L1 and are connected to the third conductors L3 to receive the first voltage signal ELVDD. For example, the first direction D1 is perpendicular to the second direction D2, but it is not limited to this. For example, the first conductor L1 extends along the first direction D1. For example, in an embodiment of this disclosure, the second conductor L2 is located only in the first display area R1. In an embodiment of this disclosure, an element extending along a certain direction is not necessarily a straight line, but may also have curved or broken lines. For example, the extension direction of an element refers to the general extension trend of the element; for example, each part of the element does not necessarily extend along that direction.

[0080] For example, as shown in Figure 5, the first conductor L1 and the second conductor L2 respectively connect the sub-pixels in the corresponding rows of two adjacent pixel islands P1. However, this is not the only possibility. In other embodiments, the pixel island P1 may also include two or more rows of sub-pixels. For example, as shown in Figures 6A to 6E, the pixel island P1 includes at least two pixel units in one row, and the second conductor L2 overlaps with the two pixel units in that row. For example, as shown in Figure 5, the first conductor L1 is located between two adjacent pixel islands P1, and the second conductor L2, which overlaps with the two adjacent pixel islands P1 respectively, is connected through the first conductor L1.

[0081] For example, as shown in Figure 5, multiple second conductors L2 are arranged sequentially along the first direction D1. For example, as shown in Figure 5, adjacent second conductors L2 are not directly connected; for example, they are connected via jumpers, i.e., connected through first conductors L1 located on different layers. This makes the mesh structure of the first power line more stable, reduces the voltage drop on the first power line, and thus improves the brightness uniformity of the display panel. Of course, adjacent second conductors L2 can also be directly connected; the embodiments of this disclosure do not limit this.

[0082] For example, as shown in Figure 5, in order to improve the light transmittance of the first display area, the length of the portion of the first conductor L1 located in the first display area R1 in the first direction D1 is greater than the length of the second conductor L2 in the first direction D1.

[0083] For example, as shown in Figure 5, the first power line 311 further includes a fourth conductor L4 extending along the second direction D2. The second conductor L2 is connected to the fourth conductor L4 to receive the first voltage signal ELVDD. The length of the fourth conductor L4 in the second direction D2 is less than or equal to the length of the third conductor L3 in the second direction D2. In the display panel shown in Figure 5, the length of the fourth conductor L4 in the second direction D2 is less than the length of the third conductor L3 in the second direction D2.

[0084] For example, as shown in Figure 5, to further improve the light transmittance of the first display area, multiple fourth conductors L4 are provided. These fourth conductors L4 are arranged sequentially along the second direction D2, with adjacent fourth conductors L4 spaced apart from each other in the second direction D2. For example, as shown in Figure 5, multiple fourth conductors L41 are located between third conductors L31 and L32, which are adjacent third conductors L3. Figure 5 shows five fourth conductors L41, but the number of fourth conductors L4 located between adjacent third conductors L3 is not limited to what is shown in the figure and can be determined as needed. Because the multiple fourth conductors L4 are spaced apart from each other in the second direction D2, it is equivalent to removing part of the first power line set along the second direction in a typical display panel, thereby reducing wiring, optimizing wiring space, and improving light transmittance.

[0085] For example, as shown in Figure 5, the first power line 311 also includes a fifth conductor L5, which extends along the first direction D1 and is located in the second display area R2. The fifth conductor L5 and the adjacent second conductor L2 are spaced apart from each other along the first direction D1. Thus, at the boundary between the first and second display areas, the wiring is reduced, and the light transmittance is improved.

[0086] In the embodiments of this disclosure, there is no limitation on the number of pixel units included in each pixel island or the arrangement of the pixel units.

[0087] As shown in Figure 5, in the display panel, the first power line 311 further includes multiple sixth conductors L6, which are located in the second display area R2 and extend along the second direction D2. In the second display area R2, multiple fifth conductors L5 and multiple sixth conductors L6 are intersecting. In the embodiments of this disclosure, both the fifth conductors L5 and the sixth conductors L6 are located only in the second display area R2.

[0088] As shown in Figure 5, the same gate line 113 connects the sub-pixels in the second display areas located on both sides of the first display area R1 and the sub-pixels located in the first display area R1, forming a row of sub-pixels. The embodiments of this disclosure do not limit the shape of the first conductor, as long as it can extend from the second display area R2 to the first display area R1. The first power line in Figure 5 can also be replaced with the first power line in other embodiments of this disclosure. Furthermore, the extension method of the gate line 113 is not limited to that shown in Figure 5, as long as the arrangement of the gate line 113 allows the pixels in the second display area R2 and the pixels in the first display area R1 to be connected. For example, in the first display area R1, the gate lines of the sub-pixels in corresponding rows between two adjacent pixel islands are connected by the seventh conductor L7 (i.e., a jumper). Of course, the gate lines of the sub-pixels in corresponding rows between two adjacent pixel islands can also be directly connected; the embodiments of this disclosure do not limit this.

[0089] For example, the correspondence between the remaining signal lines (e.g., the initialization signal line providing the initialization signal Vint, the light emission control signal line providing the light emission control signal EM) and a pixel island P1 is shown in Figure 5. The embodiments of this disclosure do not limit this, and will not be described in detail here.

[0090] For example, in the display panel shown in Figure 5, the first conductor is in contact with two adjacent second conductors, for example, through a through-hole penetrating the insulating layer.

[0091] For example, in an embodiment of this disclosure, a row of subpixels consists of subpixels connected to the same gate line 113, while a column of subpixels consists of subpixels connected to the same data line 313. In an embodiment of this disclosure, the first conductor L1, the second conductor L2, and the fifth conductor L5 extend along the row direction (i.e., the first direction D1), and the third conductor L3, the fourth conductor L4, and the sixth conductor L6 extend along the column direction (i.e., the second direction D2), but this is not a limitation. In other embodiments, the first conductor L1, the second conductor L2, and the fifth conductor L5 may all extend along the column direction, while the third conductor L3, the fourth conductor L4, and the sixth conductor L6 may extend along the row direction; correspondingly, the second direction D2 and the first direction D1 may also be interchanged.

[0092] Figure 5 illustrates a pixel island comprising two sub-pixels (e.g., one row of sub-pixels). In other embodiments, a pixel island may also comprise three or more sub-pixels (e.g., two rows of sub-pixels). In this case, the aforementioned plurality of second wires can be understood as second wires connected to the same row of sub-pixels within a pixel island. When the first wire L1, second wire L2, and fifth wire L5 extend along the column direction, and the third wire L3, fourth wire L4, and sixth wire L6 extend along the row direction, the aforementioned plurality of second wires can be understood as second wires connected to the same column of sub-pixels within a pixel island.

[0093] Some embodiments of this disclosure are described below with reference to Figures 6A to 24. Figures 6A to 24 illustrate the pixel circuit of a 7T1C as an example.

[0094] Figure 6A is a schematic diagram of a pixel circuit of a display panel according to an embodiment of the present disclosure. Figure 6B is a plan view of a semiconductor pattern in a display panel according to an embodiment of the present disclosure. Figure 6C is a plan view of a first conductive pattern layer in a display panel according to an embodiment of the present disclosure. Figure 6D is a plan view of a second conductive pattern layer in a display panel according to an embodiment of the present disclosure. Figure 23 is a cross-sectional schematic diagram of a display panel according to an embodiment of the present disclosure. Figure 24 is a cross-sectional schematic diagram of a display panel according to an embodiment of the present disclosure. In the embodiments of the present disclosure, for clarity, the insulating layer is shown in the form of vias in the plan views, and the insulating layer itself is made transparent.

[0095] It should be noted that Figures 6B-6F respectively show the hierarchical structure diagram of a pixel circuit including two sub-pixels. It should also be noted that more or fewer sub-pixels may be included, and the structure of the pixel circuit can be designed using the layout of one of the pixels shown in Figures 6B-6F. The embodiments of this disclosure do not limit this. For example, Figure 6F describes the pixel structure of the first sub-pixel 101 as an example; the pixel structures of the remaining sub-pixels, such as the second, third, and fourth sub-pixels, are similar and will not be described again.

[0096] For example, referring to FIG6A, gate line 113 is configured to provide a scan signal SCAN to pixel circuit 10. Light emission control signal line 110 is configured to provide a light emission control signal EM to sub-pixel P0. Data line 313 is configured to provide a data signal DATA to pixel circuit 10. First power line 311 is configured to provide a constant first voltage signal ELVDD to pixel circuit 10, and second power line 312 is configured to provide a constant second voltage signal ELVSS to pixel circuit 10, wherein the first voltage signal ELVDD is greater than the second voltage signal ELVSS. Initialization signal line 210 is configured to provide an initialization signal Vint to pixel circuit 10. The initialization signal Vint is a constant voltage signal, the magnitude of which may, for example, be between the first voltage signal ELVDD and the second voltage signal ELVSS, but is not limited thereto; for example, the initialization signal Vint may be less than or equal to the second voltage signal ELVSS. For example, under the control of signals such as the scan signal SCAN, data signal DATA, initialization signal Vint, first voltage signal ELVDD, second voltage signal ELVSS, and light emission control signal EM, the pixel circuit outputs a driving current to drive the light-emitting element 20 to emit light. The light-emitting element 20 emits red, green, blue, or white light under the drive of its corresponding pixel circuit 10.

[0097] As shown in Figure 6A, the pixel circuit 10 includes a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a first reset transistor T6, a second reset transistor T7, and a storage capacitor C1. The driving transistor T1 is electrically connected to the light-emitting element 20 and outputs a driving current to drive the light-emitting element 20 to emit light under the control of signals such as the scan signal SCAN, the data signal DATA, the first voltage signal ELVDD, and the second voltage signal ELVSS.

[0098] For example, the display panel provided in this embodiment further includes a data driving circuit and a scan driving circuit. The data driving circuit is configured to provide a data signal DATA to the sub-pixel P0 according to the instructions of the control circuit; the scan driving circuit is configured to provide signals such as a light emission control signal EM, a scan signal SCAN, a first reset control signal RST1, and a second reset signal RST2 to the sub-pixel P0 according to the instructions of the control circuit. For example, the control circuit includes an external integrated circuit (IC), but is not limited thereto. For example, the scan driving circuit is a GOA (Gate driver On Array) structure mounted on the display panel, or a driver chip (IC) structure bonded to the display panel. For example, different driving circuits can also be used to provide the light emission control signal EM and the scan signal SCAN respectively. For example, the display panel also includes a power supply (not shown in the figure) to provide the above voltage signals, which can be a voltage source or a current source as needed. The power supply is configured to provide a first voltage signal ELVDD, a second voltage signal ELVSS, and an initialization signal Vint to the sub-pixel P0 through a first power line 311, a second power line 312, and an initialization signal line 210 respectively.

[0099] As shown in Figure 6A, the second terminal C12 of the storage capacitor C1 is electrically connected to the first power supply line 311, and the first terminal C11 of the storage capacitor C1 is electrically connected to the second terminal T32 of the threshold compensation transistor T3. The gate T20 of the data writing transistor T2 is electrically connected to the gate line 113, and the first terminal T21 and the second terminal T22 of the data writing transistor T2 are electrically connected to the data line 313 and the first terminal T11 of the driving transistor T1, respectively. The gate T30 of the threshold compensation transistor T3 is electrically connected to the gate line 113, the first terminal T31 of the threshold compensation transistor T3 is electrically connected to the second terminal T12 of the driving transistor T1, and the second terminal T32 of the threshold compensation transistor T3 is electrically connected to the gate T10 of the driving transistor T1.

[0100] For example, as shown in Figure 6A, the gate T40 of the first light-emitting control transistor T4 and the gate T50 of the second light-emitting control transistor T5 are both connected to the light-emitting control signal line 110.

[0101] For example, as shown in Figure 6A, the first electrode T41 and the second electrode T42 of the first light-emitting control transistor T4 are electrically connected to the first power supply line 311 and the first electrode T11 of the driving transistor T1, respectively. The first electrode T51 and the second electrode T52 of the second light-emitting control transistor T5 are electrically connected to the second electrode T12 of the driving transistor T1 and the pixel electrode E1 (which can be the anode of the OLED) of the light-emitting element 20, respectively. The common electrode E2 (which can be the common electrode of the OLED, such as the cathode) of the light-emitting element 20 is electrically connected to the second power supply line 312.

[0102] For example, as shown in Figure 6A, the gate T60 of the first reset transistor T6 is electrically connected to the first reset control signal line 111, the first electrode T61 of the first reset transistor T6 is electrically connected to the initialization signal line 210 (first initialization signal line 211), and the second electrode T62 of the first reset transistor T6 is electrically connected to the gate T10 of the driving transistor T1. The gate T70 of the second reset transistor T7 is electrically connected to the second reset control signal line 112, the first electrode T71 of the second reset transistor T7 is electrically connected to the initialization signal line 210 (second initialization signal line 212), and the second electrode T72 of the second reset transistor T7 is electrically connected to the pixel electrode E1 of the light-emitting element 20.

[0103] Figure 6B shows the semiconductor pattern SCP, and Figure 6C shows the first conductive pattern layer LY1. A first gate insulating layer is disposed between the first conductive pattern layer LY1 and the semiconductor pattern SCP. The semiconductor pattern SCP is doped using the first conductive pattern layer LY1 as a mask. The areas of the semiconductor pattern SCP not covered by the first conductive pattern layer LY1 retain semiconductor properties, forming the channel of a thin-film transistor, while the areas of the semiconductor pattern SCP covered by the first conductive pattern layer LY1 are conductive, forming the source or drain of the thin-film transistor. Figure 6A shows the active layer ALT formed after the semiconductor pattern SCP is partially conductive.

[0104] As shown in Figure 6C, the first conductive pattern layer LY1 includes a first reset control signal line 111, a second reset control signal line 112, a light emission control signal line 110, a gate line 113, and the first terminal C11 of the storage capacitor C1. Figure 6C also shows a first portion DL11 (wire 114) of the first data line DL1. For example, referring to Figure 7, in an embodiment of this disclosure, the current row gate line 113 is also connected to the second reset control signal line 112 located in the same row.

[0105] Figure 6D shows a second conductive pattern layer LY2, with a second gate insulating layer disposed between the second conductive pattern layer LY2 and the first conductive pattern layer LY1. The second conductive pattern layer LY2 includes blocks BK0 and BK1, an initialization signal line 210, and the second terminal C12 of a storage capacitor C1. The second terminal C12 of the storage capacitor C1 for two sub-pixels of a pixel island is integrally formed as a second conductor L2. The second terminal C12 of the storage capacitor C1 has an opening OPN. An interlayer insulating layer is located between the second conductive pattern layer LY2 and the third conductive pattern layer LY3. Details regarding the first gate insulating layer, the second gate insulating layer, the interlayer insulating layer, the first conductive pattern layer LY1, the second conductive pattern layer LY2, and the third conductive pattern layer LY3 can be found in the descriptions in this art and will not be repeated here.

[0106] Figure 6E shows the third conductive pattern layer LY3, which includes a first conductor L1, a third conductor L3 (part of the first power line 311), a fourth conductor L4 (part of the first power line 311), a second part of the data line DL12 (part of the data line 313), a first connecting electrode 31a, a second connecting electrode 31b, a third connecting electrode 31c, and a fourth connecting electrode 31d.

[0107] For example, as shown in FIG6E, at least one of the plurality of first conductors L1 includes a first sub-trace L111 extending along a first direction D1 and a second sub-trace L112 extending along a second direction D2, wherein the second sub-trace L112 is electrically connected to at least one of the plurality of second conductors L2. For example, as shown in FIG11, the second sub-trace L112 is electrically connected to the second conductors L2 in the corresponding row of adjacent pixel islands. For example, as shown in FIG13 and FIG17, the second sub-trace L112 is electrically connected to two second conductors L2 in a pixel island and two second conductors L2 in a pixel island adjacent to that pixel island. The embodiments of this disclosure are not limited thereto.

[0108] For example, the second sub-trace L112 is connected to the stop block BK0 through a via penetrating the interlayer insulation layer, and is connected to the second conductor L2 through a via penetrating the interlayer insulation layer.

[0109] Figure 6F is a stacked structure diagram of Figures 6B-6E. Referring to Figures 6B-8A, data line 313 is electrically connected to the first terminal T21 of data writing transistor T2 through a via. First power line 311 is electrically connected to the first terminal T41 of first light-emitting control transistor T4 through a via. First power line 311 is electrically connected to the second terminal C12 of storage capacitor C1 through a via. First power line 311 is also electrically connected to conductive block BK1 through a via. One end of first connection electrode 31a is electrically connected to first initialization signal line 211 through a via. The other end of first connection electrode 31a is connected to the first terminal T61 of first reset transistor T6 through a via, thereby making the first terminal T61 of first reset transistor T6 electrically connected to first initialization signal line 211. One end of the second connection electrode 31b is electrically connected to the second terminal T62 of the first reset transistor T6 through a via, and the other end of the second connection electrode 31b is electrically connected to the gate T10 of the driving transistor T1 (i.e., the first terminal C11 of the storage capacitor C1) through a via, thereby making the second terminal T62 of the first reset transistor T6 electrically connected to the gate T10 of the driving transistor T1 (i.e., the first terminal C11 of the storage capacitor C1). One end of the third connection electrode 31c is electrically connected to the second initialization signal line 212 through a via, and the other end of the third connection electrode 31c is connected to the first terminal T71 of the second reset transistor T7 through a via, thereby making the first terminal T71 of the second reset transistor T7 electrically connected to the second initialization signal line 212. The fourth connection electrode 31d is electrically connected to the second terminal T52 of the second light-emitting control transistor T5 through a via. The fourth connection electrode 31d can be used to electrically connect to the pixel electrode E1 (see Figure 6A) of the subsequently formed light-emitting element 20. For example, the positional relationship between the first connecting electrode 31a and the third connecting electrode 31c can be referred to in Figure 6E. For clarity and simplicity, it will not be shown in Figure 6F.

[0110] It should be noted that the transistors used in some embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. The source and drain of the transistors used here can be structurally symmetrical, so their structures can be indistinguishable. In one embodiment of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is directly described as the first terminal and the other as the second terminal. Therefore, the first and second terminals of all or some transistors in this disclosure can be interchanged as needed. For example, the first terminal of the transistor described in this disclosure can be the source, and the second terminal can be the drain; or, the first terminal of the transistor is the drain, and the second terminal is the source.

[0111] Furthermore, transistors can be classified into N-type and P-type transistors based on their characteristics. This disclosure uses an example where all transistors are P-type. Based on the description and teachings of this disclosure, those skilled in the art can readily conceive of using at least some N-type transistors in the pixel circuit of this disclosure, i.e., using N-type transistors or a combination of N-type and P-type transistors, without any inventive effort. Therefore, these implementations are also within the scope of this disclosure.

[0112] Figures 6A to 6F illustrate a 7T1C pixel circuit as an example, and embodiments of this disclosure include, but are not limited to, this. It should be noted that the embodiments of this disclosure do not limit the number of thin-film transistors or capacitors included in the pixel circuit. For example, in some other embodiments, the pixel circuit of the display base panel may also be a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure; the embodiments of this disclosure do not limit this.

[0113] Figure 23 is a cross-sectional schematic diagram of the pixel circuit of a display panel provided in some embodiments of the present disclosure. For example, as shown in Figure 23, the display panel includes a thin-film transistor 50 and a storage capacitor C1. The thin-film transistor 50 includes an active layer ATL1 located on a substrate BS, a first gate insulating layer GI1 located on the side of the active layer ATL1 away from the substrate BS, and a gate GE located on the side of the first gate insulating layer GI1 away from the substrate BS. The display panel also includes a second gate insulating layer GI2 located on the side of the gate GE away from the substrate BS, an interlayer insulating layer ILD located on the side of the second gate insulating layer GI2 away from the substrate BS, and a source or drain CNE1 located on the side of the interlayer insulating layer ILD away from the substrate BS. For example, when the thin-film transistor 50 is implemented as an N-type transistor, CNE1 represents the source of the thin-film transistor 50, and CNE2 represents the drain of the thin-film transistor 50; when the thin-film transistor 50 is implemented as a P-type transistor, CNE1 represents the drain of the thin-film transistor 50, and CNE2 represents the source of the thin-film transistor 50. The active layer ATL1 includes a channel CN11 and a first electrode ET1 and a second electrode ET2 located on both sides of the channel CN11. The connecting electrode CNE1 is connected to the second electrode ET2 through a via penetrating the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulating layer ILD. The storage capacitor C1 includes a first electrode C11 and a second electrode C12. The first electrode C11 and the gate GE are located on the same layer, both located on the first conductive pattern layer LY1. The second electrode C12 is located between the second gate insulating layer GI2 and the interlayer insulating layer ILD, located on the second conductive pattern layer LY2. One of the first electrode ET1 and the second electrode ET2 is the source, and the other of the first electrode ET1 and the second electrode ET2 is the drain. The connecting electrode CNE1 is located on the third conductive pattern layer LY3. The display panel also includes a passivation layer PVX and a planarization layer PLN. For example, the source or drain CNE1 is the first part of the fourth connecting electrode 31d shown in Figures 6E or 6F above, and the thin film transistor 50 may be the second light-emitting control transistor T5 mentioned above.

[0114] As shown in Figure 23, the display panel also includes a light-emitting element (EMC), which comprises a pixel electrode E1, a light-emitting functional layer (EML), and a common electrode E2. The pixel electrode E1 is connected to a connecting electrode CNE1 through a via penetrating the passivation layer (PVX) and the planarization layer (PLN). The display panel also includes an encapsulation layer (CPS), which comprises a first encapsulation layer CPS1, a second encapsulation layer CPS2, and a third encapsulation layer CPS3. For example, the first encapsulation layer CPS1 and the third encapsulation layer CPS3 may be inorganic material layers, and the second encapsulation layer CPS2 may be an organic material layer. For example, the pixel electrode E1 may be the anode, and the common electrode E2 may be the cathode, but this is not the only possibility.

[0115] For example, the light-emitting element (EMC) includes an organic light-emitting diode (OLED). The light-emitting functional layer is located between the common electrode E2 and the pixel electrode E1. The light-emitting functional layer (EML) includes at least a light-emitting layer, and may also include at least one of a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer.

[0116] As shown in Figure 23, the display panel also includes a pixel definition layer (PDL) and spacers (PS). The PDL has openings configured to define the light-emitting area (light-emitting region, effective light-emitting area) of the pixel unit, and the PS is configured to support the fine metal mask during the formation of the light-emitting functional layer (EML). Figure 23 shows spacers (PS) on both opposite sides of the light-emitting element, but is not limited to this.

[0117] For example, a data line is configured to input a data signal to a pixel unit, and a first power line is configured to input a first voltage signal to a driving transistor. A second power line is configured to input a second voltage signal to a sub-pixel. The first voltage signal is a constant voltage, and the second voltage signal is a constant voltage; for example, the first voltage signal is a positive voltage, and the second voltage signal is a negative voltage, but this is not limited to these. For example, in some embodiments, the first voltage signal is a positive voltage, and the second power line is grounded.

[0118] Referring to FIG23, in an embodiment of the present disclosure, the first insulating layer ISL1 includes at least one of a first gate insulating layer GI1, a second gate insulating layer GI2, and an interlayer insulating layer ILD, and the second insulating layer ISL2 includes a planarization layer PLN.

[0119] For example, the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, the passivation layer PVX, the planarization layer PLN, the pixel definition layer PDL, and the spacer PS are all made of insulating materials. For example, the materials of the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, and the passivation layer PVX include at least one of SiOx and SiNx, but are not limited thereto. For example, the planarization layer PLN, the pixel definition layer PDL, and the spacer PS can be made of organic insulating materials, such as resin, but are not limited thereto.

[0120] Referring to Figure 6F, the threshold compensation transistor T3 includes a first active part CN1 and a second active part CN2, which are connected by a conductive part CP. Referring to Figures 8B and 10, the second conductor L2 also includes a connecting arm L21. The threshold compensation transistor T3 is a dual-gate transistor. When the threshold compensation transistor T3 is off, the conductive part CP is in a floating state, which is easily affected by the voltage of the surrounding lines. The voltage jump of the conductive part CP will affect the leakage current of the threshold compensation transistor T3, and thus affect the light emission brightness of the pixel unit. Therefore, it is necessary to keep the voltage of the conductive part CP stable. A block can be designed to form a capacitor with the conductive part CP. The block can have a constant voltage signal so that the voltage of the conductive part CP in the floating state also remains stable. In the embodiments of this disclosure, the block BK0, the block BK1, and the connecting arm mentioned later all play the role of stabilizing the voltage of the conductive part CP.

[0121] Figure 7 is a schematic diagram of a display panel provided in at least one embodiment of the present disclosure; Figure 8A is an enlarged schematic diagram of region A11 shown in Figure 7; Figure 8B is an enlarged schematic diagram of region A12 shown in Figure 7; Figure 8C is a plan view of the semiconductor pattern of the display panel shown in Figure 7; Figure 9 is a plan view of the first conductive pattern layer of the display panel shown in Figure 7; Figure 10 is a plan view of the second conductive pattern layer of the display panel shown in Figure 7; Figure 11 is a plan view of the third conductive pattern layer of the display panel shown in Figure 7.

[0122] For example, as shown in Figure 7, at least two sub-pixels include a first sub-pixel 101 and a second sub-pixel 102, which are arranged along a first direction D1. For example, as shown in Figure 8A, at least one of a plurality of second conductors L2 electrically connects the first sub-pixel 101 and the second sub-pixel 102, and the second sub-trace L112 is located on a different layer from the plurality of second conductors L2.

[0123] For example, as shown in FIG6A, the sub-pixel P0 also includes a light-emitting element 20. The pixel circuit includes a first transistor (e.g., a threshold compensation transistor T3) and a second transistor (e.g., the second light-emitting control transistor T5 shown in FIG6A). The first transistor T3 is connected to the second transistor T5, and the second transistor T5 is connected to the light-emitting element 20. For example, as shown in FIG6F, the first transistor T3 includes a first active part CN1 and a second active part CN2. The first active part CN1 and the second active part CN2 are connected through a conductive part CP.

[0124] For example, as shown in Figures 8B and 10, the second conductor L2 further includes a connecting arm L21, which is spaced apart from the conductive portion CP of a sub-pixel in the pixel group that overlaps with the second conductor L2 on a third direction D3 and partially overlaps with each other on a third direction D3 (see Figure 24). The third direction D3 is perpendicular to the first direction D1 and perpendicular to the second direction D2.

[0125] For example, as shown in Figures 8B and 10, the shape of the connecting arm L21 includes a C-shape. It should be noted that the connecting arm L21 can generally be C-shaped, but of course, the connecting arm L21 can also adopt other shapes, as long as it can serve the function of stabilizing the threshold compensation transistor T3.

[0126] Referring to Figure 24, the connecting arm L21 overlaps with the conductive portion CP of the threshold compensation transistor T3 to form a capacitor C0. A first gate insulating layer GI1 and a second gate insulating layer GI2 are disposed between the connecting arm L21 and the conductive portion CP. Figure 24 also shows the second active portion CN2. The capacitor C0 can be referred to as a stabilizing capacitor, and the connecting arm L21 and the conductive portion CP are the two plates of the capacitor C0. As shown in Figure 24, the gate GE2 overlaps with the second active portion CN2 in a direction perpendicular to the substrate BS. The gate GE2 is a gate of the threshold compensation transistor T3. As shown in Figure 24, a portion of the second connecting electrode 31b (shown in Figure 6E) serves as the second electrode T32 (e.g., the drain) of the threshold compensation transistor T3.

[0127] For example, a third direction D3 is perpendicular to a first direction D1 and a second direction D2, and the third direction D3 is perpendicular to the substrate BS. A first gate insulating layer GI1 and a second gate insulating layer GI2 are provided between the connecting arm L21 and the conductive part CP. For example, the first direction D1 and the second direction D2 are parallel to the main surface of the substrate BS, and the third direction D3 is perpendicular to the main surface of the substrate BS. Various components are fabricated on the main surface of the substrate BS.

[0128] Referring to Figures 6F, 8A, and 24, the conductive portions of the block BK0 and a sub-pixel in the pixel island that overlaps with the first conductor L1 are spaced apart on the third direction D3, and partially overlap on the third direction D3. Referring to Figures 6F, 8A, and 24, the conductive portions CP of the block BK0 and a sub-pixel in the pixel island that overlaps with the first conductor L1 (the sub-pixel in the lower right corner of Figure 8A) are spaced apart on the third direction D3, and partially overlap on the third direction D3.

[0129] For example, referring to Figures 6A, 6F, 8B, and 24, the second conductor L2 further includes a connecting arm L21. The connecting arm L21 and the conductive portion CP of a sub-pixel in the pixel island that overlaps with the second conductor L2 (the sub-pixel located in the upper right corner of Figure 7, i.e., the sub-pixel in Figure 8B) are spaced apart from each other on the third direction D3, and partially overlap on the third direction D3. For example, the first transistor and the second transistor mentioned above are the threshold compensation transistor T3 and the light-emitting control transistor connected to the light-emitting element in the pixel circuit 10, respectively. For example, the light-emitting control transistor connected to the light-emitting element is the second light-emitting control transistor T5 mentioned above. Of course, in other embodiments of this disclosure, the block or connecting arm that forms a capacitor with the conductive portion CP of the first transistor in the pixel island may also take other forms, which are not limited here.

[0130] For example, as shown in FIG6D, the initialization signal line 210 includes multiple cutout regions HP. The second conductor L2 is located within one cutout region HP and is surrounded by the portion of the initialization signal line that forms the cutout region HP. The second conductor L2 does not overlap with the portion of the initialization signal line that forms the cutout region HP. That is, the second conductor L2 is completely surrounded by the portion of the initialization signal line that forms the cutout region HP. In the embodiments of this disclosure, the cutout region HP corresponds to the position of the portion of the thin film removed during the fabrication of the initialization signal line 210.

[0131] For example, referring to Figure 8A, the first conductor L1 includes a first sub-trace L111 and a second sub-trace L112. The first sub-trace L111 of the first conductor L1 is not located on the same layer as the second conductor L2, and the second sub-trace L112 of the first conductor L1 is not located on the same layer as the second conductor L2. Referring to Figures 8A, 10, and 11, the second conductor L2 is located on the second conductive pattern layer LY2, and the first conductor L1 is located on the third conductive pattern layer LY3.

[0132] For example, referring to Figure 3, data line 313 includes a first data line DL1, which extends from a first display area R1 to a second display area R2. For example, as shown in Figure 8A, a first portion DL11 of the first data line DL1 overlaps with the orthographic projection of the third conductor L3 onto the substrate BS. This arrangement helps reduce wiring area and improves light transmittance.

[0133] For example, referring to Figures 6C, 6D, 7, and 8A, the first data line DL1 includes a first portion DL11 and a second portion DL12. The first portion DL11 of the first data line DL1 partially overlaps with the third conductor L3, while the second portion DL12 of the first data line DL1 does not overlap with the third conductor L4. The first portion DL11 and the second portion DL12 of the first data line DL1 are located in different layers. For example, in Figure 8A, the first portion DL11 (conductor 214) of the first data line DL1 on the left is located in the second conductive pattern layer, and the second portion DL12 of the first data line DL1 on the left is located in the third conductive pattern layer. In Figure 8A, the first portion DL11 (conductor 114) of the first data line DL1 on the right is located in the first conductive pattern layer shown in Figure 9, and the second portion DL12 of the first data line DL1 on the right is located in the third conductive pattern layer shown in Figure 11. For example, referring to Figures 3, 19, and 23, the first portion DL11 of the first data line DL1 is located between adjacent pixel islands P1.

[0134] For example, referring to Figure 3, two first data lines DL1 are provided, and the two first data lines DL1 are respectively connected to two adjacent columns of sub-pixels. For example, as shown in Figure 8A, the first portion DL11 of the two first data lines overlaps with the orthographic projection portion of the same third conductor L3 on the substrate BS. This arrangement allows the data lines located between pixel islands in two adjacent columns of sub-pixels to be hidden under the third conductor, thereby reducing the wiring area and improving light transmittance.

[0135] For example, the first conductor L1 and the second conductor L2 are located on different layers and are connected through a via penetrating the insulating layer. Referring to Figures 8A and 11, the first conductor L1 is located on the third conductive pattern layer LY3, and the second conductor is located on the second conductive pattern layer LY2. Referring to Figures 23 and 24, an interlayer dielectric layer (ILD) is provided between the second conductive pattern layer LY2 and the third conductive pattern layer LY3, that is, the second sub-trace L112 of the first conductor L2 and the second conductor L2 are connected through a via penetrating the interlayer dielectric layer (ILD).

[0136] For example, referring to Figure 11, the first conductor and the third conductor L3 are located in the same layer, both in the third conductive pattern layer LY3. The fourth conductor L4 is located in the same layer as the third conductor L3, both in the third conductive pattern layer LY3.

[0137] For example, multiple pixel groups include multiple first pixel groups (i.e., pixel islands) and multiple second pixel groups (i.e., pixel islands) arranged at intervals. Adjacent first pixel groups and second pixel groups are connected by multiple traces (e.g., traces L11 connecting gate lines of adjacent pixel islands, traces L13 (i.e., 210) connecting initialization signal lines of adjacent pixel islands, traces L14 connecting light emission control signal lines of adjacent pixel islands, and first wires L1, etc.).

[0138] For example, as shown in Figures 8A and 10, the display panel 1 further includes a connecting wire Ld, wherein at least two of the plurality of traces between adjacent first and second pixel groups have their orthographic projections on the substrate falling within the orthographic projection of the connecting wire Ld on the substrate. For example, in some examples, there are multiple gaps between the plurality of traces, and the orthographic projection of at least one of the gaps on the substrate at least partially overlaps with the orthographic projection of the connecting wire Ld on the substrate, thereby preventing light leakage from the gaps between the traces.

[0139] For example, as shown in Figures 6A-6F, the pixel circuit 10 includes a first reset signal line 111, a second reset signal line 112, a gate line 113, a light emission control signal line 110, and an initialization signal line 210, to provide the pixel circuit with a first reset signal, a second reset signal, a gate scan signal, a light emission control signal, and an initialization signal, respectively. Multiple traces are selected from at least two of the first reset signal line 111, the second reset signal line 112, the gate line 113, the light emission control signal line 110, the initialization signal line 210, and the first wire. For example, the first reset signal line 111, the second reset signal line 112, the gate line 113, the light emission control signal line 110, the initialization signal line 210, and the second wire of the first pixel group are connected to the second reset signal line 112, the gate line 113, the light emission control signal line 110, the initialization signal line 210, and the second wire of the second pixel group via multiple traces, respectively.

[0140] For example, as shown in Figures 8A and 10, at least a portion of the orthographic projection of the connecting wire Ld on the substrate is located between the orthographic projections of the adjacent first pixel group and second pixel group on the substrate, and the connecting wire Ld and the initialization signal line are located on the same layer and integrally formed.

[0141] Figure 18 is a schematic diagram of a display panel with a pixel island comprising three sub-pixels according to at least one embodiment of the present disclosure. For example, a pixel island includes a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103. Figure 19 is a plan view of the semiconductor pattern of the display panel shown in Figure 18; Figure 20 is a plan view of the first conductive pattern layer of the display panel shown in Figure 18; Figure 21 is a plan view of the second conductive pattern layer of the display panel shown in Figure 18; and Figure 22 is a plan view of the third conductive pattern layer of the display panel shown in Figure 18.

[0142] For example, the display panel shown in Figure 18 has a basically the same connection structure as the display panel shown in Figure 7, the difference being that adjacent pixel islands in Figure 18 are located in the same row, while adjacent pixel islands in Figure 7 are arranged in an alternating pattern. For a description of Figure 18, please refer to the descriptions of Figures 7-11, which will not be repeated here.

[0143] For example, as shown in Figures 18 and 21, the connecting wire Ld and the second wire L2 are located on the same layer and integrally formed. It should be noted that the connecting wire Ld can also be located on the same layer as the first wire L1 and integrally formed; the embodiments of this disclosure do not limit this.

[0144] For example, in this embodiment, as shown in FIG21, the connecting wire Ld has a stop block BK0, which is disposed in the same layer as the connecting wire Ld and integrally formed. The conductive portions of a pixel unit in the pixel group of the stop block and BK0 that overlaps with the first wire L1 are spaced apart from each other on the third direction D1 and partially overlap on the third direction D3, thereby ensuring the stability of the threshold compensation transistor T3. For a detailed description, please refer to the above introduction, which will not be repeated here.

[0145] Figure 12 is a schematic diagram of a display panel with a pixel island comprising four sub-pixels according to at least one embodiment of the present disclosure. For example, a pixel island includes a first sub-pixel 101, a second sub-pixel 102, a third sub-pixel 103, and a fourth sub-pixel 104. Figure 13 is an enlarged schematic diagram of region A21 shown in Figure 12. Figure 14 is a plan view of the semiconductor pattern of the display panel shown in Figure 12; Figure 15 is a plan view of the first conductive pattern layer of the display panel shown in Figure 12; Figure 16 is a plan view of the second conductive pattern layer of the display panel shown in Figure 12; and Figure 17 is a plan view of the third conductive pattern layer of the display panel shown in Figure 12.

[0146] For example, in some embodiments of this disclosure, as shown in FIG12, at least two sub-pixels further include a third sub-pixel 103 and a fourth sub-pixel 104. The third sub-pixel 103 and the fourth sub-pixel 104 are arranged along a first direction D1 and located on one side of the first sub-pixel 101 and the second sub-pixel 102 along a second direction D2. The third sub-pixel 103 and the fourth sub-pixel 104 are electrically connected to another of a plurality of second conductors L2 (e.g., the second conductor L21 located below the layout as shown in FIG16). The second sub-trace L112 is electrically connected to at least one of a plurality of second conductors, for example, electrically connected to the second conductor L2 located in the first row of pixels (i.e., the first sub-pixel 101 and the second sub-pixel 102) and / or the second conductor L21 located in the second row of pixels (i.e., the third sub-pixel 103 and the fourth sub-pixel 104).

[0147] For example, the display panel shown in Figure 12 is basically the same as the display panel shown in Figure 7, except that the traces connecting two adjacent pixel groups are located on different layers. Specifically, for example, as shown in Figure 15, the trace L11 connecting the gate lines of two adjacent pixel islands is located in the first conductive pattern layer LY2, while in Figure 7 it is located in the third conductive pattern layer LY3; the initialization signal line 111 extends from the second display area R2 to the first display area R1 in the first conductive pattern layer; as shown in Figure 16, the initialization signal line 111 can also be connected through the trace Lrest located in the second conductive pattern layer.

[0148] For example, as shown in Figures 16 and 10, the second sub-trace L112 has a stop block BK0. The stop block BK0 and the second sub-trace L112 are located on different layers and are connected through a via. For example, referring to Figure 24, the stop block BK0 is located on the second conductive pattern layer, and the second sub-trace L112 is located on the third conductive pattern layer LY3 shown in Figures 17 and 11. Therefore, in this embodiment, the stop block BK0 is connected to the second sub-trace L112 through a via penetrating the insulating layer to ensure the stability of the threshold compensation transistor T3.

[0149] It should be noted that the remaining structures of the display panel (e.g., the block BK0) and the first conductor L1 can be referred to the description in Figures 7-11, and will not be repeated here.

[0150] At least one embodiment of this disclosure also provides a display device, including any of the above-described display panels. For example, the display device can be a display device such as an organic light-emitting diode (OLED) display, as well as any product or component with display function, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, or navigator, which includes such display devices.

[0151] Figure 25 is a schematic diagram of a display device provided in at least one embodiment of the present disclosure. As shown in Figure 25, the display device 2 includes a display panel 1 and a sensor 3. For example, the sensor 3 is disposed on one side of the display panel 1.

[0152] For example, as shown in Figures 1A-1C, sensor 3 is disposed on the second side of display panel 1, and sensor 3 is configured to receive light from the first side of display panel 1. For example, the first side of display panel 1 is used for display, and a first display area R1 allows light from the first side of display panel 1 to be at least partially transmitted to the second side of display panel 1.

[0153] For example, the orthographic projection of sensor 3 onto the substrate overlaps at least partially with the first display area R1.

[0154] It should be noted that, for clarity and brevity, the embodiments of this disclosure do not show all the constituent units of the display device. To achieve the basic functions of the display device, those skilled in the art can provide and set other structures (not shown) according to specific needs, and the embodiments of this disclosure do not impose any limitations on this.

[0155] The technical effects of the display device 2 provided in the above embodiments can be referred to the technical effects of the display panel 1 provided in the embodiments of this disclosure, and will not be repeated here.

[0156] The following points need to be explained:

[0157] (1) Unless otherwise defined, the same reference numerals in the embodiments of this disclosure and the accompanying drawings have the same meaning.

[0158] (2) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0159] (3) For clarity, the thickness of layers or regions is magnified in the drawings used to describe embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element, or there may be intermediate elements present.

[0160] (4) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0161] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, comprising: First display area; The second display area is located at least on one side of the first display area; Multiple sub-pixels are located in the first display area and the second display area, wherein the density of sub-pixels in the first display area is less than the density of sub-pixels in the second display area, and each sub-pixel includes a pixel circuit. Multiple pixel groups are located in the first display area, and at least one of the multiple pixel groups includes at least two sub-pixels; as well as A first power line is configured to provide a first voltage signal to the pixel circuit. The first power line includes multiple first conductors and multiple second conductors. The multiple first conductors extend from the second display area to the first display area and are electrically connected to the multiple pixel groups. The multiple second conductors are located in the first display area and are located between adjacent first conductors. The multiple second conductors extend along a first direction, and adjacent second conductors are spaced apart from each other along the first direction. The multiple second conductors are electrically connected to the multiple pixel groups. Wherein, at least one of the plurality of first conductors includes a first sub-line extending along a first direction and a second sub-line extending along a second direction, the first direction and the second direction intersect, and the second sub-line is electrically connected to at least one of the plurality of second conductors.

2. The display panel according to claim 1, wherein, The at least two sub-pixels include a first sub-pixel and a second sub-pixel, the first sub-pixel and the second sub-pixel are arranged along the first direction, at least one of the plurality of second wires is electrically connected to the first sub-pixel and the second sub-pixel, and the second sub-trace is located on a different layer from the plurality of second wires.

3. The display panel according to claim 2, wherein, The sub-pixel further includes a light-emitting element. The pixel circuit includes a first transistor, a second transistor, and a storage capacitor. The first transistor is connected to the second transistor and the storage capacitor, respectively. The second transistor is connected to the light-emitting element. The first transistor includes a first active part and a second active part. The first active part and the second active part are connected through a conductive part.

4. The display panel according to claim 3, wherein, The second conductor further includes a connecting arm, which is spaced apart from the conductive portion of a sub-pixel in the pixel group that overlaps with the second conductor in a third direction and partially overlaps with it in the third direction, which is perpendicular to the first direction and perpendicular to the second direction.

5. The display panel according to claim 4, wherein, The connecting arm has a C-shaped shape.

6. The display panel according to any one of claims 1-5, wherein, The plurality of pixel groups includes a plurality of first pixel groups and a plurality of second pixel groups arranged at intervals, and adjacent first pixel groups and second pixel groups are connected by a plurality of traces.

7. The display panel according to claim 6 further includes connecting wires, wherein at least two of the plurality of traces between the adjacent first pixel group and second pixel group have their orthographic projections on the substrate falling within the orthographic projection of the connecting wires on the substrate.

8. The display panel according to claim 6, wherein, The plurality of traces are spaced apart, and at least one of the gaps at least partially overlaps with the orthographic projection of the connecting wire onto the substrate.

9. The display panel according to any one of claims 6-8, wherein, The pixel circuit includes a first reset signal line, a second reset signal line, a gate line, a light emission control signal line, and an initialization signal line, to provide the pixel circuit with a first reset signal, a second reset signal, a gate scan signal, a light emission control signal, and an initialization signal, respectively. The plurality of traces are selected from at least two of the following: the first reset signal line, the second reset signal line, the gate line, the light emission control signal line, the initialization signal line, and the first conductor.

10. The display panel according to claim 7, wherein, The connecting wire has a stop block, which is disposed in the same layer as the connecting wire and is integrally formed thereon; The sub-pixel also includes a light-emitting element. The pixel circuit includes a first transistor, a second transistor, and a storage capacitor. The first transistor is connected to the second transistor and the storage capacitor. The second transistor is connected to the light-emitting element. The first transistor includes a first active part and a second active part. The first active part and the second active part are connected through a conductive part. The block and the conductive portion of a pixel unit in the pixel group that overlaps with the first conductor are spaced apart from each other in the third direction and partially overlap in the third direction.

11. The display panel according to claim 9, wherein, The orthographic projection of the connecting wire on the substrate is at least partially located between the orthographic projections of the adjacent first pixel group and second pixel group on the substrate.

12. The display panel according to claim 11, wherein, The first reset signal line, second reset signal line, gate line, light emission control signal line, initialization signal line, and second conductor of the first pixel group are respectively connected to the first reset signal line, second reset signal line, gate line, light emission control signal line, initialization signal line, and second conductor of the second pixel group through the multiple traces.

13. The display panel according to claim 12, wherein, The connecting wire and the second wire are located on the same layer and are integrally formed; or the connecting wire and the initialization signal line are located on the same layer and are integrally formed; or the connecting wire and the first wire are located on the same layer.

14. The display panel according to claim 3, wherein, The at least two sub-pixels further include a third sub-pixel and a fourth sub-pixel, the third sub-pixel and the fourth sub-pixel being arranged along the first direction and located on one side of the first sub-pixel and the second sub-pixel along the second direction, the third sub-pixel and the fourth sub-pixel being electrically connected to another of the plurality of second conductors, and the second sub-trace being electrically connected to at least one of the plurality of second conductors.

15. The display panel according to claim 3 or 14, wherein, The second sub-trace has a stop block, which is located on a different layer from the second sub-trace and is connected via a via. The block and the conductive portion of a pixel unit in the pixel group that overlaps with the first conductor are spaced apart from each other in the third direction and partially overlap in the third direction.

16. The display panel according to any one of claims 1-15, wherein, The first direction is perpendicular to the second direction.

17. The display panel according to any one of claims 1-16, wherein, The plurality of second conductors are arranged sequentially along the first direction.

18. The display panel according to any one of claims 1-17, wherein, The adjacent second conductors are not directly connected.

19. The display panel according to any one of claims 1-18, wherein, The first conductor and the second conductor are connected through a through-hole that penetrates the insulation layer.

20. The display panel according to any one of claims 1-19, wherein, The first power line also includes a third conductor and a fourth conductor. The third conductor extends along the second direction, from the second display area to the first display area, and the second conductor is electrically connected to the third conductor. The fourth conductor extends along the second direction, the second conductor is electrically connected to the fourth conductor, and the length of the fourth conductor in the second direction is less than or equal to the length of the third conductor in the second direction.

21. The display panel according to any one of claims 1-20, comprising a plurality of fourth conductors, the plurality of fourth conductors being located between adjacent third conductors, the plurality of fourth conductors being arranged sequentially along the second direction, and adjacent fourth conductors being spaced apart from each other in the second direction.

22. The display panel according to claim 20, wherein, The first conductor and the third conductor are located on the same layer, and the fourth conductor and the third conductor are located on the same layer.

23. The display panel according to any one of claims 1-22, wherein, The first display area includes multiple light-transmitting areas located between adjacent pixel groups.

24. The display panel according to claim 22, wherein, The plurality of pixel groups and the traces connecting adjacent pixel groups surround the plurality of light-transmitting areas.

25. A display device comprising the display panel according to any one of claims 1-24.

26. The display device according to claim 25, further comprising a sensor, wherein, The sensor is disposed on one side of the display panel, and the orthographic projection of the sensor on the substrate at least partially overlaps with the first display area.

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