DISPLAY PANELS AND DISPLAY EQUIPMENT

Abstract

The invention relates to a display panel and a display device. The display panel comprises: a base (BS) comprising a display area (R1) and a circumferential area (R2), the circumferential area (R2) located on at least one side of the display area (R1); multiple subpixels (P) located within the display area (R1); multiple constant voltage lines (60) arranged in the first direction (X), constant voltage lines (60) extending in the second direction (Y), constant voltage lines (60) located at least partially within the display area (R1) and the first direction (X) intersects with the second direction (Y); and wire (61) is located in the perimeter area (R2) and is connected to several constant voltage lines (60), the constant voltage lines (60) are configured to supply constant voltage to the sub-pixels (P), and wire (61) includes the power transmission channel (612) and the first branch (601) and the second branch (602) are connected separately to the power transmission channel (612).According to the display table, by arranging the wire (61) containing the first branch (601) and the second branch (602), the uniformity of the signal on the constant voltage lines (60) is facilitated, thus facilitating the improvement of the display effect.

Description

Display panel and display device Technical Field

[0001] At least one embodiment of the present disclosure relates to a display panel and a display device. Background Art

[0002] In recent years, with the advancement of display technology, organic light-emitting diode (OLED) displays have become one of the hot topics in the field of flat panel display research. More and more active matrix organic light-emitting diode (AMOLED) display panels have entered the market. Compared with thin film transistor liquid crystal display (TFT-LCD) panels, AMOLED has faster response speed, higher contrast and wider viewing angle.

[0003] To improve display effects, engineers are constantly seeking more optimized pixel circuit designs.

[0004] Summary of the Invention

[0005] At least one embodiment of the present disclosure relates to a display panel and a display device.

[0006] At least one embodiment of the present disclosure provides a display panel, comprising: a base substrate, comprising a display area and a peripheral area, the peripheral area being located on at least one side of the display area; a plurality of sub-pixels being located in the display area; a plurality of constant voltage lines arranged along a first direction, the constant voltage lines extending along a second direction, the constant voltage lines being at least partially located in the display area, the first direction intersecting with the second direction; and a conductive line being located in the peripheral area and connected to the plurality of constant voltage lines; the constant voltage lines being configured to provide a constant voltage to the sub-pixels.

[0007] For example, the display panel also includes a first power line, which is configured to provide a constant first power voltage to the sub-pixel, and the first power line includes a first power bus, which is located in the peripheral area, and at least part of the first power bus extends along the second direction.

[0008] For example, the display panel also includes a second power line, which is configured to provide a constant second power voltage to the sub-pixel, and the second power line includes a second power bus, which is located in the peripheral area, and at least part of the second power bus extends along the second direction.

[0009] For example, the conductive line includes a conductive bus, at least part of which extends along the second direction, and the at least part of which extends along the second direction is located between the at least part of the first power bus and the at least part of the second power bus extending along the second direction.

[0010] For example, the display panel further includes an integrated circuit, and the conductive bus, the first power bus, and the second power bus are all connected to the integrated circuit.

[0011] For example, the conductive wire includes a first branch and a second branch respectively connected to the conductive bus, the first power line includes a first power connection line, the first power connection line extends along the first direction, and the orthographic projection of the first power connection line on the substrate overlaps with the orthographic projection of the first branch on the substrate.

[0012] For example, the display panel further includes a planarization layer, the planarization layer is located on a side of the first branch close to the base substrate, the first branch has a plurality of openings, and the openings are configured to expose a portion of the planarization layer.

[0013] For example, the material of the planarization layer includes an organic material.

[0014] For example, the first branch extends along the first direction, the angle between the second branch and the first branch is an obtuse angle, and the angle between the second branch and the conductive bus is an obtuse angle.

[0015] For example, the shape of the second branch includes at least one of an arc, a curve, and a broken line.

[0016] For example, the display panel further includes a plurality of conductive connection lines, the second branch is connected to the plurality of conductive connection lines, and a portion of the plurality of constant voltage lines are respectively connected to the plurality of conductive connection lines.

[0017] For example, the display panel further includes a plurality of signal connection lines, and the orthographic projection of at least a portion of the plurality of signal connection lines on the base substrate overlaps with the orthographic projection of the second branch on the base substrate.

[0018] For example, at least one signal connection line among the plurality of signal connection lines is disposed between two adjacent conductive connection lines.

[0019] For example, the signal connection line includes at least one of a clock signal line, a start input signal line of a shift register, a low level signal line, or a high level signal line.

[0020] For example, the plurality of constant voltage lines, at least a portion of the conductive bus, and the second branch are located on the same layer, and the first branch is located on another layer.

[0021] For example, the sub-pixel includes a pixel circuit and a light-emitting element, the pixel circuit is configured to drive the light-emitting element, the pixel circuit includes a reset transistor, the first electrode of the reset transistor is connected to the initialization line, the second electrode of the reset transistor is connected to the first electrode of the light-emitting element, the reset transistor is configured to reset the first electrode of the light-emitting element, and the constant voltage line is the initialization line.

[0022] For example, the sub-pixel includes a pixel circuit and a light-emitting element, the pixel circuit is configured to drive the light-emitting element, the pixel circuit includes a driving transistor, a first reset transistor and a second reset transistor, the first electrode of the first reset transistor is connected to a first initialization line, the second electrode of the first reset transistor is connected to the gate of the driving transistor, the first reset transistor is configured to reset the gate of the driving transistor, the first electrode of the second reset transistor is connected to the second initialization line, the second electrode of the second reset transistor is connected to the first electrode of the light-emitting element, and the second reset transistor is configured to reset the first electrode of the light-emitting element.

[0023] For example, the display panel further includes an initialization signal line extending along the first direction, the constant voltage line is connected to the initialization signal line, and the second initialization line includes the initialization signal line and the constant voltage line connected to each other.

[0024] For example, the pixel circuit includes a compensation transistor and an anti-leakage transistor, the gate of the compensation transistor is configured to receive a compensation control signal, the first electrode of the compensation transistor is connected to the gate of the driving transistor, and the second electrode of the compensation transistor is electrically connected to the second electrode of the driving transistor; the compensation transistor includes a first compensation sub-transistor and a second compensation sub-transistor connected in series, and the first compensation sub-transistor and the second compensation sub-transistor are connected through an intermediate node located therebetween; the first electrode of the anti-leakage transistor is connected to a reference voltage line, the second electrode of the anti-leakage transistor is connected to the intermediate node, and the constant voltage line is the reference voltage line.

[0025] At least one embodiment of the present disclosure provides a display device including any of the above-mentioned display panels. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0027] FIG1 is a schematic diagram of a display panel.

[0028] FIG2 is a schematic diagram of a display panel provided by an embodiment of the present disclosure.

[0029] FIG3 is an enlarged view of the lower left corner of FIG2.

[0030] FIG4 is a schematic diagram of a display panel provided by an embodiment of the present disclosure.

[0031] FIG5 is an enlarged view of the lower left corner of FIG4.

[0032] FIG6 is a partial schematic diagram of a stack of conductive layers LY1 and LY2 in a display panel provided by an embodiment of the present disclosure.

[0033] 7 to 9 are partial schematic diagrams of stacked layers of a conductive layer LY1 and a conductive layer LY2 in a display panel provided by an embodiment of the present disclosure.

[0034] FIG10 is a partial plan view of a conductive layer LY1 in a display panel provided by an embodiment of the present disclosure.

[0035] FIG11 is a partial plan view of a conductive layer LY2 in a display panel provided by an embodiment of the present disclosure.

[0036] FIG12 is a cross-sectional view taken along line A1-A2 of FIG9.

[0037] FIG13 is a cross-sectional view taken along line A3-A4 of FIG9.

[0038] FIG14 is a partial schematic diagram of a stack of conductive layers LY1 and LY2 in a display panel provided by an embodiment of the present disclosure.

[0039] FIG15 is a partial plan view of a conductive layer LY1 in a display panel provided by an embodiment of the present disclosure.

[0040] FIG16 is a partial plan view of a passivation layer PVX in a display panel provided by an embodiment of the present disclosure.

[0041] FIG17 is a partial plan view of a planarization layer PLN in a display panel provided by an embodiment of the present disclosure.

[0042] FIG18 is a partial plan view of the conductive layer LY2 in the display panel provided by an embodiment of the present disclosure.

[0043] FIG19 is a schematic diagram of a pixel circuit and a light-emitting element of a sub-pixel in a display panel provided in some embodiments of the present disclosure.

[0044] FIG20 is a schematic diagram of a display panel provided in an embodiment of the present disclosure.

[0045] FIG21 is a schematic diagram of a pixel circuit and a light-emitting element of a sub-pixel in a display panel provided in some embodiments of the present disclosure.

[0046] FIG22 is a schematic diagram of a display panel provided in an embodiment of the present disclosure.

[0047] FIG23 is a schematic diagram of a display panel provided in an embodiment of the present disclosure.

[0048] FIG24 is a layout diagram of a display panel provided in an embodiment of the present disclosure.

[0049] FIG. 25 is a plan view of an active layer LY0 in a display panel according to an embodiment of the present disclosure.

[0050] FIG26 is a plan view of a conductive layer LYa in a display panel according to an embodiment of the present disclosure.

[0051] FIG27 is a plan view of a conductive layer LYb in a display panel according to an embodiment of the present disclosure.

[0052] FIG. 28 is a plan view of a via hole VH1 penetrating an insulating layer in a display panel according to an embodiment of the present disclosure.

[0053] FIG29 is a plan view of a conductive layer LY1 in a display panel according to an embodiment of the present disclosure.

[0054] FIG30 is a plan view of a via hole VH2 penetrating an insulating layer in a display panel provided by an embodiment of the present disclosure.

[0055] FIG31 is a plan view of a conductive layer LYb in a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0057] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0058] Figure 1 is a schematic diagram of a display panel. As shown in Figure 1 , the display panel includes a base substrate BS. Base substrate BS includes a display area R1 and a peripheral area R2, with peripheral area R2 located on at least one side of display area R1. As shown in Figure 1 , peripheral areas R2 are located above, below, to the left, and to the right of display area R1. Figure 1 illustrates an example where peripheral areas R2 surround display area R1.

[0059] In the embodiments of the present disclosure, a first direction X and a second direction Y are shown in a plan view, and a third direction Z is shown in a cross-sectional view. The first direction X and the second direction Y are directions parallel to the main surface of the base substrate BS, and the third direction Z is a direction perpendicular to the main surface of the base substrate BS. The first direction X and the second direction Y intersect. The embodiments of the present disclosure are described using the example where the first direction X is perpendicular to the second direction Y.

[0060] As shown in FIG1 , an integrated circuit 30 is provided in the peripheral region. The integrated circuit 30 is located in the peripheral region R2. The region where the integrated circuit 30 is provided is the integrated circuit installation region R21.

[0061] As shown in Figure 1, the peripheral region R2 may further include a bending region R22. To reduce the frame of the display panel, the integrated circuit 30 may be positioned on the back side of the substrate by bending. Of course, the display panel may also not include the bending region R22.

[0062] As shown in FIG1 , the display panel includes a plurality of sub-pixels P, which are located in a display region R1. FIG1 illustrates some of the sub-pixels P in the display panel. The number of sub-pixels P in the display panel can be determined as needed. For example, in some embodiments, the sub-pixels P can be arranged in an array, but this is not limited to this arrangement. The arrangement of the sub-pixels P can be determined as needed.

[0063] Figure 2 is a schematic diagram of a display panel provided by an embodiment of the present disclosure. Figure 3 is an enlarged view of the lower left corner of Figure 2.

[0064] As shown in Figures 2 and 3, the display panel includes a conductor 61 and multiple constant-voltage lines 60. The constant-voltage lines 60 are configured to provide a constant voltage to the sub-pixels P. The conductor 61 is located in the peripheral region R2 and is connected to the multiple constant-voltage lines 60. The constant-voltage lines 60 can also be referred to as static-level input lines. The static-level input lines are configured to provide a static voltage to the sub-pixels P.

[0065] 2 and 3 , a plurality of constant pressure lines 60 are arranged along the first direction X. FIG2 does not show all the constant pressure lines 60 , and the number of the constant pressure lines 60 is not limited to that shown in the figure and can be determined as needed.

[0066] As shown in FIG2 , the display panel has a centerline C0 extending along the second direction. The left and right halves of the display panel are symmetrically arranged relative to the centerline C0. For clarity, FIG2 does not show the wiring structure located to the right of the centerline C0, nor does it show all wiring located to the left of the centerline C0.

[0067] As shown in FIG. 2 and FIG. 3 , the constant pressure line 60 extends along the second direction Y, and the first direction X intersects the second direction Y.

[0068] In the embodiments of the present disclosure, a component extending in a direction refers to the overall extension direction of the component. It is not required that every part of the component extend in this direction, and the component is not limited to being a straight line. For example, the component can be a broken line. For example, the extension direction of a component can refer to the extension direction of the length of the component.

[0069] As shown in FIG. 2 and FIG. 3 , the conductive wire 61 includes a conductive bus 612 and a first branch 601 and a second branch 602 respectively connected to the conductive bus 612 .

[0070] The display panel provided by the embodiment of the present disclosure is advantageous for uniformity of the signal on the constant voltage line 60 and for improving the display effect by providing the conductive line 61 including the first branch 601 and the second branch 602 .

[0071] For example, as shown in FIG. 2 and FIG. 3 , the conductive bus 612 extends along the second direction Y, and the first branch 601 extends along the first direction X.

[0072] As shown in Figures 2 and 3, the first branch 601 and the second branch 602 are disposed on opposite sides of the conductive bus 612. The first branch 601 extends from a position close to the conductive bus 612 to a position away from the conductive bus 612, and the second branch 602 extends from a position close to the conductive bus 612 to a position away from the conductive bus 612.

[0073] For example, as shown in FIG. 2 and FIG. 3 , the included angle between the second branch 602 and the first branch 601 is an obtuse angle, and the included angle between the second branch 602 and the conductive bus 612 is an obtuse angle.

[0074] For example, the shape of the second branch 602 includes at least one of an arc, a curve, and a broken line. Figures 2 and 3 illustrate the case where the shape of the second branch 602 is an arc.

[0075] As shown in FIG2 , the display panel is a rounded rectangular shape. As shown in FIG2 and FIG3 , the second branch 602 is located at a rounded corner of the display panel. FIG2 and FIG3 show the second branch 602 at the lower left rounded corner of the display panel. The shape of the second branch 602 can be the same as the shape of the edge of the display panel it is adjacent to.

[0076] As shown in FIG2 , the length of the second branch 602 is shorter than the length of the first branch 601 . The length of the second branch 602 is longer than the length of the conductive bus 612 .

[0077] 2 and 3 , the display panel further includes an integrated circuit 30, and the conductive bus 612 is connected to the integrated circuit 30. Since the conductive bus 612 is connected to the constant voltage line 60, the constant voltage line 60 is connected to the integrated circuit 30.

[0078] For example, as shown in FIG. 3 , the display panel further includes a plurality of conductive connection lines 610 , the second branches 602 are connected to the plurality of conductive connection lines 610 , and a portion of the plurality of constant voltage lines 60 are respectively connected to the plurality of conductive connection lines 610 .

[0079] As shown in FIG3 , the plurality of constant voltage lines 60, the conductive bus 612, and the second branch 602 are located on the same layer, while the first branch 601 is located on another layer. For example, the plurality of constant voltage lines 60, the conductive bus 612, and the second branch 602 are located on the conductive layer LY1, while the first branch 601 is located on the conductive layer LY2.

[0080] 3 , a plurality of conductive connection lines 610 are located in the conductive layer LY2 . The first branch 601 and the plurality of conductive connection lines 610 are both located in the conductive layer LY2 .

[0081] Figure 3 shows a via hole V0. For example, as shown in Figure 3, a portion of the plurality of constant voltage lines 60 is connected to the first branch 601, and each constant voltage line 60 is connected to the first branch 601 through a via hole V0.

[0082] Figure 3 shows vias V1 and V2. A portion of the plurality of constant voltage lines 60 is connected to the second branch 602. For example, as shown in Figure 3, both ends of the conductive connection line 610 are connected to the second branch 602 and the constant voltage line 60, respectively.

[0083] 3 illustrates an example of a conductive connecting line 610 connected to a constant voltage line 60. In other embodiments, a conductive connecting line 610 may be connected to multiple constant voltage lines 60. That is, a conductive connecting line 610 may be connected to at least one constant voltage line 60.

[0084] Figure 3 shows via V3. Conductive bus 612 and second branch 602 are integrally formed and connected to first branch 601 via via V3. Of course, conductive bus 612 can also be formed in segments, in which case a portion of conductive bus 612 and second branch 602 are integrally formed.

[0085] For example, an insulating layer is provided between the conductive layer LY1 and the conductive layer LY2 , and the via hole V0 , the via hole V1 , the via hole V2 , and the via hole V3 are all via holes penetrating the insulating layer between the conductive layer LY1 and the conductive layer LY2 .

[0086] Figure 4 is a schematic diagram of a display panel provided by an embodiment of the present disclosure. Figure 5 is an enlarged view of the lower left corner of Figure 4 .

[0087] For example, as shown in FIG4 and FIG5 , the display panel further includes a first power line 71 , which is configured to provide a constant first power voltage to the pixel circuit 1120 . The first power line 71 includes a first power bus 710 . The first power bus 710 is located in the peripheral region R2 , and the first power bus 710 extends along the second direction Y. For example, at least a portion of the first power bus 710 extends along the second direction Y.

[0088] For example, as shown in Figures 4 and 5, the display panel also includes a second power line 72, which is configured to provide a constant second power supply voltage to the sub-pixel P (the pixel circuit of the sub-pixel P), and the second power line 72 includes a second power bus 720, which is located in the peripheral area R2 and extends along the second direction Y.

[0089] For example, as shown in FIG. 4 and FIG. 5 , the conductive bus 612 is located between the first power bus 710 and the second power bus 720 .

[0090] For example, as shown in FIG. 4 and FIG. 5 , at least a portion of the conductive bus 612 extending along the second direction Y is located between at least a portion of the first power bus 710 and at least a portion of the second power bus 720 extending along the second direction Y.

[0091] For example, as shown in FIG. 4 and FIG. 5 , the conductive bus 612 , the first power bus 710 , and the second power bus 720 are all connected to the integrated circuit 30 .

[0092] For example, as shown in Figures 4 and 5 , the first power line 71 includes a first power connection line 716, which extends along the first direction X. Figure 4 illustrates an example in which the first power connection line 716 and the first branch 601 are spaced apart in the second direction Y. However, the embodiments of the present disclosure are not limited thereto. In other embodiments, the orthographic projection of the first power connection line 716 on the base substrate BS overlaps with the orthographic projection of the first branch 601 on the base substrate BS.

[0093] Figure 6 is a partial schematic diagram of the stack of conductive layers LY1 and LY2 in a display panel according to an embodiment of the present disclosure. Figures 7 to 9 are partial schematic diagrams of the stack of conductive layers LY1 and LY2 in a display panel according to an embodiment of the present disclosure. Figures 7 to 9 are respectively enlarged schematic diagrams of the dashed boxes A, B, and C in Figure 6.

[0094] For example, as shown in FIG7 , the display panel further includes a plurality of signal connection lines 40. The orthographic projections of at least a portion of the plurality of signal connection lines 40 on the base substrate BS overlap with the orthographic projections of the second branches 602 on the base substrate BS. As shown in FIG7 , the plurality of signal connection lines 40 are located on the conductive layer LY2. The signal connection lines 40 and the second branches 602 are insulated from each other.

[0095] For example, as shown in FIG7 , at least one signal connection line 40 from among the plurality of signal connection lines 40 is disposed between two adjacent conductive connection lines 610. FIG7 illustrates the conductive connection line 610 using a black dashed line. FIG7 shows two conductive connection lines 610. FIG7 illustrates an example of ten signal connection lines 40 disposed between two conductive connection lines 610, but the present invention is not limited thereto. The number of signal connection lines 40 between two conductive connection lines 610 can be determined as needed.

[0096] For example, the signal connection lines 40 include gate-on-array (GOA) signal lines.

[0097] For example, the signal connection line 40 includes at least one of a clock signal line CK or CB, a start input signal line STV of a shift register, a low-level signal line VGL, or a high-level signal line VGH.

[0098] 7 shows an initialization signal line 81 and an initialization signal line 82. The initialization signal line 81 and the initialization signal line 82 are configured to supply initialization signals to sub-pixels, respectively.

[0099] FIG. 8 shows that the first branch 601 has a plurality of openings 6010 .

[0100] FIG. 8 also shows a via V3 , a second branch, and a conductive bus 612 .

[0101] FIG9 shows the first branch 601 , the opening 6010 in the first branch 601 , and the constant pressure line 60 .

[0102] As shown in FIG. 9 , the display panel further includes a first power signal line 718 , which is connected to the first power connection line 716 .

[0103] 9 also shows a data signal line DT. For example, the data signal line DT is configured to provide a data voltage to a sub-pixel.

[0104] Figure 6 is a schematic diagram of the lower left corner of the entire display panel, including conductive layers LY1 and LY2. Conductor 61 originates from the integrated circuit and runs between the first power bus 710 and the second power bus 720. It then crosses the bend and runs horizontally to the right (first branch 601, conductive layer LY2) and to the upper left (second branch 602, conductive layer LY1) at the lower rounded corner. As shown in Figure 7, second branch 602 is connected to the constant voltage line 60 of the display area at the rounded corner of the display panel via a jumper wire located on conductive layer LY2 (horizontally, conductive connection line 610, conductive layer LY2).

[0105] 7 , the second branch 602 located in the conductive layer LY1 is connected to the conductive connection line 610 located in the conductive layer LY2 . The conductive connection line 610 may be disposed in the interval between the GOA signal lines.

[0106] Figure 10 is a partial plan view of a conductive layer LY1 in a display panel according to an embodiment of the present disclosure. Figure 11 is a partial plan view of a conductive layer LY2 in a display panel according to an embodiment of the present disclosure. For example, Figure 10 may be a plan view of the conductive layer LY1 in the display panel of Figure 9. Figure 11 may be a plan view of the conductive layer LY2 in the display panel of Figure 9. Figure 12 is a cross-sectional view taken along line A1-A2 in Figure 9. Figure 13 is a cross-sectional view taken along line A3-A4 in Figure 9.

[0107] As shown in FIG. 10 , a plurality of first power signal lines 718 are arranged along a first direction X, each first power signal line 718 extends along a second direction Y, and the plurality of first power signal lines 718 are connected to the first power connection line 716 .

[0108] As shown in FIG. 10 , the constant voltage line 60 is located between two adjacent first power signal lines 718 .

[0109] 9 to 11 , the constant voltage line 60 is connected to the first branch 601 through a via hole V4. The via hole V4 is a via hole that passes through the insulating layer between the conductive layer LY1 and the conductive layer LY2.

[0110] Referring to Figures 9 to 11 , the first power connection line 716 includes a first power connection portion 7161 and a second power connection portion 7162, which are connected. Referring to Figures 9 to 11 , the first power connection portion 7161 and the second power connection portion 7162 are connected via a via V5. Via V5 is a via that penetrates the insulating layer between the conductive layer LY1 and the conductive layer LY2.

[0111] As shown in Figures 11 to 13 , the first branch 601 has a plurality of openings 6010. Figure 11 takes the plurality of openings 6010 arranged in sequence along the first direction X as an example for illustration.

[0112] As shown in Figures 11 to 13, the second power connection portion 7162 has a plurality of openings 71620. As shown in Figure 11, to better arrange the openings 71620, the plurality of openings 71620 can be evenly distributed. The plurality of openings 71620 can be arranged in rows and columns, and the openings 71620 in adjacent rows can be staggered.

[0113] As shown in FIG. 11 , the maximum dimension of the second power connection portion 7162 in the second direction Y is smaller than the maximum dimension of the first branch 601 in the second direction Y.

[0114] FIG9 is a partial schematic diagram of a stack of conductive layers LY1 and LY2 in a display panel provided by an embodiment of the present disclosure.

[0115] As shown in FIG12 and FIG13 , the display panel further includes an insulating layer 501 and an insulating layer 502 . The insulating layer 501 is located on the base substrate BS, the conductive layer LY1 is located on the insulating layer 501 , the insulating layer 502 is located on the conductive layer LY1 , ​​and the conductive layer LY2 is located on the insulating layer 502 .

[0116] 12 and 13 are described by taking an example in which the insulating layer 502 includes a passivation layer PVX and a planarization layer PLN.

[0117] For example, the base substrate BS may be a glass substrate, a polyimide substrate, or the like.

[0118] For example, both insulating layer 501 and insulating layer 502 are made of insulating materials. Insulating materials include inorganic insulating materials and organic insulating materials. For example, the passivation layer PVX is made of an inorganic insulating material, and the planarization layer PLN is made of an organic insulating material. Inorganic insulating materials include, but are not limited to, at least one of silicon oxide, silicon nitride, and silicon oxynitride, and can be selected as needed. Organic insulating materials include, but are not limited to, polyimide and can be selected as needed.

[0119] For example, as shown in Figures 12 and 13, the planarization layer PLN is located on the side of the first branch 601 near the base substrate BS, and the opening 6010 is configured to expose a portion of the planarization layer PLN. For example, the material of the planarization layer PLN includes an organic material. The provision of at least one of the opening 6010 and the opening 71620 facilitates the release of moisture from the planarization layer PLN during manufacturing, preventing moisture from entering the display area along the planarization layer PLN, thereby affecting the light-emitting elements and the display effect. This allows the first branch 601 to have a wider trace width, reducing trace impedance.

[0120] FIG14 is a partial schematic diagram of the stack of conductive layers LY1 and LY2 in the display panel provided by an embodiment of the present disclosure. FIG7 to FIG9 are enlarged schematic diagrams of the dotted boxes A, B, and C in FIG14, respectively. FIG15 is a partial plan view of the conductive layer LY1 in the display panel provided by an embodiment of the present disclosure. FIG16 is a partial plan view of the passivation layer PVX in the display panel provided by an embodiment of the present disclosure. FIG17 is a partial plan view of the planarization layer PLN in the display panel provided by an embodiment of the present disclosure. FIG18 is a partial plan view of the conductive layer LY2 in the display panel provided by an embodiment of the present disclosure.

[0121] Figure 16 illustrates the passivation layer through a via in the passivation layer PVX. That is, the portion shown in the figure is the via in the passivation layer PVX, while the portion not shown is the body of the passivation layer PVX. As shown in Figure 16, in the bending region R22, the material of the passivation layer is hollowed out to form a via to facilitate bending.

[0122] Figure 17 illustrates the planarization layer PLN through a via hole. Specifically, the via hole is shown in the planarization layer PLN, while the portion not shown is the planarization layer PLN itself. As shown in Figure 17 , the material of the planarization layer PLN is retained in the bend region R22 to serve as an insulating layer between the conductive layers LY1 and LY2.

[0123] As shown in Figures 14 to 18 , the conductive bus 612 of the conductor 61 can be formed in segments, with portions located on different layers connected by vias. As shown in Figures 14 to 18 , the conductive bus 612 is formed by portions located on conductive layer LY1 and portions located on conductive layer LY2 connected by vias.

[0124] As shown in Figures 14 to 18, the first power bus 710 can be formed in sections, with sections located on different layers connected by vias. As shown in Figures 14 to 18, the first power bus 710 is formed by sections located on the conductive layer LY1 and sections located on the conductive layer LY2 connected by vias.

[0125] As shown in Figures 14 to 18, the second power bus 720 can be formed in sections, with sections located on different layers connected by vias. As shown in Figures 14 to 18, the second power bus 720 is formed by sections located on conductive layer LY1 and sections located on conductive layer LY2 connected by vias.

[0126] FIG19 is a schematic diagram of a pixel circuit and a light-emitting element of a sub-pixel in a display panel provided in some embodiments of the present disclosure. For example, as shown in FIG19 , a sub-pixel P includes a pixel circuit 1120 and a light-emitting element 1110. The pixel circuit 1120 is configured to drive the light-emitting element 1110. The constant voltage line 60 is configured to provide a constant voltage to the pixel circuit 1120.

[0127] FIG19 shows a circuit diagram of a pixel circuit of a display substrate provided by some embodiments of the present disclosure. The specific structure of the pixel circuit provided by some embodiments of the present disclosure will be briefly described below with reference to FIG19.

[0128] For example, the plurality of pixel circuits included in the plurality of sub-pixels P are disposed on a base substrate BS, as shown in FIG1 , in a display region R1 of the base substrate BS. For example, the gate driver circuit may be configured to output a plurality of output signals to the plurality of pixel circuits to control the plurality of pixel circuits to generate a plurality of drive currents to respectively drive the light-emitting elements in the plurality of sub-pixels P to emit corresponding light, thereby realizing image display.

[0129] For example, as shown in FIG. 19 , each sub-pixel P includes a pixel circuit 1120 and a light emitting element 1110 .

[0130] For example, as shown in FIG. 19 , the pixel circuit 1120 is configured to generate a driving current to control the light emitting element 1110 to emit light.

[0131] For example, the light-emitting element 1110 includes a first electrode E1, a second electrode E2, and a light-emitting functional layer disposed between the first electrode E1 and the second electrode E2. As shown in FIG19 , the first electrode E1 of the light-emitting element 1110 is electrically connected to the pixel circuit 1120, and the second electrode E2 of the light-emitting element 1110 is electrically connected to the voltage terminal VSS. When a driving current generated by the pixel circuit 1120 flows through the light-emitting element 1110, the light-emitting functional layer of the light-emitting element 1110 emits light with a brightness corresponding to the magnitude of the driving current.

[0132] For example, the light-emitting element 1110 may be a light-emitting diode, etc. The light-emitting diode may be a micro light-emitting diode (Micro Light Emitting Diode, Micro LED), an organic light-emitting diode (Organic Light Emitting Diode, OLED) or a quantum dot light-emitting diode (Quantum Dot Light Emitting Diodes, QLED), etc. The light-emitting element 1110 is configured to receive a light-emitting signal (for example, a driving current) when in operation, and emit light with an intensity corresponding to the light-emitting signal. The first electrode of the light-emitting element 1110 may be an anode, and the second electrode of the light-emitting diode may be a cathode. It should be noted that, in the embodiment of the present disclosure, the light-emitting functional layer of the light-emitting element 1110 may include the electroluminescent layer itself and a common layer located on both sides of the electroluminescent layer. For example, the common layer may include a hole injection layer, a hole transport layer, an electron injection layer and an electron transport layer, etc. In actual applications, the specific structure of the light-emitting element 1110 can be designed and determined according to the actual application environment, which is not limited here. For example, the light-emitting element 1110 has a light emission threshold voltage, and the light-emitting element 1110 emits light when the voltage between the first electrode and the second electrode of the light-emitting element 1110 is greater than or equal to the light emission threshold voltage.

[0133] For example, as shown in Figure 19, the pixel circuit 1120 includes a driving subcircuit 1121, a data writing subcircuit 1122, a storage subcircuit 1123, a compensation subcircuit 1124, a light emitting control subcircuit 1125, a first reset subcircuit 1126, and a second reset subcircuit 1127.

[0134] For example, the driver sub-circuit 1121 includes a first terminal, a second terminal, and a control terminal, and is configured to generate a driving current that drives the light-emitting element 1110 to emit light. For example, as shown in FIG19 , the control terminal of the driver sub-circuit 1121 is electrically connected to the node Nd1, the first terminal of the driver sub-circuit 1121 is electrically connected to the node Nd2, and the second terminal of the driver sub-circuit 1121 is electrically connected to the node Nd3.

[0135] For example, as shown in Figure 19, the data writing sub-circuit 1122 is electrically connected to the first end (i.e., node Nd2) of the driving sub-circuit 1121 and the data signal line, respectively, and is configured to write the data signal Vdata provided by the data signal line into the first end of the driving sub-circuit 1121 in response to the scanning signal Ga1.

[0136] For example, as shown in FIG19 , the storage sub-circuit 1123 is electrically connected to the voltage terminal VDD and the control terminal (ie, node Nd1 ) of the driving sub-circuit 1121 , and is configured to store a compensation signal based on the data signal Vdata.

[0137] For example, as shown in FIG19 , the compensation sub-circuit 1124 is electrically connected to the second terminal (i.e., node Nd3) and node Nd1 of the driver sub-circuit 1121, and is configured to perform threshold compensation on the driver sub-circuit 1121 in response to the compensation control signal Ga2. The compensation signal stored in the storage sub-circuit 1123 represents a signal obtained after threshold compensation.

[0138] For example, as shown in FIG19 , the light-emission control subcircuit 1125 is electrically connected to a first terminal and a second terminal of the driver subcircuit 1121, respectively, and is configured to control the drive current generated by the driver subcircuit 1121 to be transmitted to the light-emitting element 1110 in response to a light-emission control signal EM. For example, the light-emission control subcircuit 1125 includes a first light-emission control subcircuit 1125A and a second light-emission control subcircuit 1125B. The first light-emission control subcircuit 1125A is electrically connected to a first terminal (i.e., node Nd2) of the driver subcircuit 1121 and a voltage terminal VDD, and is configured to connect or disconnect the driver subcircuit 1121 and the voltage terminal VDD in response to the light-emission control signal EM. The second light-emitting control sub-circuit 1125B is electrically connected to the second end of the driving sub-circuit 1121 (i.e., node Nd3) and the first electrode E1 of the light-emitting element 1110, and is configured to respond to the light-emitting control signal EM to realize the connection between the driving sub-circuit 1121 and the light-emitting element 1110 (for example, the first electrode E1 of the light-emitting element 1110) being turned on or off.

[0139] For example, as shown in Figure 19, the first reset sub-circuit 1126 is electrically connected to the node Nd1 (the control end of the driving sub-circuit 1121) and the first initialization voltage end Vinit1, respectively, and is configured to reset the control end of the driving sub-circuit 1121 (i.e., the node Nd1) in response to the first reset control signal Re. For example, the first reset sub-circuit 1126 can write the first initialization voltage provided by the first initialization voltage end Vinit1 into the control end of the driving sub-circuit 1121 (i.e., the node Nd1) to reset the control end of the driving sub-circuit 1121.

[0140] For example, as shown in Figure 19, the second reset sub-circuit 1127 is electrically connected to the first electrode of the light-emitting element 1110 and the second initialization voltage terminal Vinit2, respectively, and is configured to reset the first electrode E1 of the light-emitting element 1110 in response to the second reset control signal Rst. For example, the second reset sub-circuit 1127 can write the second initialization voltage provided by the second initialization voltage terminal Vinit2 into the first electrode E1 of the light-emitting element 1110 to reset the first electrode E1 of the light-emitting element 1110.

[0141] For example, as shown in Figure 19, the driving sub-circuit 1121 includes a driving transistor T3, the control end of the driving sub-circuit 1121 includes the gate of the driving transistor T3, the first end of the driving sub-circuit 1121 includes the first electrode of the driving transistor T3, and the second end of the driving sub-circuit 1121 includes the second electrode of the driving transistor T3.

[0142] For example, as shown in Figure 19, the data writing sub-circuit 1122 includes a data writing transistor T4, the gate of the data writing transistor T4 is configured to receive the scanning signal Ga1, the first electrode of the data writing transistor T4 is electrically connected to the data signal line, and the second electrode of the data writing transistor T4 is electrically connected to the first electrode of the driving transistor T3, that is, the second electrode of the data writing transistor T4 is electrically connected to the node Nd2.

[0143] For example, as shown in Figure 19, the storage sub-circuit 1123 includes a storage capacitor Cst, and the first end of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3, that is, the first end (first plate) of the storage capacitor Cst is electrically connected to the node Nd1, and the second end (second plate) of the storage capacitor Cst is electrically connected to the voltage terminal VDD.

[0144] For example, as shown in Figure 19, the compensation sub-circuit 1124 includes a compensation transistor T2, the gate of the compensation transistor T2 is configured to receive the compensation control signal Ga2, the second electrode of the compensation transistor T2 is electrically connected to the second electrode of the driving transistor T3, that is, the second electrode of the compensation transistor T2 is electrically connected to the node Nd3, and the first electrode of the compensation transistor T2 is electrically connected to the node Nd1.

[0145] For example, as shown in FIG19 , the first emission control sub-circuit 1125A includes a first emission control transistor T5, and the second emission control sub-circuit 1125B includes a second emission control transistor T6. For example, the gate of the first emission control transistor T5 is configured to receive an emission control signal EM, a first electrode of the first emission control transistor T5 is connected to the voltage terminal VDD, and a second electrode of the first emission control transistor T5 is electrically connected to a first terminal of the driver sub-circuit 1221, that is, the second electrode of the first emission control transistor T5 is electrically connected to a node Nd2. The gate of the second emission control transistor T6 is configured to receive an emission control signal EM, a first electrode of the second emission control transistor T6 is electrically connected to a second terminal of the driver sub-circuit 1221, that is, the first electrode of the second emission control transistor T6 is electrically connected to a node Nd3, and a second electrode of the second emission control transistor T6 is electrically connected to the first electrode E1 of the light-emitting element 1110.

[0146] It should be noted that the signal used to control the first light emission control transistor T5 and the signal used to control the second light emission control transistor T6 may also be different.

[0147] For example, as shown in Figure 19, the first reset sub-circuit 1126 includes a first reset transistor T1, and the second reset sub-circuit 1127 includes a second reset transistor T7. The first electrode of the first reset transistor T1 is electrically connected to the first initialization voltage terminal Vinit1, the second electrode of the first reset transistor T1 is electrically connected to the node Nd1, and the gate of the first reset transistor T1 is configured to receive the first reset control signal Re, the first electrode of the second reset transistor T7 is electrically connected to the second initialization voltage terminal Vinit2, the second electrode of the second reset transistor T7 is electrically connected to the first electrode E1 of the light-emitting element 1110, and the gate of the second reset transistor T7 is configured to receive the second reset control signal Rst.

[0148] For example, the second initialization voltage at the second initialization voltage terminal Vinit2 is greater than the first initialization voltage at the first initialization voltage terminal Vinit1. By increasing the second initialization voltage at the second initialization voltage terminal Vinit2, carriers within the light-emitting element 1110 are reset, carrier defects are reduced, device stability is increased, and the screen flicker problem is further improved. However, the embodiments of the present disclosure are not limited thereto. The second initialization voltage at the second initialization voltage terminal Vinit2 may also be equal to the first initialization voltage at the first initialization voltage terminal Vinit1.

[0149] For example, the first reset transistor T1, the compensation transistor T2, the drive transistor T3, the data write transistor T4, the first light emission control transistor T5, the second light emission control transistor T6, and the second reset transistor T7 are all polycrystalline silicon thin film transistors, for example, low-temperature polycrystalline silicon (LTPS) thin film transistors. The embodiments of the present disclosure are not limited to this. At least some of the first reset transistor T1, the compensation transistor T2, the drive transistor T3, the data write transistor T4, the first light emission control transistor T5, the second light emission control transistor T6, and the second reset transistor T7 may also be oxide transistors.

[0150] For example, the first reset transistor T1, the compensation transistor T2, the drive transistor T3, the data writing transistor T4, the first emission control transistor T5, the second emission control transistor T6, and the second reset transistor T7 are all P-type transistors. However, the embodiments of the present disclosure are not limited thereto, and at least some of the first reset transistor T1, the compensation transistor T2, the drive transistor T3, the data writing transistor T4, the first emission control transistor T5, the second emission control transistor T6, and the second reset transistor T7 may also be N-type transistors.

[0151] For example, one of the voltages output by the voltage terminal VDD and the voltage terminal VSS is a high voltage, and the other is a low voltage. For example, in the embodiment shown in FIG. 19, the voltage output by the voltage terminal VDD is a constant positive voltage; and the voltage output by the voltage terminal VSS is a constant negative voltage. For example, in some examples, the voltage terminal VSS may be grounded.

[0152] For example, in specific implementation, in the embodiment of the present disclosure, the second initialization voltage Vi2 output by the second initialization voltage terminal Vinit2 and the voltage Vss output by the voltage terminal VSS may satisfy the following formula: Vi2 - Vss < VEL, so as to avoid the light-emitting element 1110 from emitting light during the non-light-emitting stage. VEL represents the light-emitting threshold voltage of the light-emitting element 1110.

[0153] It should be noted that in addition to the pixel circuit of 7T1C (7 transistors and 1 capacitor), the pixel circuit may also be a circuit with other suitable structures, such as 7T2C, 8T2C, 9T2C, 6T1C, 6T2C and other circuit structures, which will not be elaborated here.

[0154] FIG. 20 is a schematic diagram of a display panel provided by an embodiment of the present disclosure. As shown in FIG. 20, the display panel includes an initialization line IN1 and an initialization line IN2. The initialization line IN1 includes an initialization connection line IN11 and an initialization signal line IN12. The initialization line INr includes an initialization connection line IN21 and an initialization signal line IN22. The initialization line IN1 is connected to the first initialization voltage terminal Vinit1, and the initialization line IN2 is connected to the second initialization voltage terminal Vinit2. The initialization line IN1 and the initialization line IN2 are insulated from each other.

[0155] As shown in FIG. 20, the display panel further includes a plurality of initialization signal lines IN22. The initialization signal lines IN22 are connected to the constant voltage line 60 through vias V6. Thus, the voltage on the constant voltage line 60 is the initialization voltage. The constant voltage line 60 is connected to the second initialization voltage terminal Vinit2. For the sake of clear illustration, FIG. 20 only shows the via V6 in one row of sub-pixels. In each row of sub-pixels, the via V6 can be provided, but it is not limited thereto.

[0156] As shown in FIG. 20, the first branch 601 and the second branch 602 constitute the initialization connection line IN21. In this case, the conductive bus 612 can be referred to as the initialization bus.

[0157] For example, referring to Figures 19 and 20, the pixel circuit 1120 includes a driving transistor T3, a first reset transistor T1 and a second reset transistor T7, the first electrode of the first reset transistor T1 is connected to the initialization line IN1, the second electrode of the first reset transistor T1 is connected to the gate of the driving transistor T3, the first reset transistor T1 is configured to reset the gate of the driving transistor T3, the first electrode of the second reset transistor T7 is connected to the second initialization line IN2, the second electrode of the second reset transistor T7 is connected to the first electrode E1 of the light-emitting element 1110, and the second reset transistor T7 is configured to reset the first electrode E1 of the light-emitting element 1110.

[0158] For example, referring to Figures 19 and 20, the pixel circuit 1120 includes a reset transistor, a first electrode of the reset transistor is connected to the initialization line, a second electrode of the reset transistor is connected to the first electrode of the light-emitting element 1110, the reset transistor is configured to reset the first electrode E1 of the light-emitting element 1110, and the constant voltage line 60 is the initialization line IN2.

[0159] Figure 21 is a schematic diagram of a pixel circuit and a light-emitting element of a sub-pixel in a display panel provided by some embodiments of the present disclosure. Figure 22 is a schematic diagram of a display panel provided by an embodiment of the present disclosure.

[0160] 21 , the compensation sub-circuit 1124 includes a first compensation sub-circuit 1124A and a second compensation sub-circuit 1124B. The first compensation sub-circuit 1124A and the second compensation sub-circuit 1124B are connected via an intermediate node Nd4.

[0161] 21 , the first compensation sub-circuit 1124A includes a first compensation sub-transistor T21, and the second compensation sub-circuit 1124B includes a second compensation sub-transistor T22. The first compensation sub-transistor T21 and the second compensation sub-circuit 1124B are connected via an intermediate node Nd4 located therebetween.

[0162] For example, as shown in FIG. 21 , pixel circuit 1120 further includes a leakage prevention electronic circuit 1128 . Leakage prevention electronic circuit 1128 is electrically connected to node Nd4 and a reference voltage terminal Vref and is configured to transmit a reference voltage to node Nd4 in response to emission control signal EM. Reference voltage terminal Vref is configured to provide a reference voltage VRef to the pixel circuit. For example, the reference voltage is a constant voltage. Leakage prevention electronic circuit 1128 can stabilize the voltage at node Nd4, thereby stabilizing the voltage at node Nd1, thereby preventing leakage and facilitating a stable drive current.

[0163] For example, as shown in Figure 21, the anti-leakage electronic circuit 1128 includes an anti-leakage transistor T8, the gate of the anti-leakage transistor T8 is configured to receive the light-emitting control signal EM, the first electrode of the anti-leakage transistor T8 is connected to the reference voltage line REF, and the second electrode of the anti-leakage transistor T8 is connected to the intermediate node Nd4.

[0164] 22 , the constant voltage line 60 is a reference voltage line REF. The reference voltage line REF is connected to the reference voltage terminal Vref.

[0165] For example, as shown in Figure 21, the gate of the compensation transistor T2 is configured to receive the compensation control signal Ga2, the first electrode of the compensation transistor T2 is connected to the gate of the driving transistor T3, and the second electrode of the compensation transistor T2 is electrically connected to the second electrode of the driving transistor T3; the compensation transistor T2 includes a first compensation sub-transistor T21 and a second compensation sub-transistor T22 connected in series, and the first compensation sub-transistor T21 and the second compensation sub-transistor T22 are connected via an intermediate node Nd4 located therebetween; the first electrode of the anti-leakage transistor T8 is connected to the reference voltage line REF, the second electrode of the anti-leakage transistor T8 is connected to the intermediate node Nd4, and the constant voltage line 60 is the reference voltage line REF.

[0166] As shown in Figures 21 and 22, the display panel includes initialization lines IN1 and IN2. As shown in Figure 22, each of the initialization lines IN1, IN2, and constant voltage line 60 is insulated from each other. Initialization line IN1 is connected to a first initialization voltage terminal Vinit1, and initialization line IN2 is connected to a second initialization voltage terminal Vinit2.

[0167] As shown in Figures 21 and 22, initialization line IN1 includes initialization connection line IN11 and initialization signal line IN12, and initialization line IN2 includes initialization connection line IN21 and initialization signal line IN22. As shown in Figure 20, multiple initialization signal lines IN12 are arranged along the second direction Y and are respectively connected to initialization connection line IN11. As shown in Figure 20, multiple initialization signal lines IN22 are arranged along the second direction Y and are respectively connected to initialization connection line IN21.

[0168] 20 , multiple initialization signal lines IN12 are arranged along the second direction Y and are respectively connected to the initialization connection lines IN11 . As shown in FIG20 , multiple initialization signal lines IN22 are arranged along the second direction Y and are respectively connected to the initialization connection lines IN21 .

[0169] Figure 23 is a schematic diagram of a display panel provided by an embodiment of the present disclosure. Figure 23 also shows a first power line 71 and a second power line 72. Figure 23 does not show the entire structure of the first power line 71, nor does it show the entire structure of the second power line 72.

[0170] For example, the signal line may be connected to a flexible circuit board, and the integrated circuit is connected to the flexible circuit board, but is not limited thereto.

[0171] In an embodiment of the present disclosure, the voltage terminal VDD provides a voltage Vdd (power supply voltage), the voltage terminal VSS provides a voltage Vss (power supply voltage), the first initialization voltage terminal Vinit1 provides a first initialization voltage Vi1, and the second initialization voltage terminal Vinit2 provides a second initialization voltage Vi2.

[0172] Figure 24 is a layout diagram of a display panel provided in accordance with an embodiment of the present disclosure. Figure 25 is a plan view of an active layer LY0 in a display panel provided in accordance with an embodiment of the present disclosure. Figure 26 is a plan view of a conductive layer LYa in a display panel provided in accordance with an embodiment of the present disclosure. Figure 27 is a plan view of a conductive layer LYb in a display panel provided in accordance with an embodiment of the present disclosure. Figure 28 is a plan view of a via VH1 penetrating an insulating layer in a display panel provided in accordance with an embodiment of the present disclosure. Figure 29 is a plan view of a conductive layer LY1 in a display panel provided in accordance with an embodiment of the present disclosure. Figure 30 is a plan view of a via VH2 penetrating an insulating layer in a display panel provided in accordance with an embodiment of the present disclosure. Figure 31 is a plan view of a conductive layer LYb in a display panel provided in accordance with an embodiment of the present disclosure.

[0173] As shown in FIG. 24 and FIG. 25 , the active layer LY0 may be made of polysilicon and include a semiconductor serving as a channel of a transistor and conductor portions located on both sides of the semiconductor, wherein the conductor portions are doped polysilicon.

[0174] As shown in Figures 24 and 26, the conductive layer LYa includes a reset control signal line RST1, a gate line GT, a first electrode Ca of a storage capacitor, a light-emission control signal line EML, and a reset control signal line RST2. The reset control signal line RST1 is configured to provide a first reset control signal Re, the gate line GT is configured to provide a scan signal Ga1 and a compensation control signal Ga2, the light-emission control signal line EML is configured to provide a light-emission control signal EM, and the reset control signal line RST2 is configured to provide a second reset control signal Rst.

[0175] As shown in Figures 24 and 27, the conductive layer LYb includes an initialization signal line INT1, a block BK, a second plate Cb of the storage capacitor, and an initialization signal line INT2. The initialization signal line INT1 is connected to the first initialization voltage terminal Vinit1 to provide a first initialization voltage Vi1. The initialization signal line INT2 is connected to the second initialization voltage terminal Vinit2 to provide a second initialization voltage Vi2. Figure 27 shows that the second plate Cb of the storage capacitor has an opening OPN.

[0176] As shown in Figures 24 and 28, via VH1 is a via that penetrates at least one of the first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer. The first gate insulating layer is located between the active layer LY0 and the conductive layer LYa, the second gate insulating layer is located between the conductive layer LYa and the conductive layer LYb, and the interlayer dielectric layer is located between the conductive layer LYb and the conductive layer LY1. Figure 28 shows via Va, via Vb, via Vc, via Vd, via Ve, via Vf, via Vg, via Vh, via Vi, via Vj, via Vk, via Vm, via Vn, and via Vr.

[0177] As shown in Figures 24 and 29, the conductive layer LY1 includes a reference voltage line REF, a first power supply voltage line PL1, a connection electrode CE1, a connection electrode CE2, a connection electrode CE3, a connection electrode CE4, a connection electrode CE5, and a connection electrode CE6. The reference voltage line REF is connected to a reference voltage terminal Vref to provide a reference voltage VRef, and the first power supply voltage line PL1 is connected to a voltage terminal VDD to provide a voltage Vdd (a first power supply voltage).

[0178] As shown in Figures 24 and 30, the via hole VH2 is a via hole that penetrates the insulating layer between the conductive layer LY2 and the conductive layer LY1. Figure 30 shows the via hole Vs and the via hole Vt.

[0179] As shown in FIG. 24 and FIG. 31 , the conductive layer LY2 includes a connection electrode CE7 and a data signal line DT.

[0180] Referring to Figures 21 and 24 to 31, the reference voltage line REF is connected to the first electrode of the anti-leakage transistor T8 through the via Vm, the conductor portion CP is the intermediate node Nd4, the conductor portion CP is connected to one end of the connecting electrode CE6 through the via Vj, and the other end of the connecting electrode CE6 is connected to the second electrode of the anti-leakage transistor T8 through the via Vk.

[0181] Referring to Figures 21 and 24 to 31, one end of the connecting electrode CE1 passes through the opening OPN of the second plate Cb of the storage capacitor Cst and is connected to the first plate Ca of the storage capacitor Cst (the gate of the driving transistor T3) through the via Va, and the other end of the connecting electrode CE1 is connected to the second electrode of the first reset transistor T1 through the via Vb.

[0182] 21 and 24 to 31 , one end of the connection electrode CE2 is connected to the first electrode of the first reset transistor T1 through a via Vd, and the other end of the connection electrode CE2 is connected to the initialization signal line INT1 through a via Vc.

[0183] 21 and 24 to 31 , one end of the connection electrode CE3 is connected to the first electrode of the second reset transistor T7 through a via Vf, and the other end of the connection electrode CE3 is connected to the initialization signal line INT2 through a via Vr.

[0184] 21 and 24 to 31 , one end of the connection electrode CE4 is connected to the first electrode of the data writing transistor T4 through a via hole Vh, and the other end of the connection electrode CE4 is connected to the data signal line DT through a via hole Vt.

[0185] 21, 24 to 31, one end of the connection electrode CE5 is connected to the second electrode of the second light-emitting control transistor T6 through a via Vn, and the other end of the connection electrode CE5 is connected to the connection electrode CE7 through a via Vs. The first electrode E1 of the light-emitting element (not shown in FIG. 24) is connected to the connection electrode CE7.

[0186] 21 and 24 to 31 , the first power signal line PL1 is connected to the second plate Cb of the storage capacitor Cst through a via Ve, and is connected to the first electrode of the first light emission control transistor T5 through a via Vg.

[0187] 24 to 31 , the first power signal line PL1 is connected to the block BK through a via Vi.

[0188] For example, the first power signal line PL1 is the first power signal line 718. For example, the initialization signal line INT1 is the initialization signal line IN1. For example, the initialization signal line INT2 is the initialization signal line IN2.

[0189] FIG. 24 shows a first compensation sub-transistor T21 and a second compensation sub-transistor T22 .

[0190] Of course, as shown in FIG19 , the display panel provided by the embodiment of the present disclosure may also not include the anti-leakage transistor T8 and the reference voltage line REF connected thereto. In this case, the active portion (the channel region and the first and second electrodes located on both sides of the channel region) of the anti-leakage transistor T8, the reference voltage line REF, and the connecting electrode CE6 in the layout diagram of FIG24 may be removed to obtain the pixel circuit shown in FIG19 .

[0191] In the embodiments of the present disclosure, the conductive layers LYa, LYb, LY1, and LY2 can be made of conductive materials, such as metal materials. For example, the material of at least one of the conductive layers LYa and LYb can include molybdenum, nickel, a molybdenum alloy, a nickel alloy, etc., although the embodiments of the present disclosure are not limited thereto. The material of at least one of the conductive layers LY1 and LY2 can include titanium, a titanium alloy, aluminum, an aluminum alloy, copper, a copper alloy, or any other suitable composite material, although the embodiments of the present disclosure are not limited thereto.

[0192] For example, the first power line 71 and the second power line 72 are made of metal material.

[0193] For example, the base substrate may be a glass substrate or a polyimide substrate, but is not limited thereto and may be selected as needed. For example, the insulating layer 501, the insulating layer 502, the passivation layer PVX, and the planarization layer PLN are all made of insulating materials.

[0194] For example, the materials of the first electrode E1 and the second electrode E2 of the light-emitting element can be selected as needed. In some embodiments, the first electrode E1 can be made of at least one of a transparent conductive metal oxide and silver, but is not limited thereto. For example, the transparent conductive metal oxide includes indium tin oxide (ITO), but is not limited thereto. For example, the first electrode E1 can be made of a structure in which three sub-layers of ITO-Ag-ITO are stacked. In some embodiments, the second electrode E2 can be a metal with a low work function, and can be made of at least one of magnesium and silver, but is not limited thereto.

[0195] The embodiments of the present disclosure provide a design method for static level traces in a display panel, provide a routing method for static level traces, and provide suitable routing space for the static level traces. The static level traces are vertical traces, that is, traces extending along the second direction Y.

[0196] In the embodiments of the present disclosure, the components located in the same layer may be formed from the same film layer through the same patterning process. For example, the components located in the same layer may be located on a surface of the same component away from the base substrate.

[0197] It should be noted that, for the sake of clarity, the thickness of layers or regions in the drawings used to describe the embodiments of the present disclosure are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or intervening elements may be present.

[0198] In the embodiments of the present disclosure, the patterning or patterning process may include only photolithography, or may include photolithography and etching steps, or may include other processes such as printing and inkjet printing to form a predetermined pattern. A photolithography process includes film formation, exposure, and development, and utilizes photoresist, a mask, and an exposure machine to form a pattern. The appropriate patterning process may be selected based on the structure to be formed in the embodiments of the present disclosure.

[0199] In the absence of conflict, features in the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0200] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, comprising: A base substrate, comprising a display area and a peripheral area, wherein the peripheral area is located on at least one side of the display area; A plurality of sub-pixels are located in the display area; a plurality of constant-voltage lines arranged along a first direction, the constant-voltage lines extending along a second direction, the constant-voltage lines at least partially located in the display area, the first direction intersecting the second direction; as well as A conductor, located in the peripheral area and connected to the plurality of constant voltage lines, The constant voltage line is configured to provide a constant voltage to the sub-pixel.

2. The display panel according to claim 1, further comprising a first power line, wherein The first power line is configured to provide a constant first power voltage to the sub-pixel. The first power line includes a first power bus located in the peripheral area. At least a portion of the first power bus extends along the second direction.

3. The display panel according to claim 2, further comprising a second power line, wherein The second power line is configured to provide a constant second power voltage to the sub-pixel. The second power line includes a second power bus located in the peripheral area. At least a portion of the second power bus extends along the second direction.

4. The display panel according to claim 3, wherein: The conductive line includes a conductive bus, at least a portion of which extends along the second direction, and the at least portion of which extends along the second direction is located between the at least portion of the first power bus and the at least portion of the second power bus extending along the second direction.

5. The display panel according to claim 3 or 4, further comprising an integrated circuit, wherein: The conductive bus, the first power bus, and the second power bus are all connected to the integrated circuit.

6. The display panel according to any one of claims 2 to 5, wherein: The conductive wire includes a first branch and a second branch respectively connected to the conductive bus, the first power line includes a first power connection line, the first power connection line extends along the first direction, and the orthographic projection of the first power connection line on the base substrate overlaps with the orthographic projection of the first branch on the base substrate.

7. The display panel according to claim 6, further comprising a planarization layer, wherein The planarization layer is located on a side of the first branch close to the base substrate. The first branch has a plurality of openings configured to expose a portion of the planarization layer.

8. The display panel according to claim 7, wherein: The material of the planarization layer includes an organic material.

9. The display panel according to any one of claims 6 to 8, wherein: The first branch extends along the first direction, the included angle between the second branch and the first branch is an obtuse angle, and the included angle between the second branch and the conductive bus is also an obtuse angle.

10. The display panel according to claim 9, wherein: The shape of the second branch includes at least one of an arc, a curve, and a broken line.

11. The display panel according to any one of claims 6 to 10, further comprising a plurality of conductive connection lines, wherein: The second branch is connected to the plurality of conductive connection lines, and a portion of the plurality of constant voltage lines is respectively connected to the plurality of conductive connection lines.

12. The display panel according to claim 11, further comprising a plurality of signal connection lines, wherein: An orthographic projection of at least a portion of the plurality of signal connection lines on the base substrate overlaps with an orthographic projection of the second branch on the base substrate.

13. The display panel according to claim 12, wherein: At least one signal connection line among the plurality of signal connection lines is disposed between two adjacent conductive connection lines.

14. The display panel according to claim 13, wherein: The signal connection line includes at least one of a clock signal line, a start input signal line of a shift register, a low level signal line or a high level signal line.

15. The display panel according to any one of claims 6 to 10, wherein: The plurality of constant voltage lines, at least a portion of the conductive bus, and the second branch are located on a same layer, and the first branch is located on another layer.

16. The display panel according to any one of claims 1 to 15, wherein: The sub-pixel includes a pixel circuit and a light-emitting element, the pixel circuit is configured to drive the light-emitting element, the pixel circuit includes a reset transistor, the first electrode of the reset transistor is connected to the initialization line, the second electrode of the reset transistor is connected to the first electrode of the light-emitting element, the reset transistor is configured to reset the first electrode of the light-emitting element, and the constant voltage line is the initialization line.

17. The display panel according to any one of claims 1 to 15, wherein: The sub-pixel includes a pixel circuit and a light-emitting element, the pixel circuit is configured to drive the light-emitting element, and the pixel circuit includes a driving transistor, a first reset transistor, and a second reset transistor. A first electrode of the first reset transistor is connected to a first initialization line, a second electrode of the first reset transistor is connected to a gate of the driving transistor, and the first reset transistor is configured to reset the gate of the driving transistor. A first electrode of the second reset transistor is connected to a second initialization line, a second electrode of the second reset transistor is connected to the first electrode of the light emitting element, and the second reset transistor is configured to reset the first electrode of the light emitting element.

18. The display panel according to claim 17, further comprising an initialization signal line, wherein The initialization signal line extends along the first direction, the constant voltage line is connected to the initialization signal line, and the second initialization line includes the initialization signal line and the constant voltage line connected to each other.

19. The display panel according to claim 17, wherein: The pixel circuit includes a compensation transistor and an anti-leakage transistor, The gate of the compensation transistor is configured to receive a compensation control signal, a first electrode of the compensation transistor is connected to the gate of the driving transistor, and a second electrode of the compensation transistor is electrically connected to the second electrode of the driving transistor; The compensation transistor includes a first compensation sub-transistor and a second compensation sub-transistor connected in series, wherein the first compensation sub-transistor and the second compensation sub-transistor are connected via an intermediate node located therebetween; The first electrode of the anti-leakage transistor is connected to the reference voltage line, and the second electrode of the anti-leakage transistor is connected to the intermediate node. The constant voltage line is the reference voltage line.

20. A display device comprising the display panel according to any one of claims 1 to 19.

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