Synchronization methods involve code, communication devices, chips, chip systems, storage media readable by computers and network systems.

Abstract

The invention relates to a method for synchronizing code words, communication devices, chips, chip systems, computer-readable storage media, and network systems. In this method, the candidate bit is determined in multiple bits of the data stream received by the receiver, and the synchronization position is determined based on the candidate bit, where the synchronization position indicates the starting position of the code word in the data stream. The method is self-synchronizing, and the technical efficiency of highly accurate code word synchronization for the data stream at the receiver side can be achieved without inserting additional data into the data stream at the transmitter side, and the synchronization performance is highly reliable.

Description

Codeword synchronization method, receiver, network device and network system

[0001] The present application claims priority to Chinese Patent Application No. 202010280832.9, filed on April 10, 2020, entitled “A Codeword Synchronization Method, Receiver and Network Device” and Chinese Patent Application No. 202010424884.9, filed on May 19, 2020, entitled “Codeword Synchronization Method, Receiver, Network Device and Network System”, the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0002] The present application relates to the field of communication, and in particular to a codeword synchronization method, receiver, network device and network system. BACKGROUND

[0003] With the improvement of production process level, the loss and noise of the channel have become the key factors to limit the data transmission rate and distance. The emergence of forward error correction (FEC) provides error correction protection for the data in transmission, thereby improving the data transmission rate and transmission distance of the channel. FEC can be divided into block code and convolutional code according to the processing mode of the information sequence. For block code, it can be further divided into linear block code and non-linear block code. Linear block code is widely used in the physical layer and the media access control sublayer of the data link layer in the open system interconnection model (OSI) of Ethernet due to its simple encoding and decoding implementation.

[0004] The error detection and correction function implementation of linear block code must be based on a complete codeword, so it is necessary to determine the codeword boundary in the data stream, that is, to find the beginning and end of a complete codeword, and this process is called codeword synchronization or frame synchronization.

[0005] Currently, there are synchronization schemes for linear block codes in the industry. Taking the alignment marker (AM) synchronization scheme used in 200 / 400 GE in the 802.3 standard as an example, a fixed AM sequence needs to be inserted into each code word with a certain length interval in the scheme, and the receiving end can identify the AM sequence to perform code word synchronization. However, the existence of the AM sequence is equivalent to inserting additional data into the data stream at the sending end, which increases the redundancy information.

[0006] SUMMARY

[0007] The present application provides a self-synchronized code word synchronization method, a receiver and a network device, which are used to solve the technical problem of increasing additional data in the AM synchronization scheme.

[0008] In a first aspect, the present application provides a code word synchronization method. The method comprises: step one, receiving a data sequence, the data sequence comprising a plurality of bits; step two, determining a candidate bit in the data sequence, the candidate bit being included in the plurality of bits; and step three, determining a synchronization position according to the candidate bit, the synchronization position being used to indicate a starting position of a code word in the data sequence.

[0009] The method is performed by a receiving device in a network. Through the method, additional data does not need to be inserted into the data stream at the sending end, and the technical effect of high-precision code word synchronization of the data stream at the receiving end can be achieved, and the synchronization performance reaches a high reliability.

[0010] In a possible implementation, the step three comprises: verifying the candidate bit, and when the verification is successful, determining that the position of the candidate bit is the synchronization position.

[0011] In a possible implementation, at least one second test data block is divided according to the candidate bit in the data sequence, the position of the candidate bit being a starting position of the at least one second test data block; and a characteristic value of the at least one second test data block is verified, and when the verification is successful, the position of the candidate bit is determined as the synchronization position.

[0012] In a possible implementation, verifying the characteristic value of the at least one second test data block comprises: sequentially accumulating the characteristic value of each second test data block in the at least one second test data block to obtain an accumulated value, and when the accumulated value meets a synchronization condition, the verification is successful.

[0013] In a possible implementation, the accumulated value of the characteristic value is the number of the second test data blocks determined as correct codewords in the at least one second test data block, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold; the characteristic value is the number of all-zero sequences in a check sequence, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of zero elements in a check sequence, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of correctable test data blocks, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of test data blocks with the same recheck bits and original check bits, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold; wherein, the length of the test data block is n bits, the first k bits of the test data block are information bits, the last n-k bits of the test data block are the original check bits, the recheck bits are obtained according to the information bits, the length of the recheck bits is n-k bits, and n and k are integers.

[0014] In a possible implementation, the verification on the characteristic value of the at least one second test data block includes: adding the characteristic values of all the second test data blocks in the at least one second test data block to obtain a total value, and the verification is successful when the total value satisfies a synchronization condition.

[0015] In a possible implementation, the total value of the characteristic values is the number of second test data blocks determined as correct codewords in the at least one second test data block, the total value of the characteristic values is the number of second test data blocks determined as incorrect codewords in the at least one second test data block, and the synchronization condition is that the total value is less than or equal to a synchronization threshold; or, the characteristic value is the number of all-zero sequences in the check sequence, the synchronization condition is that the total value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of non-all-zero sequences in the check sequence, the synchronization condition is that the total value is less than or equal to a synchronization threshold; or, the characteristic value is the number of zero elements in the check sequence, the synchronization condition is that the total value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of non-zero elements in the check sequence, the synchronization condition is that the total value is less than or equal to a synchronization threshold; or, the characteristic value is the number of correctable test data blocks, the synchronization condition is that the total value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of uncorrectable test data blocks, the synchronization condition is that the total value is less than or equal to a synchronization threshold; or, the characteristic value is the number of test data blocks with the same recheck parity bits as original check parity bits, the synchronization condition is that the total value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of test data blocks with different recheck parity bits from original check parity bits, the synchronization condition is that the total value is less than or equal to a synchronization threshold; wherein, the length of the test data block is n bits, the first k bits of the test data block are information bits, the last n-k bits of the test data block are the original check parity bits, the recheck parity bits are obtained according to the information bits, the length of the recheck parity bits is n-k bits, and n and k are integers.

[0016] In a possible implementation, the position of the alternative bit is taken as the synchronization position.

[0017] In a possible implementation, a plurality of observation bits are selected from the data sequence; the alternative bit is selected from the plurality of observation bits.

[0018] In a possible implementation, the selecting the alternative bit from the plurality of observation bits comprises: determining a plurality of groups of first test data blocks from the data sequence according to the plurality of observation bits, wherein each group of first test data blocks in the plurality of groups of first test data blocks includes at least one first test data block, and the position of each observation bit in the plurality of observation bits is the starting position of each group of first test data blocks in the plurality of groups of first test data blocks; and selecting an observation bit from the plurality of observation bits as the alternative bit according to the characteristic values of the plurality of groups of first test data blocks.

[0019] In a possible implementation, the selecting one observation bit as the candidate bit from the plurality of observation bits according to the characteristic values of the plurality of groups of first test data blocks comprises: judging whether the characteristic value of each group of first test data blocks in the plurality of groups of first test data blocks satisfies a candidate condition in sequence until determining that the characteristic value of one group of first test data blocks satisfies the candidate condition; and taking the observation bit corresponding to the one group of first test data blocks as the candidate bit.

[0020] In a possible implementation, the characteristic value of the set of first test data blocks is a total value of the number of all-zero sequences in the check sequences of all the first test data blocks in the set of first test data blocks, and the alternative condition is that the total value is greater than or equal to a synchronization threshold; or, the characteristic value of the set of first test data blocks is a total value of the number of non-all-zero sequences in the check sequences of all the first test data blocks in the set of first test data blocks, and the alternative condition is that the total value is less than or equal to a synchronization threshold; or, the characteristic value of the set of first test data blocks is a total value of the number of zero elements in the check sequences of all the first test data blocks in the set of first test data blocks, and the alternative condition is that the total value is greater than or equal to a synchronization threshold; or, the characteristic value of the set of first test data blocks is a total value of the number of non-zero elements in the check sequences of all the first test data blocks in the set of first test data blocks, and the alternative condition is that the total value is less than or equal to a synchronization threshold; or, the characteristic value of the set of first test data blocks is a total value of the number of correctable test data blocks in all the first test data blocks in the set of first test data blocks, and the alternative condition is that the total value is greater than or equal to a synchronization threshold; or, the characteristic value of the set of first test data blocks is a total value of the number of uncorrectable test data blocks in all the first test data blocks in the set of first test data blocks, and the alternative condition is that the total value is less than or equal to a synchronization threshold; or, the characteristic value of the set of first test data blocks is a total value of the number of test data blocks with the same recheck check bits and original check bits in the first X first test data blocks in the set of first test data blocks, and the alternative condition is that the total value is greater than or equal to a synchronization threshold; or, the characteristic value of the set of first test data blocks is a total value of the number of test data blocks with different recheck check bits and original check bits in the first X first test data blocks in the set of first test data blocks, and the alternative condition is that the total value is less than or equal to a synchronization threshold; or, the characteristic value of the set of first test data blocks is a cumulative value of the number of all-zero sequences in the check sequences of the first X first test data blocks in the set of first test data blocks, and the alternative condition is that the cumulative value is greater than or equal to a synchronization threshold; or, the characteristic value of the set of first test data blocks is a cumulative value of the number of zero elements in the check sequences of the first X first test data blocks in the set of first test data blocks, and the alternative condition is that the cumulative value is greater than or equal to a synchronization threshold; or, the characteristic value of the set of first test data blocks is a cumulative value of the number of correctable test data blocks in the first X first test data blocks in the set of first test data blocks, and the alternative condition is that the cumulative value is greater than or equal to a synchronization threshold; or, the characteristic value of the set of first test data blocks is a cumulative value of the number of test data blocks with the same recheck check bits and original check bits in the first X first test data blocks in the set of first test data blocks, and the alternative condition is that the cumulative value is greater than or equal to a synchronization threshold.The length of the test data block is n bits, the first k bits of the test data block are information bits, the last n-k bits of the test data block are the original check bits, the re-check bits are obtained according to the information bits, the length of the re-check bits is n-k bits, and n, k and X are integers.

[0021] In a possible implementation, the selecting one observation bit as the candidate bit from the plurality of observation bits according to the characteristic values of the plurality of groups of first test data blocks comprises: comparing the characteristic values of each group of first test data blocks in the plurality of groups of first test data blocks, and taking the observation bit corresponding to the group of first test data blocks with the extreme value as the candidate bit.

[0022] In a possible implementation, the characteristic value is the number of all-zero sequences in the check sequence, and the extreme value is the maximum value; or the characteristic value is the number of non-all-zero sequences in the check sequence, and the extreme value is the minimum value; or the characteristic value is the number of zero elements in the check sequence, and the extreme value is the maximum value; or the characteristic value is the number of non-zero elements in the check sequence, and the extreme value is the minimum value; or the characteristic value is the number of correctable test data blocks, and the extreme value is the maximum value; or the characteristic value is the number of uncorrectable test data blocks, and the extreme value is the minimum value; or the characteristic value is the number of test data blocks with the same re-check bits and original check bits, and the extreme value is the maximum value; or the characteristic value is the number of test data blocks with different re-check bits and original check bits, and the extreme value is the minimum value; wherein the length of the test data block is n bits, the first k bits of the test data block are information bits, the last n-k bits of the test data block are the original check bits, the re-check bits are obtained according to the information bits, the length of the re-check bits is n-k bits, and n and k are integers.

[0023] In a possible implementation, the selecting a plurality of observation bits from the data sequence comprises: selecting one bit from every T bits in the data sequence as the observation bit, where T is an integer greater than zero; or selecting one bit from every L*n+T bits in the data sequence as the observation bit, where L is the number of interval test data blocks, the length of the test data block is n bits, and L and T are integers greater than zero.

[0024] In a possible implementation, the data sequence is a modulated signal, and the data sequence includes a plurality of modulation symbols, wherein the selecting a plurality of observation bits from the first data includes: selecting a starting bit of a modulation symbol as the observation bit from the data sequence every T modulation symbols, where T is an integer greater than zero; or selecting a starting bit of a modulation symbol as the observation bit from the data sequence every L*m+T modulation symbols, where L is a number of interval test data blocks, a length of the test data block is the m modulation symbols, and L and T are integers greater than zero.

[0025] In a possible implementation, the number of observation bits is P, where P is a positive integer, and a length of the code word is the P bits.

[0026] In a possible implementation, in the step two, the determining the candidate bits in the data sequence includes determining candidate bits in a first subsequence, and in the step three, the dividing at least one second test data block from the data sequence according to the candidate bits includes dividing at least one second test data block from a second subsequence according to the candidate bits, where the first subsequence and the second subsequence are included in the data sequence, and the second subsequence is the same as, partially the same as, or different from the first subsequence.

[0027] In a possible implementation, after the step three, the method further includes: a step four, in response to the data sequence being in a lock loss state, determining an updated synchronization position of the data sequence.

[0028] In a possible implementation, the determining the updated synchronization position of the data sequence includes: re-executing the step two and the step three, and taking a synchronization position determined by the re-executed step three as the updated synchronization position.

[0029] In a possible implementation, after the step three and before the step four, the method further includes: dividing a plurality of synchronization code words from the data sequence according to the synchronization position, where the synchronization position is a starting position of the plurality of synchronization code words; and verifying a characteristic value of the plurality of synchronization code words, and determining that the data sequence is in the lock loss state when the verification fails.

[0030] In a possible implementation, the verifying the characteristic value of the plurality of synchronization code words includes: sequentially accumulating the characteristic value of each synchronization code word in the plurality of synchronization code words to obtain an accumulated value, and the verification fails when the accumulated value meets a lock loss condition.

[0031] In a possible implementation, the characteristic value is the number of non-all-zero sequences in the check sequence, and the lock loss condition is that the cumulative value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of non-zero elements in the check sequence, and the lock loss condition is that the cumulative value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of non-correctable codewords, and the lock loss condition is that the cumulative value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of codewords in which the recheck parity bits are different from the original check parity bits, and the lock loss condition is that the cumulative value is greater than or equal to a synchronization threshold; wherein the length of the codeword is n bits, the first k bits of the codeword are information bits, the last n-k bits of the codeword are the original check parity bits, the recheck parity bits are obtained according to the information bits, the length of the recheck parity bits is n-k bits, and n and k are integers.

[0032] In a possible implementation, verifying the characteristic values of the plurality of synchronization codewords includes: adding the characteristic values of all synchronization codewords in the plurality of synchronization codewords to obtain a total value, and when the total value satisfies a lock loss condition, the verification fails.

[0033] In a possible implementation, the characteristic value is the number of all-zero sequences in the check sequence, and the lock loss condition is that the total value is less than or equal to a synchronization threshold; or, the characteristic value is the number of non-all-zero sequences in the check sequence, and the lock loss condition is that the total value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of zero elements in the check sequence, and the lock loss condition is that the total value is less than or equal to a synchronization threshold; or, the characteristic value is the number of non-zero elements in the check sequence, and the lock loss condition is that the total value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of correctable codewords, and the lock loss condition is that the total value is less than or equal to a synchronization threshold; or, the characteristic value is the number of non-correctable codewords, and the lock loss condition is that the total value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of codewords in which the recheck parity bits are the same as the original check parity bits, and the lock loss condition is that the total value is less than or equal to a synchronization threshold; or, the characteristic value is the number of codewords in which the recheck parity bits are different from the original check parity bits, and the lock loss condition is that the total value is greater than or equal to a synchronization threshold; wherein the length of the codeword is n bits, the first k bits of the codeword are information bits, the last n-k bits of the codeword are the original check parity bits, the recheck parity bits are obtained according to the information bits, the length of the recheck parity bits is n-k bits, and n and k are integers.

[0034] In a possible implementation, the data sequence is a linear block code.

[0035] In a second aspect, the present application provides a communication device, which executes the method in the first aspect or any possible implementation manner of the first aspect. Specifically, the network device comprises units for executing the method in the first aspect or any possible implementation manner of the first aspect. Details are described above.

[0036] In a third aspect, the present application provides a communication device, which comprises a processor, a communication interface and a memory. The communication interface can be a transceiver. The memory can be used to store program code, and the processor is configured to invoke the program code in the memory to execute the method in the first aspect or any possible implementation manner of the first aspect. Details are described above.

[0037] In a fourth aspect, the present application provides a network system, which comprises a sending device and a receiving device. The receiving device is the communication device provided in the second aspect or the third aspect. The receiving device is configured to receive the data sequence sent by the sending device.

[0038] In a fifth aspect, the present application provides a computer readable storage medium, which stores instructions. When the instructions are run on a computer, the computer is caused to execute the method in the above aspects.

[0039] In a sixth aspect, the present application provides a computer program product comprising computer program instructions, which, when run on a network device, causes the network device to execute the method provided in the first aspect or any possible implementation manner of the first aspect.

[0040] In a seventh aspect, the present application provides a chip, which comprises a memory and a processor. The memory is used to store a computer program. The processor is configured to invoke and run the computer program from the memory to execute the method in the first aspect or any possible implementation manner of the first aspect.

[0041] Optionally, the above chip only comprises a processor, which is configured to read and execute a computer program stored in a memory. When the computer program is executed, the processor executes the method in the first aspect or any possible implementation manner of the first aspect.

[0042] In an eighth aspect, the present application provides a network node, which comprises a main board and an interface board. The main board comprises a first processor and a first memory. The interface board comprises a second processor, a second memory and an interface card. The main board and the interface board are coupled.

[0043] The first memory can be configured to store program code, and the first processor is configured to invoke the program code in the first memory to determine candidate bits in the data sequence, the candidate bits being included in the plurality of bits, and determine a synchronization position according to the candidate bits, the synchronization position being used to indicate a starting position of a code word in the data sequence.

[0044] The second memory can be configured to store program code, and the second processor is configured to invoke the program code in the second memory to trigger the interface card to receive a data sequence, the data sequence including a plurality of bits.

[0045] In a possible implementation, an inter-process communication (IPC) channel is established between the main control board and the interface board, and the main control board and the interface board communicate through the IPC channel. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the present application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings below are only some of the drawings of the present application, and those skilled in the art can also obtain other technical solutions and drawings that can achieve the present application without creative labor on the basis of these drawings.

[0047] FIG. 1 is a synchronization position of a code word provided by an embodiment of the present application;

[0048] FIG. 2 is a synchronization flowchart provided by an embodiment of the present application;

[0049] FIG. 3 is a synchronization flowchart provided by an embodiment of the present application;

[0050] FIG. 4 is a selection method of observation bits provided by an embodiment of the present application;

[0051] FIG. 5 is a selection method of observation bits provided by an embodiment of the present application;

[0052] FIG. 6 is a selection method of observation bits provided by an embodiment of the present application;

[0053] FIG. 7 is a selection method of observation bits provided by an embodiment of the present application;

[0054] FIG. 8 is a first stage of synchronization lock judgment provided by an embodiment of the present application;

[0055] FIG. 9 is a second stage of synchronization lock judgment provided by an embodiment of the present application;

[0056] FIG. 10 is a synchronization lockout judgment provided by an embodiment of the present application;

[0057] FIG. 11 is a synchronization flowchart according to an embodiment of the present application;

[0058] FIG. 12 is a structure diagram of a communication device according to an embodiment of the present application;

[0059] FIG. 13 is a structure diagram of a communication device according to an embodiment of the present application;

[0060] FIG. 14 is a structure diagram of a communication device according to an embodiment of the present application. DETAILED DESCRIPTION

[0061] Embodiments of the present application are described below with reference to the accompanying drawings.

[0062] Due to channel loss and noise, errors occur when signals are transmitted in a channel, affecting the reliability of a communication system. When a signal is represented as a data sequence composed of multiple bits, a transmission error specifically means that the value of some bits in the data sequence changes, i.e., error bits occur. FEC is a technique for controlling transmission errors in a communication system, in which redundant information is sent together with an original data sequence for error recovery during transmission, reducing the bit error rate. FEC can be divided into block codes and convolutional codes according to the processing manner of information sequences. For block codes, linear block codes and nonlinear block codes can be further divided. Taking systematic codes in linear block codes as an example, the sending end groups the original data sequence, and each group has a length of k bits. Then, according to a specific coding rule, n-k bits of redundant information, also known as parity, are added in each group, and finally a code word with a length of n bits is obtained. Thus, in the code word with a length of n bits, the first k bits are original data, also known as information bits, and the last n-k bits are parity bits, and the entire code word is composed of information bits and parity bits. After a code word reaches a receiving end through a channel, if the number of error bits in the code word is within a correctable range, the receiving end can check and correct errors through a decoding process, restoring the received code word to the original data sent by the sending end, thereby resisting interference caused by a channel and improving the reliability of a communication system. The implementation of error detection and correction functions of linear block codes must be based on complete code words, and thus, before decoding a data sequence received by a receiving end, the boundaries of code words need to be determined in the data sequence, i.e., the starting position and ending position of a complete code word need to be found. This process is called code word synchronization or frame synchronization. If code word synchronization is incorrect, i.e., the real code word boundary cannot be determined, the subsequent decoding process cannot achieve the expected effect of error detection or correction, and even may increase the error code, causing the deterioration of the performance of a communication system.

[0063] The starting position of each code word can also be referred to as a synchronization position. Taking a systematic code as an example, FIG. 1 shows the synchronization position in a code word. As shown in FIG. 1, the length of the entire code word is n bits, where the first k bits are information bits, the last n-k bits are parity bits added by an encoding rule, and the synchronization position is the starting position of the code word, i.e., the position of the first bit in the code word. Here, n and k are integers. As can be seen, in the data sequence, the number of synchronization positions is multiple, and the multiple synchronization positions are associated with each other, where the interval between each synchronization position is fixed, and the interval is the length of the code word.

[0064] In the embodiments of the present application, although a systematic code is taken as an example, the present application is not limited to the systematic code, but is also applicable to a non-systematic code, and the present application can be applied to a communication system of all linear block codes. The linear block codes include, but are not limited to, a Reed-Solomon code (RS code), a Bose-Chaudhuri-Hocquenghem code (BCH code), a Low-Density Parity-Check code (LDPC code), a Hamming code, a Golay code, and a Reed-Muller code, etc.

[0065] The embodiments of the present application provide a code word synchronization method, and a device and a system based on the method. The methods, the device and the system are based on the same inventive concept. The method can include two stages. In the first stage, a plurality of groups of first test data blocks are divided according to a plurality of observation bits, and an observation bit most likely located at a synchronization position is selected from the plurality of observation bits according to the plurality of groups of first test data blocks. In the second stage, a group of second test data blocks is divided according to the observation bit most likely located at the synchronization position, and it is determined whether the observation bit most likely located at the synchronization position is the synchronization position according to the group of second test data blocks. The method can also only include the first stage. After the observation bit most likely located at the synchronization position is determined to be selected, the observation bit most likely located at the synchronization position is directly taken as the synchronization position. In the method, additional data does not need to be inserted in a data stream at a sending end, and a technical effect of high-precision code word synchronization of a data stream at a receiving end can be achieved, and the synchronization performance reaches a high reliability.

[0066] Figure 2 shows a flow chart of a method according to an embodiment of the application. The method is applied to a receiving device in a communication network. The receiving device can be various devices performing FEC, including but not limited to routers, switches and servers. The steps of the method include:

[0067] S210, receiving a data sequence.

[0068] Specifically, the receiving device receives a data sequence from a sending device, the data sequence including a plurality of bits, each bit being binary data. That is, the data sequence is a sequence of a plurality of bits, which can also be referred to as a bit sequence. In some embodiments, the data sequence is a linear block code. The data sequence is transmitted through a channel, and there can be errors, which need to be detected and corrected.

[0069] S220, in a first stage, determining a candidate bit in the data sequence, the candidate bit being included in the plurality of bits. The candidate bit is an observation bit in the plurality of observation bits that is most likely to be in a synchronization position, or in other words, the position of the candidate bit is a most likely synchronization position.

[0070] As shown in Figure 3, in the first stage, two steps S221 and S222 can be included:

[0071] S221, the receiving device selects a plurality of observation bits from the received data sequence. The positions of these observation bits include the synchronization position, that is, the position of a certain observation bit among these observation bits can be the synchronization position, or in other words, the positions of these observation bits can cover the synchronization position.

[0072] Optionally, in the first stage, when determining the candidate bit in the data sequence, only a part of the data sequence is used, for example, a first sub-sequence in the data sequence, that is, the candidate bit in the first sub-sequence is determined. The first sub-sequence includes a plurality of bits, and the first sub-sequence can be any part of the data sequence. The receiving device selects the plurality of observation bits from the first sub-sequence, and the positions of these observation bits can be the synchronization position. For example, the number of observation bits is P, P being an integer greater than 1.

[0073] Optionally, when selecting the plurality of observation bits from the received data sequence, the interval between every two adjacent observation bits in the plurality of observation bits is the same, and the position of each observation bit in the plurality of observation bits is sequentially moved backward.

[0074] In the code word synchronization process, the concept of test data block is introduced. The test data block is a part of the data sequence, the test data block is composed of a plurality of consecutive bits, and the length of the test data block is the same as the length of the code word. It can be said that the test data block is used to simulate a code word.

[0075] Optionally, the plurality of observation bits can be located in the same test data block, and the position of each observation bit in the same test data block is sequentially moved backward. Specifically, one bit is selected as the observation bit every T bits, and T is an integer greater than zero. Figure 4 shows the selection method of the observation bits, wherein b1, b2, and b3 are three adjacent observation bits, corresponding to x(0), x(1), and x(2) in the data sequence respectively. The interval between each observation bit is 1 bit, that is, T is 1. The three observation bits are located in the same test data block, for example, the test data block divided by x(0) as the starting position in Figure 4. In the test data block, the position of b1 is the first position in the test data block, and the positions of b2 and b3 are the second and third positions in the test data block respectively, that is, the position of each observation bit in the same test data block is sequentially moved backward. Although Figure 4 only shows three observation bits, the selection method of more observation bits can be inferred by analogy, which will not be described here.

[0076] Optionally, the multiple observation bits can be located in multiple test data blocks respectively, and the position of each observation bit in each test data block is sequentially moved backward. Specifically, one bit is selected as the observation bit every L*n+T bits, where L is the number of interval test data blocks, the length of the test data block is n bits, and L and T are integers greater than zero. FIG. 5 shows the selection of observation bits, where b1 and b2 are two adjacent observation bits, corresponding to x(0) and x(L*n+1) in the data sequence respectively. The two observation bits are located in two different test data blocks, for example, the test data block divided by x(0) as the starting position and the test data block divided by x(L*n) as the starting position. The interval between the two test data blocks is L test data blocks, and the interval between the two observation bits is L*n+1 bits, that is, T is 1. In the test data block divided by x(0) as the starting position, the position of b1 is the first position in the test data block, and in the test data block divided by x(L*n) as the starting position, the position of b2 is the second position in the test data block, that is, the position of each observation bit in each test data block is sequentially moved backward. Although FIG. 5 only shows two observation bits, the selection of more observation bits can be inferred by analogy, which will not be described here. At this time, the interval between adjacent observation bits is farther, and the correlation between observation bits is lower, so as to reduce the influence of burst error and improve the accuracy of code word synchronization.

[0077] Optionally, when the multiple observation bits are selected, the positions of the multiple observation bits can traverse all positions in the test data block.

[0078] For example, when the multiple observation bits are located in the same test data block, the positions of the multiple observation bits can traverse all positions in the same test data block, that is, the positions of the multiple observation bits can traverse all positions in the same code word. In the selection of observation bits shown in FIG. 4, the length of the code word is n bits, and the number of observation bits is P. When P is equal to n, the positions of the multiple observation bits can traverse all positions in the same test data block.

[0079] For example, when the plurality of observation bits are located in a plurality of test data blocks respectively, the same position in each of the plurality of test data blocks is regarded as an equivalent position, for example, the first position in each of the plurality of test data blocks is regarded as an equivalent position, so that the positions of the plurality of observation bits traverse all equivalent positions, i.e., the positions of the plurality of observation bits traverse all positions in the plurality of test data blocks. In the selection mode of the observation bits shown in FIG. 5, the length of the code word is n bits, the number of equivalent positions is n, the number of observation bits is P, and when P is equal to n, the positions of the plurality of observation bits can traverse all equivalent positions, i.e., the positions of the plurality of observation bits can traverse all positions in the plurality of test data blocks.

[0080] Optionally, when the plurality of observation bits are selected, the positions of the plurality of observation bits can also not traverse all positions in the code word, i.e., the value of P can be less than n.

[0081] If the positions of the plurality of observation bits traverse all positions in the test data block, the accuracy of the code word synchronization result will be higher. However, as the number of observation bits increases, the system resources consumed by the code word synchronization process will also increase.

[0082] At the sending end, the signal can be modulated to obtain a modulated signal. Common modulation methods include pulse-amplitude modulation (PAM), quadrature amplitude modulation (QAM), phase-shift keying (PSK), etc. The pulse amplitude of the modulated signal can include a plurality of orders, and the number of the plurality of orders can be referred to as the order of modulation. Taking PAM as an example, when the pulse amplitude of the modulated signal has two orders, the order of modulation is 2, and the modulation method can be referred to as PAM2; when the pulse amplitude of the modulated signal has four orders, the order of modulation is 4, and the modulation method can be referred to as PAM4, and so on. The modulated signal can be represented as a modulated data sequence. Compared with an unmodulated data sequence, the basic unit of the modulated data sequence is changed from a bit to a symbol, i.e., in the modulated data sequence, a code word is composed of a plurality of symbols, and a symbol is composed of a plurality of bits. The number of bits included in a symbol is related to the order of modulation. When the order of modulation is M, the number of bits included in a symbol is log2M, where M is an integer multiple of 2. For example, when the order of modulation is 2, one bit is included in a symbol, and when the order of modulation is 4, two bits are included in a symbol. As can be seen, the starting position of the code word must also be the starting position of a symbol, and cannot be other positions of the symbol. Therefore, for a modulated signal, when the plurality of observation bits are selected, only the starting bit of the symbol can be considered, and other bits of the symbol do not need to be considered.

[0083] Optionally, the plurality of observation bits are respectively start bits of a plurality of symbols, the plurality of symbols are in a same test data block, and positions of the plurality of symbols in the same test data block are sequentially moved backward. Specifically, every interval T modulation symbols, a start bit of a modulation symbol is selected as the observation bit, and the T is an integer greater than zero. That is, every interval T log2M bits, a start bit of a modulation symbol is selected as the observation bit. FIG. 6 shows a selection manner of the observation bits, wherein a data sequence is a modulation signal, a modulation order is 4, the data sequence includes a plurality of modulation symbols, each symbol includes 2 bits, for example, a symbol composed of x(0) and x(1), a symbol composed of x(2) and x(3), and a symbol composed of x(4) and x(5), and so on. Wherein b1, b2, b3 are three adjacent observation bits, corresponding to x(0), x(2), x(4) in the data sequence respectively. The three observation bits are respectively start bits of three symbols, the three symbols are a symbol composed of x(0) and x(1), a symbol composed of x(2) and x(3), and a symbol composed of x(4) and x(5). Every two adjacent symbols in the three symbols are separated by 1 symbol, that is, the T is 1. And, positions of the three symbols in the same test data block are sequentially moved backward. Although FIG. 6 only shows three observation bits, the selection manner of more observation bits can be analogized, which is not described herein again.

[0084] Optionally, the multiple observation bits are start bits of multiple symbols, the multiple symbols are located in multiple test data blocks respectively, and the position of each symbol in each test data block is sequentially moved backward. Specifically, every L*m+T modulation symbols, a start bit of a modulation symbol is selected as the observation bit, L is the number of interval test data blocks, the length of the test data block is the m modulation symbols, and L and T are integers greater than zero. That is, every (L*m+T)·log2M bits, a start bit of a modulation symbol is selected as the observation bit. FIG. 7 shows the selection mode of the observation bits, where the data sequence is a modulation signal, the modulation order is 4, the data sequence includes multiple modulation symbols, each symbol includes 2 bits, for example, a symbol composed of x(0) and x(1), a symbol composed of x(L*n) and x(L*n+1), and a symbol composed of x(L*n+2) and x(L*n+3), and so on. Where b1 and b2 are two adjacent observation bits, corresponding to x(0) and x(L*n+2) in the data sequence respectively. The two observation bits are start bits of two symbols, the two symbols are a symbol composed of x(0) and x(1) and a symbol composed of x(L*n+2) and x(L*n+3). And the two observation bits are located in two different test data blocks, for example, a test data block divided by x(0) as the starting position and a test data block divided by x(L*n) as the starting position. The interval between the two test data blocks is L test data blocks, and the interval between the two observation bits is L*m+1 symbols, that is, T is 1. In the test data block divided by x(0) as the starting position, the symbol where b1 is located is the first symbol in the test data block, and in the test data block divided by x(L*n) as the starting position, the symbol where b2 is located is the second symbol in the test data block, that is, the position of each symbol in each test data block is sequentially moved backward. Although FIG. 7 only shows two observation bits, the selection mode of more observation bits can be inferred by analogy, which will not be described here. At this time, the interval between adjacent observation bits is farther, the correlation between observation bits is lower, thereby reducing the influence of burst errors and improving the accuracy of code word synchronization.

[0085] S222, selecting a candidate bit from the multiple observation bits. The candidate bit is one of the multiple observation bits, and the candidate bit is the observation bit most likely to be located at the synchronization position. Specifically, S222 can include two steps of S2221 and S2222.

[0086] S2221, divide a plurality of groups of first test data blocks from the data sequence according to the plurality of observation bits, the plurality of groups of first test data blocks corresponding to the plurality of observation bits one by one. Specifically, each group of first test data blocks in the plurality of groups of first test data blocks includes at least one first test data block, and the position of each observation bit in the plurality of observation bits is the starting position of each group of first test data blocks in the plurality of groups of first test data blocks.

[0087] Optionally, N test data blocks after each observation bit in the plurality of observation bits are selected, where N is an integer greater than or equal to 1. The position of each observation bit in the plurality of observation bits is the starting position of each group of first test data blocks in the plurality of groups of first test data blocks. N test data blocks selected as the starting position of each observation bit are a group of first test data blocks, and the plurality of groups of N test data blocks selected as the starting position of each observation bit in the plurality of observation bits are the plurality of groups of first test data blocks. Each group of first test data blocks in the plurality of groups of first test data blocks corresponds to an observation bit as the starting position of the group of first test data blocks, that is, the plurality of groups of first test data blocks correspond to the plurality of observation bits one by one.

[0088] Optionally, the N test data blocks can be continuous, that is, each group of first test data blocks includes continuous N data blocks. When the length of each test data block is n bits, that is, continuous N*n bits after the observation bit are selected, that is, the N test data blocks are obtained.

[0089] Optionally, the N test data blocks can also be discontinuous, and the starting position of each test data block in the N test data blocks is associated with the observation bit corresponding to the group of test data blocks. Specifically, the interval between the starting position of each test data block and the observation bit corresponding to the group of test data blocks is an integer multiple of the length of the code word, that is, the interval between each two test data blocks in the N test data blocks is an integer multiple of the length of the code word. Moreover, the interval between each two test data blocks in the N test data blocks can be the same or different.

[0090] As shown in FIG. 4, a group of first test data blocks after the observation bit b1 is selected as the starting position, and the group of first test data blocks includes N test data blocks, that is, B1, B2, …, B N The length of each test data block is n bits. Similarly, a group of first test data blocks after the observation bit b2 or b3 can also be selected as the starting position. The plurality of groups of first test data blocks are selected as the starting position of the observation bits b1, b2 or b3, respectively. In FIGS. 5, 6 and 7, the manner of the plurality of groups of first test data blocks is similar to that of FIG. 4, which will not be described here.

[0091] S2222, according to the characteristic values of the multiple groups of first test data blocks, selecting one observation bit from the multiple observation bits as the candidate bit, i.e. the observation bit most likely to be in the synchronization position.

[0092] Optionally, when selecting one observation bit from the multiple observation bits as the observation bit most likely to be in the synchronization position according to the characteristic values of the multiple groups of first test data blocks, the selection manner can be a pre-terminated selection manner. Specifically, it is determined whether the characteristic value of each group of first test data blocks in the multiple groups of first test data blocks satisfies a candidate condition in sequence until it is determined that the characteristic value of one group of first test data blocks satisfies the candidate condition, and the observation bit corresponding to the one group of first test data blocks satisfying the candidate condition is taken as the candidate bit.

[0093] Optionally, when selecting one observation bit from the multiple observation bits as the observation bit most likely to be in the synchronization position according to the characteristic values of the multiple groups of first test data blocks, the selection manner can be an exhaustive selection manner. Specifically, the characteristic value of each group of first test data blocks in the multiple groups of first test data blocks is compared, and the observation bit corresponding to the group of first test data blocks with the extreme value of the characteristic value is taken as the candidate bit.

[0094] In the pre-terminated selection manner and the exhaustive selection manner, the calculation of the characteristic value can be performed in parallel, i.e. multiple calculation units are used to simultaneously calculate the characteristic values of multiple test data blocks. For example, 10 calculation units are used to simultaneously calculate the characteristic values of 10 test data blocks. The parallel calculation manner can save calculation time and reduce latency.

[0095] Optionally, the characteristic value can be a characteristic value of a check sequence.

[0096] A parity-check matrix can be generated for each linear block code, which describes the linear relationship between the data in the code word of the linear block code, and the parity-check matrix can be applied to the decoding process. When the data sequence is a linear block code, the parity-check matrix also exists for the data sequence, which can be referred to as the parity-check matrix of the data sequence. Specifically, the data sequence and the parity-check matrix of the data sequence satisfy the following relationship:

[0097]

[0098] Wherein, C is a code word in the data sequence, S is the check sequence of the code word, and H is the check matrix of the data sequence. According to the above relation (1), the check sequence of the code word in the data sequence is obtained by multiplying the code word and the transpose matrix of the check matrix of the data sequence, and the check sequence is a zero vector, i.e. a full zero matrix.

[0099] As described above, when the data sequence is the data sequence received by the receiving end, it is necessary to determine the starting position of the code word in the data sequence. If the code word is divided from the data sequence with a correct starting position, the obtained code word will no longer satisfy the above relation (1). At this time, the check sequence of the code word in the data sequence can be expressed by the following relation:

[0100] S R = R·H T (2)

[0101] Wherein, R is a code word in the data sequence received by the receiving end, S R is the check sequence of the code word, and H is the check matrix of the original data sequence sent by the sending end. In the above relation (2), the check sequence of the code word in the data sequence received by the receiving end is the product of the code word and the transpose matrix of the check matrix of the original data sequence sent by the sending end. According to the above analysis, for a received code word, when there is no error bit in the code word, S R is a full zero matrix; when there is an error bit in the code word, S R is no longer a full zero matrix with a high probability. Therefore, the check sequence of the test data block in the data sequence received by the receiving end can be used to realize code word synchronization. Specifically, the check sequence of the test data block in the data sequence received by the receiving end can be used to select an observation bit from the plurality of observation bits as the observation bit most likely located in the synchronization position.

[0102] Optionally, the check sequence of each group of first test data blocks in the plurality of groups of first test data blocks is calculated respectively.

[0103] As shown in FIG. 4, the check sequence of a group of first test data blocks with the observation bit b1 as the starting bit, i.e. S (1) in FIG. 4, includes S1 (1) , S2 (1) , …, S N (1) , which respectively correspond to test data blocks B1, B2, …, B N . Similarly, the check sequences of a group of first test data blocks with the observation bits b2 and b3 as the starting bits, i.e. S (2) and S (3)Although FIG. 4 only shows the calculation of the check sequence of one group of first test data blocks with three observation bits as starting bits, the calculation of more check sequences can be analogized in the same way, which will not be described here again. In FIG. 5, FIG. 6 and FIG. 7, the calculation of the check sequence of the plurality of groups of first test data blocks is similar to that of FIG. 4, which will not be described here again.

[0104] For example, the characteristic value can be the number of all-zero sequences in the check sequence. When the above-mentioned early termination selection method is adopted, the candidate condition is associated with the characteristic value. The candidate condition can be that the characteristic value of one group of first test data blocks is greater than or equal to a synchronization threshold. Specifically, the relationship between the number of all-zero sequences in the check sequence of each group of first test data blocks and the synchronization threshold is judged in sequence, and when it is determined that the number of all-zero sequences in the check sequence of one group of first test data blocks is greater than or equal to the synchronization threshold, the observation bit corresponding to the one group of first test data blocks that meets the candidate condition is taken as the candidate bit. The observation bit corresponding to one group of first test data blocks is also the observation bit taken as the starting bit of the group of first test data blocks.

[0105] The value of the synchronization threshold can be obtained through simulation analysis. For example, a data sequence is taken as the data sequence received by the receiving end, the bit error rate of the data sequence is designed to be within an acceptable range, the number of all-zero sequences in the check sequence of a group of test data blocks based on the synchronization position is counted, and the number of all-zero sequences in the check sequence of a group of test data blocks based on the non-synchronization position is counted, and the synchronization threshold is determined according to the difference between the two, so that the synchronization threshold can be used to distinguish the synchronization position and the non-synchronization position.

[0106] When the characteristic value is the number of all-zero sequences in the check sequence, and the above-mentioned early termination selection method is adopted, the selection process of the observation bit most likely located in the synchronization position can refer to FIG. 4. The synchronization threshold can be 2. As shown in FIG. 4, the relationship between the number of all-zero sequences in the check sequence S (1) ,S (2) ,S (3) is judged in sequence, for example, the number of all-zero sequences Q1 in the check sequence of the first group of first test data blocks is 0, which is less than the synchronization threshold, and the number of all-zero sequences Q2 in the check sequence of the second group of first test data blocks is 2, which is equal to the synchronization threshold, so b2 is selected as the observation bit most likely located in the synchronization position. And when b2 is judged, it is determined that b2 meets the candidate condition, so the relationship between the number of all-zero sequences in the check sequence of the subsequent observation bit and the synchronization threshold is not judged, that is, the relationship between the number of all-zero sequences in the check sequence S (3) is not judged.

[0107] Optionally, in the selection manner of the early termination, for the characteristic value of each group of the first test data blocks, a statistical manner of early termination can also be adopted. That is, the characteristic value of the group of the first test data blocks can be a total value of the number of all-zero sequences in the check sequences of all the first test data blocks in the group of the first test data blocks, and correspondingly, the alternative condition can be that the total value is greater than or equal to the synchronization threshold. In the selection process shown in FIG. 4, when the relationship between the number of all-zero sequences in each group of check sequences S (1) ,S (2) ,S (3) is sequentially judged, for each group of the first test data blocks, the check sequence of each test data block is sequentially calculated, when the check sequence is an all-zero sequence, the number of all-zero sequences is increased by 1, and when the accumulated value of the number of all-zero sequences satisfies the alternative condition, that is, the accumulated value of the number of all-zero sequences is greater than or equal to the synchronization threshold, it is considered that the group of the first test data blocks has satisfied the alternative condition, and the calculation of the test data blocks in the group that have not been calculated will not be performed. For example, for the second group of the first test data blocks, if S1 (2) ,S2 (2) are all all-zero sequences, it is considered that the number Q2 of all-zero sequences in the check sequences of the second group of the first test data blocks has accumulated to 2, reaching the synchronization threshold, the group of the first test data blocks has satisfied the alternative condition, and b2 is selected as the observation bit most likely located at the synchronization position, and the check sequences of S3 (2) to S N (2) are not calculated. Optionally, in the selection manner of the early termination, for the characteristic value of each group of the first test data blocks, a traversal statistical manner can also be adopted. That is, the characteristic value of the group of the first test data blocks can be an accumulated value of the number of all-zero sequences in the check sequences of the first X test data blocks in the group of the first test data blocks, and correspondingly, the alternative condition can be that the accumulated value is greater than or equal to the synchronization threshold. In the specific selection process, the check sequence of each first test data block in the group is calculated to determine whether the total value of the number of all-zero sequences in the group of the check sequences satisfies the alternative condition, that is, whether the total value of the number of all-zero sequences in the group of the check sequences is greater than or equal to the synchronization threshold, and the specific operation process is not described herein.

[0108] For example, the characteristic value can be the number of all-zero sequences in the check sequence. When the traversal selection manner is adopted, the extreme value is associated with the characteristic value. The extreme value can be a maximum value. Specifically, the number of all-zero sequences in the check sequence of each group of the first test data blocks can be counted, the group of the first test data blocks with the largest number of all-zero sequences is determined, and the observation bit corresponding to the group of the first test data blocks is selected as the observation bit most likely located at the synchronization position.

[0109] When the characteristic value is the number of all-zero sequences in the check sequence, the selection process of the observation bit most likely located at the synchronization position can also be seen from Figure 4. As shown in Figure 4, the number of all-zero sequences in the check sequence S (1) (2) (3) S (3) is respectively counted and recorded as Q1, Q2, Q3, the maximum value among them is determined, for example, Q1=0, Q2=0, Q3=2, that is, the maximum value is Q3=2, and b3 is selected as the observation bit most likely located at the synchronization position, and the position of b3 is the most likely synchronization position.

[0110] For example, the characteristic value can be the number of non-all-zero sequences in the check sequence. When the selection method of the early termination is adopted, the candidate condition is associated with the characteristic value. The candidate condition can be that the characteristic value of a group of first test data blocks is less than or equal to a synchronization threshold. Specifically, the relationship between the number of non-all-zero sequences in the check sequence of each group of first test data blocks and the synchronization threshold is judged in sequence, and until it is determined that the number of non-all-zero sequences in the check sequence of a group of first test data blocks is less than or equal to the synchronization threshold, the observation bit corresponding to the group of first test data blocks satisfying the candidate condition is selected as the candidate bit. The value of the synchronization threshold can also be obtained through simulation analysis, and the specific process is similar to that of the synchronization threshold corresponding to the all-zero sequence, which will not be described here.

[0111] For example, the characteristic value can be the number of non-all-zero sequences in the check sequence. When the selection method of the early termination is adopted, the candidate condition is associated with the characteristic value. The candidate condition can be that the characteristic value of a group of first test data blocks is less than or equal to a synchronization threshold. Specifically, the relationship between the number of non-all-zero sequences in the check sequence of each group of first test data blocks and the synchronization threshold is judged in sequence, and until it is determined that the number of non-all-zero sequences in the check sequence of a group of first test data blocks is less than or equal to the synchronization threshold, the observation bit corresponding to the group of first test data blocks satisfying the candidate condition is selected as the candidate bit. The value of the synchronization threshold can also be obtained through simulation analysis, and the specific process is similar to that of the synchronization threshold corresponding to the all-zero sequence, which will not be described here.

[0112] For example, the characteristic value can be the number of non-all-zero sequences in the check sequence. When the selection method of the early termination is adopted, the candidate condition is associated with the characteristic value. The candidate condition can be that the characteristic value of a group of first test data blocks is less than or equal to a synchronization threshold. Specifically, the relationship between the number of non-all-zero sequences in the check sequence of each group of first test data blocks and the synchronization threshold is judged in sequence, and until it is determined that the number of non-all-zero sequences in the check sequence of a group of first test data blocks is less than or equal to the synchronization threshold, the observation bit corresponding to the group of first test data blocks satisfying the candidate condition is selected as the candidate bit. The value of the synchronization threshold can also be obtained through simulation analysis, and the specific process is similar to that of the synchronization threshold corresponding to the all-zero sequence, which will not be described here.

[0113] For example, the characteristic value can be the number of zero elements in the check sequence. When the selection manner of the traversal is adopted, the extreme value is associated with the characteristic value. The extreme value can be a maximum value. Specifically, the number of zero elements in the check sequence of each group of first test data blocks can be counted, and a group of first test data blocks with the maximum number of zero elements is determined. The observation bit corresponding to the group of first test data blocks is taken as the observation bit most likely located at the synchronization position.

[0114] For example, the characteristic value can be the number of non-zero elements in the check sequence. When the selection manner of the early termination is adopted, the candidate condition is associated with the characteristic value. The candidate condition can be that the characteristic value of a group of first test data blocks is less than or equal to a synchronization threshold. Specifically, the relationship between the number of non-zero elements in the check sequence of each group of first test data blocks and the synchronization threshold is judged in sequence until it is determined that the number of non-zero elements in the check sequence of a group of first test data blocks is less than or equal to the synchronization threshold. The observation bit corresponding to the group of first test data blocks satisfying the candidate condition is taken as the candidate bit. The value of the synchronization threshold can also be obtained through simulation analysis.

[0115] For example, the characteristic value can be the number of non-zero elements in the check sequence. When the selection manner of the traversal is adopted, the extreme value is associated with the characteristic value. The extreme value can be a minimum value. Specifically, the number of non-zero elements in the check sequence of each group of first test data blocks can be counted, and a group of first test data blocks with the minimum number of non-zero elements is determined. The observation bit corresponding to the group of first test data blocks is taken as the observation bit most likely located at the synchronization position.

[0116] When the characteristic value is a non-all-zero sequence, a zero element or a non-zero element in the check sequence, in combination with the specific implementation process of the data sequence shown in FIG. 4, reference can be made to the introduction when the characteristic value is an all-zero sequence, which will not be repeated here.

[0117] Optionally, the characteristic value can be an error-correctable characteristic value. After the receiving end divides the code words in the data sequence, it can determine the state of the code words, which includes an error-correctable state and an error-uncorrectable state. When a code word is in the error-correctable state, the code word is also called an error-correctable code word; when a code word is in the error-uncorrectable state, the code word is also called an error-uncorrectable code word. The error-correctable characteristic value of a group of code words can be associated with the state of the code words in the group. Similarly, for the test data blocks divided by the receiving end in the data sequence received, the state of the test data blocks can also be determined, which includes an error-correctable state and an error-uncorrectable state. When a test data block is in the error-correctable state, the test data block is also called an error-correctable test data block; when a test data block is in the error-uncorrectable state, the test data block is also called an error-uncorrectable test data block. The error-correctable characteristic value of a group of test data blocks can be associated with the state of the test data blocks in the group.

[0118] For example, the error-correctable characteristic value can be the number of error-correctable test data blocks. When the above-mentioned early termination selection method is adopted, the alternative condition is associated with the characteristic value. The alternative condition can be that the characteristic value of a group of first test data blocks is greater than or equal to a synchronization threshold. Specifically, the relationship between the number of error-correctable test data blocks in each group of first test data blocks and the synchronization threshold is determined in sequence, and when it is determined that the number of error-correctable test data blocks in a group of first test data blocks is greater than or equal to the synchronization threshold, the observation bit corresponding to the group of first test data blocks that meets the alternative condition is selected as the alternative bit. The value of the synchronization threshold can also be obtained through simulation analysis.

[0119] When the error-correctable characteristic value is the number of error-correctable test data blocks, and the above-mentioned early termination selection method is adopted, the selection process of the observation bit most likely located in the synchronization position can refer to FIG. 4. The synchronization threshold can be 2. As shown in FIG. 4, the relationship between the number of error-correctable test data blocks in each group of first test data blocks and the synchronization threshold is determined in sequence, for example, the number of error-correctable test data blocks in the first group of first test data blocks Q1=0 is less than the synchronization threshold, and the number of error-correctable test data blocks in the second group of first test data blocks Q2=2 is equal to the synchronization threshold, so b2 is selected as the observation bit most likely located in the synchronization position. Moreover, when b2 is determined to meet the alternative condition, the relationship between the number of error-correctable test data blocks corresponding to the subsequent observation bits and the synchronization threshold is no longer determined, that is, the relationship between Q3 and the synchronization threshold is no longer determined.

[0120] For example, the error-correctable characteristic value can be the number of error-correctable test data blocks. When the selection mode of traversal is adopted, the extreme value is associated with the characteristic value. The extreme value can be a maximum value. Specifically, the number of error-correctable test data blocks in each group of first test data blocks can be counted, and a group of first test data blocks with the largest number of error-correctable test data blocks is determined. The observation bit corresponding to the group of first test data blocks is taken as the observation bit most likely located at the synchronization position.

[0121] When the error-correctable characteristic value is the number of error-correctable test data blocks, and the selection mode of traversal is adopted, the selection process of the observation bit most likely located at the synchronization position can also refer to FIG. 4. As shown in FIG. 4, the number of error-correctable test data blocks in each group of first test data blocks starting from observation bits b1, b2, and b3 is counted respectively and recorded as Q1, Q2, and Q3 respectively. The maximum value among them is determined, for example, Q1=0, Q2=0, and Q3=2, that is, the maximum value is Q3=2. b3 is selected as the observation bit most likely located at the synchronization position, and the position of b3 is the most likely synchronization position.

[0122] For example, the error-correctable characteristic value can be the number of error-correctable test data blocks. When the selection mode of traversal is adopted, the extreme value is associated with the characteristic value. The extreme value can be a maximum value. Specifically, the number of error-correctable test data blocks in each group of first test data blocks can be counted, and a group of first test data blocks with the largest number of error-correctable test data blocks is determined. The observation bit corresponding to the group of first test data blocks is taken as the observation bit most likely located at the synchronization position.

[0123] For example, the error-correctable characteristic value can be the number of error-correctable test data blocks. When the selection mode of traversal is adopted, the extreme value is associated with the characteristic value. The extreme value can be a maximum value. Specifically, the number of error-correctable test data blocks in each group of first test data blocks can be counted, and a group of first test data blocks with the largest number of error-correctable test data blocks is determined. The observation bit corresponding to the group of first test data blocks is taken as the observation bit most likely located at the synchronization position.

[0124] Optionally, the characteristic value can be a re-checking characteristic value. The re-checking characteristic value is associated with the relationship between the re-checking bits and the original checking bits. In combination with the above description, in a code word with a length of n bits, the first k bits are information bits, and the last n-k bits are checking bits. The checking bits of the last n-k bits are calculated according to a specific encoding rule based on the information bits of the first k bits. For a data sequence received by the receiving end, if the starting position of the code word in the data sequence is not found, the relationship between the information bits and the checking bits in the divided code word no longer satisfies the above relationship. That is, even if the same characteristic encoding rule is used, the same content as the last n-k bits in each test data block cannot be obtained based on the first k bits. In each test data block in the data sequence received by the receiving end, the last n-k bits no longer satisfy the above specific encoding rule before the first k bits. Therefore, the last n-k bits calculated according to the specific encoding rule based on the first k bits in each test data block in the data sequence received by the receiving end can be different from the last n-k bits in each test data block in the data sequence received by the receiving end. The last n-k bits in each test data block in the data sequence received by the receiving end can be referred to as original checking bits, and the last n-k bits calculated according to the specific encoding rule based on the first k bits in each test data block in the data sequence received by the receiving end can be referred to as re-checking bits.

[0125] From the above analysis, it can be seen that when there are error bits in the test data block, the re-checking bits are different from the original checking bits. Therefore, the re-checking bits and the original checking bits in each test data block in the data sequence received by the receiving end can be compared to realize code word synchronization. Specifically, the re-checking bits and the original checking bits in each test data block in the data sequence received by the receiving end can be compared, and one observation bit is selected from the plurality of observation bits as the observation bit that is most likely located at the synchronization position.

[0126] For example, the re-checking characteristic value can be the number of test data blocks in which the re-checking bits are the same as the original checking bits. When the above-mentioned early termination selection method is adopted, the alternative condition is associated with the characteristic value. The alternative condition can be greater than or equal to a synchronization threshold. Specifically, the relationship between the number of test data blocks in which the re-checking bits are the same as the original checking bits in each group of first test data blocks and the synchronization threshold is judged in sequence, and when it is determined that the number of test data blocks in which the re-checking bits are the same as the original checking bits in a group of first test data blocks is greater than or equal to the synchronization threshold, the observation bit corresponding to the group of first test data blocks that satisfies the alternative condition is selected as the alternative bit. The value of the synchronization threshold can also be obtained through simulation analysis.

[0127] When the re-check characteristic value is the number of test data blocks with the re-check bit same as the original check bit, and the selection mode of the early termination is adopted, the selection process of the observation bit most likely located at the synchronization position can refer to FIG. 4. In this case, the synchronization threshold value can be 2. As shown in FIG. 4, the relationship between the number of test data blocks with the re-check bit same as the original check bit in each group of first test data blocks and the synchronization threshold value is judged in sequence. For example, the number of test data blocks with the re-check bit same as the original check bit in the first group of first test data blocks Q1=0 is less than the synchronization threshold value, the number of test data blocks with the re-check bit same as the original check bit in the second group of first test data blocks Q2=2 is equal to the synchronization threshold value, and b2 is selected as the observation bit most likely located at the synchronization position. When b2 is judged, it is determined that b2 satisfies the candidate condition, and the relationship between the number of test data blocks with the re-check bit same as the original check bit corresponding to the subsequent observation bit and the synchronization threshold value is no longer judged, i.e., the relationship between Q3 and the synchronization threshold value is no longer judged.

[0128] For example, the re-check characteristic value can be the number of test data blocks with the re-check bit same as the original check bit. When the selection mode of the traversal is adopted, the extreme value is associated with the characteristic value. The extreme value can be a maximum value. Specifically, the number of test data blocks with the re-check bit same as the original check bit in each group of first test data blocks can be counted, the group of first test data blocks with the maximum number of test data blocks with the re-check bit same as the original check bit is determined, and the observation bit corresponding to the group of first test data blocks is selected as the observation bit most likely located at the synchronization position.

[0129] When the re-check characteristic value is the number of test data blocks with the re-check bit same as the original check bit, and the selection mode of the traversal is adopted, the selection process of the observation bit most likely located at the synchronization position can also refer to FIG. 4. As shown in FIG. 4, the number of test data blocks with the re-check bit same as the original check bit in each group of first test data blocks starting from the observation bits b1, b2 and b3 is counted respectively and recorded as Q1, Q2 and Q3 respectively, the maximum value among them is determined, for example, Q1=0, Q2=0 and Q3=2, i.e., the maximum value is Q3=2, b3 is selected as the observation bit most likely located at the synchronization position, and the position of b3 is the most likely synchronization position.

[0130] For example, the recheck characteristic value can be the number of test data blocks whose recheck bits are different from original check bits. When the above-mentioned early termination selection mode is adopted, the candidate condition is associated with the characteristic value. The candidate condition can be that the number of test data blocks whose recheck bits are different from original check bits is less than or equal to a synchronization threshold. Specifically, the relationship between the number of test data blocks whose recheck bits are different from original check bits in each group of first test data blocks and the synchronization threshold is sequentially judged until it is determined that the number of test data blocks whose recheck bits are different from original check bits in a group of first test data blocks is less than or equal to the synchronization threshold, and then the observation bit corresponding to the group of first test data blocks that meets the candidate condition is taken as the candidate bit. The value of the synchronization threshold can also be obtained through simulation analysis.

[0131] For example, the recheck characteristic value can be the number of test data blocks whose recheck bits are different from original check bits. When the above-mentioned traversal selection mode is adopted, the extreme value is associated with the characteristic value. The extreme value can be a minimum value. Specifically, the number of test data blocks whose recheck bits are different from original check bits in each group of first test data blocks can be counted, and a group of first test data blocks in which the number of test data blocks whose recheck bits are different from original check bits is the least is determined, and then the observation bit corresponding to the group of first test data blocks is taken as the observation bit that is most likely located at the synchronization position.

[0132] Optionally, according to the characteristic values of the multiple groups of first test data blocks, a synchronization possibility index of each of the multiple observation bits is determined. The greater the value of the synchronization possibility index, the greater the possibility that the position of the observation bit is a synchronization position. For example, when the characteristic values of the multiple groups of first test data blocks are the number of all-zero sequences in the check sequence of each of the multiple groups of first test data blocks, the synchronization possibility index can be positively correlated with the number of all-zero sequences, i.e., the greater the number of all-zero sequences, the greater the value of the synchronization possibility index, and the greater the possibility that the position of the observation bit is a synchronization position. For example, when the characteristic values of the multiple groups of first test data blocks are the number of non-all-zero sequences in the check sequence of each of the multiple groups of first test data blocks, the synchronization possibility index can be negatively correlated with the number of non-all-zero sequences, i.e., the smaller the number of non-all-zero sequences, the greater the value of the synchronization possibility index, and the greater the possibility that the position of the observation bit is a synchronization position. Similarly, when the characteristic values of the multiple groups of first test data blocks are the number of zero elements in the check sequence of each of the multiple groups of first test data blocks, or the number of correctable test data blocks in each of the multiple groups of first test data blocks, or the number of test data blocks in which the recheck parity bit is the same as the original check parity bit in each of the multiple groups of first test data blocks, the synchronization possibility index can be positively correlated with the number of zero elements or the number of correctable test data blocks or the number of test data blocks in which the recheck parity bit is the same as the original check parity bit; when the characteristic values of the multiple groups of first test data blocks are the number of non-zero elements in the check sequence of each of the multiple groups of first test data blocks, or the number of uncorrectable test data blocks in each of the multiple groups of first test data blocks, or the number of test data blocks in which the recheck parity bit is different from the original check parity bit in each of the multiple groups of first test data blocks, the synchronization possibility index can be negatively correlated with the number of non-zero elements or the number of uncorrectable test data blocks or the number of test data blocks in which the recheck parity bit is different from the original check parity bit; and the details are not described herein.

[0133] Optionally, when the number of observation bits with the largest value of the synchronization possibility index in the multiple groups of first test data blocks is greater than 1, one of the observation bits can be selected as the observation bit most likely located at the synchronization position according to other conditions. For example, one of the observation bits with the largest value of the synchronization possibility index is randomly selected as the observation bit most likely located at the synchronization position. For example, the observation bit with the largest value of the synchronization possibility index and ranked first in the data sequence is selected as the observation bit most likely located at the synchronization position.

[0134] In the second stage, the candidate bit is verified, and when the verification is successful, the position of the candidate bit is determined as the synchronization position. Specifically, the step S230 can include two steps, i.e., the steps S231 and S232.

[0135] In the step S231, a group of second test data blocks is divided in the data sequence according to the candidate bit, and the group of second test data blocks includes at least one second test data block. The candidate bit is the observation bit most likely located at the synchronization position.

[0136] Optionally, in the second stage, when the at least one second test data block is divided in the data sequence according to the candidate bit, only a part of the data sequence, for example, a second sub-sequence of the data sequence, can be used. According to the candidate bit, a group of second test data blocks is divided in the data sequence, that is, a group of second test data blocks is divided in the second sub-sequence according to the candidate bit.

[0137] Optionally, the second sub-sequence can be the same as the first sub-sequence in the first stage, that is, all bits of the second sub-sequence are the same as those of the first sub-sequence, and the two sub-sequences completely coincide. Optionally, the second sub-sequence can be partially the same as the first sub-sequence in the first stage, that is, part of the bits of the second sub-sequence are the same as those of the first sub-sequence, and the two sub-sequences partially coincide. Optionally, the second sub-sequence can be different from the first sub-sequence in the first stage, that is, all bits of the second sub-sequence are different from those of the first sub-sequence, and the two sub-sequences have no intersection.

[0138] When the intersection between the data used in the first stage and the second stage is smaller, the independence between the data used in the first stage and the second stage is stronger, and the accuracy of the code word synchronization result is higher. Therefore, when the first sub-sequence is different from the second sub-sequence, the accuracy of the code word synchronization result is higher.

[0139] In the second stage, a group of second test data blocks is divided in the second sub-sequence according to the candidate bit, i.e. the observation bit most likely located in the synchronization position, and the group of second test data blocks includes at least one second test data block.

[0140] In the second stage, a group of second test data blocks is divided in the second sub-sequence according to the candidate bit, i.e. the observation bit most likely located in the synchronization position, and the group of second test data blocks includes at least one second test data block.

[0141] In the second stage, a group of second test data blocks is divided in the second sub-sequence according to the candidate bit, i.e. the observation bit most likely located in the synchronization position, and the group of second test data blocks includes at least one second test data block.

[0142] Optionally, the at least one second test data block can be continuous, i.e. the at least one second test data block includes continuous N data blocks. When the length of each test data block is n bits, i.e. continuous N*n bits after the test data block are selected, the at least one second test data block is obtained.

[0143] Optionally, the at least one second test data block can also be discontinuous, and the starting position of each test data block in the at least one second test data block is associated with the candidate bit. Specifically, the interval between the starting position of each test data block and the candidate bit is an integer multiple of the length of the code word, i.e. the interval between every two test data blocks in the at least one second test data block is an integer multiple of the length of the code word. Moreover, the interval between every two test data blocks in the at least one second test data block can be the same or different.

[0144] S232, verifying the characteristic value of the at least one second test data block, and when the verification is successful, determining that the position of the candidate bit is the synchronization position.

[0145] Optionally, the characteristic value of the at least one second test data block is verified, and the verification manner can be a pre-terminated verification manner. Specifically, the characteristic values of each second test data block in the at least one second test data block are sequentially accumulated to obtain an accumulated value, and when the accumulated value meets a synchronization condition, the verification is successful, and the position of the candidate bit is determined as the synchronization position.

[0146] The synchronization condition is associated with the characteristic value, and specifically,

[0147] The characteristic value is the number of all-zero sequences in the check sequence, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold; or,

[0148] The characteristic value is the number of zero elements in the check sequence, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold; or,

[0149] The characteristic value is the number of error-correctable test data blocks, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold; or,

[0150] The characteristic value is the number of test data blocks whose recheck parity bits are the same as original parity bits, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold.

[0151] The value of the synchronization threshold can also be obtained through simulation analysis. Moreover, the synchronization threshold in the step 230 and the synchronization threshold in the step 2222 can have the same value or different values.

[0152] Optionally, the characteristic value of the at least one second test data block is verified, and the verification manner can be a traversal verification manner. Specifically, the characteristic values of all second test data blocks in the at least one second test data block are added to obtain a total value, and when the total value meets a synchronization condition, the verification is successful, and the position of the candidate bit is determined as the synchronization position.

[0153] The synchronization condition is associated with the characteristic value, and specifically,

[0154] The characteristic value is the number of all-zero sequences in the check sequence, and the synchronization condition is that the total value is greater than or equal to a synchronization threshold; or,

[0155] The characteristic value is the number of non-all-zero sequences in the check sequence, and the synchronization condition is that the total value is less than or equal to a synchronization threshold; or,

[0156] The characteristic value is the number of zero elements in the check sequence, and the synchronization condition is that the total value is greater than or equal to a synchronization threshold; or,

[0157] The characteristic value is the number of non-zero elements in the check sequence, and the synchronization condition is that the total value is less than or equal to a synchronization threshold; or

[0158] The characteristic value is the number of non-correctable test data blocks, and the synchronization condition is that the total value is greater than or equal to a synchronization threshold; or

[0159] The characteristic value is the number of non-correctable test data blocks, and the synchronization condition is that the total value is less than or equal to a synchronization threshold; or

[0160] The characteristic value is the number of test data blocks whose re-check bits are the same as the original check bits, and the synchronization condition is that the total value is greater than or equal to a synchronization threshold; or

[0161] The characteristic value is the number of test data blocks whose re-check bits are not the same as the original check bits, and the synchronization condition is that the total value is less than or equal to a synchronization threshold.

[0162] The value of the synchronization threshold can also be obtained by simulation analysis. Moreover, the synchronization threshold in step 230 and the synchronization threshold in step 2222 can be the same or different.

[0163] In the early termination verification mode and the traversal verification mode, the calculation of the characteristic value can be performed in parallel, that is, multiple calculation units are used to calculate the characteristic values of multiple test data blocks at the same time. For example, 10 calculation units are used to calculate the characteristic values of 10 test data blocks at the same time. Parallel calculation can save calculation time and reduce latency.

[0164] FIGS. 8-9 show an exemplary process of determining the observation bit most likely located at the synchronization position in the data sequence, and verifying whether the position of the observation bit most likely located at the synchronization position is the synchronization position. The linear block code shown in FIG. 8 is a BCH(360, 340) code, that is, the length of each code word is 360 bits, and the length of the information data in each code word is 340 bits. The modulation mode of the BCH(360, 340) code is non-return-to-zero (NRZ), and the modulation order M is 2, so each code element includes 1 bit. The check matrix of the BCH(360, 340) code is as follows:

[0165]

[0166] wherein a is a primitive element of Galois field GF(2 10 ).

[0167] Figure 8 shows a portion of the data sequence received by the receiver. It is necessary to confirm the start position of the codewords in this data sequence, i.e., the synchronization position. Based on the above description, in the first stage, the observation bit most likely located at the synchronization position in the data sequence is determined. As shown in Figure 8, in the first stage, the start bit of the modulation symbol is selected as the observation bit every T·log2M bits, where T is 1, meaning the start bit of the modulation symbol is selected every 1 bit. Therefore, 360 consecutive bits are selected as observation bits, i.e., the number of observation bits P is 360, as shown in Figure 8 as b1, b2, b3, ..., b 359 ,b 360 Based on these observed bits, multiple sets of first test data blocks are divided from the data sequence. The number of test data blocks N in each set of first test data blocks is 2, that is, each set of first test data blocks includes 2 test data blocks, as shown in multiple sets B1 and B2 in Figure 8.

[0168] Based on the above description, among the multiple observation bit positions in the data sequence shown in Figure 8, only one observation bit position is the true synchronization position of the data sequence. The number of all-zero sequences in the check sequence of each group of first test data blocks is used as the basis for selecting the observation bit most likely to be located at the synchronization position. As shown in Figure 8, the check sequence S is a row vector of length 4. For example, the set of check sequences for a group of first test data blocks starting with observation bit b1 is S. (1) Including S1 (1) S2 (1) These correspond to test data blocks B1, B2, and so on, to observe bits b2, b3, ..., b 359 ,b 360 The set of check sequences for the first test data block, which is a set of starting bits, are S. (2) ,S (3) ,…,S (359) ,S (360) Count the number of all-zero sequences in the check sequence of the first test data block in each group, and denote them as Q1, Q2, Q3, ..., Q 359 Q 360 As shown in Figure 8, where Q1 = 0, meaning that the check sequence of the first test data block starting with the observed bit b1 does not contain a sequence of all zeros, similarly, Q2 = 0, Q3 = 1, ..., Q... 359 =2,Q 360 =0. Assume that Q ultimately appears as 0 among all 360 Q values. 359 If the value is the largest, then bit b will be observed. 359 The observation bit is considered to be the most likely location of the synchronization position. That is, observation bit b is considered to be... 359The starting bit of a test data block, and every 360 bits thereafter are starting bits of subsequent test data blocks.

[0169] In step S220, the observation bit most likely to be in the synchronization position is selected from the data sequence. 359 After that, the part of the data sequence used in the first stage, i.e. after the first sub-sequence, is divided into a group of second test data blocks according to the b 359 The group of second test data blocks is divided. That is, the group of second test data blocks is divided in a second sub-sequence, which is different from the first sub-sequence. As shown in FIG. 9, the group of second test data blocks includes four test data blocks. The characteristic value of the at least one second test data block is verified, which is the number of all-zero sequences in the check sequence of the at least one second test data block. The verification is performed in the above-mentioned traversal manner, i.e. the number of all-zero sequences in the check sequence of all second test data blocks in the at least one second test data block is added to obtain a total value, and when the total value is greater than or equal to a synchronization threshold, the verification is successful, and the synchronization threshold is 2. As shown in FIG. 9, the number of all-zero sequences in the check sequence of the four test data blocks is 3, which is greater than 2, so it is determined that the position of b 359 is the synchronization position.

[0170] Optionally, when the verification is not successful, the above-mentioned step S220 is re-executed, i.e. the first stage is re-executed, and the observation bit most likely to be in the synchronization position is re-selected.

[0171] Step S230 is an optional step, i.e. the method can only include the first stage. At this time, after step S220, step S240 is directly entered. At this time, in the method, after the candidate bit is determined, the position of the candidate bit is directly determined as the synchronization position. That is, the most likely synchronization position is directly determined as the synchronization position.

[0172] S240, it is determined that the data sequence is in a synchronization-locked state.

[0173] After the synchronization position is determined by the receiving end, the received data sequence can be divided into multiple synchronization code words according to the synchronization position. When the data sequence is divided into multiple synchronization code words according to the synchronization position, it can be considered that the data sequence is in a synchronization-locked position. That is, after the synchronization position is determined, the receiving end determines that the data sequence is in a synchronization-locked state. When the data sequence is in a synchronization-locked state, the receiving end can perform error detection and error correction operations on the data sequence.

[0174] S250, loss of lock determination.

[0175] After the receiving end starts the error detection, error correction and other operations on the data sequence, it still needs to continuously observe whether the code word division in the data sequence is accurate, i.e. whether the synchronization position is accurate. When the synchronization position is inaccurate, the content of each test data block divided according to the synchronization position no longer corresponds to the real code word, at this time, it can also be called that the synchronization lock state of the data sequence is lost. Therefore, the process of judging whether the synchronization position of the data sequence is accurate can also be called the lock loss judgment process.

[0176] In the lock loss judgment process, a plurality of synchronization code words are divided from the data sequence according to the synchronization position, the synchronization position being the starting position of the plurality of synchronization code words; the characteristic values of the plurality of synchronization code words are verified, and when the verification fails, it is determined that the data sequence is in the lock loss state.

[0177] Optionally, the plurality of synchronization code words can be continuous, i.e. the plurality of synchronization code words include continuous N code words. When the length of each code word is n bits, i.e. the continuous N*n bits after that are selected, i.e. the plurality of synchronization code words are obtained.

[0178] Optionally, the plurality of synchronization code words can also be discontinuous, and the starting position of each code word in the plurality of synchronization code words is associated with the synchronization position. Specifically, the interval between the starting position of each synchronization code word and the synchronization position is an integer multiple of the length of the code word, i.e. the interval between each two synchronization code words in the plurality of synchronization code words is an integer multiple of the length of the code word. Moreover, the interval between each two synchronization code words in the plurality of synchronization code words can be the same or different.

[0179] Optionally, the verification of the characteristic values of the plurality of synchronization code words can be a pre-terminated verification method. Specifically, the characteristic values of the synchronization code words in the plurality of synchronization code words are sequentially accumulated to obtain an accumulated value, and when the accumulated value meets a lock loss condition, the verification fails, and it is determined that the position of the candidate bit is the synchronization position.

[0180] The lock loss condition is associated with the characteristic value, and specifically,

[0181] The characteristic value is the number of non-all-zero sequences in the check sequence, and the lock loss condition is that the accumulated value is greater than or equal to a synchronization threshold; or,

[0182] The characteristic value is the number of non-zero elements in the check sequence, and the lock loss condition is that the accumulated value is greater than or equal to a synchronization threshold; or,

[0183] The characteristic value is the number of uncorrectable code words, and the lock loss condition is that the accumulated value is greater than or equal to a synchronization threshold; or,

[0184] The characteristic value is the number of code words whose re-checking bits are different from original checking bits, and the lock loss condition is that the cumulative value is greater than or equal to a synchronization threshold value;

[0185] The length of the code word is n bits, the first k bits of the code word are information bits, the last n-k bits of the code word are the original checking bits, the re-checking bits are obtained according to the information bits, the length of the re-checking bits is n-k bits, and n and k are integers.

[0186] The value of the synchronization threshold value can also be obtained through simulation analysis. Moreover, the synchronization threshold value in the step 250 and the synchronization threshold value in the steps 230 and 2222 can be the same or different.

[0187] Optionally, the characteristic values of the plurality of synchronization code words are verified in a traversal verification manner. Specifically, the characteristic values of all the synchronization code words in the plurality of synchronization code words are added to obtain a total value, and when the total value satisfies a lock loss condition, the verification fails, and the position of the candidate bit is determined as the synchronization position.

[0188] The synchronization condition is associated with the characteristic value, and specifically,

[0189] The characteristic value is the number of all-zero sequences in the checking sequence, the lock loss condition is that the total value is less than or equal to a synchronization threshold value; or

[0190] The characteristic value is the number of non-all-zero sequences in the checking sequence, the lock loss condition is that the total value is greater than or equal to a synchronization threshold value; or

[0191] The characteristic value is the number of zero elements in the checking sequence, the lock loss condition is that the total value is less than or equal to a synchronization threshold value; or

[0192] The characteristic value is the number of non-zero elements in the checking sequence, the lock loss condition is that the total value is greater than or equal to a synchronization threshold value; or

[0193] The characteristic value is the number of correctable code words, the lock loss condition is that the total value is less than or equal to a synchronization threshold value; or

[0194] The characteristic value is the number of uncorrectable code words, the lock loss condition is that the total value is greater than or equal to a synchronization threshold value; or

[0195] The characteristic value is the number of code words whose re-checking bits are the same as original checking bits, the lock loss condition is that the total value is less than or equal to a synchronization threshold value; or

[0196] The characteristic value is the number of code words whose re-checking bits are different from original checking bits, and the lock loss condition is that the total value is greater than or equal to a synchronization threshold value.

[0197] The length of the code word is n bits, the first k bits of the code word are information bits, the last n-k bits of the code word are the original checking bits, the re-checking bits are obtained according to the information bits, the length of the re-checking bits is n-k bits, and n and k are integers.

[0198] The value of the synchronization threshold value can also be obtained through simulation analysis. In addition, the synchronization threshold value in step 250 can be the same as or different from the synchronization threshold value in steps 230 and 2222.

[0199] In the early termination verification mode and the traversal verification mode, the calculation of the characteristic value can be performed in parallel, that is, multiple computing units are used to calculate the characteristic values of multiple test data blocks at the same time. For example, 10 computing units are used to calculate the characteristic values of 10 test data blocks at the same time. The parallel calculation mode can save calculation time and reduce latency.

[0200] FIG. 10 shows an exemplary process of lock loss judgment. As shown in FIG. 10, five synchronization code words are divided from the data sequence according to the synchronization position, and the number of correctable code words is counted. For example, in the decoding state, 0 represents uncorrectable and 1 represents correctable. In the five synchronization code words shown in FIG. 10, the number of correctable code words is 1. If the lock loss threshold value is 3, the number of correctable code words is less than the lock loss threshold value, it is determined that the five synchronization code words satisfy the lock loss condition, and the data sequence is in a lock loss state.

[0201] Optionally, when the verification does not fail, it is determined that the synchronization lock state of the data sequence is not lost.

[0202] Optionally, after it is determined that the synchronization lock state of the data sequence is not lost, a certain interval can be moved backward in the data sequence, a plurality of synchronization code words are selected, and it is continued to be judged whether the plurality of synchronization code words selected backward satisfy the lock loss condition. Optionally, the certain interval moved backward can be one test data block, that is, for each synchronization code word, a plurality of synchronization code words are observed backward from it to perform lock loss judgment.

[0203] S260, determining that the data sequence is in a lock loss state.

[0204] Optionally, when it is determined that the data sequence is in the lock loss state, an updated synchronization position of the data sequence is determined. Specifically, the first stage and the second stage are re-executed, and the synchronization position determined in the re-executed second stage is taken as the updated synchronization position. In this way, a synchronization lock-lock loss-synchronization lock closed loop operation is formed, which ensures that the communication system is in the normal working state of synchronization lock for as long as possible.

[0205] The method can solve the technical problems of poor cascading expansibility and additional data in the AM synchronization scheme. Moreover, no additional data needs to be inserted into the data stream at the sending end, so no idle code block insertion and deletion mechanism needs to be introduced on the Ethernet interface, no corresponding logic processing unit needs to be designed, and no bandwidth needs to be reserved in advance for the inserted AM sequence. If a one-level FEC needs to be added on the basis of the original FEC, and a two-level FEC cascade is used, the technical problems that the original idle code block insertion and deletion mechanism cannot be applied to the AM sequence of the second-level FEC and that adding the AM sequence for the second-level FEC affects the high-precision clock synchronization performance can be avoided. The method can achieve the technical effect of high-precision code word synchronization of the data stream at the receiving end, and the synchronization performance reaches high reliability.

[0206] Steps S240, S250, and S260 are optional steps, that is, the method can be used only for determining the synchronization position, and the data sequence can not be subjected to error detection or error correction processing in the synchronization lock state, or whether the data sequence subsequently enters the lock loss state can not be judged.

[0207] Through simulation comparison, the code word synchronization method provided in the present application is superior to the existing AM synchronization scheme in terms of average synchronization lock time, average error lock occurrence time, and average error lock loss occurrence time, and other performance indicators. Therefore, as a whole, the code word synchronization method provided in the present application can achieve better synchronization performance than the AM synchronization scheme.

[0208] FIG. 11 shows a code word synchronization method according to an embodiment of the present application. The method includes the following steps:

[0209] Step one, receiving a data sequence, the data sequence including a plurality of bits. The specific process of the step one can be referred to the description of step S210 above.

[0210] Step two, determining a candidate bit in the data sequence, the candidate bit included in the plurality of bits. The candidate bit is the observation bit most likely to be in the synchronization position. The specific process of the step two can be referred to the description of step S220 above.

[0211] Step three, determining a synchronization position according to the candidate bit, the synchronization position being used to indicate a start position of the code word.

[0212] Optionally, determining the synchronization position according to the candidate bit can be further verifying whether the position of the observation bit most likely to be in the synchronization position is the synchronization position after selecting the observation bit most likely to be in the synchronization position. The candidate bit is the observation bit most likely to be in the synchronization position. At this time, the specific process of step three can refer to the description of step S230 above. At this time, the method at least includes S210, S220 and S230 shown in FIG. 2.

[0213] Optionally, determining the synchronization position according to the candidate bit can also be directly taking the observation bit most likely to be in the synchronization position as the synchronization position after selecting the observation bit most likely to be in the synchronization position. The candidate bit is the observation bit most likely to be in the synchronization position. At this time, the method at least includes S210 and S220 shown in FIG. 2.

[0214] It can be seen that in the above two ways of determining the synchronization position according to the candidate bit, the bit in the synchronization position is included in the candidate bit, and the candidate bit is the observation bit most likely to be in the synchronization position.

[0215] Optionally, after step three, the method further includes determining that the data sequence is in a synchronization-locked state. The specific process can refer to the description of step S240 above.

[0216] Optionally, after step three, the method further includes a loss-of-lock judgment. The specific process can refer to the description of step S250 above.

[0217] Optionally, the method can further include step four, determining an updated synchronization position of the data sequence in response to the data sequence being in a loss-of-lock state. The specific process can refer to the description of step S260 above.

[0218] The code word synchronization method of the embodiment of the application is executed by a communication device, which can be any device performing FEC, including but not limited to a router, a switch, a server, and a terminal device.

[0219] FIG. 12 shows a possible structural schematic diagram of a communication device related to the embodiment of the application. Referring to FIG. 12, the communication device 1200 includes a receiving unit 1201 and a processing unit 1202. These units can perform the corresponding steps of the methods shown in FIGS. 2-11 above. For example,

[0220] The receiving unit 1201 is configured to receive a data sequence, the data sequence including a plurality of bits.

[0221] determine a candidate bit in the data sequence, the candidate bit being included in the plurality of bits; and determine a synchronization position according to the candidate bit, the synchronization position being used to indicate a start position of a code word in the data sequence.

[0222] FIG. 13 is another structure of a communication device according to an embodiment of the present application. Referring to FIG. 13, the communication device 1300 includes at least one processor 1301 and at least one communication interface 1304. Optionally, the device 1300 can further include a memory 1303.

[0223] The processor 1301 can be a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a transistor logic device, a hardware component or any combination thereof. It can implement or execute various logical blocks, modules and circuits described in combination with the disclosure of the present application. The processor can also be a combination of computing functions, such as one or more microprocessor combinations, combinations of DSP and microprocessor, etc. The processor can be used to determine a candidate bit in the data sequence, and determine a synchronization position according to the candidate bit. In order to implement the method provided in the embodiments of the present application.

[0224] Optionally, a communication bus 1302 is used to transmit information between the processor 1301, the communication interface 1304 and the memory 1303. The bus can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, only one thick line is used in FIG. 13, but it does not mean that there is only one bus or only one type of bus.

[0225] The memory 1303 can be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disk storage, a magnetic disk storage or other magnetic storage devices, or any other medium capable of storing desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to this. The memory 1303 can exist independently, and is connected to the processor 1301 through the communication bus 1302. The memory 1303 can also be integrated with the processor 1301.

[0226] Optionally, the memory 1303 is configured to store program codes or instructions for implementing the solutions of the present application, and the processor 1301 is configured to control the execution. In the case of implementing the embodiment shown in FIG. 12, and in the case of implementing the units described in the embodiment of FIG. 12 by software, the software or program codes required to execute the functions of the units in FIG. 12 are stored in the memory 1303. The processor 1301 is configured to execute the program codes stored in the memory 1303. The program codes can include one or more software modules. Optionally, the processor 1301 itself can also store program codes or instructions for implementing the solutions of the present application.

[0227] The communication interface 1304 is configured to communicate with other devices or communication networks using any transceiver-like device, and the communication networks can be an Ethernet, a radio access network (RAN), a wireless local area networks (WLAN), etc. In the embodiments of the present application, the communication interface 1304 can be configured to receive packets sent by other nodes in the segment routing network, and can also be configured to send packets to other nodes in the segment routing network. The communication interface 1304 can be an Ethernet interface, a Fast Ethernet (FE) interface, a Gigabit Ethernet (GE) interface, or an Asynchronous Transfer Mode (ATM) interface.

[0228] In a particular implementation, as one embodiment, the device 1300 can include multiple processors, such as the processor 1301 and the processor 1305 shown in FIG. 13. Each of these processors can be a single-CPU processor or a multi-CPU processor. A processor here can refer to one or more devices, circuits, and / or processing cores for processing data, such as computer program instructions.

[0229] In a particular embodiment, the processor 1301 in the network device 1300 is configured to receive a data sequence including a plurality of bits via a communication interface, determine a candidate bit in the data sequence, the candidate bit included in the plurality of bits, and determine a synchronization position according to the candidate bit, the synchronization position indicating a start position of a code word in the data sequence. The detailed processing of the processor can refer to the descriptions of steps S210, S220, S230, S240, S250, S260 in the embodiment shown in FIG. 2, steps S221, S222 in the embodiment shown in FIG. 3, and steps 1-3 shown in FIG. 11, which are not repeated here.

[0230] The communication interface in the network device 1300 is configured to receive and send the data sequence by the network device 1300 via a network system. The detailed process can refer to the descriptions of S210 in the embodiment shown in FIG. 2 and step 1 shown in FIG. 11, which are not repeated here.

[0231] Figure 14 is another schematic diagram of a structure of a communication device according to an embodiment of the present application. When the communication device is a forwarding device in a network, such as a router or a switch, the communication device can have the structure shown in Figure 14. The device 1400 includes a main board and one or more interface boards, and the main board is communicatively connected to the interface boards. The main board is also referred to as a main processing unit (MPU) or a route processor card, and is responsible for the control and management of various components in the device 1400, including route computation, device management and maintenance functions. The interface board is also referred to as a line processing unit (LPU) or a line card, and is used for forwarding data. In some embodiments, the device 1400 can also include a switch fabric board, which is communicatively connected to the main board and the interface boards, and is used for forwarding data between the interface boards. The switch fabric board can also be referred to as a switch fabric unit (SFU). The interface board includes a central processing unit, a memory, a forwarding chip and a physical interface card (PIC). The central processing unit is communicatively connected to the memory, the network processor and the physical interface card. The memory is used to store a forwarding table. The forwarding chip is used to forward a received data frame based on the forwarding table stored in the memory. If the destination address of the data frame is the address of the device 1400, the data frame is sent to the CPU for processing. If the destination address of the data frame is not the address of the device 1400, the next hop and the out interface corresponding to the destination address are found from the forwarding table based on the destination address, and the data frame is forwarded to the out interface corresponding to the destination address. The forwarding chip can be a network processor (NP). The PIC, also referred to as a daughter card, can be installed on the interface board, and is responsible for converting an optical signal into a data frame and forwarding the data frame to the forwarding chip for processing after performing a legality check on the data frame. In some embodiments, the central processing unit can also perform the functions of the forwarding chip, such as implementing software forwarding based on a general-purpose CPU, so that the interface board does not need a forwarding chip. The communication connection between the main board, the interface board and the switch fabric board can be achieved through a bus. In some embodiments, the forwarding chip can be implemented through an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA).

[0232] In logic, the device 1400 includes a control plane and a forwarding plane, the control plane includes a main control board and a central processor, and the forwarding plane includes various components performing forwarding, such as a memory, a PIC, and an NP. The control plane performs functions such as router, generating a forwarding table, processing signaling and protocol packets, configuring and maintaining the state of PE1, and the like. The control plane issues the generated forwarding table to the forwarding plane, and in the forwarding plane, the NP performs table lookup and forwarding on the packets received by the PIC of the device 1400 based on the forwarding table issued by the control plane. The forwarding table issued by the control plane can be stored in the memory. In some embodiments, the control plane and the forwarding plane can be completely separated and not on the same device.

[0233] In specific embodiments, the interface board is configured to receive a data sequence, the data sequence including a plurality of bits. For details, refer to the description of step one in FIG. 11 and step S210 in the embodiment shown in FIG. 2, which will not be repeated here. The main control board is configured to determine candidate bits in the data sequence, the candidate bits included in the plurality of bits; and determine a synchronization position according to the candidate bits, the synchronization position indicating a starting position of a code word in the data sequence. For details, refer to the description of steps S210, S220, S230, S240, S250, and S260 in the embodiment shown in FIG. 2, steps S221 and S222 in the embodiment shown in FIG. 3, and steps one to three in FIG. 11, which will not be repeated here.

[0234] In a possible implementation, an inter-process communication (IPC) channel is established between the main control board and the interface board, and the main control board and the interface board communicate through the IPC channel.

[0235] The embodiments of the present application provide a chip, which includes a memory and a processor, the memory is configured to store a computer program, and the processor is configured to call and run the computer program from the memory to execute the method in the above method embodiments, i.e., the method in the embodiments shown in FIGS. 2-11.

[0236] Optionally, the above chip only includes a processor, and the processor is configured to read and execute a computer program stored in the memory, and when the computer program is executed, the processor executes the method in the above method embodiments, i.e., the method in the embodiments shown in FIGS. 2-11.

[0237] Optionally, the chip can be used in a two-stage FEC cascade application scenario. Specifically, the two-stage FEC cascade includes an inner layer FEC and an outer layer FEC, and the chip provided in the embodiment of the present application is used for the inner layer FEC. The inner layer FEC adopts the code word synchronization method described in the present application, also referred to as FEC1; the outer layer FEC can adopt an AM synchronization scheme, also referred to as FEC2. At this time, the FEC1 and the FEC2 can be located on the same chip or on different chips. That is, the chip provided in the embodiment of the present application can only include the FEC1, or can include the FEC1 and the FEC2.

[0238] The embodiment of the present application provides a network system. The network system includes a receiving device and a sending device. The receiving device is used for receiving a data sequence sent by the sending device. The receiving device can perform the steps in the embodiments shown in FIGS. 2-11.

[0239] The embodiment of the present application further provides a non-transitory storage medium for storing software instructions used in the foregoing embodiments, which includes a program for executing the method shown in the foregoing embodiments, when the program is executed on a computer or network device, so that the computer or network device shown performs the method in the foregoing method embodiments.

[0240] The embodiment of the present application further provides a computer program product including computer program instructions, when the computer program product is run on a computer, so that the network node performs the method in the foregoing method embodiments.

[0241] It should be noted that any of the device embodiments described above are only schematic, and the units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or distributed on multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the embodiment. In addition, the connection relationship between the modules in the embodiment of the network device or host provided in the present application indicates that there is a communication connection between them, which can be implemented as one or more communication buses or signal lines. Those skilled in the art can understand and implement it without creative labor.

[0242] The steps of methods or algorithms described in connection with the embodiments described herein can be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module can reside in RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. The storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium can be integral to the processor.

[0243] The above detailed description has been given to the purposes of illustrating the present application, technical solutions and advantages. It should be understood that the above description is only a specific implementation of the present application, and is not intended to limit the protection scope of the present application. Any modification, replacement, improvement, etc. made on the basis of the technical solutions of the present application should be included in the protection scope of the present application.

[0244] The terms "first", "second", and the like in the present application are used to distinguish the same items or similar items with substantially the same function and action, and it should be understood that there is no logical or time sequence between "first", "second", and "n", and the quantity and execution order are not limited. It should also be understood that although the following description uses the terms first, second, and the like to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of various described examples, a first image can be referred to as a second image, and similarly, a second image can be referred to as a first image. The first image and the second image can both be images, and in some cases, can be separate and distinct images.

[0245] The term "at least one" in the present application means one or more, and the term "multiple" in the present application means two or more, for example, multiple second packets means two or more second packets. The terms "system" and "network" are often used interchangeably in this document.

[0246] It should be understood that the words “example” and / or “exemplary” are used herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “example” and / or “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations. Likewise, the term “implies” does not mean “is limited to.” As used herein, the terms “first,” “second” and / or “third” are used to identify various elements, but do not connote any order, quantity, and / or importance of the elements.

[0247] It should also be understood that the term “and / or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The term “and / or” is a descriptive term of association between items, and means that there can be three relationships, for example, A and / or B, can mean: A exists alone, A and B exist together, B exists alone. In addition, the character “ / ” in the present application generally represents an “or” relationship between the associated objects.

[0248] It should also be understood that in various embodiments of the present application, the magnitude of the serial number of various processes does not mean the order of execution, and the execution order of various processes should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0249] It should be understood that determining B according to A does not mean that B is determined only according to A, but B can also be determined according to A and / or other information.

[0250] It should also be understood that the term “comprise” (also “comprises”, “comprising”, “includes” and / or “including”) when used in this specification specifies the presence of stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0251] It should also be understood that the term “if’ can be interpreted to mean “when” or “in response to a determination” or “in response to a detection.” Similarly, the phrase “if it is determined” or “if [a stated condition or event] is detected” can be interpreted to mean “upon a determination” or “in response to a determination” or “upon detecting [a stated condition or event]” or “in response to detecting [a stated condition or event]”.

[0252] It is to be understood that the terminology "one embodiment", "an embodiment", "one possible implementation", "possible implementation", mentioned throughout this specification can refer to a possible implementation where, in terms of this description, including a description of possible implementations of the application's components, certain features, structures, or characteristics as described are included in at least one implementation of the application. Therefore, these particular features, structures, or characteristics are not necessarily included in all implementations of the application, however, they can be included in one or more implementations of the application.

Claims

1. A method for codeword synchronization, characterized in that, the method includes: Step 1, receiving a data sequence, where the data sequence includes multiple bits; Step 2, determining candidate bits in the data sequence, where the candidate bits are included in the multiple bits; Step 3, determining a synchronization position according to the candidate bits, where the synchronization position is used to indicate the starting position of the codeword in the data sequence.

2. The method according to claim 1, characterized in that, Step 3 includes: Verifying the candidate bits, and when the verification is successful, determining the position of the candidate bits as the synchronization position.

3. The method according to claim 2, characterized in that, Step 3 includes: Dividing at least one second test data block in the data sequence according to the candidate bits, where the position of the candidate bits is the starting position of the at least one second test data block; Verifying the characteristic value of the at least one second test data block, and when the verification is successful, determining the position of the candidate bits as the synchronization position.

4. The method according to claim 3, characterized in that, Verifying the characteristic value of the at least one second test data block includes: Successively accumulating the characteristic values of each second test data block in the at least one second test data block to obtain an accumulated value, and when the accumulated value meets the synchronization condition, the verification is successful.

5. The method according to claim 4, characterized in that, The characteristic value is the number of second test data blocks determined to be correct codewords, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold; Or The characteristic value is the number of all-zero sequences in the check sequence, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold; Or, The characteristic value is the number of zero elements in the check sequence, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold; Or, The characteristic value is the number of correctable test data blocks, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold; Or, The characteristic value is the number of test data blocks with the re-verification bit being the same as the original check bit, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold; Wherein, the length of the test data block is n bits, the first k bits of the test data block are information bits, the last n-k bits of the test data block are the original check bits, the re-verification bit is obtained according to the information bits, the length of the re-verification bit is n-k bits, and the n and the k are integers.

6. The method according to claim 3, characterized in that, Verifying the characteristic value of the at least one second test data block includes: Adding up the characteristic values of all second test data blocks in the at least one second test data block to obtain a total value, and when the total value meets the synchronization condition, the verification is successful.

7. The method according to claim 6, characterized in that, The characteristic value is the number of test data blocks determined to be correct codewords among all the second test data blocks, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold; Or The characteristic value is the number of test data blocks determined as error codewords among all the second test data blocks, and the synchronization condition is that the cumulative value is less than or equal to the synchronization threshold; Or The characteristic value is the number of all-zero sequences in the check sequence, and the synchronization condition is that the total value is greater than or equal to the synchronization threshold; Or, The characteristic value is the number of non-all-zero sequences in the check sequence, and the synchronization condition is that the total value is less than or equal to the synchronization threshold; Or, The characteristic value is the number of zero elements in the check sequence, and the synchronization condition is that the total value is greater than or equal to the synchronization threshold; Or, The characteristic value is the number of non-zero elements in the check sequence, and the synchronization condition is that the total value is less than or equal to the synchronization threshold; Or, The characteristic value is the number of test data blocks that can be error-corrected, and the synchronization condition is that the total value is greater than or equal to the synchronization threshold; Or, The characteristic value is the number of test data blocks that cannot be error-corrected, and the synchronization condition is that the total value is less than or equal to the synchronization threshold; Or, The characteristic value is the number of test data blocks in which the recheck bits are the same as the original check bits, and the synchronization condition is that the total value is greater than or equal to the synchronization threshold; Or, The characteristic value is the number of test data blocks in which the recheck bits are different from the original check bits, and the synchronization condition is that the total value is less than or equal to the synchronization threshold; Wherein, the length of the test data block is n bits, the first k bits of the test data block are information bits, the last n - k bits of the test data block are the original check bits, the recheck bits are obtained according to the information bits, the length of the recheck bits is n - k bits, and n and k are integers.

8. The method according to claim 1, wherein, Step three includes: Taking the position of the alternative bit as the synchronization position.

9. The method according to claim 1, wherein, Step two includes: Selecting a plurality of observed bits from the data sequence; Selecting the alternative bit from the plurality of observed bits.

10. The method according to claim 9, wherein, The selecting the alternative bit from the plurality of observed bits includes: Determining multiple groups of first test data blocks from the data sequence according to the plurality of observed bits, wherein each group of first test data blocks in the multiple groups of first test data blocks includes at least one first test data block, and the position of each observed bit in the plurality of observed bits is the starting position of each group of first test data blocks in the multiple groups of first test data blocks; Selecting one observed bit from the plurality of observed bits as the alternative bit according to the characteristic values of the multiple groups of first test data blocks.

11. The method according to claim 10, wherein, wherein, The selecting one observed bit from the plurality of observed bits as the alternative bit according to the characteristic values of the multiple groups of first test data blocks includes: Sequentially determining whether the characteristic values of each group of first test data blocks in the multiple groups of first test data blocks meet the alternative condition until it is determined that the characteristic value of a group of first test data blocks meets the alternative condition; Use the observed bits corresponding to the set of first test data blocks that meet the alternative condition as the alternative bits.

12. The method according to claim 11, wherein, the characteristic value of the set of first test data blocks is the total value of the number of first test data blocks determined to be correct codewords in the set of first test data blocks, and the alternative condition is that the cumulative value is greater than or equal to the synchronization threshold; or the characteristic value of the set of first test data blocks is the total value of the number of first test data blocks determined to be correct codewords in the set of first test data blocks, and the alternative condition is that the cumulative value is less than or equal to the synchronization threshold; or the characteristic value of the set of first test data blocks is the total value of the number of all-zero sequences in the check sequences of all first test data blocks in the set of first test data blocks, and the alternative condition is that the total value is greater than or equal to the synchronization threshold; or, the characteristic value of the set of first test data blocks is the total value of the number of non-all-zero sequences in the check sequences of all first test data blocks in the set of first test data blocks, and the alternative condition is that the total value is less than or equal to the synchronization threshold; or, the characteristic value of the set of first test data blocks is the total value of the number of zero elements in the check sequences of all first test data blocks in the set of first test data blocks, and the alternative condition is that the total value is greater than or equal to the synchronization threshold; or, the characteristic value of the set of first test data blocks is the total value of the number of non-zero elements in the check sequences of all first test data blocks in the set of first test data blocks, and the alternative condition is that the total value is less than or equal to the synchronization threshold; or, the characteristic value of the set of first test data blocks is the total value of the number of correctable test data blocks in all first test data blocks in the set of first test data blocks, and the alternative condition is that the total value is greater than or equal to the synchronization threshold; or, the characteristic value of the set of first test data blocks is the total value of the number of uncorrectable test data blocks in all first test data blocks in the set of first test data blocks, and the alternative condition is that the total value is less than or equal to the synchronization threshold; or, the characteristic value of the set of first test data blocks is the total value of the number of test data blocks in which the re-check bits are the same as the original check bits in all first test data blocks in the set of first test data blocks, and the alternative condition is that the total value is greater than or equal to the synchronization threshold; or, the characteristic value of the set of first test data blocks is the total value of the number of test data blocks in which the re-check bits are different from the original check bits in all first test data blocks in the set of first test data blocks, and the alternative condition is that the total value is less than or equal to the synchronization threshold; or, the characteristic value of the set of first test data blocks is the cumulative value of the number of all-zero sequences in the check sequences of the first X first test data blocks in the set of first test data blocks, and the alternative condition is that the cumulative value is greater than or equal to the synchronization threshold; or, the characteristic value of the set of first test data blocks is the cumulative value of the number of zero elements in the check sequences of the first X first test data blocks in the set of first test data blocks, and the alternative condition is that the cumulative value is greater than or equal to the synchronization threshold; Alternatively, the characteristic value of the set of first test data blocks is the cumulative value of the number of correctable test data blocks in the first X first test data blocks in the set of first test data blocks, and the alternative condition is that the cumulative value is greater than or equal to the synchronization threshold; Alternatively, the characteristic value of the set of first test data blocks is the cumulative value of the number of test data blocks in the first X first test data blocks in the set of first test data blocks where the recheck bit is the same as the original check bit, and the alternative condition is that the cumulative value is greater than or equal to the synchronization threshold; wherein, the length of the test data block is n bits, the first k bits of the test data block are information bits, the last n - k bits of the test data block are the original check bits, the recheck bit is obtained according to the information bits, the length of the recheck bit is n - k bits, and n, k, and X are all integers.

13. The method according to claim 10, wherein, wherein, selecting one observation bit from the plurality of observation bits according to the characteristic value of the multiple sets of first test data blocks includes: comparing the characteristic values of each set of first test data blocks in the multiple sets of first test data blocks, and taking the observation bit corresponding to the set of first test data blocks with the extreme characteristic value as the alternative bit.

14. The method according to claim 13, wherein, the characteristic value is the number of first test data blocks determined to be correct codewords, and the extreme value is the maximum value; or the characteristic value is the number of first test data blocks determined to be incorrect codewords, and the extreme value is the minimum value; or the characteristic value is the number of all-zero sequences in the check sequence, and the extreme value is the maximum value; or, the characteristic value is the number of non-all-zero sequences in the check sequence, and the extreme value is the minimum value; or, the characteristic value is the number of zero elements in the check sequence, and the extreme value is the maximum value; or, the characteristic value is the number of non-zero elements in the check sequence, and the extreme value is the minimum value; or, the characteristic value is the number of correctable test data blocks, and the extreme value is the maximum value; or, the characteristic value is the number of uncorrectable test data blocks, and the extreme value is the minimum value; or, the characteristic value is the number of test data blocks where the recheck bit is the same as the original check bit, and the extreme value is the maximum value; or, the characteristic value is the number of test data blocks where the recheck bit is different from the original check bit, and the extreme value is the minimum value; wherein, the length of the test data block is n bits, the first k bits of the test data block are information bits, the last n - k bits of the test data block are the original check bits, the recheck bit is obtained according to the information bits, the length of the recheck bit is n - k bits, and n and k are integers.

15. The method according to any one of claims 9 - 14, wherein, wherein, selecting a plurality of observation bits from the data sequence includes: selecting one bit every T bits from the data sequence as the observation bit, where T is an integer greater than zero; or, Select one bit every L*n+T bits from the data sequence as the observation bit, where L is the number of test data blocks at intervals, the length of the test data block is n bits, and L and T are positive integers greater than zero.

16. The method according to any one of claims 9-14, characterized in that, the data sequence is a modulation signal, and the data sequence includes a plurality of modulation symbols, wherein, selecting a plurality of observation bits from the data sequence includes: selecting the starting bit of the modulation symbol every T modulation symbols from the data sequence as the observation bit, where T is a positive integer greater than zero; or, selecting the starting bit of the modulation symbol every L*m+T modulation symbols from the data sequence as the observation bit, where L is the number of test data blocks at intervals, the length of the test data block is m modulation symbols, and L and T are positive integers greater than zero.

17. The method according to any one of claims 9-16, characterized in that, the number of the observation bits is P, P is a positive integer, and the length of the codeword is P bits.

18. The method according to any one of claims 3-7, characterized in that, wherein, in step two, determining the candidate bits in the data sequence includes determining the candidate bits in the first subsequence. In step three, dividing at least one second test data block in the data sequence according to the candidate bits includes dividing at least one second test data block in the second subsequence according to the candidate bits. The first subsequence and the second subsequence are included in the data sequence, and the second subsequence is the same as, partially the same as, or different from the first subsequence.

19. The method according to any one of claims 1-18, characterized in that, after step three, the method further includes: step four, in response to the data sequence being in a loss-of-lock state, determining the update synchronization position of the data sequence.

20. The method according to claim 19, characterized in that, wherein, determining the update synchronization position of the data sequence includes: re-executing step two and step three, and using the synchronization position determined by the re-executed step three as the update synchronization position.

21. The method according to claim 19 or 20, characterized in that, wherein, after step three and before step four, the method further includes: dividing a plurality of synchronization codewords from the data sequence according to the synchronization position, and the synchronization position is the starting position of the plurality of synchronization codewords; verifying the characteristic values of the plurality of synchronization codewords, and when the verification fails, determining that the data sequence is in the loss-of-lock state.

22. The method according to claim 21, characterized in that, verifying the characteristic values of the plurality of synchronization codewords includes: accumulating the characteristic values of each synchronization codeword in the plurality of synchronization codewords in sequence to obtain an accumulated value, and when the accumulated value meets the loss-of-lock condition, the verification fails.

23. The method according to claim 22, characterized in that, The characteristic value is the number of error codewords determined among the multiple synchronization codewords, and the out-of-lock condition is that the cumulative value is greater than or equal to the synchronization threshold; Or The characteristic value is the number of non-all-zero sequences in the check sequence, and the out-of-lock condition is that the cumulative value is greater than or equal to the synchronization threshold; Or, The characteristic value is the number of non-zero elements in the check sequence, and the out-of-lock condition is that the cumulative value is greater than or equal to the synchronization threshold; Or, The characteristic value is the number of non-correctable codewords, and the out-of-lock condition is that the cumulative value is greater than or equal to the synchronization threshold; Or, The characteristic value is the number of codewords with the re-check bits different from the original check bits, and the out-of-lock condition is that the cumulative value is greater than or equal to the synchronization threshold; Wherein, the length of the codeword is n bits, the first k bits of the codeword are information bits, the last n - k bits of the codeword are the original check bits, the re-check bits are obtained according to the information bits, the length of the re-check bits is n - k bits, and the n and the k are integers.

24. The method according to claim 21, characterized in that verifying the characteristic values of the multiple synchronization codewords includes: Adding up the characteristic values of all the synchronization codewords among the multiple synchronization codewords to obtain a total value, and when the total value meets the out-of-lock condition, the verification fails.

25. The method according to claim 24, characterized in that The total characteristic value is the total number of error codewords determined among the multiple synchronization codewords, and the out-of-lock condition is that the total value is greater than or equal to the synchronization threshold; Or The total characteristic value is the total number of correct codewords determined among the multiple synchronization codewords, and the out-of-lock condition is that the total value is less than or equal to the synchronization threshold; or the characteristic value is the number of all-zero sequences in the check sequence, and the out-of-lock condition is that the total value is less than or equal to the synchronization threshold; Or, The characteristic value is the number of non-all-zero sequences in the check sequence, and the out-of-lock condition is that the total value is greater than or equal to the synchronization threshold; Or, The characteristic value is the number of zero elements in the check sequence, and the out-of-lock condition is that the total value is less than or equal to the synchronization threshold; Or, The characteristic value is the number of non-zero elements in the check sequence, and the out-of-lock condition is that the total value is greater than or equal to the synchronization threshold; Or, The characteristic value is the number of correctable codewords, and the out-of-lock condition is that the total value is less than or equal to the synchronization threshold; Or, The characteristic value is the number of non-correctable codewords, and the out-of-lock condition is that the total value is greater than or equal to the synchronization threshold; Or, The characteristic value is the number of codewords with the re-check bits the same as the original check bits, and the out-of-lock condition is that the total value is less than or equal to the synchronization threshold; Or, The characteristic value is the number of codewords with the re-check bits different from the original check bits, and the out-of-lock condition is that the total value is greater than or equal to the synchronization threshold; Wherein, the length of the codeword is n bits, the first k bits of the codeword are information bits, the last n - k bits of the codeword are the original check bits, the re-check bits are obtained according to the information bits, the length of the re-check bits is n - k bits, and the n and the k are integers.

26. The method according to any one of claims 1-25, characterized in that, the data sequence is a linear block code.

27. A communication device, characterized in that, the communication device includes: a receiving unit, configured to perform step one: receiving a data sequence, the data sequence including a plurality of bits; a processing unit, configured to perform step two: determining alternative bits in the data sequence, the alternative bits being included in the plurality of bits; and step three: determining a synchronization position according to the alternative bits, the synchronization position being used to indicate a starting position of a codeword in the data sequence.

28. The communication device according to claim 27, characterized in that, the processing unit is further configured to verify the alternative bits, and when the verification is successful, determine the position of the alternative bits as the synchronization position.

29. The communication device according to claim 28, characterized in that, the processing unit is further configured to divide at least one second test data block in the data sequence according to the alternative bits, the position of the alternative bits being a starting position of the at least one second test data block; verifying a characteristic value of the at least one second test data block, and when the verification is successful, determining the position of the alternative bits as the synchronization position.

30. The communication device according to claim 29, characterized in that, the processing unit is further configured to sequentially accumulate the characteristic values of the respective second test data blocks in the at least one second test data block to obtain an accumulated value, and when the accumulated value meets a synchronization condition, the verification is successful.

31. The communication device according to claim 30, characterized in that, the characteristic value is the number of second test data blocks determined to be correct codewords, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold; or the characteristic value is the number of all-zero sequences in a check sequence, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of zero elements in a check sequence, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of correctable test data blocks, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of test data blocks in which a re-verification bit is the same as an original check bit, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold; wherein, the length of the test data block is n bits, the first k bits of the test data block are information bits, the last n-k bits of the test data block are the original check bits, the re-verification bit is obtained according to the information bits, the length of the re-verification bit is n-k bits, and the n and the k are integers.

32. The communication device according to claim 29, characterized in that, the processing unit is further configured to add up the characteristic values of all the second test data blocks in the at least one second test data block to obtain a total value, and when the total value meets a synchronization condition, the verification is successful.

33. The communication device according to claim 32, characterized in that, The characteristic value is the number of test data blocks determined to be correct codewords among all the second test data blocks, and the synchronization condition is that the cumulative value is greater than or equal to the synchronization threshold; Or The characteristic value is the number of test data blocks determined to be incorrect codewords among all the second test data blocks, and the synchronization condition is that the cumulative value is less than or equal to the synchronization threshold; Or The characteristic value is the number of all-zero sequences in the check sequence, and the synchronization condition is that the total value is greater than or equal to the synchronization threshold; Or, The characteristic value is the number of non-all-zero sequences in the check sequence, and the synchronization condition is that the total value is less than or equal to the synchronization threshold; Or, The characteristic value is the number of zero elements in the check sequence, and the synchronization condition is that the total value is greater than or equal to the synchronization threshold; Or, The characteristic value is the number of non-zero elements in the check sequence, and the synchronization condition is that the total value is less than or equal to the synchronization threshold; Or, The characteristic value is the number of test data blocks that can be error-corrected, and the synchronization condition is that the total value is greater than or equal to the synchronization threshold; Or, The characteristic value is the number of test data blocks that cannot be error-corrected, and the synchronization condition is that the total value is less than or equal to the synchronization threshold; Or, The characteristic value is the number of test data blocks in which the re-check bits are the same as the original check bits, and the synchronization condition is that the total value is greater than or equal to the synchronization threshold; Or, The characteristic value is the number of test data blocks in which the re-check bits are different from the original check bits, and the synchronization condition is that the total value is less than or equal to the synchronization threshold; Wherein, the length of the test data block is n bits, the first k bits of the test data block are information bits, the last n - k bits of the test data block are the original check bits, the re-check bits are obtained according to the information bits, the length of the re-check bits is n - k bits, and n and k are integers.

34. The communication device according to claim 27, wherein, the processing unit is further configured to use the position of the alternative bit as the synchronization position.

35. The communication device according to claim 27, wherein, the processing unit is further configured to select a plurality of observed bits from the data sequence; and select the alternative bit from the plurality of observed bits.

36. The communication device according to claim 35, wherein, the processing unit is further configured to determine multiple groups of first test data blocks from the data sequence according to the plurality of observed bits, wherein each group of first test data blocks in the multiple groups of first test data blocks includes at least one first test data block, and the position of each observed bit in the plurality of observed bits is the starting position of each group of first test data blocks in the multiple groups of first test data blocks; and select one observed bit from the plurality of observed bits as the alternative bit according to the characteristic values of the multiple groups of first test data blocks.

37. The communication device according to claim 36, wherein, wherein, The processing unit is further configured to sequentially determine whether the characteristic values of each group of first test data blocks in the multiple groups of first test data blocks meet the alternative condition until it is determined that the characteristic value of a group of first test data blocks meets the alternative condition; and use the observed bits corresponding to the group of first test data blocks that meet the alternative condition as the alternative bits.

38. The communication device according to claim 37, wherein, the characteristic value of the group of first test data blocks is the total value of the number of first test data blocks determined to be correct codewords in the group of first test data blocks, and the alternative condition is that the cumulative value is greater than or equal to the synchronization threshold; or the characteristic value of the group of first test data blocks is the total value of the number of first test data blocks determined to be correct codewords in the group of first test data blocks, and the alternative condition is that the cumulative value is less than or equal to the synchronization threshold; or the characteristic value of the group of first test data blocks is the total value of the number of all-zero sequences in the check sequences of all first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is greater than or equal to the synchronization threshold; or, the characteristic value of the group of first test data blocks is the total value of the number of non-all-zero sequences in the check sequences of all first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is less than or equal to the synchronization threshold; or, the characteristic value of the group of first test data blocks is the total value of the number of zero elements in the check sequences of all first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is greater than or equal to the synchronization threshold; or, the characteristic value of the group of first test data blocks is the total value of the number of non-zero elements in the check sequences of all first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is less than or equal to the synchronization threshold; or, the characteristic value of the group of first test data blocks is the total value of the number of correctable test data blocks in all first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is greater than or equal to the synchronization threshold; or, the characteristic value of the group of first test data blocks is the total value of the number of uncorrectable test data blocks in all first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is less than or equal to the synchronization threshold; or, the characteristic value of the group of first test data blocks is the total value of the number of test data blocks in all first test data blocks in the group of first test data blocks where the re-check bits are the same as the original check bits, and the alternative condition is that the total value is greater than or equal to the synchronization threshold; or, the characteristic value of the group of first test data blocks is the total value of the number of test data blocks in all first test data blocks in the group of first test data blocks where the re-check bits are different from the original check bits, and the alternative condition is that the total value is less than or equal to the synchronization threshold; or, the characteristic value of the group of first test data blocks is the cumulative value of the number of all-zero sequences in the check sequences of the first X first test data blocks in the group of first test data blocks, and the alternative condition is that the cumulative value is greater than or equal to the synchronization threshold; or, The characteristic value of the set of first test data blocks is the cumulative value of the number of zero elements in the check sequences of the first X first test data blocks in the set of first test data blocks, and the alternative condition is that the cumulative value is greater than or equal to the synchronization threshold; Or, The characteristic value of the set of first test data blocks is the cumulative value of the number of correctable test data blocks in the first X first test data blocks in the set of first test data blocks, and the alternative condition is that the cumulative value is greater than or equal to the synchronization threshold; Or, The characteristic value of the set of first test data blocks is the cumulative value of the number of test data blocks in the first X first test data blocks in the set of first test data blocks where the recheck bits are the same as the original check bits, and the alternative condition is that the cumulative value is greater than or equal to the synchronization threshold; Wherein, the length of the test data block is n bits, the first k bits of the test data block are information bits, the last n - k bits of the test data block are the original check bits, the recheck bits are obtained according to the information bits, the length of the recheck bits is n - k bits, and n, k, and X are integers.

39. The communication device according to claim 36, Characterized in that, The processing unit is further configured to compare the characteristic values of each set of first test data blocks in the multiple sets of first test data blocks, and use the observation bits corresponding to the set of first test data blocks with the extreme value of the characteristic value as the alternative bits.

40. The communication device according to claim 39, Characterized in that, The characteristic value is the number of first test data blocks determined to be correct codewords, and the extreme value is the maximum value; or, The characteristic value is the number of first test data blocks determined to be incorrect codewords, and the extreme value is the minimum value; or, The characteristic value is the number of all-zero sequences in the check sequence, and the extreme value is the maximum value; or, The characteristic value is the number of non-all-zero sequences in the check sequence, and the extreme value is the minimum value; or, The characteristic value is the number of zero elements in the check sequence, and the extreme value is the maximum value; or, The characteristic value is the number of non-zero elements in the check sequence, and the extreme value is the minimum value; or, The characteristic value is the number of correctable test data blocks, and the extreme value is the maximum value; or, The characteristic value is the number of uncorrectable test data blocks, and the extreme value is the minimum value; or, The characteristic value is the number of test data blocks where the recheck bits are the same as the original check bits, and the extreme value is the maximum value; or, The characteristic value is the number of test data blocks where the recheck bits are different from the original check bits, and the extreme value is the minimum value; Wherein, the length of the test data block is n bits, the first k bits of the test data block are information bits, the last n - k bits of the test data block are the original check bits, the recheck bits are obtained according to the information bits, the length of the recheck bits is n - k bits, and n and k are integers.

41. The communication device according to any one of claims 35 - 40, Characterized in that, The processing unit is further configured to select one bit every T bits from the data sequence as the observed bit, where T is an integer greater than zero; or, The processing unit is further configured to select one bit every L*n + T bits from the data sequence as the observed bit, where L is the number of spaced test data blocks, the length of the test data block is n bits, and L and T are integers greater than zero.

42. The communication device according to any one of claims 35-40, wherein, The processing unit is further configured to select the starting bit of the modulation symbol every T modulation symbols from the data sequence as the observed bit, where T is an integer greater than zero; or, The processing unit is further configured to select the starting bit of the modulation symbol every L*m + T modulation symbols from the data sequence as the observed bit, where L is the number of spaced test data blocks, the length of the test data block is m modulation symbols, and L and T are integers greater than zero.

43. The communication device according to any one of claims 35-42, wherein, The number of the observed bits is P, P is a positive integer, and the length of the codeword is P bits.

44. The communication device according to any one of claims 29-33, wherein, wherein, In step two, determining the candidate bits in the data sequence includes determining the candidate bits in the first subsequence. In step three, dividing at least one second test data block in the data sequence according to the candidate bits includes dividing at least one second test data block in the second subsequence according to the candidate bits. The first subsequence and the second subsequence are included in the data sequence, and the second subsequence is the same as, partially the same as, or different from the first subsequence.

45. The communication device according to any one of claims 27-44, wherein, The processing unit is further configured to execute step four: in response to the data sequence being in a loss-of-lock state, determine the updated synchronization position of the data sequence.

46. The communication device according to claim 45, wherein, The processing unit is further configured to re-execute step two and step three, and use the synchronization position determined by the re-executed step three as the updated synchronization position.

47. The communication device according to claim 45 or 46, wherein, The processing unit is further configured to divide a plurality of synchronization codewords from the data sequence according to the synchronization position, where the synchronization position is the starting position of the plurality of synchronization codewords; verify the characteristic values of the plurality of synchronization codewords, and when the verification fails, determine that the data sequence is in the loss-of-lock state.

48. The communication device according to claim 47, wherein, The processing unit is further configured to sequentially accumulate the characteristic values of each of the plurality of synchronization codewords to obtain an accumulated value, and when the accumulated value satisfies the loss-of-lock condition, the verification fails.

49. The communication device according to claim 48, It is characterized in that the cumulative value of the characteristic values is the total number of error codewords determined among the multiple synchronization codewords, and the out-of-lock condition is that the cumulative value is greater than or equal to the synchronization threshold; or the characteristic value is the number of non-all-zero sequences in the check sequence, and the out-of-lock condition is that the cumulative value is greater than or equal to the synchronization threshold; or the characteristic value is the number of non-zero elements in the check sequence, and the out-of-lock condition is that the cumulative value is greater than or equal to the synchronization threshold; or the characteristic value is the number of non-correctable codewords, and the out-of-lock condition is that the cumulative value is greater than or equal to the synchronization threshold; or the characteristic value is the number of codewords with the re-check bits different from the original check bits, and the out-of-lock condition is that the cumulative value is greater than or equal to the synchronization threshold; wherein, the length of the codeword is n bits, the first k bits of the codeword are information bits, the last n-k bits of the codeword are the original check bits, the re-check bits are obtained according to the information bits, the length of the re-check bits is n-k bits, and the n and the k are integers.

50. The communication device according to claim 47, it is characterized in that the processing unit is further configured to add up the characteristic values of all the synchronization codewords among the multiple synchronization codewords to obtain a total value, and when the total value meets the out-of-lock condition, the verification fails.

51. The communication device according to claim 50, it is characterized in that the total value of the characteristic values is the total number of correct codewords determined among the multiple synchronization codewords, and the out-of-lock condition is that the total value is less than or equal to the synchronization threshold; or the total value of the characteristic values is the total number of error codewords determined among the multiple synchronization codewords, and the out-of-lock condition is that the total value is greater than or equal to the synchronization threshold; or the characteristic value is the number of all-zero sequences in the check sequence, and the out-of-lock condition is that the total value is less than or equal to the synchronization threshold; or the characteristic value is the number of non-all-zero sequences in the check sequence, and the out-of-lock condition is that the total value is greater than or equal to the synchronization threshold; or the characteristic value is the number of zero elements in the check sequence, and the out-of-lock condition is that the total value is less than or equal to the synchronization threshold; or the characteristic value is the number of non-zero elements in the check sequence, and the out-of-lock condition is that the total value is greater than or equal to the synchronization threshold; or the characteristic value is the number of correctable codewords, and the out-of-lock condition is that the total value is less than or equal to the synchronization threshold; or the characteristic value is the number of non-correctable codewords, and the out-of-lock condition is that the total value is greater than or equal to the synchronization threshold; or the characteristic value is the number of codewords with the re-check bits the same as the original check bits, and the out-of-lock condition is that the total value is less than or equal to the synchronization threshold; or the characteristic value is the number of codewords with the re-check bits different from the original check bits, and the out-of-lock condition is that the total value is greater than or equal to the synchronization threshold; wherein, the length of the codeword is n bits, the first k bits of the codeword are information bits, the last n-k bits of the codeword are the original check bits, the re-check bits are obtained according to the information bits, the length of the re-check bits is n-k bits, and the n and the k are integers.

52. The communication device according to any one of claims 27-51, characterized in that, the data sequence is a linear block code.

53. A communication device, characterized in that, the communication device comprises: a processor, a communication interface and a memory, the memory can be used to store program codes, and the processor is used to call the program codes in the memory to execute the method according to any one of claims 1-26.

54. A chip, characterized in that, the chip comprises a memory and a processor, the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory to execute the method according to any one of claims 1-26.

55. A computer-readable storage medium, characterized in that, a computer program is stored in the computer-readable storage medium, and when the computer program runs on a processor, the method according to any one of claims 1-26 is implemented.

56. A network system, characterized in that, the network system comprises a sending device and a receiving device, and the receiving device is the communication device according to any one of claims 27-53.

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