The multi-layered single-core central processor integrates an adaptive clock-based on-demand controller and corresponding control methods.

Abstract

The invention relates to a hardware system of a single-core, multi-stage (pipeline) central processing unit (CPU) incorporating an adaptive clock switching controller using an artificial intelligence model and corresponding control method to reduce the dynamic power consumption of the processor. The system comprises: (i) an adaptive clock switching controller configured to collect the processor's operating state, perform inference using an artificial intelligence model, and generate clock switching control signals; (ii) a system of control registers storing the clock switching state of each processing stage or group of registers; and (iii) a system of storage elements including pipeline registers, data registers, instruction registers, and buffers, which are fed secondary clock signals according to the control state.The control method includes steps such as initializing the artificial intelligence model, collecting the system's operating state, decoding instructions, generating input data for the AI ​​model, performing inference to predict the operational needs of the processing layers, updating control registers, and distributing secondary clock signals to the corresponding storage elements. Thanks to the adaptive clock switching control mechanism based on the inference results of the AI ​​model, the invention reduces unnecessary register switching operations, thereby reducing the dynamic power consumption of the processor while ensuring the performance and accuracy of the processing.

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