HARDWARE-BASED SECURITY MONITORING SYSTEM WITH HIERARCHICAL SECURITY CHIPS

Abstract

The hierarchical hardware security monitoring system for the security chip, as described in the invention, comprises: a hierarchical monitoring block 100, an alarm processor 200, an escalation state machine 300, an output control block 400, a trusted boot block 500, a key derivation block 600, and an OTP configuration register 700. These blocks are interconnected via internal signal buses and perform the functions of monitoring the operation of a processing block of the security chip, verifying the operational status of an external system, detecting abnormal physical conditions of the security chip, and executing a hardware security response upon detecting an abnormal event.

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