Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate comprises: a base (10) and a plurality of sub-pixels provided on the base (10), wherein at least one sub-pixel comprises a pixel circuit, which comprises a third transistor (T3) and a plurality of transistors connected to the third transistor (T3); active patterns of at least two transistors connected to a gate electrode of the third transistor (T3) are first active layers (A1); active patterns of at least two transistors connected to any one of a first electrode and a second electrode of the third transistor (T3) and an active layer of the third transistor (T3) are second active layers (A2); the first active layers (A1) and the second active layers (A2) are arranged in a first direction (D1) and at least partially extend in a second direction (D2); and the length of the first active layers (A1) in the second direction (D2) is greater than the length of the second active layers (A2) in the second direction (D2).

Description

Display substrate and display device Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and specifically to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, this disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels disposed on the substrate, at least one sub-pixel comprising: a pixel circuit, the pixel circuit comprising: a third transistor and a plurality of transistors connected to the third transistor, the transistors comprising active patterns, the active patterns of at least two transistors connected to the gate electrode of the third transistor being an integral structure and forming a first active layer, the active patterns of at least two transistors connected to either the first or second electrode of the third transistor and the active pattern of the third transistor being an integral structure and forming a second active layer;

[0006] The first active layer and the second active layer are arranged along a first direction and extend at least partially along a second direction, wherein the first direction intersects the second direction;

[0007] The length of the first active layer along the second direction is greater than the length of the second active layer along the second direction.

[0008] In an exemplary embodiment, the plurality of transistors connected to the third transistor include: a first transistor, a second transistor, a fourth transistor, and a fifth transistor, wherein the first transistor to the fifth transistor are N-type transistors;

[0009] The second terminal of the first transistor is electrically connected to the second terminal of the third transistor, the second terminals of the second transistor and the second terminals of the fourth transistor are respectively electrically connected to the gate electrode of the third transistor, and the second terminal of the fifth transistor is electrically connected to the first terminal of the third transistor;

[0010] The active pattern includes a channel region and a conductive region, with the conductive region of any active pattern located on both sides of the channel region; wherein, the active patterns of the second transistor and the fourth transistor constitute a first active layer, and the active patterns of the first transistor, the third transistor, and the fifth transistor constitute a second active layer.

[0011] In an exemplary embodiment, the active patterns of the first transistor and the fifth transistor are located on opposite sides of the active pattern of the third transistor. The active pattern of the second transistor includes a first conductive region and a second conductive region. The active pattern of the fourth transistor includes a third conductive region and a fourth conductive region. The first conductive region and the third conductive region extend along a second direction, and the second conductive region and the fourth conductive region extend along a first direction. The third conductive region is connected to the first conductive region.

[0012] In an exemplary embodiment, the second conductive region is located on the side of the first conductive region close to the second active layer, and at least a portion of the active pattern of the first transistor is located on the side of the active layer centerline, which is the centerline of the second active layer extending along the first direction.

[0013] The fourth conductive region is located on the side of the third conductive region near the second active layer, and is located on the other side of the active layer centerline along with at least a portion of the active pattern of the fifth transistor.

[0014] In an exemplary embodiment, it further includes: a first signal line disposed on the substrate, at least a portion of the first signal line extending along a first direction, and the gate electrode of at least one transistor being disposed on a different layer from the first signal line;

[0015] The resistivity of the film layer containing the first signal line is less than the resistivity of the film layer containing the gate electrode of the at least one transistor.

[0016] In an exemplary embodiment, the gate electrode of the first transistor is spaced apart from the gate electrode of the fifth transistor;

[0017] The length of the gate electrode of the third transistor along the second direction is greater than the length of the gate electrode of any one of the first transistor, the second transistor, the fourth transistor, and the fifth transistor along the second direction.

[0018] In an exemplary embodiment, the pixel circuit further includes a capacitor, the capacitor including a first plate and a second plate; the first plate of the capacitor is located on the side of the second plate of the capacitor closer to the substrate;

[0019] The orthographic projection of the first plate of the capacitor onto the substrate at least partially overlaps with the first conductive region, the active pattern of the third transistor, and the orthographic projection of the third conductive region onto the substrate.

[0020] In an exemplary embodiment, the first signal line includes: a third scan signal line, an initial signal line, a first power supply line, and a light emission signal line; the first transistor is connected to the third scan signal line and the initial signal line respectively, and the fifth transistor is connected to the first power supply line and the light emission signal line respectively;

[0021] The orthographic projection of the second plate of the capacitor onto the substrate at least partially overlaps with the orthographic projections of the third scanning signal line, the initial signal line, the first power line, the light-emitting signal line, the first plate of the capacitor, the first conductive region, and the third conductive region onto the substrate.

[0022] In an exemplary embodiment, along the second direction, the distance between the orthographic projection of the gate electrode of the second transistor on the substrate and the orthographic projection of the second plate of the capacitor on the substrate is less than the distance between the orthographic projection of the gate electrode of the second transistor on the substrate and the orthographic projection of the gate electrode of the first transistor on the substrate.

[0023] The distance between the orthogonal projection of the gate electrode of the fourth transistor onto the substrate and the orthogonal projection of the second plate of the capacitor onto the substrate is less than the distance between the orthogonal projection of the gate electrode of the fourth transistor onto the substrate and the orthogonal projection of the gate electrode of the fifth transistor onto the substrate.

[0024] In an exemplary embodiment, the second plate of the capacitor is provided with a groove, which exposes at least a portion of the first plate, the first conductive region, and the third conductive region of the capacitor.

[0025] In an exemplary embodiment, within the same sub-pixel, the opening direction of the groove is located on the side opposite to the second active layer.

[0026] In an exemplary embodiment, the second plate of the capacitor includes: a capacitor body portion, a first capacitor connection portion, and a second capacitor connection portion, wherein the first capacitor connection portion and the second capacitor connection portion are respectively located on both sides of the capacitor body portion, and the groove is disposed on one side of the capacitor body portion;

[0027] The capacitor body extends along a first direction, the first capacitor connection portion extends at least partially along a second direction, and the second capacitor connection portion extends along a second direction.

[0028] The average length of the capacitor body portion along the first direction is greater than the average length of the first capacitor connection portion along the first direction, and the average length of the first capacitor connection portion along the first direction is greater than the average length of the second capacitor connection portion along the first direction.

[0029] In an exemplary embodiment, the orthographic projection of the capacitor body onto the substrate at least partially overlaps with the orthographic projections of the first plate, the first conductive region, and the third conductive region of the capacitor onto the substrate.

[0030] The orthographic projections of the first capacitor connection portion and the second capacitor connection portion on the substrate at least partially overlap with the orthographic projections of the first conductive region and the third conductive region on the substrate, but do not overlap with the orthographic projection of the first plate of the capacitor on the substrate.

[0031] In an exemplary embodiment, the first plate of the capacitor includes: a first region and a second region; the first region is the region exposed by the groove of the second plate of the capacitor, and the second region is all regions except the first region;

[0032] The orthographic projection of the second plate of the capacitor onto the substrate covers the orthographic projection of the second region of the first plate of the capacitor onto the substrate.

[0033] In an exemplary embodiment, the first signal line further includes: a reference signal line, a first scan signal line, and a second scan signal line, wherein the second transistor is connected to the second scan signal line and the reference signal line respectively, and the fourth transistor is connected to the first scan signal line;

[0034] The reference signal line, the second scan signal line, the initial signal line, the third scan signal line, the light emission signal line, the first power supply line, and the first scan signal line are arranged sequentially along the first direction.

[0035] In an exemplary embodiment, it further includes: a second signal line disposed on the substrate, the second signal line extending along a second direction, the second signal line including: a data signal line;

[0036] The orthographic projection of the data signal line on the substrate at least partially overlaps with the orthographic projections of the first conductive region, the third conductive region, the fourth conductive region, and the second plate of the capacitor on the substrate.

[0037] In an exemplary embodiment, the data signal line includes: a data signal main line and a plurality of data signal connecting lines, wherein the data signal main line extends along a second direction and the data signal connecting lines extend along a first direction;

[0038] The orthographic projection of the main data signal line on the substrate at least partially overlaps with the orthographic projections of the first conductive region, the third conductive region, and the second plate of the capacitor on the substrate, and the orthographic projection of the data signal connection line on the substrate at least partially overlaps with the orthographic projection of the fourth conductive region on the substrate.

[0039] In an exemplary embodiment, the method further includes: a driving structure layer disposed on the substrate; the driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially stacked on the substrate;

[0040] The semiconductor layer includes at least: an active pattern of a first transistor, an active pattern of a second transistor, an active pattern of a third transistor, an active pattern of a fourth transistor, and an active pattern of a fifth transistor located at at least one sub-pixel.

[0041] The first conductive layer includes at least: a gate electrode of a first transistor, a gate electrode of a second transistor, a gate electrode of a third transistor, a gate electrode of a fourth transistor, a gate electrode of a fifth transistor, and a first plate of a capacitor located at at least one sub-pixel;

[0042] The second conductive layer includes at least: a second electrode of a capacitor located in at least one sub-pixel;

[0043] The third conductive layer includes at least: a first scan signal line, a second scan signal line, a third scan signal line, a light emission signal line, a reference signal line, a first power supply line, an initial signal line, and the second pole of a first transistor, the second pole of a second transistor, the second pole of a third transistor, and the first pole and the second pole of a fourth transistor located in at least one sub-pixel;

[0044] The fourth conductive layer includes at least: data signal lines.

[0045] In an exemplary embodiment, the driving structure layer further includes: a first planarization layer and a fifth insulating layer located between the third conductive layer and the fourth conductive layer;

[0046] The fifth insulating layer is located on the side of the first planar layer away from the substrate;

[0047] The thickness of the first planarization layer is greater than the thickness of the fifth insulating layer.

[0048] In an exemplary embodiment, the thickness of the first planarization layer is 1.4 micrometers to 2.3 micrometers, and the thickness of the fifth insulating layer is 50 nanoangstroms to 2500 nanoangstroms.

[0049] In an exemplary embodiment, the thickness of the third conductive layer is greater than the thickness of the first conductive layer or the second conductive layer;

[0050] The resistivity of the fourth conductive layer is less than that of the first conductive layer.

[0051] Secondly, this disclosure also provides a display device, including: the aforementioned display substrate.

[0052] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0053] Overview of the attached figures

[0054] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0055] Figure 1 is a schematic diagram of a display device;

[0056] Figure 2 is a schematic diagram of a planar structure of a display substrate;

[0057] Figure 3 is a schematic diagram of the planar structure of another display substrate;

[0058] Figure 4A is a schematic diagram of the equivalent circuit of a pixel circuit;

[0059] Figure 4B is the timing diagram of the pixel circuit provided in Figure 4A;

[0060] Figure 5 is a schematic diagram of the structure of the display substrate provided in an embodiment of this disclosure;

[0061] Figure 6 is a cross-sectional view of the display substrate provided in an embodiment of this disclosure;

[0062] Figure 7 is a schematic diagram of some film layers of the display substrate provided in Figure 5;

[0063] Figure 8 is a schematic diagram of a portion of the film layers of the display substrate shown in Figure 5;

[0064] Figure 9 is a schematic diagram of part of the film layers of the display substrate provided in Figure 5;

[0065] Figure 10 is a schematic diagram of part of the film layers of the display substrate shown in Figure 5;

[0066] Figure 11 is a schematic diagram after the semiconductor layer pattern has been formed;

[0067] Figure 12 is a schematic diagram of the pattern of the first conductive layer;

[0068] Figure 13 is a schematic diagram after the formation of the first conductive layer pattern;

[0069] Figure 14 is a schematic diagram of the pattern of the second conductive layer;

[0070] Figure 15 is a schematic diagram after the formation of the second conductive layer pattern;

[0071] Figure 16 is a schematic diagram after the fourth insulating layer pattern is formed;

[0072] Figure 17 is a schematic diagram of the pattern of the third conductive layer;

[0073] Figure 18 is a schematic diagram after the formation of the third conductive layer pattern;

[0074] Figure 19 is a schematic diagram after the formation of the fifth insulating layer pattern;

[0075] Figure 20 is a schematic diagram of the pattern of the fourth conductive layer;

[0076] Figure 21 is a schematic diagram after the fourth conductive layer pattern is formed.

[0077] Detailed Explanation

[0078] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0079] In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, one aspect of this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0080] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0081] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0082] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0083] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0084] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0085] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0086] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0087] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0088] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0089] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfered corners, curved edges, and other variations.

[0090] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0091] The display substrates used employ Low Temperature Poly-Silicon (LTPS) or Low Temperature Poly-Silicon+Oxide (LTPO) technology, which combines LTPS transistors with oxide transistors to form the backplane. These technologies offer advantages such as high resolution, fast response time, high brightness, and high aperture ratio, making them popular in the market. However, display products using LTPS or LTPO technology suffer from complex pixel circuit connections, a large number of gate control lines, and large electrode footprints, making it difficult to achieve high PPI and prone to leakage current.

[0092] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel circuit, which may be connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, an LED driver can sequentially provide transmit signals with cutoff level pulses to LED signal lines E1 to Eo. For example, the LED driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0093] Figure 2 is a schematic diagram of a planar structure of a display substrate, and Figure 3 is a schematic diagram of a planar structure of another display substrate. As shown in Figures 2 and 3, the display substrate may include multiple pixel units P arranged in a matrix. Each pixel unit P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and at least one third sub-pixel P3 emitting a third color light. Each of the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 includes a pixel circuit and a light-emitting device. The pixel circuits in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel circuits are configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to the pixel circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel circuit of their respective sub-pixels.

[0094] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 can be a green sub-pixel (G) emitting green light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged horizontally side by side, vertically side by side, or in a triangular arrangement; this disclosure does not limit the specific arrangement.

[0095] In an exemplary embodiment, as shown in FIG2, a pixel unit may include three sub-pixels. The three sub-pixels may be arranged horizontally side by side, vertically side by side, or in a triangular arrangement, etc., and this disclosure does not limit the arrangement. FIG2 illustrates the horizontal side by side arrangement as an example.

[0096] In an exemplary embodiment, as shown in FIG3, a pixel unit may include four sub-pixels, which may be a first sub-pixel, a second sub-pixel, and two third sub-pixels. The four sub-pixels may be arranged in a horizontally parallel, vertically parallel, or square manner, etc., and this disclosure does not limit the arrangement. FIG3 illustrates the arrangement of the four sub-pixels in a square manner as an example.

[0097] In an exemplary embodiment, the light-emitting device may be an organic light-emitting diode (OLED), including a stacked electrode (anode), an organic light-emitting layer, and a second electrode (cathode).

[0098] In an exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the hole block layers of all sub-pixels may be a common layer connected together, and the emitting layers of adjacent sub-pixels may have a small overlap or may be isolated. Similarly, the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0099] Figure 4A is an equivalent circuit diagram of a pixel circuit. In an exemplary embodiment, the pixel circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in Figure 4A, the pixel circuit may include five transistors (first transistor T1 to fifth transistor T5) and one capacitor C. The capacitor C may include a first plate C1 and a second plate C2.

[0100] In an exemplary embodiment, as shown in FIG4A, the gate electrode of the first transistor T1 is electrically connected to the third scan signal line Gate3, the first terminal of the first transistor T1 is electrically connected to the initial signal line INIT, and the second terminal of the first transistor T1 is electrically connected to the second node N2; the gate electrode of the second transistor T2 is electrically connected to the second scan signal line Gate2, the first terminal of the second transistor T2 is electrically connected to the reference signal line REF, and the second terminal of the second transistor T2 is electrically connected to the first node N1; the gate electrode of the third transistor T3 is electrically connected to the first node N1, and the first terminal of the third transistor T3 is electrically connected to the second node N2. The second electrode of the third transistor T3 is electrically connected to the third node N3; the gate electrode of the fourth transistor T4 is electrically connected to the first scan signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the first node N1; the gate electrode of the fifth transistor T5 is electrically connected to the light emission signal line EM, the first electrode of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the third node N3; the first plate C1 of the capacitor C is electrically connected to the first node N1, and the second plate C2 of the capacitor C is electrically connected to the second node N2.

[0101] In an exemplary embodiment, the light-emitting device L can be electrically connected to the second node N2 and the second power line VSS, respectively. Specifically, the first electrode of the light-emitting device L is electrically connected to the second node N2, and the second electrode of the light-emitting device L is electrically connected to the second power line VSS.

[0102] In an exemplary embodiment, the light-emitting device includes a current-driven device, which may be a current-driven light-emitting diode, such as a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum light-emitting diode (QLED). The typical size (e.g., length) of a Micro LED can be less than 100 μm, for example, 10 μm to 50 μm. The typical size (e.g., length) of a Mini LED can be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0103] In an exemplary embodiment, the first transistor T1 can be referred to as the anode reset transistor. When the signal of the third scan signal line Gate3 is an effective level signal, the initial signal of the initial signal line INIT is written into the first electrode of the light-emitting device L to initialize the first electrode of the light-emitting device L.

[0104] In an exemplary embodiment, the second transistor T2 can be referred to as the node reset transistor. When the signal of the second scan signal line Gate2 is an active level signal, the signal of the reference signal line REF is written into the first node N1 to initialize the signal of the first node N1.

[0105] In an exemplary embodiment, the third transistor T3 may be referred to as the driving transistor, which determines the driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between its gate electrode and the second electrode.

[0106] In an exemplary embodiment, the fourth transistor T4 can be referred to as the write transistor, which writes the initial signal of the data signal line Data to the second node N2 when the signal of the first scan signal line Gate1 is an active level signal.

[0107] In an exemplary embodiment, the fifth transistor T5 can be referred to as a light-emitting transistor. When the signal of the light-emitting signal line EM is at an active level, the fifth transistor T5 causes the light-emitting device to emit light by forming a drive current path between the first power line VDD and the second power line VSS.

[0108] Based on their characteristics, transistors can be classified into N-type transistors and P-type transistors. When a transistor is P-type, its turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and its turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is N-type, its turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and its turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0109] In an exemplary embodiment, the first transistor T1 to the fifth transistor T5 can be a low-temperature polysilicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both. The active layer of the LTPS is made of low-temperature polysilicon (LTPS), while the active layer of the oxide thin-film transistor is made of oxide semiconductor. LTPS transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate to form an LTPO display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0110] In an exemplary embodiment, the transistors of the first transistor T1 to the fifth transistor T5 can be N-type transistors.

[0111] In an exemplary embodiment, the first power line VDD continuously provides a high-level signal and is a constant voltage signal, the second power line VSS continuously provides a low-level signal, and the initial signal line INIT provides a constant voltage signal.

[0112] In an exemplary embodiment, the voltage value of the initial signal line INIT can be less than the voltage value of the second power line VSS, which can prevent the light-emitting device from emitting light erroneously.

[0113] Figure 4B is a timing diagram of the pixel circuit shown in Figure 4A. The following describes an exemplary embodiment of this disclosure through the operation of the pixel circuit illustrated in Figure 4A during the display stage. Figure 4B is illustrated using the example of N-type transistors T1 to T5. The pixel circuit in Figure 4B includes transistors T1 to T5, a capacitor C, and eight signal lines (data signal line Data, first scan signal line Gate1, second scan signal line Gate2, third scan signal line Gate3, initial signal line INIT, reference signal line REF, light emission signal line EM, and first power supply line VDD).

[0114] Referring to Figures 4A and 4B, the operation of the pixel circuit can include:

[0115] In the first stage, P1, called the initialization stage, the signals of the second scan signal line Gate2 and the third scan signal line Gate3 are high-level signals, while the signals of the first scan signal line Gate1 and the light emission signal line EM are low-level signals. When the signal of the second scan signal line Gate2 is high, the second transistor T2 is turned on. The signal of the reference signal line REF is written to the first node N1 through the turned-on second transistor T2 to initialize the signal of the first node N1. At this time, the voltage value of the signal of the first node N1 is V1 = V... ref V ref The voltage value of the reference signal line REF is used. The signal on the third scan signal line Gate3 is high, the first transistor T1 is turned on, and the signal on the initial signal line INIT is written to the second node N2 to initialize (reset) the first electrode of the light-emitting device L, clearing its internal pre-stored voltage and completing the initialization. At this time, the voltage value of the signal on the second node N2 is V2 = V init V init The voltage value of the initial signal line INIT is used. During this stage, since the voltage value of the initial signal line INIT can be less than the voltage value of the second power supply line VSS, the light-emitting device L does not emit light.

[0116] The second stage, P2, is called the threshold compensation stage. During this stage, the signals on the second scan signal line Gate2 and the light emission signal line EM are high-level signals, while the signals on the first scan signal line Gate1 and the third scan signal line Gate3 are low-level signals. When the signal on the second scan signal line Gate2 is high, the second transistor T2 is turned on, and the signal on the reference signal line REF is continuously written to the first node N1 through the turned-on second transistor T2. At this time, the voltage value of the signal at the first node N1 is V1 = V... ref The signal on the luminous signal line EM is a high-level signal, and the fifth transistor T5 is turned on. The signal on the first power line VDD is written to the second node N2 through the turned-on fifth transistor T5, the third node N3, and the turned-on third transistor T3, until the voltage V2 of the signal at the second node N2 equals V. ref -V th V th The threshold voltage of the third transistor T3 is given. At this time, the voltage value of the signal at the third node N3 is V3 = V vdd V vdd The capacitor C stores the voltage value of the signal from the first power line VDD, and the capacitor C stores the voltage difference V between the signals from the first node N1 and the second node N2. th During this stage, the light-emitting device L does not emit light.

[0117] The third stage, P3, is called the data writing stage. The first scan signal line, Gate1, is high, while the second scan signal line, Gate2, the third scan signal line, Gate3, and the EM signal line are low. The data signal line, Data, outputs the data signal. When the first scan signal line, Gate1, is high, the fourth transistor, T4, is turned on. The data signal on the Data line is written to the first node N1 through the turned-on fourth transistor T4. At this time, the voltage value of the signal at the first node N1, V1 = V... data V data Let V be the voltage value of the data signal. The signal at the first node N1 changes abruptly between the current voltage value and the previous voltage value. Therefore, under the influence of capacitor C, the signal at the second node N2 also changes abruptly. At this time, the voltage value of the signal at the second node N2 is V2 = V... ref -V th +α(V data -V ref During this stage, the light-emitting device L does not emit light.

[0118] The fourth stage, P4, is called the light-emitting stage. The signal on the light-emitting signal line EM is high, while the signals on the first scan signal line Gate1, the second scan signal line Gate2, and the third scan signal line Gate3 are low. When the signal on the light-emitting signal line EM is high, the fifth transistor T5 is turned on. The signal on the first power line VDD provides driving current to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, the third node N3, and the turned-on third transistor T3, thereby driving the light-emitting device L to emit light.

[0119] During pixel circuit driving, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the gate electrode (also the first node N1) and the second electrode (also the second node N2). Since the voltage value of the signal at the first node N1 is V1 = V... data The voltage value of the signal at the second node N2 is V2 = V ref -V th +α(V data -V ref Therefore, the drive current of the third transistor T3 is: I = K*(V gs -Vth) 2 =K*[(V data -V ref +V th -α(V data -V ref ))-Vth] 2 =K*[(1-α) (V data -V ref )] 2

[0120] Where I is the driving current flowing through the third transistor T3, which is also the driving current driving the light-emitting device L, K is a constant, and V gs This is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0121] In an exemplary embodiment, the signal of the light-emitting signal line EM can be either a high-level signal or a low-level signal in the third stage. Figure 4B illustrates this with an example where the signal of the light-emitting signal line EM is a low-level signal in the third stage. When the data signal line is used solely by a pixel circuit, the signal of the light-emitting signal line EM can be either a high-level signal or a low-level signal in the third stage. When the data signal line is shared by adjacent pixel circuits, the signal of the light-emitting signal line EM is a low-level signal in the third stage; otherwise, it would result in uneven display across different pixel circuits.

[0122] In an exemplary embodiment, the signal of the light-emitting signal line EM can be a continuously high-level signal or a periodic pulse signal in the fourth stage P4. When the signal of the light-emitting signal line EM is continuously high-level in the fourth stage P4, the light-emitting device continuously emits light. When the signal of the light-emitting signal line EM is a periodic pulse signal in the fourth stage P4, it can be used for pulse width modulation of the light, that is, the light-emitting device does not emit light continuously, but is constantly turning on and off.

[0123] In an exemplary embodiment, the scan signal line includes a first scan signal line, a second scan signal line, and a third scan signal line.

[0124] Figure 5 is a schematic diagram of the structure of the display substrate provided in the embodiment of this disclosure; Figure 6 is a cross-sectional view of the display substrate provided in the embodiment of this disclosure; Figure 7 is a schematic diagram of a portion of the film layers of the display substrate provided in Figure 5 (first); Figure 8 is a schematic diagram of a portion of the film layers of the display substrate provided in Figure 5 (second); and Figure 9 is a schematic diagram of a portion of the film layers of the display substrate provided in Figure 5 (third). As shown in Figures 5 to 9, the display substrate provided in the embodiment of this disclosure includes: a substrate 10 and a plurality of sub-pixels disposed on the substrate. At least one sub-pixel includes: a pixel circuit. The pixel circuit includes: a third transistor T3 and a plurality of transistors connected to the third transistor T3. The transistors include active patterns. The active patterns of at least two transistors connected to the gate electrode of the third transistor T3 are integrally structured and constitute a first active layer A1. The active patterns of at least two transistors connected to either the first or second electrode of the third transistor T3 and the active pattern T31 of the third transistor are integrally structured and constitute a second active layer A2.

[0125] As shown in Figure 7, the first active layer A1 and the second active layer A2 are arranged along the first direction D1 and extend at least partially along the second direction D2, where the first direction D1 and the second direction D2 intersect. The length L1 of the first active layer A1 along the second direction D2 is greater than the length L2 of the second active layer A2 along the second direction D2. Figure 5 illustrates this using a two-pixel circuit as an example.

[0126] In an exemplary embodiment, the active layer of each sub-pixel includes: a third transistor and an active pattern of a plurality of transistors connected to the third transistor.

[0127] In an exemplary embodiment, the display substrate may be an OLED display substrate or a Liquid Crystal Display (LCD) display substrate.

[0128] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate. The rigid substrate may be, but is not limited to, one or more of glass and conductive foil. The flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0129] In an exemplary embodiment, the display substrate includes a display area and a non-display area surrounding at least one side of the display area. A plurality of sub-pixels may be located within the display area.

[0130] In an exemplary embodiment, the shape of the display area can be square or rounded rectangle, or it can be other shapes, and this disclosure does not limit it in any way.

[0131] The display substrate provided in this embodiment includes: a substrate and a plurality of sub-pixels disposed on the substrate. At least one sub-pixel includes: a pixel circuit, the pixel circuit including: a third transistor and a plurality of transistors connected to the third transistor; the transistors include active patterns, the active patterns of at least two transistors connected to the gate electrode of the third transistor are integrally structured and constitute a first active layer, the active patterns of at least two transistors connected to either the first electrode or the second electrode of the third transistor and the active pattern of the third transistor are integrally structured and constitute a second active layer; the first active layer and the second active layer are arranged along a first direction and at least partially extend along a second direction, the first direction intersecting the second direction; the first active layer... First, by setting the active patterns of multiple transistors into an integrated structure, the active layer of each sub-pixel consists of only two parts. This allows transistors to be directly connected through the conductive active layer, simplifying the process, improving layout space utilization, and facilitating high PPI. Second, by setting the length of the first active layer along the second direction to be greater than the length of the second active layer along the second direction, the active patterns of at least two transistors connected to the gate electrode of the third transistor can be lengthened, reducing leakage current between at least two transistors connected to the gate electrode of the third transistor and improving the reliability of the display substrate.

[0132] In an exemplary embodiment, as shown in FIG5, the plurality of transistors connected to the third transistor T3 include: a first transistor T1, a second transistor T2, a fourth transistor T4, and a fifth transistor T5. The second terminal of the first transistor T1 is electrically connected to the second terminal of the third transistor T3; the second terminals of the second transistor T2 and the fourth transistor T4 are respectively connected to the gate electrode of the third transistor T3; and the second terminal of the fifth transistor T5 is electrically connected to the first terminal of the third transistor T3.

[0133] In an exemplary embodiment, the first transistor T1 to the fifth transistor T5 are N-type transistors.

[0134] In an exemplary embodiment, the active pattern includes a channel region and a conductive region, wherein the conductive regions of any active pattern are located on both sides of the channel region;

[0135] In an exemplary embodiment, as shown in FIG7, the active pattern T21 of the second transistor and the active pattern T41 of the fourth transistor constitute the first active layer A1, and the active pattern T11 of the first transistor, the active layer T31 of the third transistor, and the active pattern T51 of the fifth transistor constitute the second active layer A2.

[0136] In an exemplary embodiment, as shown in FIG7, the active pattern T11 of the first transistor and the active pattern T51 of the fifth transistor are located on both sides of the active pattern T31 of the third transistor.

[0137] In an exemplary embodiment, as shown in FIG7, the active pattern T21 of the second transistor includes a first conductive region T21A and a second conductive region T21B, and the active pattern T41 of the fourth transistor includes a third conductive region T41A and a fourth conductive region T41B.

[0138] In an exemplary embodiment, as shown in FIG7, the first conductive region T21A and the third conductive region T41A extend along the second direction D2, the second conductive region T21B and the fourth conductive region T41B extend along the first direction D1, and the third conductive region T41A is connected to the first conductive region T21A.

[0139] In an exemplary embodiment, as shown in FIG7, the second conductive region T21B is located on the side of the first conductive region T21A near the second active layer A2, and is located on the side of the active layer center line O with at least a portion of the active pattern of the first transistor. The fourth conductive region T41B is located on the side of the third conductive region T41A near the second active layer A2, and is located on the other side of the active layer center line O with at least a portion of the active pattern of the fifth transistor. The active layer center line O is the center line of the second active layer extending along the first direction D1.

[0140] In an exemplary embodiment, as shown in FIG7, the distance L3 between the second conductive region T21B and the active layer center line O is greater than the distance L4 between the boundary of the active pattern T11 of the first transistor away from the active layer center line O and the active layer center line O. In an exemplary embodiment, as shown in FIG7, the distance L5 between the fourth conductive region T41B and the active layer center line O is greater than the distance L6 between the boundary of the active pattern T51 of the fifth transistor away from the active layer center line O and the active layer center line O.

[0141] In an exemplary embodiment, as shown in FIG7, along the second direction D2, the distance between the second conductive region T21B and the second active layer A2 is less than or equal to the distance between the fourth conductive layer T41B and the second active layer A2. Specifically, along the second direction D2, the distance between the second conductive region T21B and the second active layer A2 is equal to the difference between the distance L3 between the second conductive region T21B and the center line O of the active layer and the distance L4 between the boundary of the active pattern T11 of the first transistor away from the center line O of the active layer and the center line O of the active layer. Similarly, along the second direction D2, the distance between the fourth conductive layer T41B and the second active layer A2 is equal to the difference between the distance L5 between the fourth conductive region T41B and the center line O of the active layer and the distance L6 between the center line O of the active layer.

[0142] In an exemplary embodiment, the display substrate may further include: a first signal line disposed on a substrate, at least a portion of the first signal line extending along a first direction D1, a gate electrode of at least one transistor disposed in a different layer from the first signal line, and the resistivity of the film layer in which the first signal line is located is less than the resistivity of the film layer in which the gate electrode of at least one transistor is located.

[0143] This disclosure, by having the gate electrode of at least one transistor and the first signal line disposed in a different layer, and the resistivity of the film layer containing the first signal line being less than the resistivity of the film layer containing the gate electrode of at least one transistor, allows for the use of a metal material with good stability, such as molybdenum, in the film layer containing the gate electrode of at least one transistor. Since molybdenum is heat-resistant and will not oxidize, even if over-etched during subsequent film layer etching, there will be no connection abnormalities. Secondly, the first signal line can be made of a low-resistivity metal material that is easily oxidized and not heat-resistant, such as aluminum, copper, or their alloys. The lower resistivity of the film layer containing the first signal line reduces the impedance of the first signal line, thus meeting the requirements for conductor resistance in high-PPI, large-size display products.

[0144] In an exemplary embodiment, the gate electrode T12 of the first transistor to the gate electrode T52 of the fifth transistor are spaced apart.

[0145] In an exemplary embodiment, the length of the gate electrode of the third transistor along the second direction may be greater than the length of the gate electrode of any one of the first, second, fourth, and fifth transistors along the second direction.

[0146] In an exemplary embodiment, as shown in Figures 7 and 8, the pixel circuit further includes a capacitor, which includes a first plate C1 and a second plate C2; ​​the first plate C1 is located on the side of the second plate C2 closer to the substrate. Figure 7 only shows the first plate C1 of the capacitor.

[0147] In an exemplary embodiment, as shown in FIG7, the first plate of the capacitor is disposed on the same layer as the active pattern of the transistor, or it can be disposed on the same layer as the gate electrode of the transistor. When the first plate of the capacitor is disposed on the same layer as the gate electrode of the transistor, the first plate C1 of the capacitor can be reused as the gate electrode T32 of the third transistor. By reusing the first plate C1 of the capacitor as the gate electrode T32 of the third transistor, the area of ​​the first plate of the capacitor can be increased, thereby maximizing the area of ​​the first plate of the capacitor and facilitating the achievement of high PPI. FIG5 to FIG9 are illustrated with the example of the first plate of the capacitor being disposed on the same layer as the gate electrode of the transistor.

[0148] In an exemplary embodiment, referring to Figures 7 and 8, when the first plate of the capacitor is disposed on the same layer as the gate electrode of the transistor, the orthographic projection of the first plate C1 of the capacitor on the substrate at least partially overlaps with the first conductive region, the active pattern of the third transistor, and the orthographic projection of the third conductive region on the substrate.

[0149] In an exemplary embodiment, FIG10 is a schematic diagram of a portion of the film layers of the display substrate provided in FIG5. As shown in FIG5 and FIG10, the first signal line may include: a third scan signal line Gate3, an initial signal line INIT, a first power supply line VDD, and a light emission signal line EM. The first transistor is connected to the third scan signal line and the initial signal line respectively, and the fifth transistor is connected to the first power supply line and the light emission signal line respectively.

[0150] In an exemplary embodiment, as shown in Figures 5, 7, 8, and 10, the orthographic projection of the second plate C2 of the capacitor onto the substrate at least partially overlaps with the orthographic projections of the third scan signal line Gate3, the initial signal line INIT, the first power supply line VDD, the light emission signal line EM, the first plate C1 of the capacitor, the first conductive area, and the third conductive area onto the substrate. This disclosure maximizes the capacitor area and improves the reliability of the display substrate by ensuring that the orthographic projection of the second plate of the capacitor onto the substrate at least partially overlaps with the third scan signal line, the first power supply line, and the orthographic projection of the first plate of the capacitor onto the substrate.

[0151] In an exemplary embodiment, as shown in FIG8, along the second direction D2, the distance between the orthographic projection of the gate electrode of the second transistor on the substrate and the orthographic projection of the second plate of the capacitor on the substrate is smaller than the distance between the orthographic projection of the gate electrode of the second transistor on the substrate and the orthographic projection of the gate electrode of the first transistor on the substrate, and the distance between the orthographic projection of the gate electrode of the fourth transistor on the substrate and the orthographic projection of the second plate of the capacitor on the substrate is smaller than the distance between the orthographic projection of the gate electrode of the fourth transistor on the substrate and the orthographic projection of the gate electrode of the fifth transistor on the substrate. This disclosure, by making the distance between the orthographic projection of the gate electrode of the second transistor on the substrate and the orthographic projection of the second plate of the capacitor on the substrate smaller than the distance between the orthographic projection of the gate electrode of the second transistor on the substrate and the orthographic projection of the gate electrode of the first transistor on the substrate, and the distance between the orthographic projection of the gate electrode of the fourth transistor on the substrate and the orthographic projection of the second plate of the capacitor on the substrate smaller than the distance between the orthographic projection of the gate electrode of the fourth transistor on the substrate and the orthographic projection of the gate electrode of the fifth transistor on the substrate, can increase the area of ​​the second plate of the capacitor without affecting signal transmission, thereby maximizing the area of ​​the first and second plates of the capacitor and facilitating the achievement of high PPI.

[0152] In an exemplary embodiment, as shown in FIG8, the second plate C2 of the capacitor is provided with a groove K, which exposes at least a portion of the first plate C1, the first conductive region T21A and the third conductive region T41A of the capacitor.

[0153] In an exemplary embodiment, as shown in FIG8, within the same sub-pixel, the opening direction of the groove K is located on the side away from the second active layer.

[0154] In an exemplary embodiment, as shown in FIG8, the second plate C2 of the capacitor includes: a capacitor body portion C21, a first capacitor connection portion C22, and a second capacitor connection portion C23, wherein the first capacitor connection portion C22 and the second capacitor connection portion C23 are respectively located on both sides of the capacitor body portion C21 and are respectively connected to the capacitor body portion C21, and a groove K is provided on one side of the capacitor body portion C21.

[0155] In an exemplary embodiment, as shown in FIG8, the capacitor body portion C21 extends along the first direction D1, the first capacitor connection portion C22 extends at least partially along the second direction D2, and the second capacitor connection portion C23 extends along the second direction D2.

[0156] In an exemplary embodiment, as shown in FIG8, the average length of the capacitor body portion C21 along the first direction D1 is greater than the average length of the first capacitor connection portion C22 along the first direction D1, and the average length of the first capacitor connection portion C22 along the first direction D1 is greater than the average length of the second capacitor connection portion C23 along the first direction D1.

[0157] In an exemplary embodiment, as shown in FIG8, the orthographic projection of the capacitor body C21 on the substrate at least partially overlaps with the orthographic projections of the first plate C1, the first conductive region T21A, and the third conductive region T41A of the capacitor on the substrate.

[0158] In an exemplary embodiment, as shown in FIG8, the orthographic projections of the first capacitor connection portion C22 and the second capacitor connection portion C23 on the substrate at least partially overlap with the orthographic projections of the first conductive region T21A and the third conductive region T41A on the substrate, and do not overlap with the orthographic projection of the first electrode plate C1 of the capacitor on the substrate.

[0159] In an exemplary embodiment, as shown in FIG8, the first plate C1 of the capacitor includes a first region R1 and a second region R2. The first region R1 is the area exposed by the groove of the second plate of the capacitor, and the second region R2 is all the regions except the first region R1. The orthographic projection of the second plate C2 of the capacitor onto the substrate covers the orthographic projection of the second region R2 of the first plate of the capacitor onto the substrate.

[0160] Since the first plate of the capacitor is in a floating state most of the time and is susceptible to interference, this disclosure sets the orthographic projection of the second plate C2 of the capacitor on the substrate to cover the orthographic projection of the second region R2 of the first plate of the capacitor on the substrate. This allows the first plate of the capacitor to be positioned below the second plate C2 of the capacitor to the maximum extent, which can effectively shield the first plate of the capacitor from noise interference and improve the reliability of the display substrate.

[0161] In an exemplary embodiment, as shown in FIG5, the first signal line further includes: a reference signal line REF, a first scan signal line Gate1 and a second scan signal line Gate2, a second transistor connected to the second scan signal line and the reference signal line respectively, and a fourth transistor connected to the first scan signal line.

[0162] In an exemplary embodiment, as shown in FIG5, the reference signal line REF, the second scan signal line Gate2, the initial signal line INIT, the third scan signal line Gate3, the light emission signal line EM, the first power supply line VDD, and the first scan signal line Gate1 are arranged sequentially along the first direction D1.

[0163] In an exemplary embodiment, as shown in FIG5, the display substrate may further include: a second signal line disposed on the substrate, the second signal line extending along a second direction D2, the second signal line including: a data signal line Data.

[0164] In an exemplary embodiment, as shown in Figures 5 and 9, the orthographic projection of the data signal line Data on the substrate at least partially overlaps with the orthographic projections of the first conductive region T21A, the third conductive region T41A, the fourth conductive region T41B, and the second plate C2 of the capacitor on the substrate. In this exemplary embodiment, the at least partial overlap between the orthographic projection of the data signal line Data on the substrate and the orthographic projections of the first conductive region, the third conductive region, the fourth conductive region, and the second plate of the capacitor on the substrate can save space on the display substrate and achieve a high PPI.

[0165] In an exemplary embodiment, the data signal line Data includes: a main data signal line DataA and a plurality of data signal connection lines DataB. The main data signal line DataA extends along a second direction D2, and the data signal connection lines DataB extend along a first direction D1.

[0166] In an exemplary embodiment, the orthographic projection of the main data signal line DataA on the substrate at least partially overlaps with the orthographic projections of the first conductive region, the third conductive region, and the second plate of the capacitor on the substrate, and the orthographic projection of the data signal connection line DataB on the substrate at least partially overlaps with the orthographic projection of the fourth conductive region on the substrate.

[0167] In an exemplary embodiment, as shown in FIG6, the display substrate may further include: a driving structure layer 20 disposed on the substrate 10; the driving structure layer 20 includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially stacked on the substrate 10;

[0168] The semiconductor layer includes at least: an active pattern of a first transistor, an active pattern of a second transistor, an active pattern of a third transistor, an active pattern of a fourth transistor, and an active pattern of a fifth transistor located at at least one sub-pixel.

[0169] The first conductive layer includes at least: the gate electrode of a first transistor, the gate electrode of a second transistor, the gate electrode of a third transistor, the gate electrode of a fourth transistor, the gate electrode of a fifth transistor, and the first plate of a capacitor located in at least one sub-pixel.

[0170] The second conductive layer includes at least: a second electrode of a capacitor located in at least one sub-pixel;

[0171] The third conductive layer includes at least: a first scan signal line, a second scan signal line, a third scan signal line, a light emission signal line, a reference signal line, a first power supply line, an initial signal line, and the second electrode of a first transistor, the second electrode of a second transistor, the second electrode of a third transistor, and the first and second electrodes of a fourth transistor located in at least one sub-pixel;

[0172] The fourth conductive layer includes at least: data signal lines.

[0173] In an exemplary embodiment, the driving circuit layer 20 of each sub-pixel may include a plurality of transistors and capacitors constituting the pixel circuit. In FIG6, only one transistor 210 and one capacitor 220 are used as examples.

[0174] In an exemplary embodiment, the display substrate may further include a light-emitting structure layer 30 disposed on the side of the driving circuit layer 20 away from the substrate 10, and an encapsulation structure layer disposed on the side of the light-emitting structure layer 30 away from the substrate 10. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0175] In an exemplary embodiment, the light-emitting structure layer 30 may include an anode 32, a pixel definition layer 31, an organic light-emitting layer 33, and a cathode 34. The anode 32 is connected to the drain electrode of the driving transistor 210 through a via. The organic light-emitting layer 33 is connected to the anode 32, and the cathode 34 is connected to the organic light-emitting layer 33. The organic light-emitting layer 33 emits light of the corresponding color under the drive of the anode 32 and the cathode 34.

[0176] In an exemplary embodiment, the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer 402, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0177] In an exemplary embodiment, the touch structure layer of each sub-pixel may include a first touch insulating layer disposed on the encapsulation structure layer, a first touch metal layer disposed on the first touch insulating layer, a second touch insulating layer covering the first touch metal layer, a second touch metal layer disposed on the second touch insulating layer, and a touch protective layer covering the second touch metal layer 44. The first touch metal layer may include a plurality of bridging electrodes, and the second touch metal layer may include a plurality of first touch electrodes and second touch electrodes. The first touch electrodes or the second touch electrodes may be connected to the bridging electrodes through vias.

[0178] In an exemplary embodiment, the first and second conductive layers can be fabricated using metals with good stability, such as molybdenum. Because molybdenum is heat-resistant and does not oxidize, there will be no connection abnormalities even if the first and second conductive layers are over-etched during subsequent film etching.

[0179] In an exemplary embodiment, the resistivity of the third conductive layer may be less than that of the first conductive layer.

[0180] In an exemplary embodiment, the resistivity of the fourth conductive layer is less than that of the first conductive layer. For example, it can be formed using metals such as aluminum and copper or their alloys. The lower resistivity of the fourth conductive layer can reduce the impedance of the second signal line and meet the requirements of high PPI and large size display products for conductor resistance.

[0181] In an exemplary embodiment, the thickness of the third conductive layer may be greater than the thickness of the first conductive layer or the second conductive layer.

[0182] In an exemplary embodiment, the thickness of the third conductive layer can be greater than 500 nanometers. For example, the thickness of the third conductive layer can be 500 nanometers or 650 nanometers.

[0183] In an exemplary embodiment, the thicknesses of the third conductive layer and the fourth conductive layer may be the same or different, and this disclosure does not limit them in any way.

[0184] In an exemplary embodiment, as shown in FIG6, the driving structure layer may further include: a first insulating layer 21 disposed between the substrate 10 and the semiconductor layer, a second insulating layer 22 disposed between the semiconductor layer and the first conductive layer, a third insulating layer 23 disposed between the first conductive layer and the second conductive layer, a fourth insulating layer 24 disposed between the second conductive layer and the third conductive layer, a first planarization layer 25 and a fifth insulating layer 26 disposed between the third conductive layer and the fourth conductive layer, and a second planarization layer 27 disposed on the side of the fourth conductive layer away from the substrate.

[0185] In an exemplary embodiment, the fifth insulating layer 26 is located on the side of the first planarization layer 25 away from the substrate 10. The fifth insulating layer being located on the side of the first planarization layer away from the substrate not only avoids damage to the first planarization layer when the fourth conductive layer is subsequently formed, but also does not contaminate the deposition and etching equipment for the fourth conductive layer.

[0186] In an exemplary embodiment, the thickness of the first planarization layer 25 is greater than the thickness of the fifth insulating layer 26. The thickness setting of the first planarization layer in this disclosure, resulting in a larger thickness, not only reduces the risk of short circuits between the third and fourth conductive layers but also reduces the capacitance between the signals of the third and fourth conductive layers, thereby reducing resistive-capacitive loads and making it more advantageous for driving high PPI and large-size panels.

[0187] In an exemplary embodiment, the thickness of the first planarization layer can be from 1.4 micrometers to 2.3 micrometers.

[0188] In an exemplary embodiment, the thickness of the fifth insulating layer can be from 50 nanoangiograms to 2500 nanoangiograms.

[0189] In an exemplary embodiment, the second flattening layer can flatten the step of the fourth conductive layer, thereby improving the flatness of the driving structure layer and facilitating the fabrication of the subsequent light-emitting structure layer.

[0190] In an exemplary embodiment, the driving structure layer may further include a sixth insulating layer located between the fourth conductive layer and the second planarization layer.

[0191] In an exemplary embodiment, as shown in FIG5, the second transistor T2 and the fourth transistor T4 are disposed at the edge of the entire pixel circuit, which can minimize the signal line crossing connected to the fourth transistor T4, minimize the capacitive and resistive load, and improve the driving capability of the pixel circuit.

[0192] In an exemplary embodiment, as shown in FIG5, the pixel circuits of adjacent sub-pixels have the same pixel structure. Adjacent sub-pixels include: adjacent sub-pixels located in the same row and adjacent sub-pixels located in the same column.

[0193] In exemplary embodiments, the light-emitting device can be either a top-emitting structure or a bottom-emitting structure, and this disclosure does not limit it in any way. A top-emitting structure refers to a light-emitting device where the first electrode (anode) is a reflective electrode and the second electrode (cathode) is a transmissive electrode. A bottom-emitting structure refers to a light-emitting device where the first electrode (anode) is a transmissive electrode and the second electrode (cathode) is a reflective electrode.

[0194] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0195] Figures 11 to 21 are schematic diagrams illustrating the fabrication process of a display substrate according to an exemplary embodiment. Figures 11 to 21 are illustrated using a row of two columns of sub-pixels as an example. As shown in Figures 11 to 21, the fabrication process of a display substrate according to an exemplary embodiment may include:

[0196] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, and patterning the semiconductor film by a patterning process to form a first insulating layer covering the substrate and a semiconductor layer pattern located on the first insulating layer, as shown in FIG11, FIG11 being a schematic diagram after forming the semiconductor layer pattern.

[0197] In an exemplary embodiment, as shown in FIG11, the semiconductor layer pattern may include at least: an active pattern T11 of a first transistor, an active pattern T21 of a second transistor, an active pattern T31 of a third transistor, an active pattern T41 of a fourth transistor, and an active pattern T51 of a fifth transistor located at at least one sub-pixel.

[0198] In an exemplary embodiment, as shown in FIG11, the active patterns T11 of the first transistor, T31 of the third transistor, and T51 of the fifth transistor are interconnected as a single structure. The active patterns T21 of the second transistor and T41 of the fourth transistor are interconnected as a single structure. The active patterns T11 of the first transistor and T21 of the second transistor are spaced apart.

[0199] In an exemplary embodiment, as shown in FIG11, in the first direction D1, the integrated structure of the active pattern T21 of the second transistor and the active pattern T41 of the fourth transistor of this sub-pixel is located on the side of the integrated structure of the active pattern T11 of the first transistor, the active pattern T31 of the third transistor and the active pattern T51 of the fifth transistor close to the previous column of sub-pixels.

[0200] In an exemplary embodiment, as shown in FIG11, in the second direction D2, the active pattern T11 of the first transistor of this sub-pixel may be located on the side of the active pattern T31 of the third transistor near the previous row of sub-pixels, and the active pattern T51 of the fifth transistor of this sub-pixel may be located on the side of the active pattern T31 of the third transistor near the next row of sub-pixels. The active pattern T21 of the second transistor of this sub-pixel may be located on the side of the active pattern T41 of the fourth transistor near the previous row of sub-pixels.

[0201] In an exemplary embodiment, as shown in FIG11, the shape of the active pattern T21 of the second transistor can be as follows: The shape of the character.

[0202] In an exemplary embodiment, as shown in FIG11, the active pattern T41 of the fourth transistor can be in the shape of an "L".

[0203] In an exemplary embodiment, as shown in FIG11, the shape of the integrated structure of the active pattern T21 of the second transistor and the active pattern T41 of the fourth transistor can be “[” shaped, and the opening faces the integrated structure of the active pattern T11 of the first transistor, the active pattern T31 of the third transistor and the active pattern T51 of the fifth transistor.

[0204] In an exemplary embodiment, as shown in FIG11, the integrated structure of the active pattern T11 of the first transistor, the active pattern T31 of the third transistor, and the active pattern T51 of the fifth transistor is located within the opening of the integrated structure of the active pattern T21 of the second transistor and the active pattern T41 of the fourth transistor.

[0205] In an exemplary embodiment, as shown in FIG11, the main body shapes of the active patterns T11 of the first transistor, T31 of the third transistor, and T51 of the fifth transistor can be strip-shaped extending along the second direction D2. The integral structure of the active patterns T11 of the first transistor, T31 of the third transistor, and T51 of the fifth transistor extends along the second direction D2.

[0206] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first and second regions. The first and second regions are conductive after the subsequent formation of the first conductive layer and are therefore also referred to as conductive regions. In an exemplary embodiment, the second region T11-2 of the active pattern T11 of the first transistor can simultaneously serve as the second region T31-2 of the active pattern T31 of the third transistor, the second region T21-2 of the active pattern T21 of the second transistor can simultaneously serve as the second region T41-2 of the active pattern T41 of the fourth transistor, and the first region T31-1 of the active pattern T31 of the third transistor can simultaneously serve as the second region T51-2 of the active pattern T51 of the fifth transistor. The first regions T11-1 of the active patterns T11, T21-1 of the active patterns T21, T41-1 of the active patterns T41, and T51-1 of the active patterns T51 of the fifth transistor can be configured individually.

[0207] In an exemplary embodiment, as shown in FIG11, the second region T21-2 of the active pattern T21 of the second transistor can be referred to as the first conductive region T21A of the active pattern T21 of the second transistor, and the first region T21-1 of the active pattern T21 of the second transistor can be referred to as the second conductive region T21B of the active pattern T21 of the second transistor, wherein the first conductive region T21A extends along the second direction D2, and the second conductive region T21B extends along the first direction D1.

[0208] In an exemplary embodiment, as shown in FIG11, the second region T41-2 of the active pattern T41 of the fourth transistor can be referred to as the third conductive region T41A of the active pattern T41 of the fourth transistor, and the first region T41-1 of the active pattern T41 of the fourth transistor can be referred to as the fourth conductive region T41B of the active pattern T41 of the fourth transistor, wherein the third conductive region T41A extends along the second direction D2, and the fourth conductive region T41B extends along the first direction D1.

[0209] In an exemplary embodiment, as shown in FIG11, the third conductive region T41A is connected to the first conductive region T21A.

[0210] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a second insulating layer covering the semiconductor layer pattern and a first conductive layer pattern disposed on the second insulating layer, as shown in Figures 12 and 13. Figure 12 is a schematic diagram of the first conductive layer pattern, and Figure 13 is a schematic diagram after the formation of the first conductive layer pattern. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0211] In an exemplary embodiment, as shown in Figures 12 and 13, the first conductive layer pattern may include at least: a gate electrode T12 of a first transistor, a gate electrode T22 of a second transistor, a gate electrode T32 of a third transistor, a gate electrode T42 of a fourth transistor, a gate electrode T52 of a fifth transistor, and a first plate C1 of a capacitor located in at least one sub-pixel.

[0212] In an exemplary embodiment, the first electrode C1 can also serve as the gate electrode T32 of the third transistor T3.

[0213] In an exemplary embodiment, the first electrode plate C1 may be rectangular in shape, and the orthographic projection of the first electrode plate C1 on the substrate at least partially overlaps with the orthographic projection of the active pattern of the third transistor on the substrate and the orthographic projections of the first conductive region and the third conductive region on the substrate.

[0214] In an exemplary embodiment, the gate electrode T12 of the first transistor is in the shape of a strip extending along the first direction D1.

[0215] In an exemplary embodiment, the gate electrode T22 of the second transistor is in the shape of a strip extending along the first direction D1.

[0216] In an exemplary embodiment, the gate electrode T42 of the fourth transistor is in the shape of a strip extending along the first direction D1.

[0217] In an exemplary embodiment, the gate electrode T52 of the fifth transistor is a strip-shaped structure extending along the first direction D1.

[0218] In an exemplary embodiment, the length of the integral structure of the gate electrode T32 of the third transistor and the first plate C1 of the capacitor along the second direction D2 is greater than the length of any one of the gate electrodes T12 of the first transistor, T22 of the second transistor, T42 of the fourth transistor, and T52 of the fifth transistor along the second direction D2.

[0219] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to conduct the semiconductor layer. The semiconductor layer in the region shielded by the first conductive layer forms the channel region of the active pattern of the first transistor to the channel region of the active pattern of the fifth transistor. The semiconductor layer in the region not shielded by the first conductive layer is conducted, that is, the first region and the second region of the active pattern of the first transistor to the fifth transistor are both conducted. The first region T31-1 of the active pattern T31 of the third transistor (which is also the second region T51-2 of the active pattern T51 of the fifth transistor) can be reused as the first electrode T33 of the third transistor and the second electrode T54 of the fifth transistor.

[0220] In an exemplary embodiment, the gate electrode T12 of the first transistor is disposed across the active pattern of the first transistor, the gate electrode T22 of the second transistor is disposed across the active pattern of the second transistor, the gate electrode T32 of the third transistor is disposed across the active pattern of the third transistor, the gate electrode T42 of the fourth transistor is disposed across the active pattern of the fourth transistor, and the gate electrode T52 of the fifth transistor is disposed across the active pattern of the fifth transistor. That is, the extension direction of the gate electrode of at least one transistor is perpendicular to the extension direction of the active layer.

[0221] (3) Forming a second conductive layer pattern includes: sequentially depositing a third insulating film and a second conductive film on the substrate on which the aforementioned pattern is formed; patterning the third insulating film and the second conductive film using a patterning process to form a third insulating layer and a second conductive layer pattern located on the third insulating layer, as shown in Figures 14 and 15. Figure 14 is a schematic diagram of the second conductive layer pattern, and Figure 15 is a schematic diagram after the second conductive layer pattern is formed. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0222] In an exemplary embodiment, as shown in Figures 14 and 15, the second conductive layer pattern may include at least: a second plate C2 of a capacitor located in at least one sub-pixel.

[0223] In an exemplary embodiment, as shown in Figures 14 and 15, the second electrode C2 may include: a capacitor body portion C21, a first capacitor connection portion C22, and a second capacitor connection portion C23. The first capacitor connection portion C22 and the second capacitor connection portion C23 are located on opposite sides of the capacitor body portion C21 and are respectively connected to the capacitor body portion C21.

[0224] In an exemplary embodiment, as shown in Figures 14 and 15, the first capacitor connection portion C22 of the sub-pixel can be located on the side of the capacitor body portion C21 near the previous row of sub-pixels, and the second capacitor connection portion C23 of the sub-pixel can be located on the side of the capacitor body portion C21 near the next row of sub-pixels.

[0225] In an exemplary embodiment, as shown in Figures 14 and 15, the length of the first capacitor connection portion C22 along the first direction D1 is greater than the length of the second capacitor connection portion C23 along the first direction D1, and the length of the capacitor body portion C21 along the first direction D1 is greater than the length of the first capacitor connection portion C22 along the first direction D1.

[0226] In an exemplary embodiment, as shown in Figures 14 and 15, the first capacitor connection portion C22 of this sub-pixel is flush with the boundary of the previous column of sub-pixels, and the second capacitor connection portion C22 is flush with the boundary of the previous column of sub-pixels, and the capacitor body portion C21 is flush with the boundary of the previous column of sub-pixels.

[0227] In an exemplary embodiment, as shown in FIG15, the capacitor body portion C21 can be square in shape with a groove K. The groove K is disposed on the side of the capacitor body portion C21 of this sub-pixel near the previous row of sub-pixels. The groove K exposes the first electrode plate (which is also the gate electrode of the third transistor) and the second electrode of the second transistor (which is also the second electrode of the fourth transistor).

[0228] In an exemplary embodiment, as shown in FIG15, within the same sub-pixel, the opening direction of the groove K is located on the side opposite to the second active layer.

[0229] In an exemplary embodiment, as shown in Figures 14 and 15, the shape of the groove K can be square or other shapes, and this disclosure does not limit it in any way.

[0230] In an exemplary embodiment, as shown in FIG15, the orthographic projection of the capacitor body portion C21 on the substrate at least partially overlaps with the orthographic projections of at least a portion of the first plate (which is also the gate electrode of the third transistor), the first conductive region, and the third conductive region on the substrate.

[0231] In an exemplary embodiment, as shown in Figures 14 and 15, the first capacitor connection portion C22 may be L-shaped.

[0232] In an exemplary embodiment, as shown in Figures 14 and 15, the shape of the second capacitor connection portion C23 can be a strip extending along the second direction D2.

[0233] In an exemplary embodiment, as shown in FIG15, the orthographic projection of either the first capacitor connection portion C22 or the second capacitor connection portion C23 on the substrate can at least partially overlap with the orthographic projections of the first conductive region and the third conductive region on the substrate, and does not overlap with the orthographic projection of the first plate of the capacitor (which is also the gate electrode of the third transistor) on the substrate.

[0234] In an exemplary embodiment, the length of either the first capacitor connection portion C22 or the second capacitor connection portion C23 along the first direction D1 can be greater than or equal to the length of the second electrode of the second transistor (which is also the second electrode of the fourth transistor) along the first direction D1.

[0235] In an exemplary embodiment, along the second direction, the distance between the orthographic projection of the gate electrode of the second transistor on the substrate and the orthographic projection of the second plate of the capacitor on the substrate is less than the distance between the orthographic projection of the gate electrode of the second transistor on the substrate and the orthographic projection of the gate electrode of the first transistor on the substrate; the distance between the orthographic projection of the gate electrode of the fourth transistor on the substrate and the orthographic projection of the second plate of the capacitor on the substrate is less than the distance between the orthographic projection of the gate electrode of the fourth transistor on the substrate and the orthographic projection of the gate electrode of the fifth transistor on the substrate.

[0236] (4) Forming a fourth insulating layer pattern includes: depositing a fourth insulating film on a substrate on which the aforementioned pattern has been formed, and patterning the fourth insulating film by a patterning process to form a fourth insulating layer pattern covering the aforementioned pattern. The fourth insulating layer has multiple via patterns, as shown in Figure 16. Figure 16 is a schematic diagram after the fourth insulating layer pattern has been formed.

[0237] In an exemplary embodiment, as shown in FIG16, the plurality of vias in the fourth insulating layer include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, and a tenth via V10 located in at least one sub-pixel.

[0238] In an exemplary embodiment, as shown in FIG16, the orthographic projection of the first via V1 on the substrate is within the range of the orthographic projection of the first region of the active pattern of the first transistor on the substrate. The second and third insulating layers in the first via V1 are etched away, exposing the surface of the first region of the active pattern of the first transistor. The first via V1 is configured to allow the subsequently formed initial signal line INIT to be connected to the first region of the active pattern of the first transistor through the via.

[0239] In an exemplary embodiment, as shown in FIG16, the orthographic projection of the second via V2 on the substrate is located within the range of the orthographic projection of the second region of the active pattern of the first transistor (which is also the second region of the active pattern of the third transistor) and the second plate of the capacitor on the substrate. Part of the second insulating layer and part of the third insulating layer within the second via V2 are etched away, exposing the surface of the second region of the active pattern of the first transistor (which is also the second region of the active pattern of the third transistor) and the second plate of the capacitor. The second via V2 is configured to allow the subsequently formed first connection electrode to be connected to the second region of the active pattern of the first transistor (which is also the second region of the active pattern of the third transistor) and the second plate of the capacitor through the via.

[0240] In an exemplary embodiment, as shown in FIG16, the orthographic projection of the third via V3 on the substrate is located within the orthographic projection range of the first region of the active pattern of the second transistor on the substrate. The second insulating layer and the third insulating layer within the third via V3 are etched away, exposing the surface of the first region of the active pattern of the second transistor. The third via V3 is configured to allow a subsequently formed reference signal line to be connected to the first region of the active pattern of the second transistor through the via.

[0241] In an exemplary embodiment, as shown in FIG16, the orthographic projection of the fourth via V4 on the substrate is located within the range of the orthographic projection of the second region of the active pattern of the second transistor (which is also the second region of the active pattern of the fourth transistor) and the first plate of the capacitor on the substrate. Part of the second insulating layer and part of the third insulating layer within the fourth via V4 are etched away, exposing the surface of the second region of the active pattern of the second transistor (which is also the second region of the active pattern of the fourth transistor) and the first plate of the capacitor. The fourth via V4 is configured to allow the subsequently formed second connection electrode to be connected to the second region of the active pattern of the second transistor (which is also the second region of the active pattern of the fourth transistor) and the first plate of the capacitor through the via.

[0242] In an exemplary embodiment, as shown in FIG16, the orthographic projection of the fifth via V5 on the substrate is within the range of the orthographic projection of the first region of the active pattern of the fourth transistor on the substrate. The second and third insulating layers in the fifth via V5 are etched away, exposing the surface of the first region of the active pattern of the fourth transistor. The fifth via V5 is configured to allow the first electrode of the subsequently formed fourth transistor to be connected to the first region of the active pattern of the fourth transistor through the via.

[0243] In an exemplary embodiment, as shown in FIG16, the orthographic projection of the sixth via V6 on the substrate is within the range of the orthographic projection of the first region of the active pattern of the fifth transistor on the substrate. The second and third insulating layers in the sixth via V6 are etched away, exposing the surface of the first region of the active pattern of the fifth transistor. The sixth via V6 is configured to allow a subsequently formed first power line to be connected to the first region of the active pattern of the fifth transistor through the via.

[0244] In an exemplary embodiment, as shown in FIG16, the orthogonal projection of the seventh via V7 on the substrate is within the range of the orthogonal projection of the gate electrode of the first transistor on the substrate. The third insulating layer in the seventh via V7 is etched away, exposing the surface of the gate electrode of the first transistor. The seventh via V7 is configured to allow the subsequently formed third scan signal line to be connected to the gate electrode of the first transistor through the via.

[0245] In an exemplary embodiment, as shown in FIG16, the orthographic projection of the eighth via V8 on the substrate is within the range of the orthographic projection of the gate electrode of the second transistor on the substrate. The third insulating layer in the eighth via V8 is etched away, exposing the surface of the gate electrode of the second transistor. The eighth via V8 is configured to allow the subsequently formed second scan signal line to be connected to the gate electrode of the second transistor through the via.

[0246] In an exemplary embodiment, as shown in FIG16, the orthographic projection of the ninth via V9 on the substrate is within the range of the orthographic projection of the gate electrode of the fourth transistor on the substrate. The third insulating layer in the ninth via V9 is etched away, exposing the surface of the gate electrode of the fourth transistor. The ninth via V9 is configured to allow the subsequently formed first scan signal line to be connected to the gate electrode of the fourth transistor through the via.

[0247] In an exemplary embodiment, as shown in FIG16, the orthogonal projection of the tenth via V10 on the substrate is within the range of the orthogonal projection of the gate electrode of the fifth transistor on the substrate. The third insulating layer in the tenth via V10 is etched away, exposing the surface of the gate electrode of the fifth transistor. The tenth via V10 is configured to allow the subsequently formed light-emitting signal line to be connected to the gate electrode of the fifth transistor through the via.

[0248] (5) Forming a third conductive layer pattern includes: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, and patterning the third conductive film using a patterning process to form a third conductive layer pattern located on the fourth insulating layer, as shown in Figures 17 and 18. Figure 17 is a schematic diagram of the third conductive layer pattern, and Figure 18 is a schematic diagram after the third conductive layer pattern is formed. In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0249] In an exemplary embodiment, as shown in Figures 17 and 18, the third conductive layer pattern may include at least: a first scan signal line Gate1, a second scan signal line Gate2, a third scan signal line Gate3, a light emission signal line EM, a reference signal line REF, a first power supply line VDD, an initial signal line INIT, and the second poles T14 of a first transistor, T24 of a second transistor, T34 of a third transistor, and the first pole T43 and the second pole T44 of a fourth transistor located in at least one sub-pixel.

[0250] In an exemplary embodiment, as shown in Figures 17 and 18, the reference signal line REF can be a line shape in which the main body extends along the first direction D1. The region where the reference signal line REF overlaps with the active pattern of the second transistor serves as the first electrode T23 of the second transistor.

[0251] In an exemplary embodiment, as shown in Figures 17 and 18, the reference signal line REF is connected to the first region of the active pattern of the second transistor through a third via.

[0252] In an exemplary embodiment, as shown in Figures 17 and 18, the second scan signal line Gate2 is located between the reference signal line REF and the initial signal line INIT. The shape of the second scan signal line Gate2 can be a line shape in which the main body extends along the first direction D1.

[0253] In an exemplary embodiment, as shown in Figures 17 and 18, the orthographic projection of the second scan signal line Gate2 on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the second transistor on the substrate.

[0254] In an exemplary embodiment, as shown in Figures 17 and 18, the second scan signal line Gate2 is connected to the gate electrode of the second transistor through an eighth via.

[0255] In an exemplary embodiment, as shown in Figures 17 and 18, the initial signal line INIT is located on the side of the second scan signal line Gate2 away from the reference signal line REF. The shape of the initial signal line INIT can be a line shape in which the main body extends along the first direction D1. The region where the initial signal line INIT overlaps with the active pattern of the first transistor serves as the first electrode T13 of the first transistor.

[0256] In an exemplary embodiment, as shown in Figures 17 and 18, the initial signal line INIT is connected to the first region of the active pattern of the first transistor through a first via.

[0257] In an exemplary embodiment, as shown in Figures 17 and 18, the third scan signal line Gate3 is located on the side of the initial signal line INIT away from the second scan signal line Gate2. The shape of the third scan signal line Gate3 can be a line shape in which the main body extends along the first direction D1.

[0258] In an exemplary embodiment, as shown in Figures 17 and 18, the orthographic projection of the third scan signal line Gate3 on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the first transistor on the substrate.

[0259] In an exemplary embodiment, as shown in Figures 17 and 18, the third scan signal line Gate3 is connected to the gate electrode of the first transistor through a seventh via.

[0260] In an exemplary embodiment, as shown in Figures 17 and 18, the light-emitting signal line EM is located on the side of the third scan signal line Gate3 away from the initial signal line INIT. The shape of the light-emitting signal line EM can be a line shape in which the main body extends along the first direction D1.

[0261] In an exemplary embodiment, as shown in Figures 17 and 18, the orthographic projection of the light-emitting signal line EM onto the substrate at least partially overlaps with the orthographic projection of the gate electrode of the fifth transistor onto the substrate.

[0262] In an exemplary embodiment, as shown in Figures 17 and 18, the light-emitting signal line EM is connected to the gate electrode of the fifth transistor through a tenth via.

[0263] In an exemplary embodiment, as shown in Figures 17 and 18, the first power line VDD is located on the side of the light-emitting signal line EM away from the third scan signal line Gate3. The shape of the first power line VDD can be a line shape in which the main body extends along the first direction D1. The area where the first power line VDD overlaps with the active pattern of the fifth transistor serves as the first electrode T13 of the fifth transistor.

[0264] In an exemplary embodiment, as shown in Figures 17 and 18, the first power line VDD is connected to the first region of the active pattern of the fifth transistor through a sixth via.

[0265] In an exemplary embodiment, as shown in Figures 17 and 18, the first scan signal line Gate1 is located on the side of the first power supply line VDD away from the light-emitting signal line EM. The shape of the first scan signal line Gate1 can be a line shape in which the main body extends along the first direction D1.

[0266] In an exemplary embodiment, as shown in Figures 17 and 18, the orthographic projection of the first scan signal line Gate1 on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the fourth transistor on the substrate.

[0267] In an exemplary embodiment, as shown in Figures 17 and 18, the first scan signal line Gate1 is connected to the gate electrode of the fourth transistor through a ninth via.

[0268] In an exemplary embodiment, as shown in Figures 17 and 18, the second electrode T14 of the first transistor and the second electrode T34 of the third transistor are an integral structure located between the third scan signal line Gate3 and the light emission signal line EM. The shape of the integral structure of the second electrode T14 of the first transistor and the second electrode T34 of the third transistor can be a strip extending along the first direction D1.

[0269] In an exemplary embodiment, as shown in Figures 17 and 18, the orthographic projection of the integral structure of the second electrode T14 of the first transistor and the second electrode T34 of the third transistor on the substrate at least partially overlaps with the orthographic projection of the second electrode plate of the capacitor on the substrate.

[0270] In an exemplary embodiment, as shown in Figures 17 and 18, the second terminal T14 of the first transistor (which is also the second terminal T34 of the third transistor) is connected to the second region of the active pattern of the first transistor (which is also the second region of the active pattern of the third transistor) and the second plate of the capacitor through a second via.

[0271] In an exemplary embodiment, as shown in Figures 17 and 18, the second electrode T24 of the second transistor and the second electrode T44 of the fourth transistor are an integral structure and are located between the second electrode T14 of the first transistor (which is also the second electrode T34 of the third transistor) and the light-emitting signal line EM. The second electrode T24 of the second transistor (which is also the second electrode T44 of the fourth transistor) can be a strip extending along the first direction D1.

[0272] In an exemplary embodiment, as shown in Figures 17 and 18, the orthogonal projection of the second electrode T24 of the second transistor (which is also the second electrode T44 of the fourth transistor) onto the substrate lies within the orthogonal projection of the groove of the second plate of the capacitor onto the substrate.

[0273] In an exemplary embodiment, as shown in Figures 17 and 18, the second electrode T24 of the second transistor (which is also the second electrode T44 of the fourth transistor) is connected to the second region of the active pattern of the second transistor (which is also the second region of the active pattern of the fourth transistor) and the first plate of the capacitor through a fourth via.

[0274] In an exemplary embodiment, as shown in Figures 17 and 18, the first electrode T43 of the fourth transistor is located on the side of the first scan signal line Gate1 away from the first power supply line VDD. The shape of the first electrode VL3 of the fourth transistor can be a strip extending along the first direction D1.

[0275] In an exemplary embodiment, as shown in Figures 17 and 18, the orthographic projection of the first electrode T43 of the fourth transistor onto the substrate lies within the orthographic projection of the active pattern of the fourth transistor onto the substrate.

[0276] In an exemplary embodiment, as shown in Figures 17 and 18, the first electrode T43 of the fourth transistor is connected to the first region of the active pattern of the fourth transistor through a fifth via.

[0277] In an exemplary embodiment, the first scan signal line Gate1, the second scan signal line Gate2, the third scan signal line Gate3, the light emission signal line EM, the reference signal line REF, the first power supply line VDD, and the initial signal line INIT can be designed with equal width or with non-equal width, and can be straight lines or broken lines. This not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines. This disclosure does not limit the scope of the invention.

[0278] (6) Forming a fifth insulating layer pattern includes: coating a first planar thin film on a substrate on which the aforementioned pattern has been formed; patterning the first planar thin film using a patterning process to form a first planar layer; depositing a fifth insulating thin film on the first planar layer; and patterning the fifth insulating thin film using a patterning process to form a fifth insulating layer pattern covering the aforementioned pattern. The fifth insulating layer pattern has multiple via patterns, as shown in Figure 19. Figure 19 is a schematic diagram after the fifth insulating layer pattern has been formed.

[0279] In an exemplary embodiment, as shown in FIG19, the fifth insulating layer pattern includes at least an eleventh via V11 and a twelfth via V12 located in at least one sub-pixel.

[0280] In an exemplary embodiment, as shown in FIG19, the orthographic projection of the eleventh via V11 on the substrate is located within the range of the orthographic projection of the second electrode T14 of the first transistor (which is also the second electrode T34 of the third transistor) on the substrate. The first planarization layer within the eleventh via V11 is etched away, exposing the surface of the second electrode T14 of the first transistor (which is also the second electrode T34 of the third transistor). The eleventh via V11 is configured to allow the subsequently formed anode connection electrode to be connected to the second electrode T14 of the first transistor (which is also the second electrode T34 of the third transistor) through the via.

[0281] In an exemplary embodiment, as shown in FIG19, the orthographic projection of the twelfth via V12 on the substrate is within the range of the orthographic projection of the first electrode of the fourth transistor on the substrate. The first planarization layer in the twelfth via V12 is etched away to expose the surface of the first electrode of the fourth transistor. The twelfth via V12 is configured to allow subsequently formed data signal lines to be connected to the first electrode of the fourth transistor through the via.

[0282] (7) Forming a fourth conductive layer pattern includes: depositing a fourth conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the fourth conductive thin film using a patterning process to form a fourth conductive layer pattern, as shown in Figures 20 and 21. Figure 20 is a schematic diagram of the fourth conductive layer pattern, and Figure 21 is a schematic diagram after the fourth conductive layer pattern is formed. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0283] In an exemplary embodiment, as shown in Figures 20 and 21, the fourth conductive layer pattern may include at least: a data signal line Data and an anode connection electrode VL.

[0284] In an exemplary embodiment, as shown in Figures 20 and 21, the anode connection electrode VL of this sub-pixel is located on the side of the data signal line connected to this sub-pixel closer to the next column of sub-pixels. The anode connection electrode VL is strip-shaped, extending along the second direction D2.

[0285] In an exemplary embodiment, as shown in Figures 20 and 21, the orthogonal projection of the anode connection electrode VL on the substrate at least partially overlaps with the orthogonal projections of the second electrode of the first transistor (which is also the second electrode of the third transistor) and the third scan signal line on the substrate.

[0286] In an exemplary embodiment, as shown in Figures 20 and 21, the anode connection electrode VL is connected to the second terminal of the first transistor (which is also the second terminal of the third transistor) through an eleventh via. Since the second terminal of the first transistor (which is also the second terminal of the third transistor) is connected to the second plate of the capacitor, the anode connection electrode VL is connected to the second region of the active pattern of the first transistor (which is also the second region of the active pattern of the third transistor) and the second plate of the capacitor through the second terminal of the first transistor (which is also the second terminal of the third transistor).

[0287] In an exemplary embodiment, as shown in Figures 20 and 21, the data signal line Data extends at least partially along the second direction D2.

[0288] In an exemplary embodiment, as shown in Figures 20 and 21, the orthographic projection of the data signal line Data on the substrate at least partially overlaps with the orthographic projections of the first conductive region, the third conductive region, the fourth conductive region, and the second plate of the capacitor on the substrate.

[0289] In an exemplary embodiment, as shown in Figures 20 and 21, the data signal line Data includes: a main data signal line DataA and a plurality of data signal connection lines DataB. The main data signal line DataA extends along a second direction D2, and the data signal connection lines DataB extend along a first direction D1.

[0290] In an exemplary embodiment, the orthographic projection of the main data signal line DataA on the substrate at least partially overlaps with the orthographic projections of the first conductive region, the third conductive region, and the second plate of the capacitor on the substrate, and the orthographic projection of the data signal connection line DataB on the substrate at least partially overlaps with the orthographic projection of the fourth conductive region on the substrate.

[0291] In an exemplary embodiment, as shown in Figures 20 and 21, the data signal line Data is connected to the first terminal of the fourth transistor through the twelfth via. Specifically, the data signal connection line DataB of the data signal line Data is also connected to the first terminal of the fourth transistor through the twelfth via.

[0292] (8) Forming a second planarization layer pattern includes: depositing a sixth insulating film on a substrate on which the aforementioned pattern is formed, patterning the sixth insulating film by a patterning process to form a sixth insulating layer covering the aforementioned pattern, coating the sixth insulating layer with a second planarization film, and patterning the second planarization film by a patterning process to form a second planarization layer pattern covering the aforementioned pattern.

[0293] The second planarization layer pattern includes at least a thirteenth via. The orthographic projection of the thirteenth via onto the substrate is within the range of the orthographic projection of the anode connection electrode onto the substrate. The sixth insulating layer within the thirteenth via is etched away, exposing the surface of the anode connection electrode. The thirteenth via is configured to allow the anode of a subsequently formed light-emitting device to be connected to the anode connection electrode through the via.

[0294] At this point, the driving structure layer is fabricated on the substrate. In a plane parallel to the display substrate, the driving structure layer may include multiple pixel circuits, which are connected to a first scan signal line, a second scan signal line, a third scan signal line, a light emission signal line, a reference signal line, an initial signal line, a data signal line, and a first power supply line. The driving structure layer may be disposed on the substrate. The driving structure layer may include, sequentially disposed on the substrate, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first planarization layer, a fifth insulating layer, a fourth conductive layer, a sixth insulating layer, and a second planarization layer.

[0295] In an exemplary embodiment, the semiconductor layer can be an amorphous silicon layer, a polycrystalline silicon layer, or a metal oxide layer. The metal oxide layer can be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer can be a single layer, a double layer, or a multilayer.

[0296] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They may be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo.

[0297] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0298] In an exemplary embodiment, the first planarization layer and the second planarization layer may be made of organic materials, such as resin.

[0299] In an exemplary embodiment, after the driving structure layer is prepared, a light-emitting structure layer is prepared on the driving structure layer. The preparation process of the light-emitting structure layer may include the following operations.

[0300] (9) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming a fifth conductive layer pattern may include: depositing a fifth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on a second planarization layer, wherein the fifth conductive layer includes at least a plurality of first electrode patterns.

[0301] In an exemplary embodiment, the fifth conductive layer pattern may include a plurality of first electrode patterns. The plurality of first electrode patterns may include a first electrode of a first light-emitting device, a first electrode of a second light-emitting device, a first electrode of a third light-emitting device, and a first electrode of a fourth light-emitting device. The first electrode of the first light-emitting device is located in a red sub-pixel emitting red light, the first electrode of the second light-emitting device may be located in a blue sub-pixel emitting blue light, the first electrode of the third light-emitting device may be located in a first green sub-pixel emitting green light, and the first electrode of the fourth light-emitting device may be located in a second green sub-pixel emitting green light.

[0302] In an exemplary embodiment, the first electrode of the first light-emitting device and the first electrode of the second light-emitting device may be alternately arranged along a second direction, and the first electrode of the third light-emitting device and the first electrode of the fourth light-emitting device may be alternately arranged along the second direction. Alternatively, the first electrode of the first light-emitting device and the first electrode of the second light-emitting device may be alternately arranged along a first direction, and the first electrode of the third light-emitting device and the first electrode of the fourth light-emitting device may be alternately arranged along the first direction.

[0303] In an exemplary embodiment, the first electrode of the first light-emitting device, the first electrode of the second light-emitting device, the first electrode of the third light-emitting device, and the first electrode of the fourth light-emitting device can be connected to the connection electrode of the sub-pixel through vias that expose the connection electrode of the sub-pixel.

[0304] In an exemplary embodiment, the shape and area of ​​the first electrodes of the four sub-pixels in a pixel unit may be the same or different.

[0305] In an exemplary embodiment, at least one of the first electrode of the first light-emitting device, the first electrode of the second light-emitting device, the first electrode of the third light-emitting device, and the first electrode of the fourth light-emitting device may include an anode body portion and an anode connection portion connected to each other, with the anode connection portion connected to a connection electrode.

[0306] In an exemplary embodiment, the first electrode of the first light-emitting device may include a first anode body portion and a first anode connecting portion connected to each other. The first anode body portion may be rectangular in shape, and the corners of the rectangle may be provided with rounded chamfers. The first anode connecting portion may be strip-shaped. In an exemplary embodiment, the first electrode of the second light-emitting device may include a second anode body portion and a second anode connecting portion connected to each other. The second anode body portion may be rectangular in shape, and the corners of the rectangle may be provided with rounded chamfers. The second anode connecting portion may be strip-shaped. In an exemplary embodiment, the first electrode of the third light-emitting device may include a third anode body portion and a third anode connecting portion connected to each other. The third anode body portion may be rectangular in shape, and the corners of the rectangle may be provided with rounded chamfers. The third anode connecting portion may be strip-shaped. In an exemplary embodiment, the first electrode of the fourth light-emitting device may include a fourth anode body portion and a fourth anode connecting portion connected to each other. The fourth anode body portion may be rectangular in shape, and the corners of the rectangle may be provided with rounded chamfers. The fourth anode connecting portion may be strip-shaped.

[0307] In an exemplary embodiment, the fifth conductive layer adopts a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or it can adopt a multi-layer composite structure, such as ITO / Ag / ITO.

[0308] (10) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming a sixth conductive layer may include: coating a pixel definition film on a substrate on which the aforementioned pattern is formed; depositing a pixel definition film on the substrate on which the aforementioned pattern is formed; patterning the pixel definition film using a patterning process to form a pixel definition layer pattern that exposes the fifth conductive layer pattern; coating an organic light-emitting material on a substrate on which the pixel definition layer pattern is formed; patterning the organic light-emitting material using a patterning process to form an organic structure layer pattern; depositing a sixth conductive film on a substrate on which the organic material layer pattern is formed; and patterning the sixth conductive film using a patterning process to form a sixth conductive layer.

[0309] In an exemplary embodiment, the subsequent fabrication process may include: forming an encapsulation structure layer on the sixth conductive layer. The encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0310] In an exemplary embodiment, the organic structure layer may include at least an organic light-emitting layer of a light-emitting device.

[0311] In an exemplary embodiment, the sixth conductive layer may include at least: the second electrode (cathode) of a plurality of light-emitting devices.

[0312] In an exemplary embodiment, the sixth conductive layer may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplarily, the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0313] The display substrate described in this embodiment can be used in display products of any resolution.

[0314] This disclosure also provides a display device, including a display substrate.

[0315] The display substrate is the same as the display substrate provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0316] In an exemplary embodiment, the display device can be any product or component with display function, such as a liquid crystal panel, electronic paper, OLED panel, active-matrix organic light emitting diode (AMOLED) panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc.

[0317] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0318] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0319] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising: The substrate and a plurality of sub-pixels disposed on the substrate, at least one sub-pixel including: a pixel circuit, the pixel circuit including: a third transistor and a plurality of transistors connected to the third transistor; the transistors include active patterns, the active patterns of at least two transistors connected to the gate electrode of the third transistor are integral structures and constitute a first active layer, the active patterns of at least two transistors connected to either the first or second electrode of the third transistor and the active pattern of the third transistor are integral structures and constitute a second active layer; The first active layer and the second active layer are arranged along a first direction and extend at least partially along a second direction, wherein the first direction intersects the second direction; The length of the first active layer along the second direction is greater than the length of the second active layer along the second direction.

2. The display substrate according to claim 1, wherein, The plurality of transistors connected to the third transistor include: a first transistor, a second transistor, a fourth transistor, and a fifth transistor, wherein the first transistor to the fifth transistor are N-type transistors; The second terminal of the first transistor is electrically connected to the second terminal of the third transistor, the second terminals of the second transistor and the second terminals of the fourth transistor are respectively electrically connected to the gate electrode of the third transistor, and the second terminal of the fifth transistor is electrically connected to the first terminal of the third transistor; The active pattern includes a channel region and a conductive region, with the conductive region of any active pattern located on both sides of the channel region; wherein, the active patterns of the second transistor and the fourth transistor constitute a first active layer, and the active patterns of the first transistor, the third transistor, and the fifth transistor constitute a second active layer. 3.The display substrate of claim 2, wherein, The active patterns of the first transistor and the fifth transistor are located on opposite sides of the active pattern of the third transistor. The active pattern of the second transistor includes a first conductive region and a second conductive region. The active pattern of the fourth transistor includes a third conductive region and a fourth conductive region. The first conductive region and the third conductive region extend along a second direction, and the second conductive region and the fourth conductive region extend along a first direction. The third conductive region is connected to the first conductive region. 4.The display substrate of claim 3, wherein, The second conductive region is located on the side of the first conductive region near the second active layer, and at least a portion of the active pattern of the first transistor is located on the side of the center line of the active layer, which is the center line of the second active layer extending along the first direction. The fourth conductive region is located on the side of the third conductive region near the second active layer, and is located on the other side of the active layer centerline along with at least a portion of the active pattern of the fifth transistor. 5.The display substrate of claim 3 or 4, further comprising: A first signal line is disposed on the substrate, at least a portion of the first signal line extends along a first direction, and the gate electrode of at least one transistor is disposed on a different layer from the first signal line; The resistivity of the film layer containing the first signal line is less than the resistivity of the film layer containing the gate electrode of the at least one transistor.

6. The display substrate according to claim 5, wherein, The gate electrode of the first transistor is spaced apart from the gate electrode of the fifth transistor; The length of the gate electrode of the third transistor along the second direction is greater than the length of the gate electrode of any one of the first transistor, the second transistor, the fourth transistor, and the fifth transistor along the second direction.

7. The display substrate according to claim 5 or 6, wherein, The pixel circuit further includes a capacitor, which includes a first plate and a second plate; the first plate of the capacitor is located on the side of the second plate of the capacitor closer to the substrate. The orthographic projection of the first plate of the capacitor onto the substrate at least partially overlaps with the first conductive region, the active pattern of the third transistor, and the orthographic projection of the third conductive region onto the substrate. 8.The display substrate of claim 7, wherein, The first signal line includes: a third scan signal line, an initial signal line, a first power supply line, and a light emission signal line; the first transistor is connected to the third scan signal line and the initial signal line respectively, and the fifth transistor is connected to the first power supply line and the light emission signal line respectively; The orthographic projection of the second plate of the capacitor onto the substrate at least partially overlaps with the orthographic projections of the third scanning signal line, the initial signal line, the first power line, the light-emitting signal line, the first plate of the capacitor, the first conductive area, and the third conductive area onto the substrate.

9. The display substrate according to claim 8, wherein, Along the second direction, the distance between the orthographic projection of the gate electrode of the second transistor on the substrate and the orthographic projection of the second plate of the capacitor on the substrate is less than the distance between the orthographic projection of the gate electrode of the second transistor on the substrate and the orthographic projection of the gate electrode of the first transistor on the substrate. The distance between the orthogonal projection of the gate electrode of the fourth transistor on the substrate and the orthogonal projection of the second plate of the capacitor on the substrate is less than the distance between the orthogonal projection of the gate electrode of the fourth transistor on the substrate and the orthogonal projection of the gate electrode of the fifth transistor on the substrate. 10.The display substrate according to claim 8 or 9, wherein The second plate of the capacitor is provided with a groove, which exposes at least a portion of the first plate, the first conductive region, and the third conductive region of the capacitor. 11.The display substrate of claim 10, wherein, Within the same sub-pixel, the opening direction of the groove is located on the side opposite to the second active layer.

12. The display substrate according to claim 10, wherein, The second plate of the capacitor includes: a capacitor body, a first capacitor connection part, and a second capacitor connection part, wherein the first capacitor connection part and the second capacitor connection part are respectively located on both sides of the capacitor body, and the groove is disposed on one side of the capacitor body. The capacitor body extends along a first direction, the first capacitor connection portion extends at least partially along a second direction, and the second capacitor connection portion extends along a second direction. The average length of the capacitor body portion along the first direction is greater than the average length of the first capacitor connection portion along the first direction, and the average length of the first capacitor connection portion along the first direction is greater than the average length of the second capacitor connection portion along the first direction.

13. The display substrate according to claim 12, wherein, The orthographic projection of the capacitor body onto the substrate at least partially overlaps with the orthographic projections of the first plate, the first conductive region, and the third conductive region of the capacitor onto the substrate; The orthographic projections of the first capacitor connection portion and the second capacitor connection portion on the substrate at least partially overlap with the orthographic projections of the first conductive region and the third conductive region on the substrate, but do not overlap with the orthographic projection of the first plate of the capacitor on the substrate.

14. The display substrate according to claim 10, wherein, The first plate of the capacitor includes: a first region and a second region; the first region is the area exposed by the groove of the second plate of the capacitor, and the second region is all regions except the first region; The orthographic projection of the second plate of the capacitor onto the substrate covers the orthographic projection of the second region of the first plate of the capacitor onto the substrate.

15. The display substrate according to claim 8, wherein, The first signal line further includes: a reference signal line, a first scan signal line, and a second scan signal line; the second transistor is connected to the second scan signal line and the reference signal line respectively; and the fourth transistor is connected to the first scan signal line. The reference signal line, the second scan signal line, the initial signal line, the third scan signal line, the light emission signal line, the first power supply line, and the first scan signal line are arranged sequentially along the first direction.

16. The display substrate according to claim 15, further comprising: A second signal line disposed on a substrate, the second signal line extending along a second direction, the second signal line including: a data signal line; The orthographic projection of the data signal line on the substrate at least partially overlaps with the orthographic projections of the first conductive region, the third conductive region, the fourth conductive region, and the second plate of the capacitor on the substrate.

17. The display substrate according to claim 16, wherein, The data signal line includes: a data signal main line and a plurality of data signal connecting lines, wherein the data signal main line extends along a second direction and the data signal connecting lines extend along a first direction; The orthographic projection of the main data signal line on the substrate at least partially overlaps with the orthographic projections of the first conductive region, the third conductive region, and the second plate of the capacitor on the substrate, and the orthographic projection of the data signal connection line on the substrate at least partially overlaps with the orthographic projection of the fourth conductive region on the substrate.

18. The display substrate according to claim 17, further comprising: A drive structure layer disposed on the substrate; The driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially stacked on the substrate; The semiconductor layer includes at least: an active pattern of a first transistor, an active pattern of a second transistor, an active pattern of a third transistor, an active pattern of a fourth transistor, and an active pattern of a fifth transistor located at at least one sub-pixel. The first conductive layer includes at least: a gate electrode of a first transistor, a gate electrode of a second transistor, a gate electrode of a third transistor, a gate electrode of a fourth transistor, a gate electrode of a fifth transistor, and a first plate of a capacitor located at at least one sub-pixel; The second conductive layer includes at least: a second electrode of a capacitor located in at least one sub-pixel; The third conductive layer includes at least: a first scan signal line, a second scan signal line, a third scan signal line, a light emission signal line, a reference signal line, a first power supply line, an initial signal line, and the second pole of a first transistor, the second pole of a second transistor, the second pole of a third transistor, and the first pole and the second pole of a fourth transistor located in at least one sub-pixel; The fourth conductive layer includes at least: data signal lines.

19. The display substrate of claim 18, wherein, The driving structure layer further includes: a first planarization layer and a fifth insulating layer located between the third conductive layer and the fourth conductive layer; The fifth insulating layer is located on the side of the first planar layer away from the substrate; The thickness of the first planarization layer is greater than the thickness of the fifth insulating layer. 20.The display substrate of claim 19, wherein, The thickness of the first planarization layer is 1.4 micrometers to 2.3 micrometers, and the thickness of the fifth insulating layer is 50 nanoangstroms to 2500 nanoangstroms. 21.The display substrate of claim 18, wherein, The thickness of the third conductive layer is greater than the thickness of the first conductive layer or the second conductive layer; The resistivity of the fourth conductive layer is less than that of the first conductive layer.

22. A display device, comprising: The display substrate as described in any one of claims 1 to 21.

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