Display panel and manufacturing method therefor, and display device

Abstract

A display panel, comprising a substrate, a display structure layer located in a display area, a plurality of data leads located in a signal access area, a plurality of contact pads, and an inorganic composite insulating layer. At least one contact pad comprises a plurality of contact pad metal layers electrically connected to each other, and the plurality of contact pad metal layers are electrically connected to one of the plurality of data leads. The inorganic composite insulating layer is located on the side of at least one of the plurality of contact pad metal layers close to the substrate. The orthographic projection of the inorganic composite insulating layer on the substrate does not overlap the orthographic projections of the plurality of contact pads on the substrate, or the orthographic projection of the inorganic composite insulating layer on the substrate at least partially overlaps the orthographic projection of the at least one contact pad on the substrate.

Description

Display panel and manufacturing method thereof, and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on April 27, 2023, with application number 202310476758.1 and invention name “Display panel, preparation method thereof, and display device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to but is not limited to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, and extremely fast response times. With the continuous advancement of display technology, display devices using OLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] Embodiments of the present disclosure provide a display panel, a method for manufacturing the same, and a display device.

[0007] In one aspect, this embodiment provides a display panel comprising: a substrate, a display structure layer, a plurality of data leads, a plurality of contact pads, and an inorganic composite insulating layer. The substrate includes a display area and a signal access area located at least on one side of the display area. The display structure layer is located on the substrate in the display area and includes a plurality of sub-pixels and a plurality of data lines, the plurality of sub-pixels and the plurality of data lines being electrically connected. The plurality of data lines are configured to provide data signals to the plurality of sub-pixels. A plurality of data leads are located in the signal access area and are connected to the plurality of data lines. A plurality of contact pads are located in the signal access area, at least one of the contact pads comprising a plurality of contact pad metal layers electrically connected to each other. The plurality of contact pad metal layers are electrically connected to one of the plurality of data leads. The inorganic composite insulating layer is located in the signal access area, and at least one of the plurality of contact pad metal layers is located on a side of the substrate proximal to the substrate. The inorganic composite insulating layer and the plurality of contact pads do not overlap in their orthographic projection onto the substrate, or the inorganic composite insulating layer and at least one of the contact pads at least partially overlap in their orthographic projection onto the substrate.

[0008] In some exemplary embodiments, the inorganic composite insulating layer is located on a side of the plurality of contact pad metal layers close to the substrate.

[0009] In some exemplary embodiments, an orthographic projection of the inorganic composite insulating layer on the substrate covers an orthographic projection of overlapping regions of the plurality of contact pad metal layers on the substrate.

[0010] In some exemplary embodiments, at least a portion of the inorganic composite insulating layer is located in a gap between adjacent contact pads.

[0011] In some exemplary embodiments, the at least one contact pad further includes: an ineffective contact pad metal layer; and the inorganic composite insulating layer is located between the plurality of contact pad metal layers of the at least one contact pad and the ineffective contact pad metal layer.

[0012] In some exemplary embodiments, an orthographic projection of the inorganic composite insulating layer on the substrate covers an orthographic projection of the inactive contact pad metal layer on the substrate.

[0013] In some exemplary embodiments, the at least one contact pad includes: a first contact pad metal layer in contact with a surface of the inorganic composite insulating layer away from the substrate; and the first contact pad metal layer is electrically connected to a data lead.

[0014] In some exemplary embodiments, the first contact pad metal layer and the one data lead are an integral structure connected to each other.

[0015] In some exemplary embodiments, the display panel further comprises: a plurality of access connection lines located in the signal access area; the first contact pad metal layer is electrically connected to the data lead via one access connection line; and the first contact pad metal layer and the one access connection line are interconnected as an integral structure.

[0016] In some exemplary embodiments, a connection position between the access connection line and the data lead is located on a side of the plurality of contact pads close to the display area.

[0017] In some exemplary embodiments, the display panel further comprises: a plurality of connection electrodes located in the signal access area; the access connection line is electrically connected to the data lead via the connection electrodes; the access connection line is located on a side of the data lead away from the substrate; and the connection electrodes are located on a side of the access connection line away from the substrate.

[0018] In some exemplary embodiments, at least one of the plurality of sub-pixels includes a pixel circuit, the pixel circuit including at least one first transistor and at least one second transistor; the first transistor and the second transistor being of different transistor types. The first transistor includes a first active layer and a first gate. The second transistor includes a second active layer and a second gate. The first active layer and the first gate of the first transistor are located on a side of the second active layer of the second transistor closer to the substrate; the second gate is located on a side of the second active layer farther from the substrate. A third gate insulating layer is disposed between the second active layer and the second gate. The inorganic composite insulating layer includes at least a fifth inorganic insulating layer disposed on the same layer as the third gate insulating layer.

[0019] In some exemplary embodiments, the pixel circuit further includes: at least one capacitor, the capacitor including a first plate and a second plate, the second plate being located on a side of the first plate away from the substrate, and the second plate being located on a side of the second active layer of the second transistor closer to the substrate. A first interlayer insulating layer is disposed between the second plate and the second active layer of the second transistor; and the inorganic composite insulating layer includes: the fifth inorganic insulating layer and a third inorganic insulating layer disposed on the same layer as the first interlayer insulating layer.

[0020] In some exemplary embodiments, a first buffer layer is further disposed between the second electrode plate and the second active layer of the second transistor, and the first interlayer insulating layer is located on a side of the first buffer layer closer to the substrate. The inorganic composite insulating layer includes: the third inorganic insulating layer, the fifth inorganic insulating layer, and a fourth inorganic insulating layer disposed on the same layer as the first buffer layer.

[0021] In some exemplary embodiments, the at least one contact pad includes: a first contact pad metal layer in contact with a surface of the inorganic composite insulating layer away from the substrate; the first contact pad metal layer and the second gate of the second transistor are in the same layer structure.

[0022] In some exemplary embodiments, the at least one contact pad further comprises: a second contact pad metal layer located on a side of the first contact pad metal layer away from the substrate. The display panel further comprises: a sixth inorganic insulating layer located in the signal access region and on a side of the fifth inorganic insulating layer away from the substrate. The sixth inorganic insulating layer and the orthographic projection of the at least one contact pad on the substrate do not overlap; alternatively, the sixth inorganic insulating layer covers an edge of the first contact pad metal layer of the at least one contact pad, and the surface of the first contact pad metal layer exposed by the sixth inorganic insulating layer contacts the second contact pad metal layer.

[0023] In some exemplary embodiments, a portion of the sixth inorganic insulating layer is disposed in a gap between adjacent contact pads.

[0024] In some exemplary embodiments, the sixth inorganic insulating layer has a ring structure covering an edge of the first contact pad metal layer.

[0025] In some exemplary embodiments, the second transistor further includes a second source and a second drain, and a second interlayer insulating layer is disposed between the second gate of the second transistor and the second source and drain. The sixth inorganic insulating layer is disposed on the same layer as the second interlayer insulating layer. The second contact pad metal layer is disposed on the same layer as the second source and drain of the second transistor.

[0026] In some exemplary embodiments, the at least one contact pad includes: a first contact pad metal layer located on a side of the inorganic composite insulating layer close to the substrate; and a second contact pad metal layer located on a side of the inorganic composite insulating layer away from the substrate, the second contact pad metal layer being connected to the first contact pad metal layer. The inorganic composite insulating layer covers an edge of the first contact pad metal layer.

[0027] In some exemplary embodiments, the inorganic composite insulating layer has a ring structure covering an edge of the first contact pad metal layer.

[0028] In some exemplary embodiments, the at least one sub-pixel further includes a light-emitting element, and the pixel circuit is electrically connected to the light-emitting element via a first switching electrode. The at least one contact pad includes a first contact pad metal layer, a second contact pad metal layer, and a third contact pad metal layer, sequentially arranged in a direction away from the substrate. The third contact pad metal layer and the first switching electrode are co-layered.

[0029] In some exemplary embodiments, the display panel further comprises: a touch structure layer located on a side of the display structure layer remote from the substrate, the touch structure layer comprising at least one touch conductive layer. The at least one contact pad further comprises: a fourth contact pad metal layer located on a side of the third contact pad metal layer remote from the substrate, the fourth contact pad metal layer and one of the touch conductive layers of the touch structure layer being co-layered.

[0030] In some exemplary embodiments, a side of the inorganic composite insulating layer is in contact with the second contact pad metal layer or the third contact pad metal layer.

[0031] In some exemplary embodiments, the display panel further includes: a first organic insulating layer located in the signal access area and on a side of the inorganic composite insulating layer away from the substrate; and a side of the inorganic composite insulating layer in contact with the first organic insulating layer.

[0032] On the other hand, this embodiment provides a display device including the display panel as described above.

[0033] On the other hand, this embodiment provides a method for manufacturing a display panel, comprising: providing a substrate, the substrate comprising a display area and a signal access area located on at least one side of the display area; forming a display structure layer in the display area, and forming a plurality of data leads, a plurality of contact pads, and an inorganic composite insulating layer in the signal access area. The display structure layer comprises a plurality of sub-pixels and a plurality of data lines, wherein the plurality of sub-pixels and the plurality of data lines are electrically connected. The plurality of data lines are configured to provide data signals to the plurality of sub-pixels; the plurality of data leads are connected to the plurality of data lines; at least one of the plurality of contact pads comprises a plurality of contact pad metal layers electrically connected to each other, wherein the plurality of contact pad metal layers are electrically connected to one of the plurality of data leads. The inorganic composite insulating layer is located on a side of at least one of the plurality of contact pad metal layers that is closer to the substrate; the inorganic composite insulating layer and the plurality of contact pads do not overlap with each other in their orthographic projection on the substrate, or the inorganic composite insulating layer and the at least one contact pad at least partially overlap with each other in their orthographic projection on the substrate.

[0034] On the other hand, this embodiment provides a display panel comprising: a substrate, a display structure layer, a plurality of data leads, a plurality of contact pads, an inorganic composite insulating layer, and a first organic insulating layer. The substrate comprises a display area and a signal access area located on at least one side of the display area. The display structure layer is located on the substrate of the display area, the display structure layer comprising a plurality of sub-pixels and a plurality of data lines, the plurality of sub-pixels and the plurality of data lines being electrically connected, the plurality of data lines being configured to provide data signals to the plurality of sub-pixels. A plurality of data leads are located in the signal access area, the plurality of data leads being connected to the plurality of data lines. A plurality of contact pads are located in the signal access area, at least one of the plurality of contact pads comprising a plurality of contact pad metal layers electrically connected to each other, the plurality of contact pad metal layers being electrically connected to one of the plurality of data leads. An inorganic composite insulating layer is located in the signal access area, the inorganic composite insulating layer being located on a side of at least one of the plurality of contact pad metal layers that is closer to the substrate. A first organic insulating layer is located in the signal access region, and the first organic insulating layer is located on a side of the inorganic composite insulating layer and at least one of the plurality of contact pad metal layers away from the substrate. A side edge of the inorganic composite insulating layer contacts the first organic insulating layer or one of the plurality of contact pad metal layers.

[0035] In some exemplary embodiments, the inorganic composite insulating layer is located on a side of the multiple contact pad metal layers close to the substrate, and an orthographic projection of the inorganic composite insulating layer on the substrate covers an orthographic projection of an overlapping region of the multiple contact pad metal layers on the substrate.

[0036] In some exemplary embodiments, the at least one contact pad further includes an ineffective contact pad metal layer, and the inorganic composite insulating layer is located between the plurality of contact pad metal layers of the at least one contact pad and the ineffective contact pad metal layer.

[0037] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0038] Summary of the Figures

[0039] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of one or more components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0040] FIG1A is a schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0041] FIG1B is another schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0042] FIG2 is a partial cross-sectional schematic diagram of a display area of ​​a display panel according to at least one embodiment of the present disclosure;

[0043] FIG3 is a partial schematic diagram of a signal access area according to at least one embodiment of the present disclosure;

[0044] FIG4 is an example diagram of a partial cross section along the PP' direction in FIG3;

[0045] FIG5 is a partial enlarged schematic diagram of area S1 in FIG3 ;

[0046] FIG6A is a schematic diagram of the first gate metal layer in FIG5 ;

[0047] FIG6B is a schematic diagram of the third gate metal layer in FIG5 ;

[0048] FIG7 is a schematic partial cross-sectional view along the QQ' direction in FIG5;

[0049] FIG8 is an example diagram of a partial enlargement of the area S2 in FIG3 ;

[0050] FIG9 is another partial cross-sectional schematic diagram along the PP' direction in FIG3;

[0051] FIG10 is another example diagram of a partial enlargement of the area S2 in FIG3 ;

[0052] FIG11 is another partial cross-sectional schematic diagram along the PP' direction in FIG3;

[0053] FIG12 is another partial cross-sectional schematic diagram along the PP' direction in FIG3;

[0054] FIG13 is another example diagram of a partial enlargement of the area S1 in FIG3 ;

[0055] FIG14A is a schematic diagram of the third gate metal layer in FIG13;

[0056] FIG14B is a schematic diagram of the first gate metal layer in FIG13;

[0057] FIG15 is a schematic partial cross-sectional view along the RR' direction in FIG13;

[0058] FIG16 is another example of a partial cross-section along the PP' direction in FIG3;

[0059] FIG17 is another example of a partial cross-section along the PP' direction in FIG3;

[0060] FIG18 is another partial schematic diagram of a signal access area according to at least one embodiment of the present disclosure;

[0061] FIG19 is a schematic diagram of the first gate metal layer in FIG18 ;

[0062] FIG20 is a schematic partial cross-sectional view along the VV' direction in FIG18;

[0063] FIG21 is a partial enlarged schematic diagram of area S3 in FIG18 ;

[0064] FIG22 is another example of a partial cross-section along the VV' direction in FIG18;

[0065] FIG. 23 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0066] Details

[0067] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0068] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0069] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0070] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0071] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the circumstances.

[0072] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0073] In this specification, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, the channel region refers to the region through which current primarily flows.

[0074] In this specification, the first electrode can be referred to as the drain and the second electrode as the source, or vice versa. The functions of "source" and "drain" are sometimes interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" can be interchanged. Furthermore, the gate electrode can also be referred to as the control electrode.

[0075] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0076] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0077] In this disclosure, the terms "approximately" and "substantially" are used without strict boundaries, allowing for process and measurement errors. In this disclosure, "substantially the same" means that the values ​​differ by no more than 10%. In this disclosure, the term "symmetrical" is used without strict boundaries, allowing for approximately symmetric values ​​within the range of process and measurement errors.

[0078] In this disclosure, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In this disclosure, "A extends along direction B" means "the main portion of A extends along direction B." In this disclosure, "A and B are an integral structure" means that A and B are interconnected and integrally formed.

[0079] Typically, after the preparation process of the display panel, it is necessary to connect the display panel to an external circuit (such as a control chip or other circuit) so that the display panel can be controlled or driven by the external circuit during the display process. For example, the external circuit may include a flexible circuit board on which a control chip or a driver chip is provided. Contact pads are provided on the display panel to be connected to the circuit of the flexible circuit board through a bonding process. If there is a step difference between the contact pad of the display panel and its surrounding area, for example, the height of the inorganic film layer in the surrounding area is large, then in the binding process, the pressure applied by the pressure head of the device for providing pressure on the display panel is unevenly distributed. The display panel may break due to uneven force. For example, the inorganic film layer in the gap between the contact pads may break under the action of the tensile stress caused by the uneven force, thereby damaging the display panel.

[0080] For example, during the manufacturing process of a display panel, a film layer (such as an insulating layer) included in the display panel can be formed by physical or chemical vapor deposition (such as plasma enhanced chemical vapor deposition (PECVD)), and the crystals in the film layer usually have defects in the microstructure. In the actual process, when there is a step difference between the contact pad and its surrounding area, the binding area will be subjected to uneven force during the binding process, resulting in stress concentration. For example, the stress is concentrated in the area where the tip (such as the corner) of the contact pad is located. This stress concentration will aggravate the crystal defects in the film layer, further making the film layer prone to breakage.

[0081] This embodiment provides a display panel comprising: a substrate, a display structure layer, multiple data leads, multiple contact pads, and an inorganic composite insulating layer. The substrate comprises a display area and a signal access area located on at least one side of the display area. The display structure layer is located on the substrate in the display area and comprises multiple sub-pixels and multiple data lines. The multiple sub-pixels and the multiple data lines are electrically connected, and the multiple data lines are configured to provide data signals to the multiple sub-pixels. Multiple data leads are located in the signal access area and are connected to the multiple data lines. Multiple contact pads are located in the signal access area, and at least one contact pad comprises multiple contact pad metal layers electrically connected to each other. The multiple contact pad metal layers are electrically connected to one of the multiple data leads. The inorganic composite insulating layer is located in the signal access area, and at least one of the multiple contact pad metal layers is located on a side of the substrate that is closer to the substrate. The inorganic composite insulating layer and the multiple contact pads do not overlap in their orthographic projection onto the substrate, or the inorganic composite insulating layer and at least one contact pad at least partially overlap in their orthographic projection onto the substrate.

[0082] The display panel provided in this embodiment can reduce the step difference between the contact pad and the peripheral film layer by setting an inorganic composite insulating layer or removing the inorganic composite insulating layer, thereby improving the film layer crack situation existing in the binding process, and can improve the stability of the binding process and the product yield of the display panel.

[0083] In some exemplary embodiments, the inorganic composite insulating layer may be located on the side of the multiple contact pad metal layers closest to the substrate. In some examples, the orthographic projection of the inorganic composite insulating layer on the substrate may cover the orthographic projection of the overlapping region of the multiple contact pad metal layers on the substrate. In this example, the inorganic composite insulating layer can be used to raise the contact pad metal layer, thereby reducing the step difference between the contact pad and the surrounding film layer, thereby improving the film layer cracking during the bonding process, thereby improving the stability of the bonding process and the product yield of the display panel.

[0084] In some exemplary embodiments, at least one contact pad may further include an inactive contact pad metal layer. An inorganic composite insulating layer may be located between the multiple contact pad metal layers and the inactive contact pad metal layer of the contact pad. In this example, the inactive contact pad metal layer is used to raise the contact pad metal layer, thereby reducing the step difference between the contact pad and the surrounding film layer. This improves film cracking during the bonding process, thereby enhancing the stability of the bonding process and the product yield of the display panel.

[0085] The solution of this embodiment is illustrated below through multiple examples.

[0086] Figure 1A is a schematic diagram of a display panel according to at least one embodiment of the present disclosure. Figure 1B is another schematic diagram of a display panel according to at least one embodiment of the present disclosure. Figures 1A and 1B are both planar schematic diagrams of the display panel before the bending process is performed.

[0087] In some examples, as shown in Figures 1A and 1B, the display panel may include: a display area AA, and a peripheral area BB surrounding the periphery of the display area AA. For example, the peripheral area BB may include: a first border area B1 located on one side of the display area AA, and border areas located on other sides of the display area AA (for example, may include a second border area B2, a third border area B3, and a fourth border area B4). The first border area B1 may be, for example, the bottom border of the display panel, the second border area B2 may be, for example, the top border of the display panel, the third border area B3 may be, for example, the left border of the display panel, and the fourth border area B4 may be, for example, the right border of the display panel.

[0088] In some examples, as shown in Figures 1A and 1B, the display area AA can be a flat area including a plurality of sub-pixels PX constituting a pixel array, and the plurality of sub-pixels PX can be configured to display a dynamic image or a still image. The display area AA can be referred to as an active area. In some examples, the display area AA can be a rectangle. However, this embodiment is not limited to this. For example, the display area AA can be other shapes such as a circle or an ellipse. In some examples, the display panel can be a flexible panel, and thus the display panel can be deformable, such as curling, bending, folding, or rolling up.

[0089] In some examples, as shown in Figures 1A and 1B, the display area AA may include at least: multiple sub-pixels PX, multiple gate lines GL, and multiple data lines DL. The multiple gate lines GL may extend along a first direction X, and the multiple data lines DL may extend along a second direction Y. The orthographic projections of the multiple gate lines GL and the multiple data lines DL on the substrate may intersect to form multiple sub-pixel areas, and a sub-pixel PX may be provided in each sub-pixel area. The multiple data lines DL may be electrically connected to the multiple sub-pixels PX, and the multiple data lines DL may be configured to provide data signals to the multiple sub-pixels PX. The multiple gate lines GL may be electrically connected to the multiple sub-pixels PX, and the multiple gate lines GL may be configured to provide gate control signals to the multiple sub-pixels PX. In some examples, the gate control signals may include scan signals and light-emitting control signals, or may include scan signals, or may include scan signals, reset control signals, and light-emitting control signals.

[0090] In some examples, as shown in FIG1A and FIG1B , the first direction X may be an extending direction (e.g., a row direction) of the gate lines GL in the display area AA, and the second direction Y may be an extending direction (e.g., a column direction) of the data lines DL in the display area AA. The first direction X and the second direction Y may intersect each other, for example, may be perpendicular to each other.

[0091] In some examples, a pixel unit in display area AA may include three sub-pixels, where the three sub-pixels are red, green, and blue. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, where the four sub-pixels are red, green, blue, and white.

[0092] In some examples, the shape of the sub-pixels can be a rectangle, a diamond, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern; when a pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally, vertically, or in a square pattern. However, this embodiment is not limited to this.

[0093] In some examples, a sub-pixel may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors. However, this embodiment is not limited to this.

[0094] In some examples, multiple transistors in the pixel circuit can use low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor uses low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor uses oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, and oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display panel, that is, an LTPS+Oxide (LTPO for short) display panel, can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0095] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, which may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0096] In some examples, the display panel may integrate a touch structure. The display panel may include: an organic light-emitting diode (OLED) display substrate, or a plasma display device (PDP) display substrate, or an electrophoretic display (EPD) display substrate. For example, the display panel may include an OLED display substrate and a touch structure. The touch structure may be provided on the encapsulation layer of the display substrate to form a touch structure on thin film encapsulation (Touch on Thin Film Encapsulation, referred to as Touch on TFE) structure. The display structure and the touch structure are integrated together, which has the advantages of being light, thin, and foldable, and can meet product requirements such as flexible folding and narrow bezels.

[0097] In some examples, the Touch on TFE structure mainly includes a Flexible Multi-Layer On Cell (FMLOC) structure and a Flexible Single-Layer On Cell (FSLOC) structure. The FMLOC structure is based on the working principle of mutual capacitance detection. Generally, two layers of metal are used to form the drive (Tx) electrode and the sense (Rx) electrode. The integrated circuit (IC) realizes touch action by detecting the mutual capacitance between the drive electrode and the sense electrode. The FSLOC structure is based on the working principle of self-capacitance (or voltage) detection. Generally, a single layer of metal is used to form the touch electrode. The integrated circuit realizes touch action by detecting the self-capacitance (or voltage) of the touch electrode.

[0098] Figure 2 is a schematic partial cross-sectional view of the display area of ​​a display panel according to at least one embodiment of the present disclosure. Figure 2 illustrates the structure of a sub-pixel in the display area as an example. In this example, the multiple transistors in the pixel circuit can be of different transistor types, for example, including low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The display panel of this example can integrate a touch structure, such as a mutual capacitance touch structure, to form an FMLOC structure.

[0099] In some examples, as shown in FIG2 , in a direction perpendicular to the display panel, the display area of ​​the display panel may include: a substrate 10, and a circuit structure layer 12, a light-emitting structure layer 13, an encapsulation structure layer 14, and a touch structure layer 15 sequentially disposed on the substrate. The display structure layer may include at least the circuit structure layer 12 and the light-emitting structure layer 13. The circuit structure layer 12 may include at least pixel circuits for multiple sub-pixels, each of which may include multiple transistors and at least one capacitor. The light-emitting structure layer 13 may include at least light-emitting elements for multiple sub-pixels.

[0100] In some examples, FIG2 illustrates an example of each sub-pixel including a first transistor 21, a second transistor 22, and a capacitor 23. The first transistor 21 and the second transistor 22 may be of different transistor types. The first transistor 21 may be a low-temperature polysilicon thin-film transistor, and the second transistor 22 may be an oxide thin-film transistor.

[0101] In some examples, the circuit structure layer 12 in the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, disposed on the substrate 10. The multiple display area metal layers of the display structure layer in this example may include: a first gate metal layer, a second gate metal layer, a third gate metal layer, a first source-drain metal layer, and a second source-drain metal layer. A first gate insulating (GI) layer 101 may be provided between the first semiconductor layer and the first gate metal layer, and a second gate insulating layer 102 may be provided between the first gate metal layer and the second gate metal layer; a first interlayer insulating (ILD) layer 103 and a first buffer layer 104 may be provided between the second gate metal layer and the second semiconductor layer, and the first buffer layer 104 may be located on the side of the first interlayer insulating layer 103 away from the substrate 10; a third gate insulating layer 105 may be provided between the second semiconductor layer and the third gate metal layer; a second interlayer insulating layer 106 may be provided between the third gate metal layer and the first source-drain metal layer; a passivation (PVX) layer 107 and a first flattening (PLN) layer 108 may be provided between the first source-drain metal layer and the second source-drain metal layer, and the first flattening layer 108 may be located on the side of the passivation layer 107 away from the substrate 10; a second flattening layer 109 may be provided on the side of the second source-drain metal layer away from the substrate 10. Among them, the first gate insulating layer 101, the second gate insulating layer 102, the first interlayer insulating layer 103, the first buffer layer 104, the third gate insulating layer 105, the second interlayer insulating layer 106 and the passivation layer 107 can be inorganic insulating layers, and the first flat layer 108 and the second flat layer 109 can be organic insulating layers. However, this embodiment is not limited to this. In other examples, a second buffer layer can be provided on the side of the first semiconductor layer close to the substrate. The second buffer layer can prevent harmful substances in the substrate from invading the interior of the display panel and can also increase the adhesion of the film layer in the display panel to the substrate. In other examples, a bottom shielding metal layer (BSM) can be provided on the side of the second buffer layer close to the substrate. The bottom shielding metal layer can be configured to at least partially cover the active layer of the transistor of the pixel circuit to prevent external light from affecting the performance of the transistor. In other examples, the passivation layer can be omitted between the first source and drain metal layer and the second source and drain metal layer, and only the first flat layer can be provided between the first source and drain metal layer and the second source and drain metal layer. In some other examples, the first buffer layer may be omitted between the second gate metal layer and the second semiconductor layer, and only the first interlayer insulating layer 103 may be provided.

[0102] In some examples, as shown in FIG2 , the first semiconductor layer in the display area may include at least a first active layer 210 of the first transistor 21. The first active layer 210 of the first transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least a first gate electrode 213 of the first transistor 21 and a first plate 231 of the capacitor 23. The orthographic projection of the first gate electrode 213 of the first transistor 21 on the substrate 10 may overlap the orthographic projection of the channel region 2100 of the first active layer 210 on the substrate 10. The second gate metal layer may include at least a second plate 232 of the capacitor 23 and a third gate electrode 224 of the second transistor 22. The orthographic projections of the second plate 232 and the first plate 231 of the capacitor 23 on the substrate 10 may at least partially overlap, for example, they may overlap. The second semiconductor layer may include at least a second active layer 220 of the second transistor 22. The third gate metal layer may include at least a second gate 223 of the second transistor 22. The orthographic projection of the second gate 223 of the second transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 on the substrate 10. The orthographic projection of the third gate 224 of the second transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 on the substrate 10. The third gate 224 may be the bottom gate of the second transistor 22, and the second gate 223 may be the top gate of the second transistor 22.

[0103] In some examples, as shown in FIG. 2 , the first source-drain metal layer may include at least a first source 211 and a first drain 212 of the first transistor 21 , and a second source 221 and a second drain 222 of the second transistor 22 . The second interlayer insulating layer 106 may have multiple pixel via holes (e.g., including a first pixel via hole, a second pixel via hole, a third pixel via hole, and a fourth pixel via hole) in the display area. The second interlayer insulating layer 106, the third gate insulating layer 105, the first buffer layer 104, the first interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the first pixel via hole may be removed to expose at least a portion of the surface of the first region 2101 of the first active layer 210. The second interlayer insulating layer 106, the third gate insulating layer 105, the first buffer layer 104, the first interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the second pixel via hole may be removed to expose at least a portion of the surface of the second region 2102 of the first active layer 210. The second interlayer insulating layer 106 and the third gate insulating layer 105 within the third and fourth pixel via holes may be removed to expose at least a portion of the surface of both ends of the second active layer 220. The first source electrode 211 of the first transistor 21 can be electrically connected to the first region 2101 of the first active layer 210 through a first pixel via, and the first drain electrode 212 can be electrically connected to the second region 2102 of the first active layer 210 through a second pixel via. The second source electrode 221 of the second transistor 22 can be electrically connected to one end of the second active layer 220 through a third pixel via, and the second drain electrode 222 of the second transistor 22 can be electrically connected to the other end of the second active layer 220 through a fourth pixel via. The second source-drain metal layer can include at least a first transition electrode 241. The first transition electrode 241 can be electrically connected to the first drain electrode 212 of the first transistor 21 of the pixel circuit through a fifth pixel via defined through the passivation layer 107 and the first planar layer 108. In this example, the first transition electrode 241 can be used to achieve electrical connection between the pixel circuit and the light-emitting element.

[0104] In some examples, the gate lines of the display area may be located in the first gate metal layer and the third gate metal layer, the data lines of the display area may be located in the second source / drain metal layer, and the high-potential power lines of the display area may be located in the second source / drain metal layer. This embodiment is not limited to this.

[0105] In some examples, as shown in FIG2 , the light-emitting structure layer 13 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element may be an anode. The first electrode 131 may be disposed on the second planar layer 109 and electrically connected to the first transfer electrode 241 through a sixth pixel via provided in the second planar layer 109. The pixel definition layer 134 is disposed on the first electrode 131 and the second planar layer 109. The pixel definition layer 134 may have multiple pixel openings, each of which may expose at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 may be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on and connected to the organic light-emitting layer 132. Driven by the first electrode 131 and the second electrode 133, the organic light-emitting layer 132 may emit light of a corresponding color.

[0106] In some examples, the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML), and one or more film layers including a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting characteristics of the organic material can be used to emit light according to the required grayscale.

[0107] In some examples, the light-emitting layers of light-emitting elements of different colors may be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. In order to reduce the difficulty of the process and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may adopt a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may adopt a common layer. In some examples, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer can be made by a one-time process (a one-time evaporation process or a one-time inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM) or an open mask (Open Mask), or by inkjet technology.

[0108] In some examples, as shown in FIG2 , the encapsulation structure layer 14 may include a stacked first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143. The first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, and the like. The second encapsulation layer 142 may be disposed between the first and third encapsulation layers 141, 143 to prevent external moisture from entering the light-emitting element. The second encapsulation layer 142 may be made of an organic material, such as a polymer material containing a desiccant or a polymer material that can block moisture, or a polymer resin to planarize the surface of the display panel and relieve stress in the first and third encapsulation layers 141, 143. It may also include a desiccant or other absorbent material to absorb intrusive water, oxygen, and other substances. However, this embodiment is not limited to this. For example, the encapsulation structure layer may have a five-layer stacked structure: inorganic / organic / inorganic / organic / inorganic.

[0109] In some examples, the touch structure layer of the display area may include: a plurality of first touch electrodes, a plurality of first connecting portions, a plurality of second touch electrodes, and a plurality of second connecting portions. The plurality of first touch electrodes may be arranged in the same layer, and adjacent first touch electrodes may be connected via the first connecting portions. The plurality of second touch electrodes may be arranged in the same layer, and adjacent second touch electrodes may be connected via the second connecting portions.

[0110] In some examples, as shown in FIG2 , in a direction perpendicular to the display panel, the touch structure layer 15 of the display area may include: a touch buffer layer (TBL) 150, a first touch conductive layer 151, a touch interlayer insulating layer (TLD) 153, a second touch conductive layer 152, and a protective layer 154, which are arranged in sequence. The touch buffer layer 150 and the touch interlayer insulating layer 153 may be inorganic insulating layers, and the protective layer 154 may be an organic insulating layer. For example, the first touch conductive layer 151 may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connecting portions. The first touch electrodes and the first connecting portions may be an integrated structure connected to each other. The second touch conductive layer 152 may include a plurality of second connecting portions. The second connecting portions may be connected to adjacent second touch electrodes through vias provided in the touch interlayer insulating layer. However, this embodiment is not limited to this. In other examples, the first touch conductive layer may include: a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of second connecting portions, wherein the second touch electrodes and the second connecting portions may be an interconnected integral structure; the second touch conductive layer may include a plurality of first connecting portions, wherein the first connecting portions may be interconnected with adjacent first touch electrodes via vias defined in the touch interlayer insulating layer. In some examples, the first touch electrodes may be drive (Tx) electrodes, and the second touch electrodes may be sense (Rx) electrodes. Alternatively, the first touch electrodes may be sense (Rx) electrodes, and the second touch electrodes may be drive (Tx) electrodes. This embodiment is not limited to this.

[0111] In some examples, the first touch electrode and the second touch electrode may have a rhombus shape, such as a regular rhombus, a horizontally elongated rhombus, or a vertically elongated rhombus. In other examples, the first touch electrode and the second touch electrode may have any one or more of a triangle, a square, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygonal shapes, which are not limited in the embodiments of the present disclosure.

[0112] In some examples, the first and second touch electrodes may be transparent conductive electrodes. In other examples, the first and second touch electrodes may be in the form of a metal mesh. The metal mesh may be formed by interweaving multiple metal wires. The metal mesh may include multiple mesh patterns, and the mesh pattern may be a polygon formed by multiple metal wires. The metal mesh-type first and second touch electrodes have advantages such as low resistance, small thickness, and fast response speed.

[0113] In some examples, as shown in FIG1A , the first border region B1 of the display panel may include: a fan-out routing region B11 and a signal access region B12 , which are sequentially arranged in a direction away from the display area AA. FIG1A illustrates only a few routing lines within the first border region. This example does not limit the number of routing lines in the first border region.

[0114] In some examples, as shown in FIG1A , the fan-out routing area B11 may be connected between the display area AA and the signal access area B12. The fan-out routing area B11 may be provided with at least a plurality of data fan-out lines 42. The plurality of data fan-out lines 42 may be electrically connected to the plurality of data lines DL in the display area AA. For example, the plurality of data fan-out lines 42 and the plurality of data lines DL may be electrically connected in a one-to-one correspondence. The plurality of data fan-out lines 42 may extend to the signal access area B12 in a fan-out routing manner. The plurality of data fan-out lines 42 and the plurality of data lines DL may be located in different film layers, and the data fan-out lines 42 may be connected to the data lines DL through vias opened in the insulating layer.

[0115] In some examples, as shown in FIG1A , the signal access area B12 may include at least one first signal access area B121. This example uses one first signal access area as an example for illustration and description. In other examples, the display panel is a large-size panel, and the display panel may include multiple first signal access areas, and the multiple first signal access areas may be arranged sequentially along the first direction X.

[0116] In some examples, as shown in FIG1A , the first signal access area B121 may also be referred to as a driver chip (IC) setting area. The first signal access area B121 may be provided with a plurality of contact pads (Bump) 31, and the plurality of contact pads 31 may be configured to be bound and connected to at least one driver chip. The driver chip may be configured to generate a drive signal required to drive the sub-pixel and provide the drive signal to the data line DL of the display area AA. For example, the drive signal may be a data signal for driving the sub-pixel. In some examples, the driver chip may be a central processing unit, a digital signal processor, a system-on-chip (SoC), etc. For example, the driver chip may also include hardware circuits and computer executable code, etc. The hardware circuit may include conventional very large scale integration (VLSI) circuits or gate arrays and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field programmable gate arrays, programmable array logic, programmable logic devices, etc.

[0117] In some examples, as shown in FIG1A , the signal access area B12 may be provided with at least a plurality of data leads 41, and the plurality of data leads 41 may be electrically connected to the plurality of data fan-out lines 42 of the fan-out routing area B11, for example, electrically connected one to one. For example, the data leads 41 and the connected data fan-out lines 42 may be an integrated structure connected to each other. The plurality of data leads 41 may extend into the first signal access area B121 and be electrically connected to the plurality of contact pads 31 in the first signal access area B121. For example, the plurality of data leads 41 may be electrically connected to the plurality of contact pads 31 one to one, or one data lead 41 may be electrically connected to at least one contact pad 31. The data leads 41 and the data fan-out lines 42 may transmit the data signals provided by the driver chip to the data lines DL of the display area.

[0118] In some examples, as shown in Figure 1A, the multiple contact pads 31 of the first signal access area B121 can be arranged in multiple rows (for example, two rows or three rows). The multiple contact pads 31 included in each row can be arranged in sequence along the first direction X, and the multiple rows of contact pads 31 can be arranged in sequence along the second direction Y. The contact pads 31 of two adjacent rows can be staggered in the first direction X. However, this embodiment is not limited to this. In other examples, the multiple contact pads of the first signal access area B121 can be arranged in a row. In this example, a row of contact pads can also be referred to as a group of contact pads.

[0119] In some examples, as shown in FIG1B , the first border region B1 of the display panel may include: a fan-out routing region B11, a bend region B13, and a signal access region B12, which are sequentially arranged in a direction away from the display area AA. FIG1B illustrates only a few routing lines within the first border region. This example does not limit the number of routing lines in the first border region.

[0120] In some examples, as shown in Figure 1B, the bending area B13 can be connected between the fan-out routing area B11 and the signal access area B12, and can be configured to bend the signal access area B12 to the back of the display area AA. The bending area B13 can be provided with at least a plurality of data bending connection lines 43. One end of the data bending connection line 43 can be connected to the data fan-out line 42 in the fan-out routing area B11, and the other end can be connected to the data lead 41 in the signal access area B12. The multiple data bending connection lines 43 can be a same-layer structure, for example, located in the first source and drain metal layer or the second source and drain metal layer. Regarding the remaining structure of the first border area B1 of this example, reference can be made to the description of the aforementioned embodiment, so it will not be repeated here.

[0121] Figure 3 is a partial schematic diagram of the signal access area of ​​at least one embodiment of the present disclosure. In some examples, the multiple contact pads 31 in the first signal access area can be divided into at least multiple groups (for example, three groups). Figure 3 is illustrated and explained by taking two groups of contact pads (for example, the first group of contact pads and the second group of contact pads) as an example. The second group of contact pads can be located on the side of the first group of contact pads away from the display area. The first group of contact pads may include a plurality of contact pads 31 arranged along the first direction X. The second group of contact pads may include a plurality of contact pads 31 arranged along the first direction X. The first group of contact pads and the second group of contact pads may be staggered in the first direction X. For example, the contact pads in the first group of contact pads and the second group of contact pads may not be aligned in the second direction Y. There are gaps between adjacent contact pads in the same group, and there are gaps between contact pads in adjacent groups. A group of contact pads in this example can be a row of contact pads. This example does not limit the number of rows of contact pads and the number of contact pads in each row.

[0122] In some examples, as shown in FIG3 , a plurality of data leads 41 may extend substantially along the second direction Y between the plurality of contact pads 31. For example, two data leads 41 may be disposed between two adjacent contact pads 31 in a group of contact pads. One data lead 41 may be electrically connected to at least one contact pad 31, for example, one data lead 41 may be connected to one contact pad 31.

[0123] FIG4 is an example of a partial cross-section taken along the P-P' direction in FIG3 . FIG4 illustrates the cross-sectional structure of a contact pad 31 as an example. In some examples, as shown in FIG3 and FIG4 , a contact pad 31 may include four stacked contact pad metal layers, for example, a first contact pad metal layer 311, a second contact pad metal layer 312, a third contact pad metal layer 313, and a fourth contact pad metal layer 314. The first contact pad metal layer 311, the second contact pad metal layer 312, the third contact pad metal layer 313, and the fourth contact pad metal layer 314 may be arranged sequentially in a direction away from the substrate 10. The first contact pad metal layer 311 may be in direct contact with the second contact pad metal layer 312, the third contact pad metal layer 313 may be in direct contact with the second contact pad metal layer 312, and the fourth contact pad metal layer 314 may be in contact with the third contact pad metal layer 313 through vias defined in the first organic insulating layer 109a, the touch buffer layer 150, and the touch interlayer insulating layer 153.

[0124] In some examples, as shown in FIG4 , the orthographic projection of the second contact pad metal layer 312 on the substrate 10 may overlap the orthographic projection of the first contact pad metal layer 311 on the substrate 10. The second contact pad metal layer 312 may cover the edge of the first contact pad metal layer 311. The orthographic projection of the third contact pad metal layer 313 on the substrate 10 may overlap the orthographic projection of the second contact pad metal layer 312 on the substrate 10. The third contact pad metal layer 313 may cover the edge of the second contact pad metal layer 312. The orthographic projection of the fourth contact pad metal layer 314 on the substrate 10 may overlap the orthographic projection of the third contact pad metal layer 313 on the substrate 10. The fourth contact pad metal layer 314 may partially contact the surface of the third contact pad metal layer 313 away from the substrate 10. In this example, the third contact pad metal layer 313 covers the edge of the second contact pad metal layer 312, and the second contact pad metal layer 312 covers the edge of the first contact pad metal layer 311, thereby maintaining the structural stability of the contact pad.

[0125] In some examples, as shown in Figure 4, the first contact pad metal layer 311 can be located in the third gate metal layer and can be in the same layer structure as the second gate of the second transistor in the display area. The second contact pad metal layer 312 can be located in the first source and drain metal layer and can be in the same layer structure as the first source and first drain of the first transistor in the display area and the second source and second drain of the second transistor. The third contact pad metal layer 313 can be located in the second source and drain metal layer and can be in the same layer structure as the first transfer electrode in the display area. The fourth contact pad metal layer 314 can be located in the second touch conductive layer, for example, can be in the same layer structure as the second connection portion of the touch structure layer in the display area. However, this embodiment is not limited to this. In other examples, the fourth contact pad metal layer can be located in the first touch conductive layer. In other examples, when the touch structure layer includes only one touch conductive layer, the fourth contact pad metal layer can be arranged in the same layer as the touch conductive layer.

[0126] In some examples, as shown in Figures 3 and 4, the contact pad 31 may further include: an invalid contact pad metal layer 310 located on the side of the multiple contact pad metal layers close to the substrate 10. The invalid contact pad metal layer 310 may be located on the side of the first contact pad metal layer 311 close to the substrate 10. The orthographic projection of the first contact pad metal layer 311 on the substrate 10 may cover the orthographic projection of the invalid contact pad metal layer 310 on the substrate 10. There is no direct electrical connection between the first contact pad metal layer 311 and the invalid contact pad metal layer 310. In this example, by providing the invalid contact pad metal layer 310, the multiple contact pad metal layers can be raised, thereby reducing the step difference between the contact pad and the surrounding film layer, and improving the film layer crack situation existing in the binding process of the driver chip.

[0127] In some examples, as shown in FIG4 , a first inorganic insulating layer 101 a may be provided on the side of the ineffective contact pad metal layer 310 close to the substrate 10. For example, the first inorganic insulating layer 101 a may be provided on the same layer as the first gate insulating layer of the display region. A second inorganic insulating layer 102 a, a third inorganic insulating layer 103 a, a fourth inorganic insulating layer 104 a, and a fifth inorganic insulating layer 105 a may be provided between the first contact pad metal layer 311 of the contact pad and the ineffective contact pad metal layer 310. The second inorganic insulating layer 102 a, the third inorganic insulating layer 103 a, the fourth inorganic insulating layer 104 a, and the fifth inorganic insulating layer 105 a may be provided sequentially in a direction away from the substrate 10. For example, the second inorganic insulating layer 102a can be set on the same layer as the second gate insulating layer of the display area, the third inorganic insulating layer 103a can be set on the same layer as the first interlayer insulating layer of the display area, the fourth inorganic insulating layer 104a can be set on the same layer as the first buffer layer of the display area, and the fifth inorganic insulating layer 105a can be set on the same layer as the third gate insulating layer of the display area.

[0128] In some examples, as shown in FIG4 , the orthographic projections of the first inorganic insulating layer 101a and the second inorganic insulating layer 102a on the substrate 10 may overlap the orthographic projections of the contact pads on the substrate 10 and may also be disposed in the spaces between adjacent contact pads. The inorganic composite insulating layer in this example may include a third inorganic insulating layer 103a, a fourth inorganic insulating layer 104a, and a fifth inorganic insulating layer 105a. The inorganic composite insulating layer is located on the side of the first contact pad metal layer 311 that is closest to the substrate 10, between the first contact pad metal layer 311 and the ineffective contact pad metal layer 310. The orthographic projection of the inorganic composite insulating layer on the substrate 10 may overlap the orthographic projection of the ineffective contact pad metal layer 310 on the substrate 10. The orthographic projection of the inorganic composite insulating layer on the substrate 10 may also overlap the orthographic projection of the overlapping region of the first contact pad metal layer 311, the second contact pad metal layer 312, the third contact pad metal layer 313, and the fourth contact pad metal layer 314 on the substrate 10. The side of the inorganic composite insulating layer contacts the second contact pad metal layer 312. The inorganic composite insulating layer of this example is disposed below the four contact pad metal layers, which can raise the four contact pad metal layers, thereby reducing the step difference between the contact pads and the surrounding film layers, and improving the film layer cracking condition that occurs during the bonding process of the driver chip.

[0129] In some examples, as shown in FIG4 , a first organic insulating layer 109 a may be provided on the side of the third contact pad metal layer 313 facing away from the substrate 10. The first organic insulating layer 109 a may, for example, be provided on the same layer as the second planar layer 109 in the display area. The orthographic projection of the first organic insulating layer 109 a on the substrate 10 may partially overlap with the orthographic projection of the third contact pad metal layer 313 on the substrate 10. For example, the first organic insulating layer 109 a may cover the edge of the third contact pad metal layer 313. The first organic insulating layer 109 a may not be provided in the gap between adjacent contact pads. A touch buffer layer 150 and a touch interlayer insulating layer 153 may be provided in sequence on the side of the first organic insulating layer 109 a facing away from the substrate 10. The orthographic projections of the touch buffer layer 150 and the touch interlayer insulating layer 153 on the substrate 10 may overlap the orthographic projection of the first organic insulating layer 109 a on the substrate 10. The fourth contact pad metal layer 314 may be electrically connected to the third contact pad metal layer 313 through via holes opened on the touch interlayer insulating layer 153 , the touch buffer layer 150 , and the first organic insulating layer 109 a .

[0130] Figure 5 is a partial enlarged schematic diagram of region S1 in Figure 3. Figure 6A is a schematic diagram of the first gate metal layer in Figure 5. Figure 6B is a schematic diagram of the third gate metal layer in Figure 5. Figure 7 is a partial cross-sectional schematic diagram along the QQ' direction in Figure 5.

[0131] In some examples, as shown in Figures 3 and 5, the signal access area may also be provided with a plurality of access connection lines 44. The plurality of access connection lines 44 may extend approximately along the second direction Y to the first signal access area B121 and be connected to the contact pads within the first signal access area B121. The plurality of data leads 41 may extend approximately along the second direction Y to the first signal access area B121. The plurality of access connection lines 44 may be electrically connected to the plurality of data leads 41, for example, the plurality of access connection lines 44 and the plurality of data leads 41 may be electrically connected one-to-one. The orthographic projections of the access connection lines 44 and the connected data leads 41 on the substrate may at least partially overlap, for example, the orthographic projections of the access connection lines 44 on the substrate may be located within the orthographic projection range of the corresponding data leads 41 on the substrate. The access connection lines 44 and the data leads 41 may be electrically connected via connection electrodes 45. The plurality of connection electrodes 45 may be located on the side of the plurality of contact pads 31 close to the display area. The plurality of connecting electrodes 45 may, for example, be located on a side of the first group of contact pads away from the second group of contact pads (i.e., a side close to the display area), and the plurality of connecting electrodes 45 may be arranged in a row along the first direction X. However, this embodiment is not limited thereto. In other examples, the plurality of connecting electrodes may be arranged in multiple rows.

[0132] In some examples, as shown in Figures 5 and 6A, multiple data leads 41 can be located in the first gate metal layer. Multiple data leads 41 can extend approximately along the second direction Y and be arranged in sequence along the first direction X. A data lead 41 and the invalid contact pad metal layer 310 of at least one contact pad can be an integrated structure connected to each other. The length L1 of the invalid contact pad metal layer 310 along the first direction X can be greater than the line width L2 of the data lead 41 (i.e., the length along the first direction X). Two data leads 41 can be set between two adjacent invalid contact pad metal layers 310. However, this embodiment is not limited to this. For example, one or more than three data leads can be set between two adjacent invalid contact pad metal layers.

[0133] In some examples, as shown in Figures 5 and 6B, multiple access connection lines 44 can be located in the third gate metal layer. Multiple access connection lines 44 can extend approximately along the second direction Y and be arranged in sequence along the first direction X. An access connection line 44 can be electrically connected to at least one contact pad. The access connection line 44 and the first contact pad metal layer 311 of the connected contact pad can be an integrated structure connected to each other. The length L3 of the first contact pad metal layer 311 along the first direction X can be greater than the line width L4 of the access connection line 44 (i.e., the length along the first direction X). Two access connection lines 44 can be set between two adjacent first contact pad metal layers 311. However, this embodiment is not limited to this. For example, one or more than three data leads can be set between two adjacent first contact pad metal layers.

[0134] In some examples, as shown in Figures 5 and 7, an access connection line 44 can be electrically connected to a data lead 41 via a connection electrode 45. The connection electrode 45 can be located on the side of the access connection line 44 and data lead 41 that is away from the substrate 10. For example, the connection electrode 45 can be located in the first source / drain metal layer. The data lead 41 can be located in the first gate metal layer, and the side of the data lead 41 that is closer to the substrate 10 can be provided with a first inorganic insulating layer 101a that is disposed in the same layer as the first gate insulating layer. The access connection line 44 can be located in the third gate metal layer. Between the data lead 41 and the access connection line 44, a second inorganic insulating layer 102a that is disposed in the same layer as the second gate insulating layer, a third inorganic insulating layer 103a that is disposed in the same layer as the first interlayer insulating layer, a fourth inorganic insulating layer 104a that is disposed in the same layer as the first buffer layer, and a fifth inorganic insulating layer 105a that is disposed in the same layer as the third gate insulating layer can be disposed in that order. A sixth inorganic insulating layer 106a can be disposed between the access connection line 44 and the connection electrode 45. For example, the sixth inorganic insulating layer 106 a may be provided on the same layer as the second interlayer insulating layer in the display region.

[0135] In some examples, as shown in Figures 5 and 7, the sixth inorganic insulating layer 106a in the signal access area can be provided with a plurality of first via holes K1 and a plurality of second via holes K2. The sixth inorganic insulating layer 106a, the fifth inorganic insulating layer 105a, the fourth inorganic insulating layer 104a, the third inorganic insulating layer 103a, and the second inorganic insulating layer 102a within the first via holes K1 can be removed to expose a portion of the surface of the data lead 41. The sixth inorganic insulating layer 106a within the second via holes K2 can be removed to expose a portion of the surface of the access connection line 44.

[0136] In some examples, as shown in Figures 5 and 7, the connecting electrode 45 can be a strip structure extending along the second direction Y. One end of the connecting electrode 45 can be electrically connected to the data lead 41 through a plurality of first vias K1 (for example, four first vias K1 arranged along the second direction Y), and the other end can be electrically connected to the access connection line 44 through a plurality of second vias K2 (for example, four second vias K2 arranged along the second direction Y). In this example, the electrical connection between the data lead 41 and the access connection line 44 is achieved through the connecting electrode 45. There is no direct electrical connection between the data lead 41 and the access connection line 44 arranged in the gap between adjacent contact pads, and the two only overlap in their orthographic projections on the substrate. A fifth inorganic insulating layer 105a, a fourth inorganic insulating layer 104a, a third inorganic insulating layer 103a, and a second inorganic insulating layer 102a can be provided between the data lead 41 and the access connection line 44 arranged in the gap between adjacent contact pads. In this example, part of the inorganic composite insulating layer (including the fifth inorganic insulating layer 105a, the fourth inorganic insulating layer 104a and the third inorganic insulating layer 103a) is located in the gap between adjacent contact pads. The orthographic projection of the inorganic composite insulating layer in the gap between adjacent contact pads on the substrate may overlap with the orthographic projection of the data lead 41 and the access connection line 44 on the substrate, for example, it may cover the orthographic projection of the data lead 41 on the substrate. The inorganic composite insulating layer in the gap between the data lead 41 and the adjacent contact pads and in the gap between adjacent data leads 41 can be removed. However, this embodiment is not limited to this. In this example, by removing the inorganic composite insulating layer in the gap between adjacent contact pads except for the location of the data lead and the access connection line, the height of the film layer surrounding the contact pad can be reduced, thereby reducing the step difference between the contact pad and the surrounding film layer, and improving the film layer crack situation existing in the binding process of the driver chip.

[0137] In some examples, as shown in FIG5 , the orthographic projection of the sixth inorganic insulating layer 106a in the signal access area onto the substrate may partially overlap with the orthographic projections of the multiple data leads 41 and the multiple access connection lines 44 onto the substrate, while the orthographic projection of the sixth inorganic insulating layer 106a onto the substrate may not overlap with the orthographic projections of the multiple contact pads 31 onto the substrate. The orthographic projections of the data leads 41 and the access connection lines 44 between the sixth inorganic insulating layer 106a and the multiple contact pads 31 onto the substrate may not overlap. For example, the signal access area may include a first signal access area B121 and a second area B122 located on a side of the first signal access area B121 closer to the display area. The multiple contact pads 31 may be located in the first signal access area B121, and the multiple connection electrodes 45 may be located in the second area B122. The sixth inorganic insulating layer 106a within the first signal access area B121 may be removed, while the sixth inorganic insulating layer 106 within the second area B122 may remain. In this example, the sixth inorganic insulating layer is not set in the first signal access area B121 (including the location of the contact pad and the spacing area between the contact pads), which can improve the step difference between the contact pad and the surrounding film layer; moreover, the risk of short circuit caused by metal over-etching caused by the etching process of the sixth inorganic insulating layer in the first signal access area B121 can be avoided.

[0138] The following is an exemplary description of the preparation process of the display panel with reference to Figures 2 to 7. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0139] The phrase "A and B are co-layered" or "A and B are co-layered" in this disclosure means that A and B are formed simultaneously through the same patterning process. The "thickness" of the film layer refers to the dimension of the film layer perpendicular to the display panel, and the "height" of the film layer refers to the distance between the surface of the film layer facing away from the substrate and the plane of the substrate. In exemplary embodiments of this disclosure, "the orthographic projection of A includes the orthographic projection of B" or "the orthographic projection of B is within the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0140] In some examples, the process of preparing a display panel may include the following operations.

[0141] (1) Provide a substrate. In some examples, the substrate 10 may be a flexible substrate, for example, including a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier. The first flexible material layer and the second flexible material layer may be made of materials such as polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The first inorganic material layer and the second inorganic material layer may be made of silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate. The first inorganic material layer and the second inorganic material layer may also be referred to as a barrier layer. However, this embodiment is not limited to this.

[0142] In some examples, taking the laminated structure of the first flexible material layer / first barrier layer / second barrier layer / second flexible material layer as an example, the preparation process includes: first coating a layer of polyimide on a glass carrier, and curing it into a film to form a first flexible material layer; then depositing a barrier film on the first flexible material layer to form a first barrier layer covering the first flexible layer; then coating another layer of polyimide on the first barrier layer, and curing it into a film to form a second flexible material layer; then depositing a barrier film on the second flexible material layer to form a second barrier layer covering the second flexible material layer, thereby completing the preparation of the flexible substrate 10.

[0143] (2) Preparing a first semiconductor layer on a substrate. In some examples, a first semiconductor thin film is deposited on a substrate and patterned using a patterning process to form a first semiconductor layer. As shown in FIG. 2 , the first semiconductor layer can be formed in a display region and include at least a first active layer 210 of a first transistor 21.

[0144] (3) Prepare a first gate metal layer on a substrate. In some examples, a first insulating film and a first conductive film are sequentially deposited on a substrate forming the aforementioned structure, and the first conductive film is patterned by a patterning process to form a first gate metal layer disposed on the first insulating film. The first insulating film can form a first gate insulating layer 101 in the display area and a first inorganic insulating layer 101a in the signal access area. As shown in Figures 2, 4 and 7, the first gate metal layer can include at least: a first gate 213 of a first transistor 21 located in the display area, a first electrode 231 of a capacitor 23, and a data lead 41 and an ineffective contact pad metal layer 310 located in the signal access area. A data lead 41 and at least one ineffective contact pad metal layer 310 can be an integrated structure connected to each other.

[0145] (4) Prepare a second gate metal layer on the substrate. In some examples, a second insulating film is deposited on the substrate forming the aforementioned structure to form a second gate insulating layer 102 located in the display area and a second inorganic insulating layer 102a located in the signal access area. Subsequently, a second conductive film is deposited and patterned by a patterning process to form a second gate metal layer. As shown in Figures 2, 4, and 7, the second gate metal layer may include at least: a second electrode 232 of the capacitor 23 located in the display area and a third gate 224 of the second transistor 22.

[0146] (5) Prepare a second semiconductor layer on the substrate. In some examples, a third insulating film, a fourth insulating film, and a second semiconductor film are deposited on the substrate forming the aforementioned structure, and the second semiconductor film is patterned by a patterning process to form a second semiconductor layer. As shown in Figures 2, 4, and 7, the second semiconductor layer may include at least: a second active layer 220 of the second transistor 22 located in the display area. The third insulating film may form a first interlayer insulating layer 103 in the display area and a third inorganic insulating layer 103a in the signal access area. The fourth insulating film may form a first buffer layer 104 in the display area and a fourth inorganic insulating layer 104a in the signal access area.

[0147] (6) Prepare a third gate metal layer on the substrate. In some examples, a fifth insulating film and a third conductive film are sequentially deposited on the substrate forming the aforementioned structure, and the third conductive film is patterned by a patterning process to form a third gate metal layer. As shown in Figures 2, 4 and 7, the third gate metal layer may include at least: a second gate 223 of the second transistor 22 located in the display area, an access connection line 44 located in the signal access area, and a first contact pad metal layer 311 of the contact pad 31. The access connection line 44 and the connected first contact pad metal layer 311 may be an integrated structure connected to each other. The fifth insulating film may form a third gate insulating layer 105 in the display area and a fifth inorganic insulating layer 105a in the signal access area.

[0148] In some examples, after forming the third gate metal layer, the fifth insulating film, the fourth insulating film, and the third insulating film in the signal access region can be etched to form the fifth inorganic insulating layer 105 a, the fourth inorganic insulating layer 104 a, and the third inorganic insulating layer 103 a. For example, in the signal access region, the fifth insulating film, the fourth insulating film, and the third insulating film that are not blocked by the third gate metal layer can be etched away.

[0149] In some examples, the fourth inorganic insulating layer 104 a may have a thickness of approximately 2000 angstroms to 4000 angstroms, and the fifth inorganic insulating layer 105 a may have a thickness of approximately 1000 angstroms to 2000 angstroms, which is not limited in this embodiment.

[0150] (7) Prepare a second interlayer insulating layer and a sixth inorganic insulating layer on the substrate. In some examples, a sixth insulating film is deposited on the substrate forming the aforementioned structure, and the sixth insulating film is patterned by a patterning process to form a second interlayer insulating layer 106 in the display area and a sixth inorganic insulating layer 106a in the signal access area. For example, the second interlayer insulating layer in the display area may be provided with a plurality of pixel vias (for example, including a first pixel via to a fourth pixel via). The sixth inorganic insulating layer 106a in the signal access area may be provided with a plurality of vias (for example, including a first via and a second via). In some examples, the sixth inorganic insulating layer 106a in the first signal access area B121 may be removed. In some examples, the thickness of the sixth inorganic insulating layer may be approximately 4000 angstroms to 6000 angstroms.

[0151] (8) Prepare a first source-drain metal layer on the substrate. In some examples, a fourth conductive film is deposited on the substrate forming the aforementioned structure, and the fourth conductive film is patterned by a patterning process to form a first source-drain metal layer. As shown in Figures 2, 4 and 7, the first source-drain metal layer may include at least: a first source 211 and a first drain 212 of the first transistor 21 located in the display area, a second source 221 and a second drain 222 of the second transistor 22, and a second contact pad metal layer 312 of the connecting electrode 45 and the contact pad 31 located in the signal access area. The first source 211 and the first drain 212 of the first transistor 21 may be connected to the two ends of the first active layer 210 of the first transistor 21 through the first pixel via and the second pixel via, respectively, and the second source 221 and the second drain 222 of the second transistor 22 may be connected to the two ends of the second active layer 220 of the second transistor 22 through the third pixel via and the fourth pixel via, respectively. The connection electrode 45 can be electrically connected to the data lead 41 located on the first gate metal layer and the access connection line 44 located on the third gate metal layer through at least one first via K1 and at least one second via K2. Because the sixth inorganic insulating layer within the first signal access region is removed, the second contact pad metal layer 312 of the contact pad can directly contact the first contact pad metal layer 311 located on the third gate metal layer, achieving electrical connection. The second contact pad metal layer 312 can cover the edge of the first contact pad metal layer 311 and can also contact the side of the inorganic composite insulating layer, not only ensuring the stability of the contact pad metal layer stacking, but also protecting the first contact pad metal layer 311.

[0152] (9) Prepare a second source-drain metal layer on the substrate. In some examples, a seventh insulating film is deposited on the substrate forming the aforementioned structure to form a passivation layer 107, and then an eighth insulating film is coated, and the eighth insulating film is patterned by a patterning process to form a first flat layer 108. For example, the passivation layer 107 and the first flat layer 108 in the signal access area can both be removed. As shown in FIG2 , the first flat layer 108 in the display area can be provided with a fifth pixel via, and the passivation layer 107 and the first flat layer 108 in the fifth pixel via can be removed to expose a portion of the surface of the first drain 212 of the first transistor 21 of the pixel circuit.

[0153] In some examples, a sixth conductive film is deposited on a substrate forming the aforementioned structure, and the sixth conductive film is patterned by a patterning process to form a second source-drain metal layer. As shown in Figures 2, 4, and 7, the second source-drain metal layer may include at least: a first transfer electrode 241 located in the display area, and a third contact pad metal layer 313 of the contact pad 31 located in the signal access area. The first transfer electrode 241 can be electrically connected to the first drain 212 of the first transistor 21 of the pixel circuit through a fifth pixel via. Since the passivation layer 107 and the first flat layer 108 in the first signal access area are removed, the third contact pad metal layer 313 of the contact pad can directly contact the second contact pad metal layer 312 located in the first source-drain metal layer to achieve electrical connection. The third contact pad metal layer 313 can cover the edge of the second contact pad metal layer 312, which not only ensures the stability of the stacking of the contact pad metal layers, but also protects the first contact pad metal layer 311 and the second contact pad metal layer 312.

[0154] (10) Prepare a second flat layer on the substrate. In some examples, a ninth insulating film is coated on the substrate forming the aforementioned structure, and the ninth insulating film is patterned by a patterning process to form a second flat layer 109 located in the display area and a first organic insulating layer 109a located in the signal access area. As shown in FIG2 , the second flat layer 109 in the display area can be provided with a sixth pixel via hole, and the second flat layer 109 in the sixth pixel via hole can be removed to expose a portion of the surface of the first transfer electrode 241. The first organic insulating layer 109a in the signal access area can cover the edge of the third contact pad metal layer 311 and expose a portion of the surface of the third contact pad metal layer 311 away from the substrate 10. The first organic insulating layer 109a between adjacent contact pads can be removed.

[0155] At this point, the circuit structure layer of the display area is completed on the substrate.

[0156] In some examples, the first insulating film, the second insulating film, the third insulating film, the fourth insulating film, the fifth insulating film, the sixth insulating film, and the seventh insulating film can be made of inorganic materials, for example, any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer. The eighth insulating film and the ninth insulating film can be made of organic materials, for example, organic materials such as polyimide, acrylic, or polyethylene terephthalate. The first gate metal layer, the second gate metal layer, and the third gate metal layer can be made of metal materials, for example, any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), and can be a single layer structure. For example, the first gate metal layer, the second gate metal layer, and the third gate metal layer can each include a Mo metal layer. The first source-drain metal layer and the second source-drain metal layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti. For example, the first source-drain metal layer and the second source-drain metal layer can adopt a three-layer stacked structure of Ti / Al / Ti. The first semiconductor layer can be made of one or more materials such as amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene, etc., and the second semiconductor layer can be made of one or more materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), etc., that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology and organic technology. This embodiment is not limited to this.

[0157] (11) Prepare a light-emitting structure layer on a substrate. In some examples, a transparent conductive film is deposited on the substrate 10 forming the aforementioned structure, and the transparent conductive film is patterned by a patterning process to form a pattern of the first electrode 131 of the light-emitting element. A pixel definition film is coated on the substrate 10 forming the aforementioned structure, and a pixel definition layer (PDL, Pixel Definition Layer) 134 pattern is formed by masking, exposing, and developing processes. As shown in FIG2 , a pixel opening is opened on the pixel definition layer 134 of the display area AA, and the pixel definition film in the pixel opening is developed away to expose at least part of the surface of the first electrode 131. For example, the pixel definition layer 134 can be made of an organic material such as polyimide, acrylic, or polyethylene terephthalate.

[0158] Subsequently, an organic light-emitting layer 132 and a second electrode 133 are sequentially formed on the substrate 10 on which the aforementioned pattern is formed. As shown in FIG2 , the organic light-emitting layer 132 may include a stacked hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, and is formed within the pixel opening of the display area AA to connect the organic light-emitting layer 132 to the first electrode 131. Since the first electrode 131 is connected to the first drain electrode 212 of the first transistor 21, light emission control of the organic light-emitting layer 132 is achieved. A portion of the second electrode 133 may be formed on the organic light-emitting layer 132. After the light-emitting structure layer 13 is formed in the display area AA, the film structure of the signal access area may not change.

[0159] (12) Prepare an encapsulation structure layer. In some examples, an encapsulation structure layer 14 is formed on the substrate 10 on which the aforementioned pattern is formed. As shown in FIG2 , the encapsulation structure layer 14 can be formed in the display area AA and can adopt a laminated structure of inorganic material / organic material / inorganic material. The organic material layer can be disposed between two inorganic material layers. After the encapsulation structure layer 14 is formed, the film layer structure of the signal access area can remain unchanged.

[0160] (13) Prepare a touch structure layer. In some examples, a first touch insulating film is deposited on a substrate forming the aforementioned structure, and the first touch insulating film is patterned by a patterning process, and the touch buffer layer 150 is formed, as shown in FIG2 and FIG4. The touch buffer layer in the signal access area may be provided with a via exposing the surface of the third contact pad metal layer 313. In some examples, the touch buffer layer 150 may be made of an inorganic insulating material, for example, any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer.

[0161] Subsequently, a first touch conductive film is deposited and patterned through a patterning process to form a first touch conductive layer 151. For example, the first touch conductive layer may include at least touch electrodes located in the display area. After the first touch conductive layer is formed, the film structure in the signal access area may remain unchanged.

[0162] Subsequently, a touch interlayer insulating film is applied and patterned through a patterning process to form a touch interlayer insulating layer 153 covering the first touch conductive layer 151. The touch interlayer buffer layer 153 in the signal access area may be provided with vias that expose the surface of the third contact pad metal layer 313. In some examples, the touch interlayer insulating layer 153 may be made of an inorganic insulating material, such as one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or a composite layer.

[0163] Subsequently, a second touch conductive film is deposited and patterned through a patterning process to form a second touch conductive layer 152 on the touch interlayer insulating layer 153. For example, as shown in Figures 2, 4, and 7, the second touch conductive layer 152 may include at least a second connection portion located in the display area and a fourth contact pad metal layer 314 located in the signal access area. The fourth contact pad metal layer 314 may be connected to the third contact pad metal layer 313 located in the second source / drain metal layer through vias defined in the touch interlayer insulating layer 153, the touch buffer layer 150, and the first organic insulating layer 109a.

[0164] In some examples, the first touch conductive layer 151 and the second touch conductive layer 152 can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), and can be a single-layer structure or a stacked-layer structure.

[0165] Subsequently, a protective film is applied and patterned by a patterning process to form a protective layer 154. For example, the protective layer 154 in the first signal access area can be removed to expose the surface of the fourth contact pad metal layer 314 for easy bonding and connection of the driver chip.

[0166] The contact pad of this example may include four stacked contact pad metal layers. Forming the contact pad by providing multiple stacked contact pad metal layers can help reduce the contact pad resistance and improve the signal transmission performance of the contact pad.

[0167] After research, the inventors found that: compared with display panels in which multiple transistors in the pixel circuit are of the same type, the pixel circuit of the display panel of this example includes two different types of transistors. Therefore, the display structure layer adds a film layer where the second active layer and the second gate of the second transistor are located, a film layer between the second active layer and the second gate, and an insulating layer between the second active layer and the second gate and other conductive film layers. For example, the newly added film layers may include: a first buffer layer 104, a third gate insulating layer 105, and a second interlayer insulating layer 106, wherein the thickness of the first buffer layer 104 can be approximately 2000 angstroms to 4000 angstroms, the thickness of the third gate insulating layer 105 can be approximately 1000 angstroms to 2000 angstroms, and the thickness of the second interlayer insulating layer 106 can be approximately 4000 angstroms to 6000 angstroms. Therefore, the total thickness of the newly added film layers can be approximately 9000 angstroms to 1 micron. When these newly added film layers are set in the signal access area, they will affect the step difference between the contact pad and the surrounding film layer, thereby causing the risk of cracking the film layer surrounding the contact pad during the driver chip bonding process, affecting the product yield. This example improves the step difference between the contact pad and the surrounding film layer by adjusting the arrangement of these newly added film layers in the signal access area, thereby reducing the risk of cracks in the film layer surrounding the contact pad of the driver chip during the bonding process.

[0168] The display panel of this example utilizes an ineffective contact pad metal layer and an inorganic composite insulating layer to increase the height of the contact pad, thereby reducing the step difference between the contact pad and the surrounding film layer, thereby improving the film layer cracking condition that occurs during the bonding process of the driver chip, thereby improving the stability of the bonding process and the product yield.

[0169] The display panel of this example can reduce the step difference between the contact pad and the surrounding film layer by removing part of the inorganic composite insulating layer in the spacing area between adjacent contact pads, thereby improving the film layer crack situation that occurs during the bonding process of the driver chip, thereby improving the stability of the bonding process and the product yield.

[0170] The display panel of this example can reduce the step difference between the contact pad and the surrounding film layer by removing the sixth inorganic insulating layer in the first signal access area. Moreover, it can avoid the risk of short circuit caused by metal over-etching during the etching process of the sixth inorganic insulating layer in the first signal access area, thereby improving the stability of the binding process and the product yield.

[0171] Fig. 8 is an example of a partial enlarged view of the region S2 in Fig. 3. Fig. 9 is another partial cross-sectional view along the PP' direction in Fig. 3.

[0172] In some examples, as shown in Figures 8 and 9, a contact pad 31 may include four stacked contact pad metal layers, for example, a first contact pad metal layer 311, a second contact pad metal layer 312, a third contact pad metal layer 313, and a fourth contact pad metal layer 314. The first contact pad metal layer 311, the second contact pad metal layer 312, the third contact pad metal layer 313, and the fourth contact pad metal layer 314 may be arranged sequentially in a direction away from the substrate 10. The second contact pad metal layer 312 may contact the first contact pad metal layer 311 through a via formed in the sixth inorganic insulating layer 106a. The orthographic projection of the second contact pad metal layer 312 on the substrate 10 may overlap the orthographic projection of the first contact pad metal layer 311 on the substrate 10. The third contact metal layer 313 can directly contact the second contact metal layer 312. The orthographic projection of the third contact metal layer 313 on the substrate 10 can overlap the orthographic projection of the second contact metal layer 312 on the substrate 10, and the third contact metal layer 313 can cover the edge of the second contact metal layer 312. The orthographic projection of the fourth contact metal layer 314 on the substrate 10 can overlap the orthographic projection of the third contact metal layer 313 on the substrate 10. The fourth contact metal layer 314 can contact the third contact metal layer 313 through vias defined in the first organic insulating layer 109a, the touch buffer layer 150, and the touch interlayer insulating layer 153. The contact pad 31 may further include an inactive contact metal layer 310 located on the side of the first contact metal layer 311 closer to the substrate 10.

[0173] 8 and 9 , the sixth inorganic insulating layer 106a of the signal access region may be disposed between adjacent contact pads 31. For example, the sixth inorganic insulating layer 106a may cover the edge of the first contact pad metal layer 311 of the contact pad 31 and may also cover the access connection line 44.

[0174] In some examples, as shown in Figures 8 and 9, both the data lead 41 and the access connection line 44 extend between adjacent contact pads 31 in the first signal access area. A second inorganic insulating layer 102a, a third inorganic insulating layer 103a, a fourth inorganic insulating layer 104a, and a fifth inorganic insulating layer 105a may be sequentially disposed between the data lead 41 and the access connection line 44. A second inorganic insulating layer 102a, a third inorganic insulating layer 103a, a fourth inorganic insulating layer 104a, and a fifth inorganic insulating layer 105a may be sequentially disposed between the first contact pad metal layer 311 and the inactive contact pad metal layer 310. The inorganic composite insulating layer in this example may include a second inorganic insulating layer 102a, a third inorganic insulating layer 103a, a fourth inorganic insulating layer 104a, and a fifth inorganic insulating layer 105a. The orthographic projection of the inorganic composite insulating layer on the substrate may overlap the orthographic projection of the contact pad on the substrate. The orthographic projection of the inorganic composite insulating layer on the substrate may overlap the space between adjacent contact pads. In some examples, the thickness of the inorganic composite insulating layer below the first contact pad metal layer 311 can be substantially the same as the thickness of the inorganic composite insulating layer in the spaced region between adjacent contact pads. In other examples, the thickness of the inorganic composite insulating layer below the first contact pad metal layer 311 can be greater than the thickness of the inorganic composite insulating layer in the spaced region between adjacent contact pads. For example, the inorganic composite insulating layer in the spaced region between adjacent contact pads can be thinned, for example, by reducing the thickness of at least one of the third inorganic insulating layer 103a, the fourth inorganic insulating layer 104a, and the fifth inorganic insulating layer 105a in the inorganic composite insulating layer.

[0175] The display panel of this example utilizes an invalid contact pad metal layer located in the first gate metal layer, or can utilize an invalid contact pad metal layer and an inorganic composite insulating layer to increase the height of the contact pad, thereby reducing the step difference between the contact pad and the surrounding film layer, thereby improving the film layer crack situation that occurs during the binding process of the driving chip, thereby improving the stability of the binding process and the product yield.

[0176] The remaining structures of the display panel of this example can be referred to the description of the aforementioned embodiment, and thus will not be described again here.

[0177] Fig. 10 is another example of a partial enlarged view of the region S2 in Fig. 3. Fig. 11 is another partial cross-sectional view along the PP' direction in Fig. 3.

[0178] In some examples, as shown in Figures 10 and 11, a contact pad 31 may include four stacked contact pad metal layers, for example, a first contact pad metal layer 311, a second contact pad metal layer 312, a third contact pad metal layer 313, and a fourth contact pad metal layer 314, sequentially arranged in a direction away from the substrate 10. The contact pad 31 may also include an inactive contact pad metal layer 310 located on a side of the first contact pad metal layer 311 closer to the substrate 10. A second inorganic insulating layer 102a, a third inorganic insulating layer 103a, a fourth inorganic insulating layer 104a, and a fifth inorganic insulating layer 105a may be sequentially arranged between the inactive contact pad metal layer 310 and the first contact pad metal layer 311. The inorganic composite insulating layer in this example may include a second inorganic insulating layer 102a, a third inorganic insulating layer 103a, a fourth inorganic insulating layer 104a, and a fifth inorganic insulating layer 105a. The orthographic projection of the inorganic composite insulating layer on the substrate may at least cover the orthographic projection of the overlapping region of the four contact pad metal layers and the ineffective contact pad metal layer on the substrate. The side of the inorganic composite insulating layer may contact the first organic insulating layer 109a.

[0179] In some examples, as shown in Figures 10 and 11, a sixth inorganic insulating layer 106a may be disposed between the first contact pad metal layer 311 and the second contact pad metal layer 312 of the contact pad 31. The sixth inorganic insulating layer 106a may cover the edge of the first contact pad metal layer 311. The sixth inorganic insulating layer 106a may have a via hole that exposes the surface of the middle portion of the first contact pad metal layer 311 to facilitate connection between the second contact pad metal layer 312 and the first contact pad metal layer 311. The sixth inorganic insulating layer 106a may form an annular structure, such as a quadrilateral annular structure, surrounding the edge of the first contact pad metal layer 311. The sixth inorganic insulating layer 106a may also cover the edge of the access connection line 44 and expose the middle portion of the access connection line 44. In other words, the edge of the second gate metal layer within the first signal access region may be covered by the sixth inorganic insulating layer 106a. The gap between the contact pad and the adjacent access connection line, or the gap between adjacent access connection lines, may not be provided with the sixth inorganic insulating layer 106a.

[0180] In some examples, as shown in FIG11 , the coverage length of the sixth inorganic insulating layer 106a on the single-sided edge of the first contact pad metal layer 311 may be a first length d1. The first length d1 may be approximately 2.5 microns to 3.5 microns, for example, approximately 3 microns. The length of the sixth inorganic insulating layer 106a on the single-sided edge of the first contact pad metal layer 311 that does not cover the first contact pad metal layer 311 may be a second length d2. The second length may be approximately 1 micron to 2 microns, for example, approximately 1.5 microns. The coverage length of the sixth inorganic insulating layer 106a on the single-sided edge of the access connection line may be less than the coverage length on the single-sided edge of the first contact pad metal layer, and the length of the sixth inorganic insulating layer 106a on the single-sided edge of the access connection line that does not cover the access connection line may be approximately the same as the second length. This embodiment is not limited to this.

[0181] In this example, the display panel utilizes a sixth inorganic insulating layer to provide annular coverage and protection around the edges of the first contact pad metal layer. This sixth inorganic insulating layer is positioned between adjacent contact pads, but is not integrally connected. The inorganic composite insulating layer is also positioned between adjacent contact pads, but is not integrally connected. This prevents cracks from occurring during the driver chip bonding process by blocking the fracture path of the inorganic film layer.

[0182] The remaining structures of the display panel of this example can be referred to the description of the aforementioned embodiment, and thus will not be described again here.

[0183] FIG12 is another partial cross-sectional schematic diagram along the P-P' direction in FIG3 . In some examples, as shown in FIG12 , a contact pad 31 may include four stacked contact pad metal layers, for example, including a first contact pad metal layer 311, a second contact pad metal layer 312, a third contact pad metal layer 313, and a fourth contact pad metal layer 314 sequentially arranged in a direction away from the substrate 10. The first contact pad metal layer 311 may be located in the third gate metal layer, the second contact pad metal layer 312 may be located in the first source / drain metal layer, the third contact pad metal layer 313 may be located in the second source / drain metal layer, and the fourth contact pad metal layer 314 may be located in the second touch conductive layer. The contact pad 31 may also include an ineffective contact pad metal layer 310 located on the side of the first contact pad metal layer 311 close to the substrate 10. The ineffective contact pad metal layer 310 may be located in the second gate metal layer.

[0184] In some examples, as shown in FIG12 , a third inorganic insulating layer 103 a, a fourth inorganic insulating layer 104 a, and a fifth inorganic insulating layer 105 a may be disposed sequentially between the inactive contact pad metal layer 310 and the first contact pad metal layer 311 in a direction away from the substrate 10. The inactive contact pad metal layer 310 may be interconnected with a data lead 41 as an integral structure, and the first contact pad metal layer 311 may be interconnected with a connected access connection line 44 as an integral structure. The third inorganic insulating layer 103 a, the fourth inorganic insulating layer 104 a, and the fifth inorganic insulating layer 105 a may be disposed between the data lead 41 and the access connection line 44.

[0185] In some examples, as shown in FIG12 , the inorganic composite insulating layer may include: a third inorganic insulating layer 103a, a fourth inorganic insulating layer 104a, and a fifth inorganic insulating layer 105a, sequentially disposed in a direction away from the substrate 10. The orthographic projection of the inorganic composite insulating layer on the substrate may at least cover the orthographic projection on the substrate 10 of the overlapping region of the four contact pad metal layers and the inactive contact pad metal layer 310. The inorganic composite insulating layer may be partially disposed in the spaces between adjacent contact pads. The inorganic composite insulating layer in the spaces between contact pads and adjacent access connection lines, and in the spaces between adjacent access connection lines, may be removed. The side edges of the inorganic composite insulating layer may contact the third contact pad metal layer 313. The third contact pad metal layer 313 may cover the edges of the second contact pad metal layer 312 and the first contact pad metal layer 311 on the substrate 10, thereby maintaining the structural stability of the contact pads and protecting the first contact pad metal layer 311 and the second contact pad metal layer 312.

[0186] In some examples, as shown in FIG12 , the sixth inorganic insulating layer in the first signal access region may be entirely removed. The second contact pad metal layer 312 may be in direct contact with the first contact pad metal layer 311 .

[0187] The display panel of this example utilizes the ineffective contact pad metal layer and the inorganic composite insulating layer located in the second gate metal layer to increase the height of the contact pad, and removes the sixth inorganic insulating layer in the first signal access area as a whole, thereby reducing the step difference between the contact pad and the surrounding film layer, thereby improving the film layer cracks that occur during the binding process of the driving chip, thereby improving the stability of the binding process and the product yield.

[0188] The remaining structures of the display panel of this example can be referred to the description of the aforementioned embodiment, and thus will not be described again here.

[0189] In other examples, the features of the above embodiments may be combined with each other. For example, the first contact pad metal layer of the contact pad may be located in the third gate metal layer, the inactive contact pad metal layer may be located in the second gate metal layer, and the sixth inorganic insulating layer may cover the edge of the first contact pad metal layer, or the sixth inorganic insulating layer may form a ring structure covering the edge of the first contact pad metal layer.

[0190] Figure 13 is another example of a partial enlarged view of region S1 in Figure 3. Figure 14A is a schematic diagram of the third gate metal layer in Figure 13. Figure 14B is a schematic diagram of the first gate metal layer in Figure 13. Figure 15 is a schematic diagram of a partial cross-section taken along the R-R' direction in Figure 13. Figure 16 is another example of a partial cross-section taken along the P-P' direction in Figure 3.

[0191] In some examples, as shown in Figures 13 to 16, the plurality of data leads 41 do not extend between adjacent contact pads 31, nor do they extend under the contact pads 31. The plurality of data leads 41 are electrically connected to the plurality of access connection lines 44, and the plurality of access connection lines 44 are electrically connected to the plurality of contact pads 31. The plurality of data leads 41 can be electrically connected to the plurality of contact pads 31 through the plurality of access connection lines 44.

[0192] In some examples, as shown in Figures 13 to 16, multiple data leads 41 can be located in the first gate metal layer, and multiple access connection lines 44 can be located in the third gate metal layer. For example, the orthographic projections of the access connection lines 44 and the data leads 41 on the substrate may not overlap. The data leads 41 can be electrically connected to the access connection lines 44 via a connection electrode 45. For example, one end of the connection electrode 45 located in the first source / drain metal layer can be electrically connected to the data leads 41 located in the first gate metal layer via a plurality of first vias K1, and the other end can be electrically connected to the access connection lines 44 located in the third gate metal layer via a plurality of second vias K2.

[0193] In some examples, as shown in FIG16 , a contact pad 31 may include four stacked contact pad metal layers, for example, a first contact pad metal layer 311, a second contact pad metal layer 312, a third contact pad metal layer 313, and a fourth contact pad metal layer 314, sequentially arranged in a direction away from the substrate 10. The first contact pad metal layer 311 may be located in the third gate metal layer and may be an integral structure interconnected with the access connection line 44 to which it is connected. On the side of the first contact pad metal layer 311 close to the substrate 10, a fifth inorganic insulating layer 105a, a fourth inorganic insulating layer 104a, a third inorganic insulating layer 103a, a second inorganic insulating layer 102a, and a first inorganic insulating layer 101a are sequentially arranged in a direction close to the substrate 10. The inorganic composite insulating layer in this example may include, for example, a fifth inorganic insulating layer 105a, a fourth inorganic insulating layer 104a, a third inorganic insulating layer 103a, a second inorganic insulating layer 102a, and a first inorganic insulating layer 101a. The orthographic projection of the inorganic composite insulating layer on the substrate 10 can cover the orthographic projection of the overlapping region of the four contact pad metal layers on the substrate 10. The inorganic composite insulating layer can be partially disposed within the space between adjacent contact pads. For example, the orthographic projection of the inorganic composite insulating layer on the substrate can overlap with the orthographic projection of the access connection line on the substrate. The inorganic composite insulating layer in the space between the contact pad and the adjacent access connection line, and in the space between adjacent access connection lines, can be removed. The side edge of the inorganic composite insulating layer contacts the second contact pad metal layer 312.

[0194] In some examples, as shown in FIG16 , the contact pad does not include an inactive contact pad metal layer. However, this embodiment is not limited to this. In other examples, an inactive contact pad metal layer that is not electrically connected may be provided separately. For example, the inactive contact pad metal layer may be located in the first gate metal layer or in the second gate metal layer, thereby increasing the height of the contact pad using the inactive contact pad metal layer.

[0195] In some examples, as shown in Figure 16, the second contact pad metal layer 312 may be in direct contact with the first contact pad metal layer 311. The sixth inorganic insulating layer in the first signal access region may be entirely removed.

[0196] The display panel of this example can use the inorganic composite insulating layer located below the first contact pad metal layer to increase the height of the contact pad, thereby reducing the step difference between the contact pad and the surrounding film layer, thereby improving the film layer crack situation that occurs during the binding process of the driving chip, thereby improving the stability of the binding process and the product yield.

[0197] In the display panel of this example, the inorganic composite insulating layer is provided in the space between adjacent contact pads and is not connected as a whole. In this way, the fracture derivative path of the inorganic film layer in the driver chip binding process can be cut off, thereby preventing cracks.

[0198] The remaining structures of the display panel of this example can be referred to the description of the aforementioned embodiment, and thus will not be described again here.

[0199] FIG17 is another example of a partial cross-section taken along the P-P' direction in FIG3 . In some examples, as shown in FIG17 , a contact pad 31 may include four stacked contact pad metal layers, for example, a first contact pad metal layer 311, a second contact pad metal layer 312, a third contact pad metal layer 313, and a fourth contact pad metal layer 314, sequentially arranged in a direction away from the substrate 10. The first contact pad metal layer 311 may be located in the third gate metal layer. In this example, the contact pad 31 may not include an inactive contact pad metal layer.

[0200] In some examples, as shown in FIG17 , the inorganic composite insulating layer may include: a fifth inorganic insulating layer 105a, a fourth inorganic insulating layer 104a, a third inorganic insulating layer 103a, a second inorganic insulating layer 102a, and a first inorganic insulating layer 101a. The orthographic projection of the inorganic composite insulating layer on the substrate 10 may cover the orthographic projection of the four contact pad metal layers on the substrate 10. The side edges of the inorganic composite insulating layer may contact the first organic insulating layer 109a. A sixth inorganic insulating layer 106a may be disposed between the second contact pad metal layer 312 and the first contact pad metal layer 311. The sixth inorganic insulating layer 106a may cover the edge of the first contact pad metal layer 311. The first contact pad metal layer 311 may be electrically connected to the second contact pad metal layer 312 via a via provided in the sixth inorganic insulating layer 106a. For example, the sixth inorganic insulating layer 106a may provide an annular cover and protection around the edge of the first contact pad metal layer 311.

[0201] The display panel of this example uses an inorganic composite insulating layer located below the first contact pad metal layer to increase the height of the contact pad, thereby reducing the step difference between the contact pad and the surrounding film layer, thereby improving the film layer cracking that occurs during the bonding process of the driver chip, thereby improving the stability of the bonding process and the product yield. The sixth inorganic insulating layer can be used to annularly cover and protect the edge of the first contact pad metal layer of the contact pad. The sixth inorganic insulating layer of this example is set in the interval between adjacent contact pads and is not connected as a whole. The inorganic composite insulating layer is also partially set in the interval between adjacent contact pads and is not connected as a whole. In this way, the fracture derivative path of the inorganic film layer in the driver chip bonding process can be cut off, thereby playing a role in preventing cracks.

[0202] The remaining structures of the display panel of this example can be referred to the description of the aforementioned embodiment, and thus will not be described again here.

[0203] Figure 18 is another partial schematic diagram of the signal access area of ​​at least one embodiment of the present disclosure. Figure 19 is a schematic diagram of the first gate metal layer in Figure 18. Figure 20 is a partial cross-sectional schematic diagram along the V-V' direction in Figure 18.

[0204] In some examples, as shown in Figures 18 to 20, a contact pad 31 may include four stacked contact pad metal layers, for example, a first contact pad metal layer 311, a second contact pad metal layer 312, a third contact pad metal layer 313, and a fourth contact pad metal layer 314. The first contact pad metal layer 311, the second contact pad metal layer 312, the third contact pad metal layer 313, and the fourth contact pad metal layer 314 may be arranged sequentially in a direction away from the substrate 10. The first contact pad metal layer 311 may be located in the first gate metal layer, the second contact pad metal layer 312 may be located in the first source and drain metal layer, the third contact pad metal layer 313 may be located in the second source and drain metal layer, and the fourth contact pad metal layer 314 may be located in the second touch conductive layer.

[0205] In some examples, as shown in Figure 19, the data lead 41 may extend between adjacent contact pads. The data lead 41 and the first contact pad metal layer 311 of the contact pad to which it is connected may be an integrated structure connected to each other.

[0206] In some examples, as shown in FIG20 , the second contact pad metal layer 312 can be connected to the first contact pad metal layer 311 through a via hole defined in the second inorganic insulating layer 102 a. The orthographic projection of the second contact pad metal layer 312 on the substrate can overlap the orthographic projection of the first contact pad metal layer 311 on the substrate. The second inorganic insulating layer 102 a can cover the edge of the first contact pad metal layer 311.

[0207] In this example, the third, fourth, fifth, and sixth inorganic insulating layers in the first signal access region can be entirely removed. The inorganic composite insulating layer in this example may include: a third, fourth, and fifth inorganic insulating layers.

[0208] This example can reduce the step difference between the contact pad and the surrounding film layer by removing the third inorganic insulating layer, the fourth inorganic insulating layer, the fifth inorganic insulating layer and the sixth inorganic insulating layer in the first signal access area, thereby improving the film crack situation that occurs during the binding process of the driver chip, thereby improving the stability of the binding process and the product yield.

[0209] The remaining structures of the display panel of this example can be referred to the description of the aforementioned embodiment, and thus will not be described again here.

[0210] Fig. 21 is a partial enlarged schematic diagram of region S3 in Fig. 18. Fig. 22 is another exemplary diagram of a partial cross section along the VV' direction in Fig. 18.

[0211] In some examples, as shown in Figures 21 and 22, a contact pad 31 may include four stacked contact pad metal layers, for example, a first contact pad metal layer 311, a second contact pad metal layer 312, a third contact pad metal layer 313, and a fourth contact pad metal layer 314. The first contact pad metal layer 311, the second contact pad metal layer 312, the third contact pad metal layer 313, and the fourth contact pad metal layer 314 may be arranged sequentially in a direction away from the substrate 10. The first contact pad metal layer 311 may be located in the first gate metal layer, the second contact pad metal layer 312 may be located in the first source and drain metal layer, the third contact pad metal layer 313 may be located in the second source and drain metal layer, and the fourth contact pad metal layer 314 may be located in the second touch conductive layer.

[0212] In some examples, as shown in FIG22 , a sixth inorganic insulating layer 106 a, a fifth inorganic insulating layer 105 a, a fourth inorganic insulating layer 104 a, a third inorganic insulating layer 103 a, and a second inorganic insulating layer 102 a may be disposed between the second contact pad metal layer 312 and the first contact pad metal layer 311. The second contact pad metal layer 312 may be connected to the first contact pad metal layer 311 through vias defined in the sixth inorganic insulating layer 106 a, the fifth inorganic insulating layer 105 a, the fourth inorganic insulating layer 104 a, the third inorganic insulating layer 103 a, and the second inorganic insulating layer 102 a. The sixth inorganic insulating layer 106 a, the fifth inorganic insulating layer 105 a, the fourth inorganic insulating layer 104 a, the third inorganic insulating layer 103 a, and the second inorganic insulating layer 102 a may cover the edges of the first contact pad metal layer 311. For example, the second inorganic insulating layer 102a may cover the space between adjacent contact pads; the sixth inorganic insulating layer 106a, the fifth inorganic insulating layer 105a, the fourth inorganic insulating layer 104a, and the third inorganic insulating layer 103a may not be provided in the space between adjacent contact pads. The sixth inorganic insulating layer 106a, the fifth inorganic insulating layer 105a, the fourth inorganic insulating layer 104a, and the third inorganic insulating layer 103a may be stacked to form a ring-shaped structure covering the edge of the first contact pad metal layer 311. In this example, the inorganic composite insulating layer may include the third inorganic insulating layer 103a, the fourth inorganic insulating layer 104a, and the fifth inorganic insulating layer 105a. The side edges of the inorganic composite insulating layer may contact the first organic insulating layer 109a. The inorganic composite insulating layer in this example may provide ring-shaped coverage and protection for the edge of the first contact pad metal layer 311, and the sixth inorganic insulating layer 106a may also provide ring-shaped coverage and protection for the edge of the first contact pad metal layer 311.

[0213] In some examples, the total thickness of the sixth inorganic insulating layer 106a, the fifth inorganic insulating layer 105a, and the fourth inorganic insulating layer 104a covering the edge of the first contact pad metal layer can be 4500 angstroms to 1 micron, for example, approximately 9000 angstroms. For example, the sixth inorganic insulating layer 106a, the fifth inorganic insulating layer 105a, and the fourth inorganic insulating layer 104a in the signal access region can be thinned to reduce the step between the contact pad and the surrounding film layer.

[0214] The display panel of this example sets the sixth inorganic insulating layer in the gap between adjacent contact pads without connecting them as a whole, and also sets the inorganic composite insulating layer in the gap between adjacent contact pads without connecting them as a whole. In this way, the fracture derivative path of the inorganic film layer in the driving chip binding process can be cut off, thereby preventing cracks.

[0215] The remaining structures of the display panel of this example can be referred to the description of the aforementioned embodiment, and thus will not be described again here.

[0216] This embodiment also provides a display panel, comprising: a substrate, a display structure layer, a plurality of data leads, a plurality of contact pads, an inorganic composite insulating layer, and a first organic insulating layer. The substrate comprises a display area and a signal access area located on at least one side of the display area. The display structure layer is located on the substrate of the display area, the display structure layer comprises a plurality of sub-pixels and a plurality of data lines, the plurality of sub-pixels and the plurality of data lines are electrically connected, and the plurality of data lines are configured to provide data signals to the plurality of sub-pixels. A plurality of data leads are located in the signal access area, the plurality of data leads are connected to the plurality of data lines. A plurality of contact pads are located in the signal access area, at least one of the plurality of contact pads comprises a plurality of contact pad metal layers electrically connected to each other, the plurality of contact pad metal layers are electrically connected to one of the plurality of data leads. An inorganic composite insulating layer is located in the signal access area, the inorganic composite insulating layer is located on a side of at least one of the plurality of contact pad metal layers that is close to the substrate. A first organic insulating layer is located in the signal access region, and the first organic insulating layer is located on a side of the inorganic composite insulating layer and at least one of the plurality of contact pad metal layers away from the substrate. A side edge of the inorganic composite insulating layer contacts the first organic insulating layer or one of the plurality of contact pad metal layers.

[0217] In some exemplary embodiments, the inorganic composite insulating layer is located on a side of the multiple contact pad metal layers close to the substrate, and an orthographic projection of the inorganic composite insulating layer on the substrate covers an orthographic projection of an overlapping region of the multiple contact pad metal layers on the substrate.

[0218] In some exemplary embodiments, the at least one contact pad further includes an ineffective contact pad metal layer, and the inorganic composite insulating layer is located between the plurality of contact pad metal layers of the at least one contact pad and the ineffective contact pad metal layer.

[0219] For the relevant description of the display panel of this example, reference can be made to the description of the aforementioned embodiment, and thus no further details will be given here.

[0220] Figure 23 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 23 , this embodiment provides a display device 91 comprising a display panel 910 according to the aforementioned embodiment. In some examples, display panel 910 may be an OLED display panel with an integrated touchscreen structure. Display device 91 may be any product or component with display and touchscreen functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0221] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures may refer to the general design. In the absence of conflict, the embodiments of this disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments. It should be understood by those skilled in the art that the technical solutions of this disclosure can be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of this disclosure, and should be included in the scope of the claims of this disclosure.

Claims

1. A display panel, comprising: A substrate, comprising a display area and a signal access area located at at least one side of the display area; A display structure layer, located on the substrate of the display area, the display structure layer includes a plurality of sub-pixels and a plurality of data lines, the plurality of sub-pixels are electrically connected to the plurality of data lines, and the plurality of data lines are configured to provide data signals to the plurality of sub-pixels; A plurality of data leads, located in the signal access area, the plurality of data leads being connected to the plurality of data lines; A plurality of contact pads, located in the signal access area, at least one of the plurality of contact pads comprises a plurality of contact pad metal layers electrically connected to each other, and the plurality of contact pad metal layers are electrically connected to one of the plurality of data leads; an inorganic composite insulating layer, located in the signal access area; the inorganic composite insulating layer is located on a side of at least one contact pad metal layer among the plurality of contact pad metal layers close to the substrate; The inorganic composite insulating layer and the plurality of contact pads have no overlap in their orthographic projections on the substrate, or the inorganic composite insulating layer and the at least one contact pad at least partially overlap in their orthographic projections on the substrate.

2. The display panel according to claim 1, wherein: The inorganic composite insulating layer is located on a side of the plurality of contact pad metal layers close to the substrate.

3. The display panel according to claim 2, wherein: The orthographic projection of the inorganic composite insulating layer on the substrate covers the orthographic projection of overlapping regions of the plurality of contact pad metal layers on the substrate.

4. The display panel according to claim 2, characterized in that: At least a portion of the inorganic composite insulating layer is located in the gap between adjacent contact pads.

5. The display panel according to claim 2, wherein: The at least one contact pad further comprises: an ineffective contact pad metal layer; the inorganic composite insulating layer is located between the plurality of contact pad metal layers of the at least one contact pad and the ineffective contact pad metal layer.

6. The display panel according to claim 5, wherein: The orthographic projection of the inorganic composite insulating layer on the substrate covers the orthographic projection of the ineffective contact pad metal layer on the substrate.

7. The display panel according to any one of claims 2 to 6, wherein: The at least one contact pad includes: a first contact pad metal layer in contact with a surface of the inorganic composite insulating layer away from the substrate; the first contact pad metal layer is electrically connected to a data lead.

8. The display panel according to claim 7, wherein: The first contact pad metal layer and the one data lead are an integrated structure connected to each other.

9. The display panel according to claim 7, further comprising: A plurality of access connection lines located in the signal access area; The first contact pad metal layer is electrically connected to the data lead through an access connection line; The first contact pad metal layer and the one access connection line are an integrated structure connected to each other.

10. The display panel according to claim 9, wherein: The connection position between the access connection line and the data lead line is located on a side of the plurality of contact pads close to the display area.

11. The display panel according to claim 9 or 10, further comprising: A plurality of connection electrodes located in the signal access area; The access connection line is electrically connected to the data lead through the connection electrode; the access connection line is located on a side of the data lead away from the substrate; and the connection electrode is located on a side of the access connection line away from the substrate.

12. The display panel according to any one of claims 1 to 11, wherein: At least one sub-pixel of the plurality of sub-pixels comprises: a pixel circuit, wherein the pixel circuit comprises: at least one first transistor and at least one second transistor; the first transistor and the second transistor are of different transistor types; The first transistor includes: a first active layer and a first gate; The second transistor comprises: a second active layer and a second gate; the first active layer and the first gate of the first transistor are located on a side of the second active layer of the second transistor close to the substrate; the second gate is located on a side of the second active layer away from the substrate; A third gate insulating layer is provided between the second active layer and the second gate; The inorganic composite insulating layer at least includes: a fifth inorganic insulating layer disposed on the same layer as the third gate insulating layer.

13. The display panel according to claim 12, wherein: The pixel circuit further includes: at least one capacitor, the capacitor including a first plate and a second plate, the second plate being located on a side of the first plate away from the substrate, and the second plate being located on a side of the second active layer of the second transistor close to the substrate; A first interlayer insulating layer is provided between the second electrode plate and the second active layer of the second transistor; The inorganic composite insulating layer includes: the fifth inorganic insulating layer and a third inorganic insulating layer disposed on the same layer as the first interlayer insulating layer.

14. The display panel according to claim 13, wherein: A first buffer layer is further disposed between the second electrode plate and the second active layer of the second transistor, and the first interlayer insulating layer is located on a side of the first buffer layer close to the substrate; The inorganic composite insulating layer includes: the third inorganic insulating layer, the fifth inorganic insulating layer, and a fourth inorganic insulating layer disposed on the same layer as the first buffer layer.

15. The display panel according to claim 12, wherein: The at least one contact pad includes: a first contact pad metal layer in contact with a surface of the inorganic composite insulating layer away from the substrate; the first contact pad metal layer and the second gate of the second transistor are in the same layer structure.

16. The display panel according to claim 15, wherein: The at least one contact pad further comprises: a second contact pad metal layer located on a side of the first contact pad metal layer away from the substrate; The display panel further includes: a sixth inorganic insulating layer located in the signal access area and located on a side of the fifth inorganic insulating layer away from the substrate; The sixth inorganic insulating layer and the at least one contact pad do not overlap in their orthographic projection on the substrate; or, the sixth inorganic insulating layer covers the edge of the first contact pad metal layer of the at least one contact pad, and the surface of the first contact pad metal layer exposed by the sixth inorganic insulating layer is in contact with the second contact pad metal layer.

17. The display panel according to claim 16, wherein: Part of the sixth inorganic insulating layer is disposed in a gap between adjacent contact pads.

18. The display panel according to claim 16, wherein: The sixth inorganic insulating layer has a ring structure covering an edge of the first contact pad metal layer.

19. The display panel according to claim 16, wherein: The second transistor further includes a second source and a second drain, and a second interlayer insulating layer is provided between the second gate of the second transistor and the second source and the second drain; The sixth inorganic insulating layer is disposed on the same layer as the second interlayer insulating layer; The second contact pad metal layer and the second source and the second drain of the second transistor are in the same layer structure.

20. The display panel according to claim 1, wherein: The at least one contact pad comprises: a first contact pad metal layer located on a side of the inorganic composite insulating layer close to the substrate, and a second contact pad metal layer located on a side of the inorganic composite insulating layer away from the substrate, wherein the second contact pad metal layer is connected to the first contact pad metal layer; The inorganic composite insulating layer covers the edge of the first contact pad metal layer.

21. The display panel according to claim 20, wherein: The inorganic composite insulating layer has a ring structure covering an edge of the first contact pad metal layer.

22. The display panel according to any one of claims 12 to 21, wherein: The at least one sub-pixel further includes: a light-emitting element, the pixel circuit being electrically connected to the light-emitting element via a first switching electrode; The at least one contact pad comprises: a first contact pad metal layer, a second contact pad metal layer and a third contact pad metal layer arranged in sequence along a direction away from the substrate; The third contact pad metal layer and the first transfer electrode are in the same layer structure.

23. The display panel according to claim 22, further comprising: A touch control structure layer located on a side of the display structure layer away from the substrate, the touch control structure layer comprising at least one touch control conductive layer; The at least one contact pad further includes: a fourth contact pad metal layer located on a side of the third contact pad metal layer away from the substrate, and the fourth contact pad metal layer and one of the touch conductive layers of the touch structure layer are in the same layer structure.

24. The display panel according to claim 22 or 23, wherein: A side edge of the inorganic composite insulating layer contacts the second contact pad metal layer or the third contact pad metal layer.

25. The display panel according to any one of claims 1 to 24, further comprising: A first organic insulating layer located in the signal access area and located on a side of the inorganic composite insulating layer away from the substrate; A side edge of the inorganic composite insulating layer contacts the first organic insulating layer.

26. A display device comprising the display panel according to any one of claims 1 to 25.

27. A method for preparing a display panel, comprising: Providing a substrate, the substrate comprising a display area and a signal access area located at at least one side of the display area; A display structure layer is formed in the display area, and a plurality of data leads, a plurality of contact pads and an inorganic composite insulating layer are formed in the signal access area; wherein the display structure layer includes a plurality of sub-pixels and a plurality of data lines, the plurality of sub-pixels are electrically connected to the plurality of data lines, and the plurality of data lines are configured to provide data signals to the plurality of sub-pixels; the plurality of data leads are connected to the plurality of data lines; at least one of the plurality of contact pads includes a plurality of contact pad metal layers electrically connected to each other, and the plurality of contact pad metal layers are electrically connected to one of the plurality of data leads; The inorganic composite insulating layer is located on a side of at least one contact pad metal layer among the multiple contact pad metal layers close to the substrate; the inorganic composite insulating layer and the multiple contact pads have no overlap in their orthographic projections on the substrate, or the inorganic composite insulating layer and the at least one contact pad have at least partially overlapped in their orthographic projections on the substrate.

28. A display panel comprising: A substrate, comprising a display area and a signal access area located at at least one side of the display area; A display structure layer, located on the substrate of the display area, the display structure layer includes a plurality of sub-pixels and a plurality of data lines, the plurality of sub-pixels are electrically connected to the plurality of data lines, and the plurality of data lines are configured to provide data signals to the plurality of sub-pixels; A plurality of data leads, located in the signal access area, the plurality of data leads being connected to the plurality of data lines; A plurality of contact pads, located in the signal access area, at least one of the plurality of contact pads comprises a plurality of contact pad metal layers electrically connected to each other, and the plurality of contact pad metal layers are electrically connected to one of the plurality of data leads; an inorganic composite insulating layer, located in the signal access region, and the inorganic composite insulating layer is located on a side of at least one contact pad metal layer among the plurality of contact pad metal layers close to the substrate; A first organic insulating layer, located in the signal access region, wherein the first organic insulating layer is located on a side of the inorganic composite insulating layer and at least one of the plurality of contact pad metal layers away from the substrate; A side edge of the inorganic composite insulating layer contacts the first organic insulating layer or one of the contact pad metal layers.

29. The display panel according to claim 28, wherein: The inorganic composite insulating layer is located on a side of the plurality of contact pad metal layers close to the substrate, and an orthographic projection of the inorganic composite insulating layer on the substrate covers an orthographic projection of an overlapping region of the plurality of contact pad metal layers on the substrate.

30. The display panel according to claim 28, wherein: The at least one contact pad further includes an ineffective contact pad metal layer, and the inorganic composite insulating layer is located between the plurality of contact pad metal layers of the at least one contact pad and the ineffective contact pad metal layer.

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