Computing core and data processing method

By designing a flexible computing core structure, using multiplexers and hardware multi-threaded control circuits, the memory wall problem of neural network processors and the problem of low computing resource utilization are solved, and efficient computing power utilization and cost reduction are achieved , suitable for a variety of network algorithms.

WO2025001203A1PCT designated stage expired Publication Date: 2025-01-02HUAWEI TECH CO LTD
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Patent Information

Application Number
PCT/CN2024/078172
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2023-06-30
Filing Date
2024-02-22
Publication Date
2025-01-02

AI Technical Summary

Technical Problem

Due to the memory wall problem, existing neural network processors are difficult to meet the high computing power requirements of deep learning algorithms, and have low computing resource utilization and high hardware cost, making it difficult to compatible with the number of layers and computing power requirements of different network algorithms.

Method used

Design a computing core to couple the output end of each convolutional circuit with the input end of the multiplexer, and use the selection function of the multiplexer to flexibly meet the computing resource requirements, improve the utilization rate of the computing resource, and use addition The multi-threaded control circuit of the machine and hardware realizes the expansion of input channels and output channels, optimizing data access and processing efficiency.

Benefits of technology

It improves the utilization rate of computing resources, reduces hardware costs and circuit area, enhances the applicability of computing and verification of different network algorithms, and solves the memory wall problem and the problem of low computing resource utilization.

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Abstract

Embodiments of the present application relate to the technical field of chips, and provide a computing core and a data processing method, solving the problems of low computing resource utilization rate and high hardware cost of existing computing-in-memory devices. The specific solution is as follows: the computing core comprises a plurality of convolution circuits (81) and a plurality of multiplexers (82); each multiplexer (82) comprises an output end and at least two input ends; the output ends of the multiplexers (82) are in one-to-one correspondence with input ends of the convolution circuits (81); an output end of each convolution circuit (81) among the plurality of convolution circuits (81) is coupled to input ends of L multiplexers (82), wherein L is an integer greater than or equal to 2; at least one multiplexer (82) among the L multiplexers (82) further comprises an external data output end, and at least one convolution circuit (81) among L convolution circuits (81) corresponding to the L multiplexers (82) further comprises an external data input end. A multiplexer (82) is used for connecting, to the output end of the multiplexer (82), the output end of at least one convolution circuit (81) coupled with the multiplexer (82).
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Citation Information

Patent Citations

  • Computing core and data processing method

    CN119226676A

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    CN111047025A

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    CN111275180A

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