Filter and manufacturing method therefor, and electronic device

Abstract

The present disclosure belongs to the technical field of passive devices. Provided are a filter and a manufacturing method therefor, and an electronic device. The filter comprises a dielectric substrate, and at least one capacitor and at least one inductor which are arranged on the dielectric substrate. The capacitor comprises a first polar plate and a second polar plate which are arranged opposite to each other, the first polar plate being located on the side of the second polar plate close to the dielectric substrate, and at least one of the first polar plate and the second polar plate being electrically connected to the inductor. The inductor comprises a plurality of layers of coil structures arranged in order on the dielectric substrate, at least one first interlayer insulation layer being arranged between adjacent coil structures. The coil structures of adjacent layers are electrically connected by means of a first connection via that passes through the first interlayer insulation layer therebetween, and orthographic projections of any two of the plurality of layers of coil structures on the dielectric substrate partially overlap.

Description

Filter and preparation method thereof, and electronic equipment Technical Field

[0001] The present disclosure belongs to the technical field of passive devices, and particularly relates to a filter, a preparation method thereof, and an electronic device. Background Art

[0002] Advances in communications technology are placing higher demands on the performance and size of electronic components. Passive components such as capacitors, inductors, and resistors account for approximately 70% of the printed circuit board (PCB) area. Emerging technologies, such as Integrated Product Development (IPD), can reduce the area of ​​passive components by over 80%. By integrating the most common passive components in electronic components, IPD effectively reduces the size of discrete components and the wiring of component combinations.

[0003] Inductors are crucial components in electronic devices, serving as both discrete devices and integral circuit components, such as in common LC filters or as interconnects within package substrates. Traditional inductors, due to their spiral structure, occupy a significant portion of passive components, making miniaturization and performance optimization crucial for their development.

[0004] Summary of the Invention

[0005] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provides a filter and a preparation method thereof, and an electronic device.

[0006] In a first aspect, the technical solution adopted to solve the technical problem of the present disclosure is a filter, comprising a dielectric substrate, at least one capacitor and at least one inductor provided on the dielectric substrate;

[0007] The capacitor includes a first plate and a second plate arranged opposite to each other, wherein the first plate is located on a side of the second plate close to the dielectric substrate; at least one of the first plate and the second plate is electrically connected to the inductor;

[0008] The inductor includes a multi-layer coil structure sequentially arranged on the dielectric substrate, and at least one first interlayer insulating layer is arranged between adjacent coil structures; the coil structures of adjacent layers are electrically connected through a first connecting via penetrating the first interlayer insulating layer therebetween;

[0009] The orthographic projections of any two of the multiple layers of the coil structures on the dielectric substrate partially overlap.

[0010] In some embodiments, the capacitor is disposed on a side of the inductor close to the dielectric substrate, and at least one second interlayer insulating layer is disposed between the capacitor and the inductor.

[0011] In some embodiments, the coil structure closest to the dielectric substrate in the multi-layer coil structure is a first coil structure; and the second pole plate is electrically connected to the first coil structure.

[0012] In some embodiments, the capacitor further includes a first lead terminal;

[0013] The first lead end and the second electrode plate are arranged on the same layer, and the two are an integrally formed structure; the first lead end and the first coil structure are electrically connected through a second connecting via, and the second connecting via passes through the second interlayer insulating layer between the second electrode plate and the first coil structure.

[0014] In some embodiments, the coil structure closest to the dielectric substrate in the multi-layer coil structure is a first coil structure;

[0015] The first pole plate and the first coil structure are arranged on the same layer and are electrically connected.

[0016] In some embodiments, the first electrode plate and the first coil structure are integrally formed.

[0017] In some embodiments, the coil structure adjacent to the first coil structure in the multi-layer coil structure is a second coil structure;

[0018] A third interlayer insulating layer is provided between the second coil structure and the dielectric substrate, and the third interlayer insulating layer covers the second pole plate, and the integrally formed first pole plate and the first coil structure.

[0019] In some embodiments, the coil structure adjacent to the first coil structure in the multi-layer coil structure is a second coil structure;

[0020] A fourth interlayer insulating layer and a fifth interlayer insulating layer are provided between the second coil structure and the dielectric substrate. The fourth interlayer insulating layer is provided with a first accommodating portion extending through the fourth interlayer insulating layer in a thickness direction thereof. The integrally formed first electrode plate and the first coil structure are confined within the first accommodating portion. Surfaces of the integrally formed first electrode plate and the first coil structure facing away from the dielectric substrate are flush with a surface of the fourth interlayer insulating layer facing away from the dielectric substrate.

[0021] The fifth interlayer insulating layer is arranged on a side of the fourth interlayer insulating layer away from the dielectric substrate, and the fifth interlayer insulating layer covers the second electrode plate.

[0022] In some embodiments, the coil structure closest to the dielectric substrate in the multi-layer coil structure is a first coil structure;

[0023] The first coil structure includes a first sub-coil and a second sub-coil that are stacked, and the first sub-coil is located on a side of the second sub-coil close to the dielectric substrate;

[0024] The first pole plate and the first sub-coil are arranged in the same layer and are electrically connected.

[0025] In some embodiments, the first pole plate and the first sub-coil are an integrally formed structure.

[0026] In some embodiments, the inductor further includes a connecting structure, which is arranged on a side of the inductor facing away from the dielectric substrate and is electrically connected to a third coil structure in the inductor that is farthest from the dielectric substrate through a third connecting via; the third connecting via passes through a sixth interlayer insulating layer between the connecting structure and the third coil structure.

[0027] In some embodiments, the first interlayer insulating layer between any adjacent coil structures includes a first surface and a second surface oppositely disposed along its thickness direction, and the first surface and the second surface are parallel to a reference plane of the dielectric substrate extending along the first direction.

[0028] In some embodiments, any seventh interlayer insulating layer on the same layer as the coil structure includes a first surface and a second surface oppositely disposed along its thickness direction, and the first surface and the second surface are both parallel to a reference plane of the dielectric substrate extending along the first direction.

[0029] In a second aspect, an embodiment of the present disclosure further provides a method for preparing a filter, comprising: providing a dielectric substrate, and forming at least one capacitor and at least one inductor on the dielectric substrate; wherein the step of forming the at least one capacitor and the at least one inductor comprises:

[0030] forming a first conductive pattern on the dielectric substrate; the first conductive pattern at least includes a first plate of the capacitor;

[0031] A second conductive pattern is formed on a side of the first conductive pattern facing away from the dielectric substrate; the second conductive pattern includes a second plate of the capacitor; and at least one of the second plate and the first plate is electrically connected to the inductor;

[0032] A plurality of layers of third conductive patterns are formed on a side of the second conductive pattern facing away from the dielectric substrate, and at least one first interlayer insulating layer is formed between adjacent third conductive patterns. The third conductive pattern includes a coil structure of the inductor, and the coil structures of adjacent layers are electrically connected via a first connecting via penetrating the first interlayer insulating layer therebetween. The orthographic projections of any two of the plurality of layers of coil structures on the dielectric substrate partially overlap.

[0033] In some embodiments, forming the first conductive pattern on the dielectric substrate includes: forming the first conductive pattern including the first electrode plate on the dielectric substrate;

[0034] The forming of a multi-layer third conductive pattern on a side of the second conductive pattern facing away from the dielectric substrate includes: forming a multi-layer coil structure on a side of the second conductive pattern facing away from the dielectric substrate, wherein the coil structure closest to the dielectric substrate in the multi-layer coil structure is a first coil structure; and the first coil structure is electrically connected to the second electrode plate through a second connecting via penetrating a second interlayer insulating layer between the first electrode plate and the second electrode plate.

[0035] In some embodiments, the coil structure closest to the dielectric substrate in the multi-layer coil structure of the inductor is a first coil structure;

[0036] Forming a first conductive pattern on the dielectric substrate includes:

[0037] A first conductive pattern including the first electrode plate and the first coil structure is formed on the dielectric substrate.

[0038] In some embodiments, the first electrode plate and the first coil structure are integrally formed; wherein, after forming the second conductive pattern, the method further includes:

[0039] A third interlayer insulating layer is formed on a side of the second conductive pattern away from the first conductive pattern; the third interlayer insulating layer covers the second electrode plate, and the integrally formed first electrode plate and the first coil structure.

[0040] In some embodiments, the first electrode plate and the first coil structure are an integrally formed structure;

[0041] The step of forming a first conductive pattern including the first electrode plate and the first coil structure on the dielectric substrate includes:

[0042] forming a fourth interlayer insulating layer on the dielectric substrate; the fourth interlayer insulating layer including a first accommodating portion penetrating along a thickness direction thereof;

[0043] The first accommodating portion is filled with the first pole plate and the first coil structure formed integrally to form the first conductive pattern; the first pole plate and the first coil structure formed integrally are away from the surface of the dielectric substrate and are flush with the surface of the fourth interlayer insulating layer away from the dielectric substrate.

[0044] In some embodiments, after forming the second conductive pattern, the method further includes:

[0045] A fifth interlayer insulating layer is formed on a side of the second conductive pattern away from the first conductive pattern, and a surface of the fifth interlayer insulating layer away from the dielectric substrate is parallel to a reference plane of the dielectric substrate extending along the first direction.

[0046] In some embodiments, the step of forming any layer of the third conductive pattern includes:

[0047] forming a seventh interlayer insulating layer on the dielectric substrate having the second conductive pattern formed thereon; wherein the seventh interlayer insulating layer includes a second accommodating portion penetrating along a thickness direction thereof;

[0048] The coil structure material of the inductor is filled in the second receiving portion to form the third conductive pattern; the third conductive pattern faces away from the surface of the dielectric substrate and is flush with the surface of the seventh interlayer insulating layer facing away from the dielectric substrate.

[0049] In some embodiments, the step of forming any layer of the third conductive pattern includes:

[0050] A third conductive pattern including the coil structure is formed by electroplating on a side of the first interlayer insulating layer facing away from the dielectric substrate.

[0051] In some embodiments, the dielectric substrate includes a glass substrate.

[0052] In a third aspect, an embodiment of the present disclosure further provides an electronic device, comprising a filter as described in any one of the first aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] FIG1 is a front view of a planar (2D) spiral inductor in the prior art;

[0054] FIG2 is a schematic diagram of a filter provided by an embodiment of the present disclosure;

[0055] FIG3 is a front view of a filter provided by an embodiment of the present disclosure;

[0056] FIG4 is a schematic diagram of a specific structure of an exemplary filter provided by an embodiment of the present disclosure;

[0057] FIG5 is a schematic diagram of the specific structure of another exemplary filter provided in an embodiment of the present disclosure;

[0058] FIG6 is a schematic diagram of the specific structure of another exemplary filter provided in an embodiment of the present disclosure;

[0059] FIG7 is a schematic diagram of the specific structure of another exemplary filter provided in an embodiment of the present disclosure;

[0060] FIG8 is a schematic diagram of the specific structure of another exemplary filter provided in an embodiment of the present disclosure;

[0061] 9a to 9j are schematic diagrams of preparing the filter shown in FIG. 4 according to an embodiment of the present disclosure;

[0062] Figures 10a to 10h are schematic diagrams of preparing the filter shown in Figure 5 according to an embodiment of the present disclosure;

[0063] Figures 11a to 11i are schematic diagrams of preparing the filter shown in Figure 6 according to an embodiment of the present disclosure;

[0064] Figures 12a to 12h are schematic diagrams of preparing the filter shown in Figure 7 according to an embodiment of the present disclosure;

[0065] 13a to 13k are schematic diagrams of preparing the filter shown in FIG. 8 according to an embodiment of the present disclosure.

[0066] 1 , dielectric substrate; X, first direction; 2, capacitor; 21, first electrode plate; 22, second electrode plate; 23, first lead terminal; 3, inductor; 31, first coil structure; 32, second coil structure; 33, third coil structure; O1, first connection terminal; O2, second connection terminal; 311, first sub-coil; 312, second sub-coil; 41, first interlayer insulating layer; 42, second interlayer insulating layer; 43, third interlayer insulating layer; 44, fourth interlayer insulating layer; 45, fifth interlayer insulating layer; 46, sixth interlayer insulating layer; 47, seventh interlayer insulating layer; 40, insulating layer; Via1, first connecting via; Via2, second connecting via; Via3, third connecting via; 441, first accommodating portion; 471, second accommodating portion; M1, first conductive pattern; M2, second conductive pattern; M3, third conductive pattern; 5. Connection structure; 51. First sub-connection layer; 52. Second sub-connection layer; 53. Barrier layer. DETAILED DESCRIPTION

[0067] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the disclosure for which protection is sought, but merely represents selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure.

[0068] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0069] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0070] In the related art, Figure 1 is a main view of a planar (2D) spiral inductor in the prior art. As shown in Figure 1, the 2D IPD currently uses a metal film layer to form a spiral inductor on the glass surface. Since the inductor is made of the same layer of metal, the area of ​​the inductor is large, resulting in a large area of ​​the final device, which is not conducive to the realization of miniaturized devices.

[0071] In view of this, the embodiments of the present disclosure provide a filter that substantially eliminates one or more of the problems caused by the limitations and defects of the related art. Specifically, the filter in the embodiments of the present disclosure includes a dielectric substrate, at least one capacitor and at least one inductor disposed on the dielectric substrate; the capacitor includes a first plate and a second plate disposed opposite each other, the first plate being located on a side of the second plate closer to the dielectric substrate; at least one of the first plate and the second plate is electrically connected to the inductor; the inductor includes a multilayer coil structure sequentially disposed on the dielectric substrate, with at least one first interlayer insulating layer disposed between adjacent coil structures; the coil structures of adjacent layers are electrically connected via a first connecting via extending through the first interlayer insulating layer therebetween; and the orthographic projections of any two of the multilayer coil structures on the dielectric substrate partially overlap.

[0072] The disclosed embodiments form a three-dimensional spiral inductor (a multi-layer coil structure) and interconnect it with a capacitor to create an LC filter. Because the orthographic projections of any two layers of the spiral inductor on the dielectric substrate overlap, compared to existing technologies, the disclosed embodiment can reduce the overall coil area of ​​the inductor when viewed from above, even when forming a coil structure with the same number of turns, thereby saving device space.

[0073] The specific structure of a filter provided by an embodiment of the present disclosure is described in detail below.

[0074] FIG2 is a schematic diagram of a filter provided in an embodiment of the present disclosure; FIG3 is a front view of a filter provided in an embodiment of the present disclosure; as shown in FIG2 and FIG3, the filter includes a dielectric substrate 1, at least one capacitor 2 and at least one inductor 3 disposed on the dielectric substrate 1; the capacitor 2 includes a first plate 21 and a second plate 22 disposed opposite each other, with the first plate 21 being located on a side of the second plate 22 closer to the dielectric substrate 1; at least one of the first plate 21 and the second plate 22 is electrically connected to the inductor 3; the inductor 3 includes a multilayer coil structure sequentially disposed on the dielectric substrate 1, with at least one first interlayer insulating layer 41 disposed between adjacent coil structures; the coil structures of adjacent layers are electrically connected via a first connecting via 1 penetrating the first interlayer insulating layer 41 therebetween; and the orthographic projections of any two of the multilayer coil structures on the dielectric substrate 1 partially overlap.

[0075] For example, as shown in FIG3 , the multilayer coil structure includes N layers; an N-layer coil structure is also an N-turn three-dimensional spiral structure, with different coil structures located on different layers. N ≥ 2, and N is an integer. The end of the i-th coil structure is electrically connected to the beginning of the (i+1)-th coil structure via a first connection via 1 penetrating the first interlayer insulating layer 41; where i is an integer less than or equal to N. The inductor 3 includes two first connection terminals O1 and O2 that are electrically connected to other components. The first connection terminal O1 is the beginning of the first coil structure (also described below as the first coil structure 31 ), and the second connection terminal O2 is the end of the N-th coil structure (also described below as the third coil structure 33 ). The first coil structure is the coil structure closest to the dielectric substrate 1 in the multilayer coil structure, and the N-th coil structure is the coil structure farthest from the dielectric substrate 1 in the multilayer coil structure.

[0076] Exemplarily, as shown in FIG3 , the orthographic projections of the coil structures in the multi-layer coil structure on the dielectric substrate 1 partially overlap.

[0077] In combination with the above examples, by arranging coils in a sequential manner and with most of their projections overlapping, the overall coil area of ​​the inductor 3 when viewed from above can be reduced, thereby saving device wiring space and facilitating device miniaturization.

[0078] Figure 4 is a schematic diagram of the specific structure of an exemplary filter provided in an embodiment of the present disclosure; Figure 5 is a schematic diagram of the specific structure of another exemplary filter provided in an embodiment of the present disclosure; Figure 6 is a schematic diagram of the specific structure of another exemplary filter provided in an embodiment of the present disclosure; Figure 7 is a schematic diagram of the specific structure of another exemplary filter provided in an embodiment of the present disclosure; Figure 8 is a schematic diagram of the specific structure of another exemplary filter provided in an embodiment of the present disclosure.

[0079] In some embodiments, as shown in FIG4 , the capacitor 2 is disposed on a side of the inductor 3 close to the dielectric substrate 1 , and at least one second interlayer insulating layer 42 is disposed between the capacitor 2 and the inductor 3 .

[0080] Exemplarily, as shown in FIG4 , a second interlayer insulating layer 42 is provided between the capacitor 2 and the inductor 3 , and the second interlayer insulating layer 42 covers the capacitor 2 , that is, covers the first plate 21 , the second plate 22 , and the insulating layer 40 between the first plate 21 and the second plate 22 in the capacitor 2 .

[0081] The capacitor 2 is arranged on the side of the inductor 3 close to the dielectric substrate 1 for example only. Of course, the capacitor 2 can also be arranged on the side of the inductor 3 away from the dielectric substrate 1 , which is not specifically limited in the embodiment of the present disclosure.

[0082] In order to make the structure of the filter of the embodiment of the present disclosure clearer, the filter of the embodiment of the present disclosure is described below with reference to a specific example, taking the capacitor 2 being arranged on the side of the inductor 3 close to the dielectric substrate 1 as an example.

[0083] A first example: as shown in FIG. 4 , the coil structure closest to the dielectric substrate 1 in the multi-layer coil structure is the first coil structure 31 ; the second electrode plate 22 is electrically connected to the first coil structure 31 .

[0084] For example, the second electrode plate 22 may be electrically connected to the first coil structure 31 through a second connection via 2 penetrating the second interlayer insulating layer 42 between the second electrode plate 22 and the first coil structure 31 .

[0085] In a possible implementation, as shown in FIG. 2 , the capacitor 2 further includes a first lead terminal 23 .

[0086] As shown in Figure 4, the first lead terminal 23 and the second electrode plate 22 are arranged on the same layer, and the two are integrally formed. The first lead terminal 23 is electrically connected to the first coil structure 31 through a second connecting via 2, which extends through the second interlayer insulating layer 42 between the second electrode plate 22 and the first coil structure 31. Here, the first electrode plate 21 and the second electrode plate 22 of the capacitor 2 are arranged opposite each other, and their orthographic projections on the dielectric substrate 1 completely overlap. The capacitor 2 is provided with a first lead terminal 23, which is connected to the inductor 3 through the first lead terminal 23 to prevent the generation of coupling capacitance 2 between the capacitor 2 and the inductor 3 and affect the device.

[0087] For the filter shown in FIG4 , by arranging coils in a sequential manner and with most of their projections overlapping, the overall coil area of ​​the inductor 3 when viewed from above can be reduced, thereby saving device wiring space and facilitating device miniaturization.

[0088] Second example: As shown in FIG5 , the coil structure closest to the dielectric substrate 1 in the multi-layer coil structure is the first coil structure 31 ; the first pole plate 21 and the first coil structure 31 are arranged on the same layer and are electrically connected.

[0089] In one possible embodiment, as shown in FIG5 , the first electrode plate 21 and the first coil structure 31 are integrally formed. In this case, by providing an integrally formed first electrode plate 21 and first coil structure 31, the number of process steps can be reduced, thereby reducing production costs. Furthermore, the integrally formed first electrode plate 21 and first coil structure 31 can effectively reduce the thickness of the overall structure of the inductor 3, thereby achieving a thinner and lighter device.

[0090] In one possible embodiment, as shown in FIG5 , the coil structure adjacent to the first coil structure 31 in the multi-layer coil structure is the second coil structure 32 ; a third interlayer insulating layer 43 is provided between the second coil structure 32 and the dielectric substrate 1 , and the third interlayer insulating layer 43 covers the second electrode plate 22 , and the integrally formed first electrode plate 21 and first coil structure 31 .

[0091] In this case, a third interlayer insulating layer 43 is formed through a single patterning process to cover the second electrode 22, as well as the integrally formed first electrode 21 and the first coil structure 31, thereby achieving insulation between the capacitor 2 and the first coil structure 31 and the upper second coil structure 32, reducing the number of process steps and thus reducing production costs.

[0092] A third example: as shown in FIG6 , the coil structure closest to the dielectric substrate 1 in the multi-layer coil structure is the first coil structure 31 ; the first pole plate 21 and the first coil structure 31 are arranged on the same layer and are electrically connected.

[0093] In one possible embodiment, as shown in FIG6 , the first electrode plate 21 and the first coil structure 31 are integrally formed. In this case, by forming the first electrode plate 21 and the first coil structure 31 integrally, the number of process steps can be reduced, thereby lowering production costs. Furthermore, forming the first electrode plate 21 and the first coil structure 31 integrally can effectively reduce the thickness of the overall structure of the inductor 3, thereby achieving a thinner and lighter device.

[0094] Exemplarily, the integrally formed first electrode plate 21 and the first coil structure 31 can be formed by an electroplating process through a seed layer; the material of the seed layer can be selected from titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), etc.; the electroplating material can be selected from metal materials such as copper (Cu), gold (Au), aluminum (Al), and silver (Ag).

[0095] The disclosed method of forming the integrally formed first electrode plate 21 and first coil structure 31 by electroplating growth of a seed layer can improve the adhesion between the integrally formed metal first electrode plate 21 and first coil structure 31 and the dielectric substrate 1 .

[0096] In one possible embodiment, as shown in FIG6 , the coil structure adjacent to the first coil structure 31 in the multi-layer coil structure is the second coil structure 32 ; a fourth interlayer insulating layer 44 and a fifth interlayer insulating layer 45 are disposed between the second coil structure 32 and the dielectric substrate 1 ; the fourth interlayer insulating layer 44 is provided with a first accommodating portion 441 extending through the fourth interlayer insulating layer 44 along its thickness direction; the integrally formed first electrode plate 21 and the first coil structure 31 are confined within the first accommodating portion 441 , and the surface of the integrally formed first electrode plate 21 and the first coil structure 31 facing away from the dielectric substrate 1 is flush with the surface of the fourth interlayer insulating layer 44 facing away from the dielectric substrate 1 ; the fifth interlayer insulating layer 45 is disposed on a side of the fourth interlayer insulating layer 44 facing away from the dielectric substrate 1 , and the fifth interlayer insulating layer 45 covers the second electrode plate 22 .

[0097] In this case, the surface of the fourth interlayer insulating layer 44 facing away from the dielectric substrate 1 is flush with the surfaces of the integrally formed first electrode plate 21 and first coil structure 31 facing away from the dielectric substrate 1. As a result, the surface of the fifth interlayer insulating layer 45 located on the fourth interlayer insulating layer 44 and arranged opposite to each other in the thickness direction is parallel to the reference plane of the dielectric substrate 1 extending along the first direction X. This reduces the undulation of some film layers and can even form a smooth interlayer insulating layer surface, which is beneficial for improving the thickness uniformity of some film layers at different locations, thereby improving the uniformity of device performance.

[0098] Fourth example: As shown in FIG7 , the coil structure closest to the dielectric substrate 1 in the multi-layer coil structure is the first coil structure 31. The first coil structure 31 includes a first sub-coil 311 and a second sub-coil 321 stacked together, with the first sub-coil 311 located on a side of the second sub-coil 321 closer to the dielectric substrate 1. The first pole plate 21 and the first sub-coil 311 are arranged on the same layer and are electrically connected.

[0099] Exemplarily, there is no other structure between the stacked first sub-coil 311 and the second sub-coil 321 , that is, the second sub-coil 321 is arranged on the surface of the first sub-coil 311 away from the dielectric substrate 1 , and the two are seamlessly connected.

[0100] Exemplarily, the first sub-coil 311 and the second sub-coil 321 may be an integrally formed structure.

[0101] For example, the first sub-coil 311 can serve as a seed layer for the second sub-coil 321. The second sub-coil 321 is formed on the seed layer through an electroplating process. The material of the second sub-coil 321 can be selected from metal materials such as copper (Cu), gold (Au), aluminum (Al), and silver (Ag). This improves the adhesion between the second sub-coil 321 and the dielectric substrate 1.

[0102] In one possible embodiment, as shown in Figure 7 , the first electrode plate 21 and the first sub-coil 311 are integrally formed. In this case, by providing an integrally formed first electrode plate 21 and first sub-coil 311, the number of process steps can be reduced, thereby lowering production costs. Furthermore, the integrally formed first electrode plate 21 and first sub-coil 311 can effectively reduce the thickness of the overall structure of the inductor 3, achieving a thinner and lighter device.

[0103] For example, the integrally formed first pole plate 21 and first sub-coil 311 may be made of titanium (Ti) having good adhesion, thereby improving adhesion between the metal first pole plate 21 and first sub-coil 311 and the dielectric substrate 1 .

[0104] Fifth example: As shown in FIG8 , the coil structure closest to the dielectric substrate 1 in the multi-layer coil structure is the first coil structure 31 ; the first pole plate 21 and the first coil structure 31 are arranged on the same layer and are electrically connected.

[0105] In one possible embodiment, as shown in FIG8 , the first electrode plate 21 and the first coil structure 31 are integrally formed. In this case, by forming the first electrode plate 21 and the first coil structure 31 integrally, the number of process steps can be reduced, thereby lowering production costs. Furthermore, forming the first electrode plate 21 and the first coil structure 31 integrally can effectively reduce the thickness of the overall structure of the inductor 3, thereby achieving a thinner and lighter device.

[0106] Exemplarily, the integrally formed first electrode plate 21 and the first coil structure 31 can be formed by an electroplating process through a seed layer; the material of the seed layer can be selected from titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), etc.; the electroplating material can be selected from metal materials such as copper (Cu), gold (Au), aluminum (Al), and silver (Ag).

[0107] In the embodiment of the present disclosure, the material of the integrally formed first electrode plate 21 and the first coil structure 31 may be titanium (Ti) having good adhesion, thereby improving the adhesion between the metal first electrode plate 21 and the first coil structure 31 and the dielectric substrate 1 .

[0108] In one possible embodiment, as shown in FIG8 , the coil structure adjacent to the first coil structure 31 in the multi-layer coil structure is the second coil structure 32 ; a fourth interlayer insulating layer 44 and a fifth interlayer insulating layer 45 are disposed between the second coil structure 32 and the dielectric substrate 1 ; the fourth interlayer insulating layer 44 is provided with a first accommodating portion 441 extending through the fourth interlayer insulating layer 44 along its thickness direction; the integrally formed first electrode plate 21 and the first coil structure 31 are confined within the first accommodating portion 441 , and the surface of the integrally formed first electrode plate 21 and the first coil structure 31 facing away from the dielectric substrate 1 is flush with the surface of the fourth interlayer insulating layer 44 facing away from the dielectric substrate 1 ; the fifth interlayer insulating layer 45 is disposed on a side of the fourth interlayer insulating layer 44 facing away from the dielectric substrate 1 , and the fifth interlayer insulating layer 45 covers the second electrode plate 22 .

[0109] 8 , the first interlayer insulating layer 41 between any adjacent coil structures includes a first surface and a second surface oppositely disposed along its thickness direction, and both the first surface and the second surface are parallel to a reference plane extending along the first direction X of the dielectric substrate 1 .

[0110] 8 , any seventh interlayer insulating layer 47 on the same layer as the coil structure includes a first surface and a second surface opposite to each other along its thickness direction, and both the first surface and the second surface are parallel to a reference plane extending along the first direction X of the dielectric substrate 1 .

[0111] Combining the above-mentioned embodiments, the filter shown in FIG8 reduces the undulation of each film layer, forming an interlayer insulating layer surface without undulations, which is beneficial to improving the thickness uniformity of each film layer at different positions, thereby improving the uniformity of device performance.

[0112] The above examples are structural descriptions of corresponding types of filters.

[0113] In some embodiments, a flattened film structure can be provided for various types of filters. Specifically, the first interlayer insulating layer 41 between any adjacent coil structures includes a first surface and a second surface disposed opposite each other along its thickness direction, and both the first surface and the second surface are parallel to a reference plane extending along the first direction X of the dielectric substrate 1. This improves the thickness uniformity of the first interlayer insulating layer 41 at different locations, thereby improving the uniformity of device performance.

[0114] In some embodiments, a flattened film structure can be provided for various types of filters. Specifically, any seventh interlayer insulating layer 47 in the same layer as the coil structure includes a first surface and a second surface disposed opposite each other along its thickness direction, and both the first surface and the second surface are parallel to a reference plane extending along the first direction X of the dielectric substrate 1. This improves the thickness uniformity of the seventh interlayer insulating layer 47 in the same layer as the coil structure and the coil structure at different locations, thereby improving the uniformity of device performance.

[0115] In some embodiments, as shown in Figures 4 to 8, the filter further includes a connecting structure 5, which is arranged on a side of the inductor 3 facing away from the dielectric substrate 1 and is electrically connected to the third coil structure 33 in the inductor 3 farthest from the dielectric substrate 1 through a third connecting via 3; the third connecting via 3 penetrates the sixth interlayer insulating layer 46 between the connecting structure 5 and the third coil structure 33.

[0116] For example, the connection structure 5 may be a copper pillar or a solder ball, and may serve as a lead-out terminal of the inductor 3 .

[0117] Exemplarily, the connection structure 5 may include a first sub-connection layer 51 and a second sub-connection layer 52 located on a side of the first sub-connection layer 51 facing away from the dielectric substrate 1. The first sub-connection layer 51 may be made of a metal such as copper (Cu), gold (Au), aluminum (Al), or silver (Ag), and the second sub-connection layer 52 may be made of a silver-tin alloy (Sn-Ag) or tin (Sn). The present embodiment is described using an example in which the first sub-connection layer 51 is made of copper (Cu) and the second sub-connection layer 52 is made of a silver-tin alloy (Sn-Ag).

[0118] Exemplarily, the connection structure 5 may further include a barrier layer 53 disposed between the first sub-connection layer 51 and the second sub-connection layer 52 ; the material of the barrier layer 53 may be nickel (Ni) to prevent Sn in the second sub-connection layer 52 from penetrating into the first sub-connection layer 51 .

[0119] Exemplarily, the sixth insulating layer includes a first surface and a second surface arranged opposite to each other along the thickness direction thereof, and both the first surface and the second surface are parallel to a reference plane of the dielectric substrate 1 extending along the first direction X, thereby improving the thickness uniformity of the sixth interlayer insulating layer 46 and further improving the uniformity of the overall performance of the device.

[0120] In some embodiments, the dielectric substrate 1 can be made of materials with high insulation and low dielectric loss, such as glass, high-resistance silicon, and ceramics. Preferably, the dielectric substrate 1 is made of glass, which has a high dielectric constant and lower dielectric loss.

[0121] In addition, the present disclosure also provides a method for preparing a filter, which can be used to prepare any of the above filters. The method includes: providing a dielectric substrate 1, forming at least one capacitor 2 and at least one inductor 3 on the dielectric substrate 1; wherein the steps of forming at least one capacitor 2 and at least one inductor 3 include:

[0122] S11 , forming a first conductive pattern M1 on the dielectric substrate 1 .

[0123] The first conductive pattern M1 at least includes the first electrode 21 of the capacitor 2 .

[0124] Illustratively, for the first example filter, the first conductive pattern M1 only includes the first electrode 21 ; for the second to fifth example filters, the first conductive pattern M1 includes the first electrode 21 and the first coil structure 31 of the inductor 3 .

[0125] S12 , forming a second conductive pattern M2 on a side of the first conductive pattern M1 facing away from the dielectric substrate 1 .

[0126] The second conductive pattern M2 includes the second electrode plate 22 of the capacitor 2 ; at least one of the second electrode plate 22 and the first electrode plate 21 is electrically connected to the inductor 3 .

[0127] After forming the first conductive pattern M1, an insulating layer 40 is formed on the side of the first electrode 21 facing away from the dielectric substrate 1 to isolate the second electrode 22. Therefore, the step of forming the second electrode 22 includes forming a second conductive pattern M2 including the second electrode 22 on the side of the insulating layer 40 facing away from the dielectric substrate 1.

[0128] S13 , forming multiple layers of third conductive patterns M3 on a side of the second conductive pattern M2 facing away from the dielectric substrate 1 , and forming at least one first interlayer insulating layer 41 between adjacent third conductive patterns M3 .

[0129] Among them, the third conductive pattern M3 includes the coil structure of the inductor 3, and the coil structures of adjacent layers are electrically connected through the first connecting via 1 penetrating the first interlayer insulating layer 41 therebetween; the orthographic projections of any two of the multi-layer coil structures on the dielectric substrate 1 partially overlap.

[0130] The disclosed embodiment forms a three-dimensional spiral inductor 3 (a multi-layer coil structure) and interconnects it with capacitor 2 to form an LC filter. Because the orthographic projections of any two layers of the coil structure in the three-dimensional spiral inductor 3 on the dielectric substrate 1 partially overlap, compared to the prior art, the disclosed embodiment can reduce the overall coil area of ​​the inductor 3 when viewed from above, even when forming a coil structure with the same number of turns, thereby saving device space.

[0131] In order to make the preparation method of the filter according to the embodiment of the present disclosure clearer, the preparation methods of the filters of different examples are described below respectively.

[0132] In some embodiments, FIG. 9a to FIG. 9j are schematic diagrams of preparing the filter shown in FIG. 4 according to an embodiment of the present disclosure. As shown in FIG. 9a to FIG. 9j , steps S21 to S27 are included, wherein:

[0133] S21. Provide a dielectric substrate 1.

[0134] For example, a dielectric substrate 1 with a thickness of 0.15 to 2 mm suitable for mass production is prepared based on process equipment requirements. The dielectric substrate 1 can be made of materials with high insulation and low dielectric loss, such as glass, high-resistance silicon, or ceramic. Step S21 includes a pre-preparation cleaning process for the dielectric substrate 1. Ultrasonic cleaning is performed sequentially with deionized water, ethanol, isopropyl alcohol, and other organic solvents for at least 15 minutes. After ultrasonic cleaning, the substrate is oven-dried, and drying can be continued at 75°C for a specific time, depending on the final cleaning solvent.

[0135] S22 , as shown in FIG9 a , forming a first conductive pattern M1 including a first electrode plate 21 on the dielectric substrate 1 .

[0136] For example, as shown in Figure 9a, a first bonding layer is formed on the dielectric substrate 1 by methods including electroplating, chemical plating, or sputtering. The material for the first bonding layer can generally be selected from metals or metal nitrides with high glass adhesion, such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), or tantalum nitride (TaN). The thickness of the bonding layer can be adjusted as needed, generally ranging from 30 to 100 nm. A first conductive pattern material is deposited on the first bonding layer using a PVD process; the first conductive pattern material can generally be selected from metals with good conductivity, such as Au, Al, Ag, and Cu. The thickness of the first conductive pattern material can be adjusted as needed, generally ranging from 0.2 to 2 μm. A layer of photoresist is applied to the surface of the first conductive pattern material facing away from the dielectric substrate 1. The photoresist can be a conventional photosensitive photoresist, either positive or negative, to a thickness sufficient to completely cover the surface of the first conductive pattern material. The photoresist thickness can be set between 1 μm and 4 μm. Afterwards, the PR resin is exposed using a mask and developed. The PR resin above the pattern of the first electrode 21 to be retained is retained, and all other areas are removed. The first conductive pattern material outside the pattern is then removed. When Cu is used as the first conductive pattern material, wet etching can be used. When Al is used as the first conductive pattern material, wet or dry etching can be used. Different etching methods can be used for different metals. The PR resin above the metal pattern is then removed, forming the first conductive pattern M1 including the first electrode 21.

[0137] S23 , as shown in FIG9 b , forming a second conductive pattern M2 on a side of the first conductive pattern M1 away from the dielectric substrate 1 .

[0138] The second conductive pattern M2 includes the second plate 22 of the capacitor 2 , and the second plate 22 is electrically connected to the inductor 3 .

[0139] For example, as shown in FIG9b , an insulating layer material can be deposited on the side of the first conductive pattern M1 away from the dielectric substrate 1 by a CVD process. The insulating layer material can be silicon nitride (SiNx) as the dielectric layer of the upper and lower plates of the capacitor 2. The thickness of the insulating layer material can be designed and determined according to the requirements of the capacitor 2 value, and the thickness can usually be set between 80 and 200 nm. Afterwards, a second conductive pattern material can be deposited on the side of the insulating layer material away from the dielectric substrate 1 by a PVD process. The second conductive pattern material can be made of a material with good conductivity such as Cu and Al. The metal thickness is made according to the requirements and the thickness can be selected between 0.2 and 2 μm. A second bonding layer can be formed between the insulating layer material and the second conductive pattern material. The second bonding layer can be made of a metal or metal nitride with high adhesion such as Ti, Ta, TiN, TaN, etc. The thickness is adjusted according to the process capability and can be selected between 30 and 100 nm. Afterwards, a layer of PR glue is applied on the side of the second conductive pattern material facing away from the dielectric substrate 1. The PR glue uses ordinary photosensitive PR glue, and positive PR glue or negative PR glue can be selected. The thickness can ensure that the surface of the second conductive pattern material is completely covered to a certain thickness. The thickness of the PR glue can be considered to be between 1um and 4um. Afterwards, the PR glue is exposed using a mask and developed. The PR glue above the pattern of the second electrode 22 that needs to be retained is retained, and all other areas are removed. Afterwards, the second conductive pattern material outside the pattern is removed. When Cu is selected as the second conductive pattern material, wet etching can be used. When Al is selected as the second conductive pattern material, wet etching or dry etching can be used. Different metals can choose different etching methods. Afterwards, the PR glue above the metal pattern is removed to form a second conductive pattern M2 containing the second electrode 22. Next, a layer of PR glue is applied to the side of the second conductive pattern M2 facing away from the dielectric substrate 1. The PR glue uses a conventional photosensitive PR glue, either positive or negative. The thickness is sufficient to ensure complete coverage of the surface of the insulating layer material. The PR glue thickness can be between 1 μm and 4 μm. The PR glue is then exposed using a mask and developed. The PR glue above the pattern of the insulating layer 40 to be retained is retained, while all other areas are removed. The insulating layer material outside the pattern is then removed, typically using dry etching. The PR glue above the pattern of the insulating layer 40 is then removed, forming the insulating layer 40.

[0140] S24 , as shown in FIG9 c , forming a second interlayer insulating layer 42 on the side of the second conductive pattern M2 facing away from the dielectric substrate 1 .

[0141] A second connecting via hole via 2 is formed on the second interlayer insulating layer 42 and passes through the second interlayer insulating layer 42 in a thickness direction. The second electrode plate 22 is electrically connected to the first coil structure 31 through the second connecting via hole via 2 .

[0142] For example, as shown in FIG9c , the material of the second interlayer insulating layer 42 can be a photosensitive PI material, and the thickness is determined according to the design requirements, usually between 3 and 8 um; through exposure and development, the PI material at the overlap position of the first coil structure 31 and the second electrode 22 is removed and cured to form a second connecting via 2; the PI material is changed from a soft film to a hard film to increase the strength of the film layer. Since the PI material is usually a negative resin, the bottom size of the PI via is smaller than the top size of the via, and the slope angle can be adjusted between 20° and 90° by changing the process conditions to form the second interlayer insulating layer 42.

[0143] S25 , forming multiple layers of third conductive patterns M3 on a side of the second interlayer insulating layer 42 facing away from the dielectric substrate 1 , and forming at least one layer of first interlayer insulating layer 41 between adjacent third conductive patterns M3 .

[0144] At least a third conductive pattern M3 including a coil structure is formed by electroplating on a side of the first interlayer insulating layer 41 facing away from the dielectric substrate 1 .

[0145] Taking the inductor 3 including a three-layer coil structure as an example, the process specifically includes steps S251 to S255, wherein:

[0146] S251 , as shown in FIG9 d , forming a first coil structure 31 on a side of the second interlayer insulating layer 42 facing away from the dielectric substrate 1 .

[0147] Step S251 may include forming a first conductive film as a first seed layer on the side of the second interlayer insulating layer 42 facing away from the dielectric substrate 1 by methods including electroplating, chemical plating, etc., or by sputtering, and then spin-coating photoresist, exposing and developing, electroplating, and chemically plating metal on the side of the first seed layer facing away from the dielectric substrate 1 to form a first coil structure 31.

[0148] The material of the first conductive film is typically a metal or metal nitride with high adhesion, such as Ti, Ta, TiN, or TaN. The material of the first coil structure is typically a metal such as Au, Al, Ag, or Cu. The thickness of the first coil structure 31 is typically between 3 and 7 μm. To ensure the flatness of the first coil structure 31, the upper surface of the first coil structure 31 (i.e., the surface facing away from the dielectric substrate 1) is processed using chemical mechanical polishing (CMP).

[0149] For example, the first conductive film can be formed by electroplating using an additive method or a subtractive method. For example, using the additive method, a first conductive film material is deposited on the side of the second interlayer insulating layer 42 facing away from the dielectric substrate 1 through a PVD process. The first conductive film material is generally Ti. The thickness of the first conductive film material can be adjusted as needed to ensure that the surface of the second interlayer insulating layer 42 is completely covered, especially the first conductive film material in the PI via and on the sidewall of the via is completely covered without cracks. Then, a layer of PR glue is applied on the side of the first conductive film material facing away from the dielectric substrate 1. The PR glue uses ordinary photosensitive PR glue, and positive PR glue or negative PR glue can be selected. The thickness can be determined according to the thickness of the electroplated first coil structure 31. Under normal circumstances, the thickness of the PR glue is greater than the thickness of the electroplated first coil structure 31; then, use Mask to expose the PR glue and develop it to form the pattern of the first coil structure 31, and remove the PR glue outside the pattern of the first coil structure 31; if positive photoresist is selected, the slope angle of the pattern is generally acute. Combined with the slope angle of the edge of the subsequent electroplated metal pattern and subsequent processes, the closer the slope angle of the PR glue pattern is to a right angle, the better. If negative photoresist is selected, the slope angle of the pattern is generally obtuse. Afterwards, Cu is electroplated on the first seed layer to form the first coil structure material. The thickness of the first coil structure material is determined according to demand and can usually be selected between 3 and 7um. Afterwards, the remaining PR glue is removed to expose the remaining first seed layer. The first seed layer outside the first coil structure 31 pattern is completely etched away to prevent the first seed layer below the first coil structure 31 from being etched to form a chamfer and affect the bonding force between the film layers. The final shape is shown in Figure 9d.

[0150] For example, as shown in FIG9 d , the coil structure closest to the dielectric substrate 1 in the multilayer coil structure is the first coil structure 31 ; the first coil structure 31 is electrically connected to the second pole plate 22 through a second connecting via 2 penetrating the second interlayer insulating layer 42 between the first coil structure and the second pole plate 22 .

[0151] S252 , as shown in FIG9 e , forming a first interlayer insulating layer 41 on a side of the first coil structure 31 facing away from the dielectric substrate 1 .

[0152] Here, the process of forming the first interlayer insulating layer 41 is similar to the specific process of forming the second interlayer insulating layer 42 , and the repeated parts are not repeated here.

[0153] A first connecting via hole via 1 penetrating the thickness direction of the first interlayer insulating layer 41 is formed on the first interlayer insulating layer 41 . The first coil structure 31 is electrically connected to the adjacent second coil structure 32 through the first connecting via hole via 1 .

[0154] For example, the material of the first interlayer insulating layer 41 can be a photosensitive PI material. The thickness of the first interlayer insulating layer 41 can be determined according to design requirements, and is generally between 3 and 8 μm.

[0155] S253 , as shown in FIG9 f , forming a second coil structure 32 on the side of the first interlayer insulating layer 41 facing away from the dielectric substrate 1 .

[0156] Step S253 may include forming a second conductive film as a second seed layer on the side of the first interlayer insulating layer 41 facing away from the dielectric substrate 1 by methods including electroplating, chemical plating, etc., or by sputtering, and then spin-coating photoresist on the side of the second seed layer facing away from the dielectric substrate 1, exposing and developing, electroplating, and chemically plating metal to form a second coil structure 32.

[0157] The second conductive film is typically made of a highly adhesive metal or metal nitride such as Ti, Ta, TiN, or TaN. The second coil structure is typically made of a metal such as Au, Al, Ag, or Cu. The thickness of the second coil structure 32 is typically between 3 and 7 μm. To ensure the flatness of the second coil structure 32, the upper surface of the second coil structure 32 (i.e., the surface facing away from the dielectric substrate 1) is processed using chemical mechanical polishing (CMP).

[0158] The specific process of forming the second coil structure 32 can refer to the specific process of forming the first coil structure 31 described above, and the repeated parts will not be repeated.

[0159] S254 , as shown in FIG9 g , forming a second first interlayer insulating layer 41 on a side of the second coil structure 32 facing away from the dielectric substrate 1 .

[0160] Here, the process of forming the first interlayer insulating layer 41 is similar to the specific process of forming the second interlayer insulating layer 42 , and the repeated parts are not repeated here.

[0161] A first connection via 1 penetrating the thickness direction of the second first interlayer insulating layer 41 is formed on the second first interlayer insulating layer 41 . The first coil structure 31 is electrically connected to the adjacent third coil structure 33 through the first connection via 1 .

[0162] For example, the material of the second interlayer insulating layer 42 may be a photosensitive PI material. The thickness of the second interlayer insulating layer 41 may be determined according to design requirements, and is generally between 3 and 8 μm.

[0163] S255 , as shown in FIG9 h , forming a third coil structure 33 on the side of the second first interlayer insulating layer 41 facing away from the dielectric substrate 1 .

[0164] Step S255 may include forming a third conductive film as a third seed layer on the side of the second first interlayer insulating layer 41 facing away from the dielectric substrate 1 by methods including electroplating, chemical plating, etc., or by sputtering, and then spin-coating photoresist, exposing and developing, electroplating, and chemically plating metal on the side of the third seed layer facing away from the dielectric substrate 1 to form a third coil structure 33.

[0165] The material of the third conductive film is typically a metal or metal nitride with high adhesion, such as Ti, Ta, TiN, or TaN. The material of the first coil structure is typically a metal such as Au, Al, Ag, or Cu. The thickness of the second coil structure 32 is typically 3 to 7 μm. To ensure the flatness of the second coil structure 32, the upper surface of the second coil structure 32 (i.e., the surface facing away from the dielectric substrate 1) is processed using chemical mechanical polishing (CMP).

[0166] The specific process of forming the third coil structure 33 can refer to the specific process of forming the first coil structure 31 described above, and the repeated parts will not be repeated.

[0167] S26 . As shown in FIG. 9 i , a sixth interlayer insulating layer 46 is formed on the side of the third coil structure 33 facing away from the dielectric substrate 1 .

[0168] Here, the process of forming the sixth interlayer insulating layer 46 is similar to the specific process of forming the second interlayer insulating layer 42 , and the repeated parts are not repeated here.

[0169] A third connection via hole via 3 is formed on the sixth interlayer insulating layer 46 and passes through the sixth interlayer insulating layer 46 in a thickness direction. The third coil structure 33 is electrically connected to the connection structure 5 through the third connection via hole via 3 .

[0170] For example, a photosensitive PI material may be selected as the material of the sixth interlayer insulating layer 46. The thickness of the first interlayer insulating layer 41 may be determined according to design requirements, and is generally between 3 and 8 μm.

[0171] S27 . As shown in FIG. 9 j , a connection structure 5 is formed on the side of the sixth interlayer insulating layer 46 facing away from the dielectric substrate 1 .

[0172] The connection structure 5 can be prepared by selecting a packaging method corresponding to a solder ball or a copper pillar. The solder ball 1 can be made by printing, ball planting, etc., and the copper pillar is made by electroplating.

[0173] For example, taking the additive method as an example, a fourth conductive film material can be deposited on the side of the sixth interlayer insulating layer 46 facing away from the dielectric substrate 1 by a PVD process, and the fourth conductive film serves as a fourth seed layer of the connection structure 5 . Ti is generally selected as the material for the fourth conductive film. The thickness of the fourth conductive film material can be adjusted according to needs, and can usually be selected between 100 and 500 nm to ensure that the surface of the sixth interlayer insulating layer 46 is completely covered. In particular, it is necessary to ensure that the fourth conductive film material in the PI via and on the side wall of the via are completely covered without breakage. Then, a layer of PR glue is coated on the side of the fourth conductive film material away from the dielectric substrate 1. The PR glue uses ordinary photosensitive PR glue, and positive PR glue or negative PR glue can be selected. The thickness can be determined according to the thickness of the electroplated connection structure 5. Usually, the thickness of the PR glue is greater than the thickness of the electroplated connection structure 5. Then, the PR glue is exposed and developed using a mask to form a pattern of the connection structure 5, and the PR glue outside the pattern of the connection structure 5 is removed. If a positive photoresist is selected, the slope angle of the pattern is generally an acute angle. Combined with the slope angle of the edge of the subsequent electroplated metal pattern and the subsequent process, the closer the slope angle of the PR glue pattern is to a right angle, the better. Next, Cu is electroplated on the fourth seed layer to form the first sub-connection layer 51; the thickness of the first sub-connection layer 51 can be selected between 20 and 60 μm. A barrier layer 53 is formed on the side of the first sub-connection layer 51 facing away from the dielectric substrate 1. The material of the barrier layer 53 can be Ni, and the thickness of the barrier layer 53 can be selected between 3 and 10 μm. Silver-tin alloy (Sn-Ag) or tin (Sn) is electroplated on the side of the barrier layer 53 facing away from the dielectric substrate 1 to form the second sub-connection layer 52; the thickness of the second sub-connection layer 52 can be selected between 20 and 50 μm. Next, the remaining PR adhesive is removed, exposing the remaining fourth seed layer. The fourth seed layer outside the connection structure 5 pattern is completely etched away to prevent the fourth seed layer below the connection structure 5 from being etched, forming a chamfer and affecting the bonding strength between the film layers. Next, the second sub-connection layer 52 is reflowed, changing the top of the SnAg or Sn film from a flat surface to an arc shape, ensuring the soldering effect of subsequent devices. The final shape is shown in Figure 9j.

[0174] The above steps S21 to S27 can reduce the overall coil area of ​​the inductor 3 when viewed from above by sequentially connecting and arranging the coils with most of their projections overlapping, thereby saving device wiring space and facilitating device miniaturization.

[0175] In some embodiments, FIG. 10 a to FIG. 10 h are schematic diagrams of preparing the filter shown in FIG. 5 according to an embodiment of the present disclosure. As shown in FIG. 10 a to FIG. 10 h , steps S31 to S37 are included, wherein:

[0176] S31. Provide a dielectric substrate 1.

[0177] For example, a dielectric substrate 1 with a thickness of 0.15 to 2 mm suitable for mass production is prepared based on process equipment requirements. The dielectric substrate 1 can be made of materials with high insulation and low dielectric loss, such as glass, high-resistance silicon, or ceramic. Step S21 includes a pre-preparation cleaning process for the dielectric substrate 1. The process involves ultrasonic cleaning with deionized water, ethanol, isopropyl alcohol, and other organic solvents for at least 15 minutes. The substrate is then oven-dried, which can be continued at 75°C for a specific time, depending on the final cleaning solvent.

[0178] S32 , forming a first conductive pattern M1 including a first electrode plate 21 and a first coil structure 31 on the dielectric substrate 1 .

[0179] As shown in FIG10 a , step S32 may include forming a first conductive film on the dielectric substrate 1 by methods including electroplating, chemical plating, etc., or by sputtering, as a first seed layer; then, spin-coating photoresist, exposing and developing, electroplating, and chemically plating metal on the side of the first seed layer facing away from the dielectric substrate 1 to form a first conductive pattern M1 including the first electrode 21 and the first coil structure 31.

[0180] The material of the first seed layer is generally a metal or metal nitride with high adhesion, such as Ti, Ta, TiN, or TaN. The thickness of the first seed layer can be adjusted according to demand, and the thickness is generally between 30 and 200 nm. Alternatively, the material of the first seed layer can also be copper (Cu), and the thickness of Cu is generally between 0.1 and 1 μm. The material of the first conductive pattern M1 is generally a metal material such as Au, Al, Ag, or Cu. The first electrode plate 21 and the first coil structure 31 can be an integrally formed structure, and the thickness of the integrally formed first electrode plate 21 and the first coil structure 31 is generally between 3 and 7 μm. In order to ensure the flatness of the integrally formed first electrode plate 21 and the first coil structure 31, the upper surface of the first coil structure 31 (i.e., the surface facing away from the dielectric substrate 1) can be processed by chemical mechanical polishing (CMP).

[0181] For example, as shown in Figure 10a, a photoresist is applied to the side of the first conductive film facing away from the dielectric substrate 1. The photoresist is a standard photosensitive photoresist, either positive or negative. The thickness can be selected based on the thickness of the electroplated first conductive pattern M1; typically, the thickness of the photoresist is greater than the thickness of the electroplated first conductive pattern M1. The photoresist is then exposed using a mask and developed to form the pattern of the first conductive pattern M1. The photoresist corresponding to the pattern of the first conductive pattern M1 is then removed. If a positive photoresist is used, the slope angle of the pattern is generally acute. Considering the slope angle of the edge of the subsequently electroplated metal pattern and subsequent processing, the closer the slope angle of the photoresist pattern is to a right angle, the better. If a negative photoresist is used, the slope angle of the pattern is generally obtuse. The product morphology shown in Figure 10a is the exposure morphology of the negative photoresist. Next, Cu is electroplated on the area of ​​the first seed layer not covered by the photoresist, forming the integral first electrode 21 and first coil structure 31. Because the electroplated metal will completely fill the internal space of the PR glue, the slope angle of the electroplated M1 metal is determined by the properties of the PR glue. If a positive PR glue is selected, the slope angle of the M1 metal sidewall grown by the additive electroplating method is obtuse, that is, the length of the upper surface of the metal is longer than the lower surface. If a negative PR glue is selected, the slope angle of the metal grown by the additive electroplating method is acute. The metal morphology of the M1 layer shown in the figure is formed by the additive electroplating of the negative PR glue. The surface of the electroplated metal will have slight undulations under microscopic observation, and the roughness is generally above 10nm. Afterwards, the remaining PR glue is removed to expose the first seed layer. Afterwards, the first seed layer outside the metal Cu cover is completely etched away to form the first conductive pattern M1.

[0182] S33 , forming a second conductive pattern M2 on a side of the first conductive pattern M1 facing away from the dielectric substrate 1 .

[0183] The second conductive pattern M2 includes the second electrode plate 22 of the capacitor 2 . The first electrode plate 21 is electrically connected to the inductor 3 .

[0184] For example, as shown in FIG10b , an insulating layer material can be deposited on the side of the first conductive pattern M1 away from the dielectric substrate 1 by a CVD process. The insulating layer material can be silicon nitride (SiNx) as the insulating layer 40 of the upper and lower plates of the capacitor 2. The thickness of the insulating layer material can be designed and determined according to the requirements of the capacitor 2 value, and the thickness can usually be set between 80 and 200 nm. Afterwards, a second conductive pattern material can be deposited on the side of the insulating layer material away from the dielectric substrate 1 by a PVD process. The second conductive pattern material can be made of a material with good conductivity such as Cu and Al. The metal thickness is made according to the requirements and the thickness can be selected between 0.2 and 2 μm. An adhesive layer can be formed between the insulating layer material and the second conductive pattern material. The adhesive layer can be made of a metal or metal nitride with high adhesion such as Ti, Ta, TiN, TaN, etc. The thickness is adjusted according to the process capability and can be selected between 30 and 100 nm. Afterwards, a layer of PR glue is applied on the side of the second conductive pattern material facing away from the dielectric substrate 1. The PR glue uses ordinary photosensitive PR glue, and positive PR glue or negative PR glue can be selected. The thickness can ensure that the surface of the second conductive pattern material is completely covered to a certain thickness. The thickness of the PR glue can be considered to be between 1um and 4um. Afterwards, the PR glue is exposed using a mask and developed. The PR glue above the pattern of the second electrode 22 that needs to be retained is retained, and all other areas are removed. Afterwards, the second conductive pattern material outside the pattern is removed. When Cu is selected as the second conductive pattern material, wet etching can be used. When Al is selected as the second conductive pattern material, wet etching or dry etching can be used. Different metals can choose different etching methods. Afterwards, the PR glue above the metal pattern is removed to form a second conductive pattern M2 containing the second electrode 22. Next, a layer of PR glue is applied to the side of the second conductive pattern M2 facing away from the dielectric substrate 1. The PR glue uses a conventional photosensitive PR glue, either positive or negative. The thickness is sufficient to ensure complete coverage of the surface of the insulating layer material. The PR glue thickness can be between 1 μm and 4 μm. The PR glue is then exposed using a mask and developed. The PR glue above the pattern of the insulating layer 40 to be retained is retained, while all other areas are removed. The insulating layer material outside the pattern is then removed, typically using dry etching. The PR glue above the pattern of the insulating layer 40 is then removed, forming the insulating layer 40.

[0185] S34 , forming a third interlayer insulating layer 43 on a side of the second conductive pattern M2 away from the first conductive pattern M1 .

[0186] The third interlayer insulating layer 43 covers the second electrode plate 22 , and the integrally formed first electrode plate 21 and first coil structure 31 .

[0187] A first connection via hole via 1 is formed on the third interlayer insulating layer 43 and passes through the third interlayer insulating layer 43 in a thickness direction thereof. The first coil structure 31 is electrically connected to the adjacent second coil structure 32 through the first connection via hole via 1 .

[0188] For example, as shown in FIG10c , the material of the third interlayer insulating layer 43 can be a photosensitive PI material, and the thickness is determined according to the design requirements, usually between 3 and 8 um; through exposure and development, the PI material at the overlapping position of the first coil structure 31 and the second electrode 22 is removed and cured to form a first connecting via 1; the PI material is changed from a soft film to a hard film to increase the strength of the film layer. Since the PI material is usually a negative resin, the bottom size of the PI via is smaller than the top size of the via, and the slope angle can be adjusted between 20° and 90° by changing the process conditions to form the third interlayer insulating layer 43.

[0189] It should be noted that the gentler the slope angle, the more evenly the via sidewalls will be covered by the subsequent electroplated metal seed layer, and the less likely it is that the film will peel off. However, a gentler slope angle will cause the size of the via top to increase, and the via slope angle needs to be adjusted based on the size of the previous metal pattern.

[0190] In this step S34, a third interlayer insulating layer 43 is formed through a single patterning process to cover the second electrode 22, as well as the integrally formed first electrode 21 and the first coil structure 31. This can achieve insulation between the capacitor 2 and the first coil structure 31 and the upper second coil structure 32, reduce process steps, and thus reduce production costs.

[0191] S35 , forming multiple layers of third conductive patterns M3 on a side of the third interlayer insulating layer 43 facing away from the dielectric substrate 1 , and forming at least one layer of the first interlayer insulating layer 41 between adjacent third conductive patterns M3 .

[0192] Taking the inductor 3 including a three-layer coil structure as an example, the process specifically includes steps S351 to S353, wherein:

[0193] S351 , as shown in FIG10 d , forming a second coil structure 32 on a side of the third interlayer insulating layer 43 facing away from the dielectric substrate 1 .

[0194] Step S351 may include forming a second conductive film as a second seed layer on the side of the third interlayer insulating layer 43 facing away from the dielectric substrate 1 by methods including electroplating, chemical plating, etc., or by sputtering, and then spin-coating photoresist, exposing and developing, electroplating, and chemically plating metal on the side of the second seed layer facing away from the dielectric substrate 1 to form a second coil structure 32.

[0195] The second conductive film is typically made of a highly adhesive metal or metal nitride such as Ti, Ta, TiN, or TaN. The second coil structure is typically made of a metal such as Au, Al, Ag, or Cu. The thickness of the second coil structure 32 is typically between 3 and 7 μm. To ensure the flatness of the second coil structure 32, the upper surface of the second coil structure 32 (i.e., the surface facing away from the dielectric substrate 1) is processed using chemical mechanical polishing (CMP).

[0196] For example, a second conductive film material can be deposited on the side of the third interlayer insulating layer 43 facing away from the dielectric substrate 1 through a PVD process. The second conductive film material is generally Ti, and the thickness of the second conductive film material can be adjusted as needed to ensure that the surface of the second interlayer insulating layer 42 is completely covered. In particular, it is necessary to ensure that the first conductive film material in the PI via and on the sidewall of the via are completely covered without breakage. Normally, the thickness of the second conductive film material can be selected to be above 0.2 nm. Thereafter, a layer of PR glue is coated on the side of the second conductive film material facing away from the dielectric substrate 1. The PR glue is an ordinary photosensitive PR glue, and positive PR glue or negative PR glue can be selected. The thickness can be determined according to the thickness of the electroplated second coil structure 32. Normally, the thickness of the PR glue is greater than the thickness of the electroplated second coil structure 32. Afterwards, the PR glue is exposed using a mask and developed to form the pattern of the second coil structure 32, and the PR glue outside the pattern of the second coil structure 32 is removed; if a positive photoresist is selected, the slope angle of the pattern is generally an acute angle. Combined with the slope angle of the edge of the subsequent electroplated metal pattern and the subsequent process, the closer the slope angle of the PR glue pattern is to a right angle, the better. If a negative photoresist is selected, the slope angle of the pattern is generally an obtuse angle. Afterwards, Cu is electroplated on the second seed layer to form the second coil structure material. Afterwards, the remaining PR glue is removed, the remaining second seed layer is completely exposed, and the second seed layer outside the pattern of the second coil structure 32 is completely etched away to prevent the second seed layer below the second coil structure 32 from being etched, forming a chamfer, and affecting the bonding force between the film layers. The final shape is shown in Figure 10d.

[0197] S352 , as shown in FIG10 e , forming a first interlayer insulating layer 41 on a side of the second coil structure 32 facing away from the dielectric substrate 1 .

[0198] Here, the process of forming the first interlayer insulating layer 41 is similar to the specific process of forming the third interlayer insulating layer 43 , and the repeated parts are not repeated here.

[0199] A first connecting via hole via 1 is formed on the first interlayer insulating layer 41 and passes through the first interlayer insulating layer 41 in a thickness direction thereof. The second coil structure 32 is electrically connected to the adjacent third coil structure 33 through the first connecting via hole via 1 .

[0200] For example, a photosensitive PI material may be selected as the material of the first interlayer insulating layer 41. The thickness of the first interlayer insulating layer 41 may be determined according to design requirements, and is generally between 3 and 8 μm.

[0201] S353 , as shown in FIG10 f , forming a third coil structure 33 on a side of the first interlayer insulating layer 41 away from the dielectric substrate 1 .

[0202] Step S353 may include forming a third conductive film as a third seed layer on the side of the first interlayer insulating layer 41 facing away from the dielectric substrate 1 by methods including electroplating, chemical plating, etc., or by sputtering, and then spin-coating photoresist, exposing and developing, electroplating, and chemically plating metal on the side of the third seed layer facing away from the dielectric substrate 1 to form a third coil structure 33.

[0203] The material of the third conductive film is typically a metal or metal nitride with high adhesion, such as Ti, Ta, TiN, or TaN. The material of the third coil structure 33 is typically a metal such as Au, Al, Ag, or Cu. The thickness of the third coil structure 33 is typically between 3 and 7 μm. To ensure the flatness of the third coil structure 33, the upper surface of the second coil structure 32 (i.e., the surface facing away from the dielectric substrate 1) is processed using chemical mechanical polishing (CMP).

[0204] The specific process of forming the third coil structure 33 can refer to the specific process of forming the second coil structure 32 described above, and the repeated parts will not be repeated.

[0205] S36 , as shown in FIG10 g , forming a sixth interlayer insulating layer 46 on the side of the third coil structure 33 facing away from the dielectric substrate 1 .

[0206] Here, the process of forming the sixth interlayer insulating layer 46 is similar to the specific process of forming the third interlayer insulating layer 43 , and the repeated parts are not repeated here.

[0207] A third connection via hole via 3 is formed on the sixth interlayer insulating layer 46 and passes through the sixth interlayer insulating layer 46 in a thickness direction. The third coil structure 33 is electrically connected to the connection structure 5 through the third connection via hole via 3 .

[0208] For example, a photosensitive PI material may be selected as the material of the sixth interlayer insulating layer 46. The thickness of the first interlayer insulating layer 41 may be determined according to design requirements, and is generally between 3 and 8 μm.

[0209] S37 , as shown in FIG10 h , forming a connection structure 5 on the side of the sixth interlayer insulating layer 46 facing away from the dielectric substrate 1 .

[0210] The specific process of step S37 can refer to the specific implementation process of forming the connection structure 5 in step S27, and the repeated parts will not be repeated.

[0211] In the above steps S31 to S37, compared with the embodiment of steps S21 to S27, the first electrode 21 of the capacitor 2 and the first coil structure 31 of the inductor 3 are on the same layer and connected as an integrally formed structure, which can reduce the process steps and thus reduce production costs. In addition, the generation of the integrally formed first electrode 21 and first coil structure 31 can effectively reduce the thickness of the overall structure of the inductor 3 and achieve a lightweight and thin device. Specifically, compared with the preparation process of the filter in Figure 4, this embodiment can reduce a layer of thin film metal, a layer of back-pass and an insulating layer. As a result, the process flow of this embodiment is shorter, the risk is lower, and the cost is lower.

[0212] In some embodiments, FIG. 11a to FIG. 11i are schematic diagrams of preparing the filter shown in FIG. 6 according to an embodiment of the present disclosure. As shown in FIG. 11a to FIG. 11i , steps S41 to S48 are included, wherein:

[0213] S41, providing a dielectric substrate 1.

[0214] Please refer to the detailed description of step S31 above, and the repeated parts will not be repeated.

[0215] S42 , as shown in FIG11 a , forming a fourth interlayer insulating layer 44 on the dielectric substrate 1 .

[0216] The fourth interlayer insulating layer 44 includes a first receiving portion 441 penetrating along a thickness direction thereof.

[0217] Exemplarily, the material of the fourth interlayer insulating layer 44 can be a photosensitive PI material, or an oxide film such as SiNx or SiO2. If SiNx or SiO2 is used, it is necessary to first deposit a film layer on the glass surface, and then form the fourth interlayer insulating layer 44 pattern by exposing and developing the PR glue and dry etching the oxide film. The advantage of selecting a photosensitive PI material is that the material stress is small, which can effectively reduce the warping of the glass caused by stress, and is conducive to improving the uniformity of the pattern. The fourth interlayer insulating layer 44 is used as the cut-off layer of the CMP process, and at the same time shares the pressure applied to the metal layer during the CMP process to avoid collapse of the metal under pressure. As shown in Figure 11a, the process flow is displayed with a photosensitive PI material.

[0218] Exemplarily, the fourth interlayer insulating layer 44 is made of a photosensitive PI material, with its thickness determined by the required thickness of the first conductive pattern M1. The fourth interlayer insulating layer 44 is typically between 3 and 8 μm thick. Exposure and development are performed to remove the PI material from the patterned area of ​​the first conductive pattern M1, and curing is performed to transform the PI layer from a soft film to a hard film, increasing its strength. Because PI material is typically a negative resist, the bottom dimension of the PI pattern is smaller than the top dimension of the via, and the slope angle is preferably as close to a right angle as possible to prevent the chamfer at the bottom of the pattern from affecting the subsequent deposition of the seed layer.

[0219] S43 , as shown in FIG. 11 b , the first receiving portion 441 is filled with the integrally formed first electrode plate 21 and the first coil structure 31 to form a first conductive pattern M1 .

[0220] The surface of the integrally formed first electrode plate 21 and the first coil structure 31 facing away from the dielectric substrate 1 is flush with the surface of the fourth interlayer insulating layer 44 facing away from the dielectric substrate 1 .

[0221] As shown in FIG11b , step S42 may include forming a first conductive film on the dielectric substrate 1 by methods including electroplating, chemical plating, etc., or by sputtering, as a first seed layer; then, spin-coating photoresist, exposing and developing, electroplating, and chemically plating metal on the side of the first seed layer facing away from the dielectric substrate 1 to form a first conductive pattern M1 including the first electrode 21 and the first coil structure 31.

[0222] The material of the first seed layer is generally a metal or metal nitride with high adhesion, such as Ti, Ta, TiN, or TaN. The thickness of the first seed layer can be adjusted as needed. The material of the first conductive pattern M1 is generally a metal material such as Au, Al, Ag, or Cu. The first electrode plate 21 and the first coil structure 31 can be an integrally formed structure. The thickness of the integrally formed first electrode plate 21 and the first coil structure 31 is generally 3 to 7 μm. In order to ensure the flatness of the integrally formed first electrode plate 21 and the first coil structure 31, the upper surface of the first coil structure 31 (i.e., the surface facing away from the dielectric substrate 1) can be processed by chemical mechanical polishing (CMP).

[0223] Illustratively, a first seed layer is deposited on the fourth interlayer insulating layer 44 using a PVD process, ensuring that the first seed layer completely covers the fourth interlayer insulating layer 44, particularly ensuring that the first seed layer completely covers the sidewalls of the first accommodating portion 441 of the fourth interlayer insulating layer 44 without cracking. Cu can be electroplated using an additive method on the surface of the first seed layer facing away from the dielectric substrate 1, typically ensuring that the electroplated Cu metal grows beyond the first accommodating portion 441 and that electroplated Cu is also present on the surface of the fourth interlayer insulating layer 44 facing away from the dielectric substrate 1. Subsequently, a CMP process is used to remove the electroplated metal and the first seed layer above the PI surface, thereby forming an integrally formed first electrode plate 21 and first coil structure 31. The surfaces of the integrally formed first electrode plate 21 and first coil structure 31 facing away from the dielectric substrate 1 are flush with the surface of the fourth interlayer insulating layer 44 facing away from the dielectric substrate 1.

[0224] S44 , as shown in FIG11 c , forming a second conductive pattern M2 on a side of the first conductive pattern M1 away from the dielectric substrate 1 .

[0225] The second conductive pattern M2 includes the second electrode plate 22 of the capacitor 2 . The first electrode plate 21 is electrically connected to the inductor 3 .

[0226] Please refer to the detailed description of step S33 above, and the repeated parts will not be repeated here.

[0227] S45 , as shown in FIG. 11 d , forming a fifth interlayer insulating layer 45 on a side of the second conductive pattern M2 away from the first conductive pattern M1 .

[0228] The surface of the fifth interlayer insulating layer 45 facing away from the dielectric substrate 1 is parallel to a reference plane of the dielectric substrate 1 extending along the first direction X.

[0229] The step of forming the fifth insulating layer can refer to the detailed description of the above step S34, and the repeated parts will not be repeated.

[0230] A first connection via hole via 1 is formed on the fifth interlayer insulating layer 45 and passes through the fifth interlayer insulating layer 45 in a thickness direction thereof. The first coil structure 31 is electrically connected to the adjacent second coil structure 32 through the first connection via hole via 1 .

[0231] S46 , forming multiple layers of third conductive patterns M3 on the side of the fifth interlayer insulating layer 45 facing away from the dielectric substrate 1 , and forming at least one layer of first interlayer insulating layer 41 between adjacent third conductive patterns M3 .

[0232] Taking the inductor 3 including a three-layer coil structure as an example, the process specifically includes steps S461 to S463, wherein:

[0233] S461 , as shown in FIG11 e , forming a second coil structure 32 on a side of the fifth interlayer insulating layer 45 facing away from the dielectric substrate 1 .

[0234] The process of forming the second coil structure 32 in step S351 can be referred to in step S461 , and the repeated parts will not be repeated.

[0235] S462 , as shown in FIG11 f , forming a first interlayer insulating layer 41 on a side of the second coil structure 32 facing away from the dielectric substrate 1 .

[0236] The process of forming the first interlayer insulating layer 41 in step S462 can refer to the above-mentioned step S352, and the repeated parts are not repeated here.

[0237] S463 , as shown in FIG11 g , forming a third coil structure 33 on a side of the first interlayer insulating layer 41 facing away from the dielectric substrate 1 .

[0238] The principle of forming the third coil structure 33 in this step S463 is the same as the principle of forming the second coil structure 32 in the above step S351. Please refer to the specific implementation process of forming the second coil structure 32 in the above step S351, and the repeated parts will not be repeated.

[0239] S47 . As shown in FIG. 11 h , a sixth interlayer insulating layer 46 is formed on the side of the third coil structure 33 facing away from the dielectric substrate 1 .

[0240] Here, the principle of forming the sixth interlayer insulating layer 46 is the same as the process of forming the third interlayer insulating layer 43 in the above step S34. Please refer to the specific implementation process of forming the third interlayer insulating layer 43 in the above step S34, and the repeated parts will not be repeated.

[0241] S48 . As shown in FIG. 11 i , a connection structure 5 is formed on the side of the sixth interlayer insulating layer 46 facing away from the dielectric substrate 1 .

[0242] Here, the principle of forming the connection structure 5 is the same as the principle of forming the connection structure 5 in the above step S24. Please refer to the specific implementation process of forming the connection structure 5 in the above step S24, and the repeated parts will not be repeated.

[0243] In steps S41 to S48, the surface of the fourth interlayer insulating layer 44 facing away from the dielectric substrate 1 is flush with the surfaces of the integrally formed first electrode plate 21 and first coil structure 31 facing away from the dielectric substrate 1. As a result, the surface of the fifth interlayer insulating layer 45 located on the fourth interlayer insulating layer 44 and arranged opposite to each other in the thickness direction is parallel to a reference plane of the dielectric substrate 1 extending along the first direction X. This reduces the undulation of some film layers and, more importantly, forms a smooth interlayer insulating layer surface. This helps to improve the thickness uniformity of some film layers at different locations, thereby improving the uniformity of device performance.

[0244] In addition, this embodiment uses a CMP process to reduce the roughness of the electroplated metal surface of the first conductive pattern M1, thereby improving the uniformity of the thickness of the first conductive pattern M1, which is beneficial to controlling the uniformity of the thickness of the insulating layer 40 and further beneficial to improving the uniformity of the capacitance value. Compared with the preparation process of the filter shown in Figure 7, it also reduces a PR glue process, shortens the process flow, and reduces costs.

[0245] In some embodiments, FIG. 12a to FIG. 12h are schematic diagrams of preparing the filter shown in FIG. 7 according to an embodiment of the present disclosure. As shown in FIG. 12a to FIG. 12h , steps S51 to S57 are included, wherein:

[0246] S51. Provide a dielectric substrate 1.

[0247] Please refer to the detailed description of step S31 above, and the repeated parts will not be repeated.

[0248] S52 , as shown in FIG12 a , forming a first conductive pattern M1 including a first electrode plate 21 and a first coil structure 31 on the dielectric substrate 1 .

[0249] The first coil structure 31 includes a first sub-coil 311 and a second sub-coil 321 which are stacked. The first sub-coil 311 is located on a side of the second sub-coil 321 close to the dielectric substrate 1 .

[0250] Step S52 may include forming a first conductive film as a first seed layer on the dielectric substrate 1 by methods including electroplating, chemical plating, or sputtering; wherein at least a portion of the structure of the first seed layer serves as the first sub-coil 311; then, spin-coating photoresist, exposing and developing, electroplating, and chemically plating metal on a side of the first seed layer facing away from the dielectric substrate 1 to form a second sub-coil 321 opposite to the first sub-coil 311.

[0251] The material of the first conductive film is typically a metal or metal nitride with high adhesion, such as Ti, Ta, TiN, or TaN. The material of the second sub-coil 321 is typically a metal such as Au, Al, Ag, or Cu. The thickness of the second sub-coil 321 is typically between 3 and 7 μm. To ensure the flatness of the first coil structure 31, the upper surface of the first coil structure 31 (i.e., the surface facing away from the dielectric substrate 1) is processed using chemical mechanical polishing (CMP).

[0252] For example, as shown in FIG12a , the first conductive film can be formed by electroplating using either an additive or subtractive method. For example, using the additive method, a first conductive film material, typically Ti, is deposited on a dielectric substrate 1 using a PVD process. A layer of photoresist (PR) is then applied to the side of the first conductive film material facing away from the dielectric substrate 1. The PR adhesive is a standard photosensitive PR adhesive, either positive or negative. The thickness is determined based on the thickness of the electroplated first coil structure 31. Typically, the thickness of the PR adhesive is greater than the thickness of the electroplated second sub-coil 321. The PR adhesive is then exposed using a mask and developed to form the pattern of the second sub-coil 321. The PR adhesive outside the pattern of the second sub-coil 321 is then removed. If a positive photoresist is used, the pattern slope angle is typically acute. Considering the slope angle of the subsequent electroplated metal pattern edge and subsequent processing, the closer the PR adhesive pattern slope angle is to a right angle, the better. If a negative photoresist is used, the pattern slope angle is typically obtuse. Afterwards, Cu is electroplated on the first seed layer to form the material for the second sub-coil 321. The thickness of the second sub-coil 321 material is determined according to requirements and can generally be selected between 3 and 7 μm. The remaining PR glue is then removed, exposing the entire remaining first seed layer. PR glue is then reapplied to the exposed first seed layer and the surface of the second sub-coil 321 facing away from the dielectric substrate 1. The thickness of the PR glue should be sufficient to cover the surface of the second sub-coil 321. The thickness of the PR glue is generally selected between 5 μm and 10 μm. The PR glue is then exposed using a mask and developed. The PR glue above the pattern of the first electrode 21 to be retained is retained, while the PR glue in all other areas is removed. The first seed layer corresponding to the portion not covered by the PR glue is then removed, forming an integrally formed first electrode 21, first sub-coil 311, and second sub-coil 321.

[0253] S53 , as shown in FIG12 b , forming a second conductive pattern M2 on a side of the first conductive pattern M1 away from the dielectric substrate 1 .

[0254] The second conductive pattern M2 includes the second electrode plate 22 of the capacitor 2. The first electrode plate 21 and the first sub-coil 311 are integrally formed.

[0255] Here, the principle of forming the second conductive pattern M2 is the same as the principle of forming the second conductive pattern M2 in the above step S33. Please refer to the specific implementation process of forming the second conductive pattern M2 in the above step S33, and the repeated parts will not be repeated.

[0256] S54 , as shown in FIG12 c , forming a third interlayer insulating layer 43 on a side of the second conductive pattern M2 away from the first conductive pattern M1 .

[0257] Here, the principle of forming the third interlayer insulating layer 43 is the same as the principle of forming the third interlayer insulating layer 43 in the above step S34. Please refer to the specific implementation process of forming the third interlayer insulating layer 43 in the above step S34, and the repeated parts will not be repeated.

[0258] S55 , forming multiple layers of third conductive patterns M3 on a side of the third interlayer insulating layer 43 facing away from the dielectric substrate 1 , and forming at least one layer of the first interlayer insulating layer 41 between adjacent third conductive patterns M3 .

[0259] Taking the inductor 3 including a three-layer coil structure as an example, the process specifically includes steps S551 to S553, wherein:

[0260] S551 , as shown in FIG12 d , forming a second coil structure 32 on a side of the third interlayer insulating layer 43 facing away from the dielectric substrate 1 .

[0261] S552 , as shown in FIG12 e , forming a first interlayer insulating layer 41 on a side of the second coil structure 32 facing away from the dielectric substrate 1 .

[0262] S553 , as shown in FIG12 f , forming a third coil structure 33 on a side of the first interlayer insulating layer 41 away from the dielectric substrate 1 .

[0263] S56 , as shown in FIG12 g , forming a sixth interlayer insulating layer 46 on the side of the third coil structure 33 facing away from the dielectric substrate 1 .

[0264] S57 , as shown in FIG12 h , forming a connection structure 5 on the side of the sixth interlayer insulating layer 46 facing away from the dielectric substrate 1 .

[0265] The principle of forming each third conductive pattern M3, the sixth interlayer insulating layer 46 and the connection structure 5 in the above steps S55 to S57 is the same as the principle of forming each third conductive pattern M3, the sixth interlayer insulating layer 46 and the connection structure 5 in the above steps S35 to S37. For details, please refer to the specific implementation process of the above steps S35 to S37, and the repeated parts will not be repeated.

[0266] The above steps S51 to S57 prepare a filter, wherein the common first electrode and the first sub-coil are formed by PVD, so the roughness of the metal surface is higher when intersecting with the electroplated metal, which is beneficial to controlling the uniformity of the thickness of the insulating layer 40 and is more beneficial to improving the uniformity of the capacitance value. Moreover, since the common first electrode and the first sub-coil are the seed layers of the second sub-coil, there is no need to add an additional thin layer metal PVD process for the first coil structure. In addition, the first electrode and the first sub-coil can be directly connected to the second sub-coil through metal, and there is no need to overlap through vias between the insulating layers, thereby reducing process risks.

[0267] In some embodiments, FIG. 13a to FIG. 13k are schematic diagrams of preparing the filter shown in FIG. 8 according to an embodiment of the present disclosure. As shown in FIG. 13a to FIG. 13k , steps S61 to S68 are included, wherein:

[0268] S61. Provide a dielectric substrate 1.

[0269] Please refer to the detailed description of step S41 above, and the repeated parts will not be repeated.

[0270] S62 , as shown in FIG13 a , forming a fourth interlayer insulating layer 44 on the dielectric substrate 1 .

[0271] Please refer to the detailed description of step S42 above, and the repeated parts will not be repeated.

[0272] S63 , as shown in FIG13 b , the first receiving portion 441 is filled with the integrally formed first electrode plate 21 and the first coil structure 31 to form a first conductive pattern M1 .

[0273] Please refer to the detailed description of step S43 above, and the repeated parts will not be repeated.

[0274] S64 , as shown in FIG13 c , forming a second conductive pattern M2 on a side of the first conductive pattern M1 away from the dielectric substrate 1 .

[0275] Please refer to the detailed description of step S44 above, and the repeated parts will not be repeated.

[0276] S65 , as shown in FIG13 d , forming a fifth interlayer insulating layer 45 on a side of the second conductive pattern M2 away from the first conductive pattern M1 .

[0277] Please refer to the detailed description of step S45 above, and the repeated parts will not be repeated.

[0278] S66 , forming multiple layers of third conductive patterns M3 on the side of the fifth interlayer insulating layer 45 facing away from the dielectric substrate 1 , and forming at least one layer of first interlayer insulating layer 41 between adjacent third conductive patterns M3 .

[0279] Taking the inductor 3 including a three-layer coil structure as an example, the process specifically includes steps S661 to S665, wherein:

[0280] S661 , as shown in FIG13 e , forming a first seventh interlayer insulating layer 47 on the side of the fifth interlayer insulating layer 45 facing away from the dielectric substrate 1 .

[0281] The first seventh interlayer insulating layer 47 includes a second receiving portion 471 penetrating along a thickness direction thereof.

[0282] Here, the principle of forming the seventh interlayer insulating layer 47 is the same as the principle of forming the fourth interlayer insulating layer 44 in the above step S42. Please refer to the specific implementation process of forming the fourth interlayer insulating layer 44 in the above step S42, and the repeated parts will not be repeated.

[0283] S662 , as shown in FIG13 f , filling the second receiving portion 471 of the first seventh interlayer insulating layer 47 with the coil structure material of the inductor 3 to form a second coil structure 32 .

[0284] The second coil structure 32 faces away from the surface of the dielectric substrate 1 and is flush with the surface of the seventh interlayer insulating layer 47 facing away from the dielectric substrate 1 .

[0285] Here, the principle of forming the second coil structure 32 is the same as the principle of forming the integrally formed first electrode plate 21 and the first coil structure 31 in step S43 above. Please refer to the specific implementation process of forming the first conductive pattern M1 in step S43 above, and the repeated parts will not be repeated.

[0286] S663 , as shown in FIG13 g , forming a first interlayer insulating layer 41 on a side of the second coil structure 32 facing away from the dielectric substrate 1 .

[0287] Here, the principle of forming the first interlayer insulating layer 41 is the same as the principle of forming the fifth interlayer insulating layer 45 in the above S45. Please refer to the specific implementation process of forming the fifth interlayer insulating layer 45 in the above step S45, and the repeated parts will not be repeated.

[0288] Here, the first interlayer structure includes a first surface and a second surface that are oppositely arranged along the thickness direction thereof, and both the first surface and the second surface are parallel to a reference plane extending along the first direction X of the dielectric substrate 1 .

[0289] S664 , as shown in FIG13 h , forming a second seventh interlayer insulating layer 47 on the side of the first interlayer insulating layer 41 facing away from the dielectric substrate 1 .

[0290] The second seventh interlayer insulating layer 47 includes a second receiving portion 471 penetrating along a thickness direction thereof.

[0291] Here, the principle of forming the seventh interlayer insulating layer 47 is the same as the principle of forming the fourth interlayer insulating layer 44 in the above step S42. Please refer to the specific implementation process of forming the fourth interlayer insulating layer 44 in the above step S42, and the repeated parts will not be repeated.

[0292] S665 , as shown in FIG13 i , the coil structure material of the inductor 3 is filled in the second receiving portion 471 of the second seventh interlayer insulating layer 47 to form a third coil structure 33 .

[0293] The third coil structure 33 faces away from the surface of the dielectric substrate 1 and is flush with the surface of the second interlayer insulating layer 42 facing away from the dielectric substrate 1 .

[0294] The principle of forming the third coil structure 33 in this step S665 is the same as the principle of forming the first conductive pattern M1 in the above step S43. Please refer to the specific implementation process of forming the first conductive pattern M1 in the above step S43, and the repeated parts will not be repeated.

[0295] S67 . As shown in FIG. 13 j , a sixth interlayer insulating layer 46 is formed on the side of the third coil structure 33 facing away from the dielectric substrate 1 .

[0296] Here, the principle of forming the sixth interlayer insulating layer 46 is the same as the principle of forming the fifth interlayer insulating layer 45 in the above S45. Please refer to the specific implementation process of forming the fifth interlayer insulating layer 45 in the above step S45, and the repeated parts will not be repeated.

[0297] Here, the sixth interlayer structure includes a first surface and a second surface disposed opposite to each other along the thickness direction thereof, and both the first surface and the second surface are parallel to a reference plane extending along the first direction X of the dielectric substrate 1 .

[0298] S68 , as shown in FIG13 k , forming a connection structure 5 on the side of the sixth interlayer insulating layer 46 facing away from the dielectric substrate 1 .

[0299] Here, the principle of forming the connection structure 5 is the same as the principle of forming the connection structure 5 in the above step S24. Please refer to the specific implementation process of forming the connection structure 5 in the above step S24, and the repeated parts will not be repeated.

[0300] The process of steps S61 to S68 forms an interlayer insulating layer surface with no undulations, which is beneficial to improving the thickness uniformity of each film layer at different positions, thereby improving the uniformity of device performance.

[0301] In addition, the present disclosure provides an electronic device that may include the above-mentioned filter. Other essential components of the electronic device are well understood by those skilled in the art and are not described in detail here and should not be construed as limiting the present disclosure.

[0302] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A filter comprising a dielectric substrate, at least one capacitor and at least one inductor arranged on the dielectric substrate; The capacitor comprises a first plate and a second plate which are arranged opposite to each other, wherein the first plate is located on a side of the second plate close to the dielectric substrate; at least one of the first plate and the second plate is electrically connected to the inductor; The inductor comprises a multi-layer coil structure sequentially arranged on the dielectric substrate, and at least one first interlayer insulating layer is arranged between adjacent coil structures; the coil structures of adjacent layers are electrically connected through a first connecting via penetrating the first interlayer insulating layer therebetween; The orthographic projections of any two of the multiple layers of the coil structures on the dielectric substrate partially overlap.

2. The filter according to claim 1, wherein The capacitor is arranged on a side of the inductor close to the dielectric substrate, and at least one second interlayer insulating layer is arranged between the capacitor and the inductor.

3. The filter according to claim 2, wherein: The coil structure closest to the dielectric substrate in the multi-layer coil structure is the first coil structure; the second pole plate is electrically connected to the first coil structure.

4. The filter according to claim 3, wherein: The capacitor further includes a first lead terminal; The first lead end and the second electrode plate are arranged in the same layer, and the two are an integrally formed structure; the first lead end and the first coil structure are electrically connected through a second connecting via, and the second connecting via passes through the second interlayer insulating layer between the second electrode plate and the first coil structure.

5. The filter according to claim 1, wherein The coil structure closest to the dielectric substrate in the multi-layer coil structure is a first coil structure; The first pole plate and the first coil structure are arranged in the same layer and are electrically connected.

6. The filter according to claim 5, wherein The first pole plate and the first coil structure are an integrally formed structure.

7. The filter according to claim 6, wherein: The coil structure adjacent to the first coil structure in the multi-layer coil structure is a second coil structure; A third interlayer insulating layer is provided between the second coil structure and the dielectric substrate, and the third interlayer insulating layer covers the second pole plate, and the first pole plate and the first coil structure formed in one piece.

8. The filter according to claim 6, wherein: The coil structure adjacent to the first coil structure in the multi-layer coil structure is a second coil structure; A fourth interlayer insulating layer and a fifth interlayer insulating layer are provided between the second coil structure and the dielectric substrate, the fourth interlayer insulating layer is provided with a first accommodating portion penetrating along the thickness direction thereof, the first pole plate and the first coil structure formed integrally are confined in the first accommodating portion, and the surfaces of the first pole plate and the first coil structure formed integrally away from the dielectric substrate are flush with the surface of the fourth interlayer insulating layer away from the dielectric substrate; The fifth interlayer insulating layer is arranged on a side of the fourth interlayer insulating layer away from the dielectric substrate, and the fifth interlayer insulating layer covers the second electrode plate.

9. The filter according to claim 1, wherein: The coil structure closest to the dielectric substrate in the multi-layer coil structure is a first coil structure; The first coil structure includes a first sub-coil and a second sub-coil which are stacked, and the first sub-coil is located on a side of the second sub-coil close to the dielectric substrate; The first pole plate and the first sub-coil are arranged in the same layer and are electrically connected.

10. The filter according to claim 9, wherein The first pole plate and the first sub-coil are an integrally formed structure.

11. The filter according to any one of claims 1 to 10, wherein: It also includes a connection structure, which is arranged on a side of the inductor away from the dielectric substrate and is electrically connected to a third coil structure in the inductor farthest from the dielectric substrate through a third connection via hole; the third connection via hole penetrates a sixth interlayer insulating layer between the connection structure and the third coil structure.

12. The filter according to any one of claims 1 to 10, wherein: The first interlayer insulating layer between any adjacent coil structures includes a first surface and a second surface that are arranged opposite to each other along a thickness direction thereof, and the first surface and the second surface are parallel to a reference plane of the dielectric substrate extending along a first direction.

13. The filter according to any one of claims 1 to 10, wherein: Any seventh interlayer insulating layer in the same layer as the coil structure includes a first surface and a second surface arranged opposite to each other along the thickness direction thereof, and the first surface and the second surface are parallel to a reference surface of the dielectric substrate extending along the first direction.

14. A method for preparing a filter, comprising: A dielectric substrate is provided, and at least one capacitor and at least one inductor are formed on the dielectric substrate; wherein the steps of forming at least one capacitor and at least one inductor include: A first conductive pattern is formed on the dielectric substrate; the first conductive pattern at least includes a first electrode plate of the capacitor; A second conductive pattern is formed on a side of the first conductive pattern away from the dielectric substrate; the second conductive pattern includes a second electrode plate of the capacitor; at least one of the second electrode plate and the first electrode plate is electrically connected to the inductor; A multi-layer third conductive pattern is formed on a side of the second conductive pattern away from the dielectric substrate, and at least one first interlayer insulating layer is formed between adjacent third conductive patterns; the third conductive pattern includes a coil structure of the inductor, and the coil structures of adjacent layers are electrically connected through a first connecting via penetrating the first interlayer insulating layer therebetween; and the orthographic projections of any two of the multi-layer coil structures on the dielectric substrate partially overlap.

15. The method for preparing a filter according to claim 14, wherein: The forming of the first conductive pattern on the dielectric substrate comprises: forming a first conductive pattern including the first electrode plate on the dielectric substrate; The forming of a multi-layer third conductive pattern on a side of the second conductive pattern away from the dielectric substrate comprises: forming a multi-layer coil structure on a side of the second conductive pattern away from the dielectric substrate, wherein the coil structure closest to the dielectric substrate among the multi-layer coil structure is a first coil structure; and the first coil structure is electrically connected to the second pole plate through a second connecting via hole penetrating a second interlayer insulating layer between the first pole plate and the second pole plate.

16. The method for preparing a filter according to claim 14, wherein: The coil structure closest to the dielectric substrate in the multi-layer coil structure of the inductor is the first coil structure; Forming a first conductive pattern on the dielectric substrate includes: A first conductive pattern including the first pole plate and the first coil structure is formed on the dielectric substrate.

17. The method for preparing a filter according to claim 16, wherein: The first electrode plate and the first coil structure are an integrally formed structure; wherein, after forming the second conductive pattern, the method further includes: A third interlayer insulating layer is formed on a side of the second conductive pattern away from the first conductive pattern; the third interlayer insulating layer covers the second electrode plate, and the first electrode plate and the first coil structure formed in one piece.

18. The method for preparing a filter according to claim 16, wherein: The first pole plate and the first coil structure are an integrally formed structure; The first conductive pattern including the first electrode plate and the first coil structure is formed on the dielectric substrate, comprising: forming a fourth interlayer insulating layer on the dielectric substrate; the fourth interlayer insulating layer comprises a first accommodating portion penetrating along a thickness direction thereof; The first accommodating portion is filled with the first pole plate and the first coil structure formed integrally to form the first conductive pattern; the first pole plate and the first coil structure formed integrally are away from the surface of the dielectric substrate and are flush with the surface of the fourth interlayer insulating layer away from the dielectric substrate.

19. The method for preparing a filter according to claim 18, wherein: After forming the second conductive pattern, the method further includes: A fifth interlayer insulating layer is formed on a side of the second conductive pattern away from the first conductive pattern, and a surface of the fifth interlayer insulating layer away from the dielectric substrate is parallel to a reference plane of the dielectric substrate extending along the first direction.

20. The method for preparing a filter according to any one of claims 14 to 19, wherein the step of forming any layer of the third conductive pattern comprises: forming a seventh interlayer insulating layer on the dielectric substrate having the second conductive pattern formed thereon; The seventh interlayer insulating layer includes a second receiving portion penetrating along the thickness direction thereof; The coil structure material of the inductor is filled in the second accommodation portion to form the third conductive pattern; the third conductive pattern faces away from the surface of the dielectric substrate and is flush with the surface of the seventh interlayer insulating layer faces away from the dielectric substrate.

21. The method for preparing a filter according to any one of claims 14 to 19, wherein the step of forming any layer of the third conductive pattern comprises: A third conductive pattern including the coil structure is formed by electroplating on a side of the first interlayer insulating layer facing away from the dielectric substrate.

22. The method for preparing a filter according to any one of claims 14 to 19, wherein: The dielectric substrate includes a glass substrate.

23. An electronic device, wherein: The invention comprises the filter according to any one of claims 1 to 13.

Images