Chip and manufacturing method therefor, and electronic device
By designing a chip structure that directly connects the pixel unit to the DRAM capacitor in the CMOS image sensor, the problem of signal reading speed limit during high-speed cameras is solved, and high-speed data transmission and storage are achieved.
Patent Information
- Application Number
- PCT/CN2023/124302
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-07-18
- Filing Date
- 2023-10-12
- Publication Date
- 2025-03-13
AI Technical Summary
During high-speed cameras, existing CMOS image sensors have a row by line transmission of signals, resulting in limited reading speed, resulting in roller shutter distortion.
A chip is designed, including a pixel chip layer, a memory chip layer and a logic circuit chip layer, where the pixel units of the pixel chip layer are directly connected to the capacitors of the memory chip layer, avoiding the intermediary of the logic circuit and realizing the direct storage of electrical signals.
By directly connecting the pixel units to the DRAM capacitor, the data transmission speed is improved, the delay is reduced, the number of frames transmitted per second is greater than 1000fps, and the speed of storage and reading is improved.
Smart Images
Figure CN2023124302_13032025_PF_FP_ABST
Abstract
Description
Chip and manufacturing method thereof, and electronic device
[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 18, 2023, with application number 202310886437.9 and invention name “Chip and its manufacturing method, electronic device”, the content of which should be understood as incorporated into this application by reference. Technical Field
[0002] The embodiments of the present disclosure relate to, but are not limited to, semiconductor technology, and in particular to a chip and a manufacturing method thereof, and electronic equipment. Background Art
[0003] Sensors used for video and photography generate images by converting light from an external source into electrical signals. High-speed complementary metal oxide semiconductor (CMOS) image sensors (CIS) are an important development direction for CIS sensors used for video and photography. In traditional CIS, light signals are converted from a photosensitive array into electrical signals, which are then transmitted line by line to the interface via a logic control circuit. This line-by-line transmission interface limits the readout speed of the CIS signal, resulting in rolling shutter distortion, a phenomenon where high-speed motion images produce distorted images.
[0004] Summary of the Invention
[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
[0006] In one aspect, an exemplary embodiment of the present disclosure provides a chip, comprising:
[0007] A pixel chip layer, comprising a plurality of pixel units, each pixel unit comprising at least a photoelectric conversion unit, a transfer transistor, a source follower and a floating diffusion portion;
[0008] a memory chip layer disposed below the pixel chip layer and comprising a plurality of memories, each memory comprising a plurality of vertically stacked transistors and capacitors; and
[0009] a logic circuit chip layer, which is arranged below the memory chip layer and includes a plurality of logic circuits for controlling reading and writing of the memory;
[0010] A pixel unit in the pixel chip layer is directly connected to part of the capacitors in the memory chip layer.
[0011] In an exemplary embodiment, one pixel unit in the pixel chip layer is directly connected to one capacitor array.
[0012] In an exemplary embodiment, the source follower in the one pixel unit is directly connected to a capacitor array of the memory chip layer.
[0013] In an exemplary embodiment, the transistor includes a vertically extending active pillar located on a substrate; each active pillar includes a channel layer and a first source / drain located on a side of the channel layer away from the substrate and a second source / drain located on a side of the channel layer close to the substrate; two adjacent columns of active pillars are separated by a first trench extending along a second direction, and two adjacent rows of active pillars are separated by a second trench extending along the first direction; a groove extending along the second direction is provided in the substrate; and the transistor also includes a gate surrounding the channel layer.
[0014] In an exemplary embodiment, the memory further includes a plurality of bit lines extending along the second direction and arranged at intervals in the first direction, each of the bit lines being located in the groove and connected to the second source / drain.
[0015] In an exemplary embodiment, the plurality of bit lines are connected in parallel in the first direction.
[0016] In an exemplary embodiment, the memory further includes a plurality of word lines extending along the first direction and spaced apart in the second direction, the plurality of transistors arranged along the first direction share a word line, and the gate of each transistor is part of the shared word line.
[0017] In an exemplary embodiment, the plurality of word lines are connected in parallel in the second direction.
[0018] In an exemplary embodiment, multi-level through silicon vias are further included to connect the peripheral area of the pixel chip layer, the peripheral area of the memory chip layer, and the logic circuit chip layer.
[0019] In another aspect, an exemplary embodiment of the present disclosure provides a method for manufacturing a chip, comprising the following steps:
[0020] Manufacturing pixel chip layer, memory chip layer and logic circuit chip layer respectively;
[0021] The pixel chip layer, the memory chip layer and the logic circuit chip layer are connected and a pixel unit in the pixel chip layer is directly connected to a part of the capacitors in the memory chip layer.
[0022] In an exemplary embodiment, connecting the pixel chip layer, the memory chip layer, and the logic circuit chip layer comprises the following steps:
[0023] thinning the substrate of the memory chip layer;
[0024] turning over the memory chip layer;
[0025] bonding the memory chip layer to the pixel chip layer;
[0026] flipping the bonded assembly of the pixel chip layer and the memory chip layer so that the pixel chip layer is on top of the memory chip layer; and
[0027] The memory chip layer and the logic circuit chip layer are bonded.
[0028] In an exemplary embodiment, connecting the pixel chip layer, the memory chip layer, and the logic circuit chip layer further comprises the following steps:
[0029] The peripheral area of the pixel chip layer, the peripheral area of the memory chip layer and the logic circuit chip layer are connected by means of a plurality of through silicon vias.
[0030] In another aspect, exemplary embodiments of the present disclosure provide an electronic device including the above chip.
[0031] In exemplary embodiments, the electronic device may include a smartphone, a computer, a tablet, an artificial intelligence device, a wearable device, an imaging system, and the like.
[0032] Other features and advantages of the present disclosure will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present disclosure. Other advantages of the present disclosure can be realized and obtained through the solutions described in the description and the drawings.
[0033] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.
[0034] Summary of the Figures
[0035] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the exemplary embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.
[0036] FIG1A is a schematic cross-sectional view of a chip according to an exemplary embodiment of the present disclosure;
[0037] FIG1B is a schematic diagram of an equivalent circuit of a chip provided according to an exemplary embodiment of the present disclosure;
[0038] FIG2 is a schematic plan view of the working principle of a chip provided according to an exemplary embodiment of the present disclosure;
[0039] FIG3 is a schematic cross-sectional view of a pixel chip layer in a chip according to an exemplary embodiment of the present disclosure;
[0040] 4A is a schematic cross-sectional view of an intermediate product obtained in a memory chip layer manufacturing step in a chip manufacturing method according to an exemplary embodiment of the present disclosure;
[0041] 4B is a schematic cross-sectional view of an intermediate product obtained in a memory chip layer manufacturing step in a chip manufacturing method according to an exemplary embodiment of the present disclosure;
[0042] 4C is a schematic cross-sectional view of an intermediate product obtained in a memory chip layer manufacturing step in a chip manufacturing method according to an exemplary embodiment of the present disclosure;
[0043] 4D is a schematic cross-sectional view of an intermediate product obtained in a memory chip layer manufacturing step in a chip manufacturing method according to an exemplary embodiment of the present disclosure;
[0044] 4E is a schematic cross-sectional view of an intermediate product obtained in a memory chip layer manufacturing step in a chip manufacturing method according to an exemplary embodiment of the present disclosure;
[0045] 4F is a schematic cross-sectional view of an intermediate product obtained in a memory chip layer manufacturing step in a chip manufacturing method according to an exemplary embodiment of the present disclosure;
[0046] 4G is a schematic cross-sectional view of an intermediate product obtained in a memory chip layer manufacturing step in a chip manufacturing method according to an exemplary embodiment of the present disclosure;
[0047] 4H is a schematic cross-sectional view of an intermediate product obtained in a memory chip layer manufacturing step in a chip manufacturing method according to an exemplary embodiment of the present disclosure;
[0048] FIG4I is a schematic cross-sectional view of an intermediate product obtained in a memory chip layer manufacturing step in a chip manufacturing method according to an exemplary embodiment of the present disclosure; and
[0049] FIG5 is a schematic cross-sectional view of a logic circuit chip layer in a chip according to an exemplary embodiment of the present disclosure.
[0050] Details
[0051] The embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of the present application can be combined with each other in any manner.
[0052] The embodiments herein can be implemented in a variety of different forms. A person skilled in the art can easily understand that the implementation and content can be transformed into various forms without departing from the purpose and scope of this application. Therefore, this application should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in this application and the features in the embodiments can be combined with each other in any manner.
[0053] The scales of the figures in this application are intended to serve as a reference for actual processes, but are not limited thereto. For example, the aspect ratio of the semiconductor layer, the thickness of each film layer, and the spacing between them can be adjusted according to actual needs. The figures described in this application are merely schematic diagrams of the structure, and one embodiment of this application is not limited to the shapes or values shown in the figures.
[0054] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the words and phrases are not limited to those described in the specification and may be appropriately replaced according to the circumstances.
[0055] In this specification, unless otherwise specified or limited, the terms "disposed" and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through an intermediary, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances.
[0056] In the description of the present disclosure, ordinal numbers such as “first” and “second” are provided to avoid confusion among constituent elements, rather than to limit the quantity.
[0057] In this specification, "film" and "layer" can be interchanged. For example, "metal layer" can sometimes be replaced with "metal film".
[0058] In the description of this disclosure, a transistor refers to an element comprising at least three terminals: a gate, a drain, and a source. The transistor has a channel layer between the drain (drain terminal, drain region, or drain) and the source (source terminal, source region, or source), and current can flow through the drain, the channel layer, and the source. In this disclosure, the channel layer refers to the area through which current mainly flows. In this disclosure, the terms "semiconductor layer," "channel layer," and "channel region" are interchangeable.
[0059] To increase data transmission speeds in chips used for video and photography and reduce the rolling shutter phenomenon, a CIS+DRAM+LOGIC solution has been proposed. Specifically, a pixel photosensitive array converts light signals into electrical signals and transmits them to a logic circuit chip, which then transmits the electrical signals to a memory device such as DRAM, which then stores the data. However, the applicants of the present disclosure have discovered that because this solution relies on peripheral circuits to connect the CIS chip to the logic circuit chip, and the logic circuit chip to the DRAM chip, that is, between the CIS and DRAM, data transmission requires a certain amount of time, resulting in a certain delay. Furthermore, the data bandwidth in this structure is still relatively small.
[0060] Therefore, an exemplary embodiment of the present application provides a chip, including a pixel chip layer, including a plurality of pixel units, each pixel unit including at least a photoelectric conversion unit, a transfer transistor, a source follower and a floating diffusion; a memory chip layer, which is arranged below the pixel chip layer and includes a plurality of memories, each memory including a plurality of vertically stacked transistors and capacitors; and a logic circuit chip layer, which is arranged below the memory chip layer and includes a plurality of logic circuits for controlling the reading and writing of the memories; wherein one pixel unit in the pixel chip layer is directly connected to part of the capacitors in the memory chip layer.
[0061] In an exemplary embodiment, one pixel unit in the pixel chip layer is directly connected to one capacitor array.
[0062] In an exemplary embodiment, the source follower in the one pixel unit is directly connected to a capacitor array in the memory chip layer.
[0063] As used in this disclosure, the term "first direction" X is defined as a direction parallel to the direction in which the word lines extend; the term "second direction" Y is defined as a direction intersecting the "first direction" X and parallel to the direction in which the bit lines extend; and the term "third direction" Z is defined as a direction perpendicular to the plane in which the substrate lies. The plane formed by the first direction X and the second direction Y is parallel to the substrate. The "first direction" X, the "second direction" Y, and the "third direction" Z can be shown in Figures 4A-4I, etc.
[0064] Figure 1A is a cross-sectional schematic diagram of a chip provided according to an exemplary embodiment of the present disclosure. As shown in Figure 1A, the chip may include a pixel chip layer 10, a memory chip layer 20, and a logic circuit chip layer 30 stacked vertically from top to bottom. The pixel chip layer 10 may include a pixel unit array, which is used to convert a received light signal into an electrical signal. Each pixel unit in the pixel unit array may include at least a photoelectric conversion unit 110 configured to generate an electric charge in response to light, a transfer transistor 120, a source follower 150, and a floating diffusion portion 130. The memory chip layer 20 may include a memory (such as a DRAM) for storing the electrical signal, and each memory cell of the DRAM may include a transistor and a capacitor 290. The logic circuit chip layer 30 may include a plurality of logic circuits for controlling the reading and writing of the plurality of memory cells.
[0065] In an exemplary embodiment, a pixel unit array may be composed of a plurality of pixel units, such as tens of thousands or even hundreds of millions of pixel units. A pixel unit may also be sometimes referred to as a photosensitive unit. A pixel unit may be used to convert a received light signal into an electrical signal.
[0066] In an exemplary embodiment, the photoelectric conversion unit 110 may be a photoelectric conversion unit for converting received light into electric charge and accumulating the electric charge generated by the photoelectric conversion. The magnitude of the electrical signal (such as current) depends on the intensity of the incident light received by the corresponding photoelectric conversion unit. The photoelectric conversion unit 110 may be a photodiode (PD), but may also be replaced by other devices with photoelectric conversion functions, such as phototransistors, photomultiplier tubes, etc.
[0067] In an exemplary embodiment, the transfer transistor (TX) 120 may be driven according to a transfer signal and transfer charges generated in the photoelectric conversion unit 110 to the floating diffusion (FD) 130 .
[0068] In an exemplary embodiment, the floating diffusion (FD) 130 may include a floating diffusion region of a predetermined storage capacitance and temporarily accumulate charges transferred from the photoelectric conversion unit 110 via the transfer transistor 120 and induce a corresponding voltage signal according to the amount of charge output by the transfer transistor.
[0069] In an exemplary embodiment, the gate of the source follower (SF) 150 can be connected to the floating diffusion portion 130 and can be used to receive the voltage signal of the floating diffusion portion 130 and generate a follow-up signal of the voltage signal of the floating diffusion portion 130 (or the output signal of the source follower SF).
[0070] In other exemplary embodiments, each pixel unit may further include other components, such as a reset transistor (also referred to as a reset transistor) (RST) 140, a row selection transistor, and the like. The reset transistor 140 may be driven according to a reset signal to release the charge accumulated in the floating diffusion 130 and reset the pixel unit for the next signal acquisition. Those skilled in the art will appreciate that these components may not always be within each pixel unit, as they may also be shared between pixel units. For example, two adjacent pixel units may share a floating diffusion.
[0071] In an exemplary embodiment, the DRAM is used as a frame memory with high transmission bandwidth and a temporary buffer for image data. Each memory cell of the DRAM may include a transistor and a capacitor 290. Each transistor may include a first source / drain 230, a channel layer 240, and a second source / drain 250 arranged vertically from top to bottom, and a gate 280 surrounding the channel layer 240, i.e., each transistor has a vertical gate-all-around structure.
[0072] Although references to a first source / drain and a second source / drain are used herein to designate two separate and distinct sources / drains, it is not intended that the sources / drains referred to as the "first" source / drain and / or the "second" source / drain have a unique meaning. It is intended that only one of the sources / drains be connected to a bit line and the other be connected to a capacitor. In an exemplary embodiment, the first source / drain and the second source / drain are independent of each other, and one of the first source / drain and the second source / drain can be the source of a transistor and the other can be the drain of a transistor, or one of the first source / drain and the second source / drain can be the drain of a transistor and the other can be the source of a transistor.
[0073] In an exemplary embodiment, the plurality of transistors include a plurality of active pillars 220. Each transistor includes a vertically extending active pillar 220; each active pillar 220 includes a channel layer 240 and a first source / drain 230 and a second source / drain 250 respectively connected to the channel layer; two adjacent columns of active pillars 220 are separated by a first trench extending along the second direction Y, and two adjacent rows of active pillars are separated by a second trench extending along the first direction X; a recess extending along the second direction Y is provided in the substrate below a column of active pillars 220.
[0074] In an exemplary embodiment, the memory further includes a plurality of bit lines extending along the second direction Y and arranged at intervals in the first direction X, each of the bit lines being located in the groove and connected to the second source / drain 250. In an exemplary embodiment, the plurality of bit lines are connected in parallel in the first direction X.
[0075] In an exemplary embodiment, the memory further includes a plurality of word lines extending along the first direction X and spaced apart in the second direction Y. The plurality of transistors arranged along the first direction X share a word line, and the gate 280 of each transistor is part of the shared word line. In an exemplary embodiment, the plurality of word lines are connected in parallel in the second direction Y.
[0076] In the present disclosure, the current of the memory can be increased by connecting multiple bit lines in parallel and / or connecting multiple word lines in parallel, thereby better matching the photoelectric conversion units in the corresponding pixel chip layer.
[0077] In an exemplary embodiment, the transistor of each memory cell may be vertically stacked with the capacitor.Capacitor 290 may have various shapes, such as a pillar (eg, a round pillar or a square pillar) or a cup shape.
[0078] In an exemplary embodiment, the pixel chip layer 10 may further include a peripheral region, and the memory chip layer 20 may further include a peripheral region. FIG1A shows that the peripheral region of the pixel chip layer 10 and the peripheral region of the memory chip layer 20 can be connected to the logic circuit chip layer 30 by means of multi-level through silicon vias (TSVs) 40. In other exemplary embodiments, the peripheral region of the pixel chip layer 10 and the peripheral region of the memory chip layer 20 can also be connected to the logic circuit chip layer 30 by means of direct metal connections, such as Cu-Cu connections or Al-Al connections, that is, by direct connections via Cu pads or Al pads constructed on each stacking surface.
[0079] FIG1A shows that the chip includes a pixel chip layer 10 , a memory chip layer 20 , and a logic circuit chip layer 30 which are arranged vertically from top to bottom.
[0080] FIG1B is a schematic diagram of an equivalent circuit of a chip provided according to an exemplary embodiment of the present disclosure. As shown in FIG1B , a pixel unit of the pixel chip layer 10 is directly connected to a capacitor 290 in the memory chip layer 20. For example, the source electrode of the source follower (SF) 150 of a pixel unit of the pixel chip layer 10 can be directly connected to the top electrode of the capacitor 290.
[0081] FIG1B shows that a source follower (SF) 150 in a pixel unit can be connected to multiple capacitors 290 connected in parallel, or can be connected to a corresponding capacitor array. The capacitor array can be a 3*3 array, a 4*4 array, a 5*5 array, or a larger array. The number of capacitors can be determined based on the amount of charge generated by the pixel chip layer and the capacity of the DRAM capacitor. FIG1A shows in a cross-sectional schematic diagram that a pixel unit can correspond to a 3*3 capacitor array.
[0082] In existing technologies, the electrical signals generated by the pixel chip are temporarily stored in DRAM via peripheral circuits. This requires a logic circuit layer to mediate the transmission between the pixel sensor (CIS) and the DRAM, and data transfer takes time. In contrast, the present invention connects the DRAM capacitors directly to the pixel cells, allowing the electrical signals generated by the pixel chip layer to be directly transferred to the DRAM capacitors for storage, thereby significantly improving speed.
[0083] Figure 2 is a schematic plan view illustrating the operating principle of a chip according to an exemplary embodiment of the present disclosure. As shown in Figure 2, each pixel unit in the pixel chip layer corresponds to a set of DRAM capacitors, resulting in extremely high bandwidth. After the logic circuit issues a command, the pixel array in the pixel chip layer converts the optical signal into an electrical signal. Each DRAM memory in the DRAM chip layer rapidly receives and stores the electrical signal according to the command, and then transmits it at high speed through the logic circuit chip layer. Simultaneously, the pixel array in the pixel chip layer takes the next picture.
[0084] The present disclosure directly connects the pixel units of the pixel chip layer to the capacitors in a memory such as DRAM, that is, each pixel unit is correspondingly connected to the capacitors of several DRAMs. Therefore, there is no need to rely on the intermediary of the logic circuit chip layer to transmit the electrical signals generated by the pixel units of the pixel chip layer to the memory chip. Instead, the electrical signals generated by the pixel units are directly transmitted to the capacitors in the memory via components such as source followers in the pixel chip for storage, thereby avoiding data transmission delays and achieving high-speed storage and reading of data. The number of frames per second (Frames Per Second) can be greater than 1000fps.
[0085] In addition, the data width of the connection between the pixel unit and the DRAM memory is also greater than the data bandwidth connected to the logic circuit, thereby also being able to increase the storage and reading speed.
[0086] The chip disclosed herein can be used as a chip for video and photography.
[0087] The technical solution of the present disclosure will be further illustrated below using the memory manufacturing process according to an exemplary embodiment of the present disclosure. The "patterning process" referred to in this exemplary embodiment includes film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, and is a mature manufacturing process in the relevant art. The "photolithography process" referred to in this exemplary embodiment includes film coating, mask exposure, and development, and is a mature manufacturing process in the relevant art. Deposition can be achieved using known processes such as sputtering, evaporation, and chemical vapor deposition; coating can be achieved using known coating processes; and etching can be achieved using known methods, without specific limitations here. In the description of this exemplary embodiment, it should be understood that a "thin film" refers to a thin film of a certain material deposited on a substrate using a deposition or coating process. If the "thin film" does not require patterning or photolithography during the entire manufacturing process, it can also be referred to as a "layer." If the "thin film" also requires patterning or photolithography during the entire manufacturing process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. A "layer" after the patterning or photolithography process contains at least one "pattern."
[0088] In an exemplary embodiment, the chip manufacturing process may include manufacturing a pixel chip layer 10 , manufacturing a memory chip layer 20 , and manufacturing a logic circuit chip layer 30 , and may include the following steps.
[0089] S100: manufacturing a pixel chip layer 10 .
[0090] Fabricating the pixel chip layer 10 may include forming a pixel cell array consisting of a plurality of pixel cells arranged along a plurality of rows and a plurality of pixel cells arranged along a plurality of columns.
[0091] In an exemplary embodiment, the formation of each pixel unit may include the following steps:
[0092] S1100: forming a photoelectric conversion unit 110, a transfer transistor 120, a floating diffusion 130, a reset transistor 140, a source follower 150 and other components on a substrate 101;
[0093] S1200: forming a plurality of contact holes 160;
[0094] S1300: forming a dielectric layer 102 by chemical vapor deposition, plasma enhanced chemical vapor deposition, or the like;
[0095] S1400: Photolithography and etching, followed by growth of a barrier layer and a metal (e.g., copper) seed layer, electrochemical plating (ECP) to plate metal, and chemical mechanical polishing (CMP) to form a first metallization layer 103. The first metallization layer 103 may include multiple connection elements, such as metal pads 170 and metal wires.
[0096] S1500: Based on steps similar to S1400, a second metallization layer 104 is formed to form a pixel chip layer 10, as shown in Figure 3. Figure 3 is a cross-sectional schematic diagram of a pixel chip layer in a chip according to an exemplary embodiment of the present disclosure.
[0097] In an exemplary embodiment, substrate 101 may be a semiconductor substrate; for example, it may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In an exemplary embodiment, substrate 101 may include an N-type substrate region and / or a P-type substrate region.
[0098] In an exemplary embodiment, the dielectric layer 102 may be made of any one or more insulating materials selected from silicon oxide, silicon oxynitride (SiON), silicon nitride (SiN), and silicon carbonitride (SiCN).
[0099] In an exemplary embodiment, the contact hole 160 may be made of metal silicide, such as metal cobalt or nickel silicide.
[0100] In an exemplary embodiment, the metal pad 170 may be made of metal such as Cu and Al.
[0101] In an exemplary embodiment, each pixel unit may be implemented as a digital pixel. When the pixel unit is implemented as a digital pixel, each pixel unit may further include an analog-to-digital converter for outputting a digital pixel signal.
[0102] S200 : manufacturing a memory chip layer 20 .
[0103] The fabrication of the memory chip layer 20 may include the following steps:
[0104] S2100: Photolithography and etching are performed with the help of the hard mask layer 202 to form a plurality of bit line trenches (Bit Line Trench) T1 extending along the second direction Y and spaced along the first direction X in the silicon substrate 201, as shown in FIG4A . FIG4A is a cross-sectional schematic diagram of an intermediate product obtained in the memory chip layer manufacturing step in the chip manufacturing method provided according to an exemplary embodiment of the present disclosure.
[0105] In an exemplary embodiment, substrate 201 may be a semiconductor substrate. Semiconductor materials include, but are not limited to, silicon, germanium, gallium nitride, gallium arsenide, and silicon carbide. In an exemplary embodiment, substrate 201 may have a single-layer structure or a multi-layer stacked structure. The stacked structure substrate may include: flexible material / inorganic material / flexible material. The inorganic material may be, for example, any one or more of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON).
[0106] In an exemplary embodiment, the bit line trench T1 may be formed using a self-aligned double patterning (SADP) process.
[0107] In an exemplary embodiment, the hard mask layer 202 may be made of silicon dioxide.
[0108] 4A shows two groups of bit line grooves T1 separated by the partition 210 , and each group may include three bit line grooves T1 . However, in other exemplary embodiments, each group may include more bit line grooves T1 .
[0109] S2200: Filling the bit line trench T1 with a first isolation layer material to cover the bottom and sidewalls of the bit line trench T1 to form a first isolation layer 203; continuing to fill the bit line trench T1 with a second isolation layer material to form a second isolation layer 204 covering the first isolation layer 203, so that the first isolation layer 203 and the second isolation layer 204 together fill the bit line trench T1; and using a chemical mechanical planarization (CMP) method to make the upper surface of the first isolation layer 203 and the upper surface of the second isolation layer 204 flush with the hard mask layer 202, as shown in Figure 4B, Figure 4B is a cross-sectional schematic diagram of an intermediate product obtained in the memory chip layer manufacturing step in the chip manufacturing method provided according to an exemplary embodiment of the present disclosure.
[0110] In an exemplary embodiment, the first isolation layer 203 and the second isolation layer 204 may be independently formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes.
[0111] In an exemplary embodiment, the first isolation layer material and the second isolation layer material may be selected from silicon nitride, silicon dioxide, etc. For example, the first isolation layer 203 may be made of silicon dioxide, and the second isolation layer 204 may be made of silicon nitride.
[0112] S2300: By photolithography and etching, a plurality of word line trenches T2 extending along the first direction X and spaced apart along the second direction Y are formed in the structure formed in the aforementioned step S2200. The word line trenches T2 are shallower in depth than the bit line trenches T1. An active pillar array including a plurality of active pillars 220 is formed by the bit line trenches T2 and the word line trenches T2. A third isolation layer material is filled in the word line trenches T2 to cover the bottom and sidewalls of the word line trenches T2 to form a third isolation layer 205. A fourth isolation layer material is further filled in the word line trenches T2 to form a fourth isolation layer 206 covering the third isolation layer 205, so that the third isolation layer 205 and the fourth isolation layer 206 together fill the word line trenches T2. Chemical mechanical planarization is performed. The upper surface of the third isolation layer 205 and the upper surface of the fourth isolation layer 206 are made flush with the hard mask layer 202 by a carbon-metallic chloride (CMP) method; the active pillar 220 is doped to form a first source / drain 230, a channel layer 240 and a second source / drain 250 of the transistor arranged from top to bottom; finally, a bit line doping region 207 is formed in the silicon substrate 201 at the bottom of the word line trench T2, as shown in FIG4C , which is a cross-sectional schematic diagram of an intermediate product obtained in the memory chip layer manufacturing step in the chip manufacturing method provided according to an exemplary embodiment of the present disclosure.
[0113] In an exemplary embodiment, the first source / drain 230 and the second source / drain 250 may be formed by doping N-type impurities such as P or As into the active pillar 220 ; and the channel layer 240 may be formed by doping P-type impurities such as B into the active pillar 220 .
[0114] In an exemplary embodiment, doping may be achieved by using a blanket implantation process.
[0115] In an exemplary embodiment, N-type impurities P or As elements may be doped into the bit line doping region 207 by doping and annealing, and the doping concentration may be relatively high.
[0116] In an exemplary embodiment, the word line trench T2 may be formed using a self-aligned double patterning (SADP) process.
[0117] In an exemplary embodiment, the third isolation layer 205 and the fourth isolation layer 206 may be independently formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes.
[0118] In an exemplary embodiment, the third isolation layer material and the fourth isolation layer material may be selected from silicon nitride, silicon dioxide, etc. For example, the third isolation layer 205 may be made of silicon dioxide, and the fourth isolation layer 206 may be made of silicon nitride (SiN).
[0119] S2400: The fourth isolation layer 206 is removed by etching back, and the exposed silicon substrate 201 is etched downward and laterally to form a plurality of grooves 260 in the bit line doping region 207, as shown in FIG4D . FIG4D is a cross-sectional schematic diagram of an intermediate product obtained in the memory chip layer manufacturing step in the chip manufacturing method provided according to an exemplary embodiment of the present disclosure.
[0120] In an exemplary embodiment, the shape of the longitudinal section of the recess 260 on a plane perpendicular to the word line trench may be a bowl shape, an ellipse shape, a sigma shape, a diamond shape, or the like.
[0121] S2500: depositing metal silicide in the groove 260 to form a metal silicide layer on the inner wall of the groove 260; then depositing the bit line metal, and through the CMP process and the etch-back process, the bit line metal is terminated at the bottom of the word line groove T2, as shown in FIG4E , which is a cross-sectional schematic diagram of an intermediate product obtained in the memory chip layer manufacturing step in the chip manufacturing method provided according to an exemplary embodiment of the present disclosure.
[0122] In an exemplary embodiment, the metal silicide may be titanium or cobalt silicide. Forming the metal silicide layer can form an ohmic contact and reduce resistance.
[0123] In an exemplary embodiment, the bit line metal material may include, but is not limited to, tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN) and tantalum (Ta), or a composite metal material such as a composite structure of titanium nitride (TiN) / tungsten (W).
[0124] S2600: Refill the word line trench T2 with the fourth isolation layer material to form a fourth isolation layer 206 covering the third isolation layer 205, so that the third isolation layer 205 and the fourth isolation layer 206 together fill the word line trench T2; remove the material in the third isolation layer 205 to a certain height by wet etching, thereby forming two vertical grooves 270 on both sides of the fourth isolation layer 206, as shown in Figure 4F, Figure 4F is a cross-sectional schematic diagram of an intermediate product obtained in the memory chip layer manufacturing step in the chip manufacturing method provided according to an exemplary embodiment of the present disclosure.
[0125] S2700: growing a gate insulating material in the vertical groove 270 to form a gate insulating layer (not shown); then depositing a word line material and etching back to form a gate 280 and expose the vertical groove 270 above the gate 280, as shown in FIG4G , which is a cross-sectional schematic diagram of an intermediate product obtained in the memory chip layer manufacturing step in the chip manufacturing method provided according to an exemplary embodiment of the present disclosure.
[0126] In an exemplary embodiment, the gate insulating layer may be a high-k dielectric layer, i.e., a dielectric layer with a K value of ≥ 3.9. The high-k dielectric layer may serve as a gate oxide. The gate insulating layer may be made of one or more of silicon oxide, aluminum oxide (Al2O3), or hafnium oxide (HfO2).
[0127] In an exemplary embodiment, the gate 280 may be made of P-type amorphous silicon, metal tungsten W, tungsten nitride, titanium nitride, or a composite material of tungsten and titanium nitride.
[0128] S2800: Refill the third isolation layer material in the vertical groove 270 above the gate 280 to form a third isolation layer 205, and perform a CMP process to make the upper surface of the third isolation layer 205 flush with the hard mask layer 202; wet-etch the surface of the active pillar 220 to deposit polysilicon containing a high doping concentration P; photolithography and etching to form a first island portion 291 of multiple polysilicon; perform oxide deposition and CMP process; finally, grow metal silicide on the surface, as shown in Figure 4H, which is a cross-sectional schematic diagram of the intermediate product obtained in the memory chip layer manufacturing step in the chip manufacturing method provided according to an exemplary embodiment of the present disclosure.
[0129] In an exemplary embodiment, the metal silicide may be nickel or cobalt silicide.
[0130] As shown in FIG. 4H , six island portions 291 are shown, wherein three first island portions 291 are formed on both sides of the word line trench having the largest width.
[0131] S2900: Forming capacitor 290, exemplary steps may include first growing a TiN bottom electrode, then growing a dielectric film, and finally growing a TiN top electrode; then depositing an interlayer dielectric (ILD) oxide to a suitable thickness; growing a dielectric film, then performing photolithography and etching of a first metallization layer, blocking the seed crystal, and then performing an electrochemical plating process of Cu to form an interconnect structure, which is connected to the second island 292 on the capacitor 290, as shown in FIG4I , FIG4I is a cross-sectional schematic diagram of an intermediate product obtained in the memory chip layer manufacturing step in the chip manufacturing method provided according to an exemplary embodiment of the present disclosure.
[0132] In an exemplary embodiment, the dielectric film may be made of oxides such as ZrO 2 and Al 2 O 3 .
[0133] In other exemplary embodiments, photolithography and etching of the second metallization layer may also be performed.
[0134] S300 : manufacturing a logic circuit chip layer 30 .
[0135] In an exemplary embodiment, the manufacture of the logic circuit chip layer 30 may include the following steps: forming an active area AA, forming a well, forming a gate ring, a metal interconnection structure, etc. on the substrate 301, as shown in Figure 5, which is a cross-sectional schematic diagram of the logic circuit chip layer in a chip provided according to an exemplary embodiment of the present disclosure.
[0136] After forming the three chip layers, the next step is to connect the chip layers. This can include the following steps:
[0137] S400: thinning the substrate 201 of the memory chip layer 20 (e.g., reducing it to a thickness of about 2-10 μm), then flipping the memory chip layer 20 over and connecting it to the pixel chip layer 10 (chemical connection may be used, such as bonding);
[0138] S500: Flip the connected pixel chip layer 10 and the memory chip layer 20, that is, the pixel chip layer 10 is above the memory chip layer 20; the memory chip layer 20 is connected to the logic circuit chip layer 30 (chemical connection method such as bonding can be used).
[0139] Through silicon via (TSV) technology or metal direct connection technology, the peripheral area of the pixel chip layer 10 and the peripheral area of the memory chip layer 20 are connected to the logic circuit chip layer 30, thereby obtaining the chip of the present disclosure.
[0140] In an exemplary embodiment, the substrate of the pixel chip layer 10 is thinned (e.g., reduced to a thickness of 3-6 μm); a filter 180 connected to the photoelectric conversion unit 110 and a lens or microlens 190 connected to the filter 180 can be formed on the back side of the silicon substrate 101 of the pixel chip layer 10.
[0141] In an exemplary embodiment, the capacitor 290 in the memory chip layer 20 is connected to the source follower (SF) 150 in the pixel chip layer 10 by connecting the second island 292 on the capacitor 290 to the second metallization layer 104 in the pixel chip layer 10 .
[0142] The exemplary embodiment of the present disclosure further provides a method for manufacturing a chip, comprising the following steps:
[0143] Manufacturing pixel chip layer, memory chip layer and logic circuit chip layer respectively;
[0144] The pixel chip layer, the memory chip layer and the logic circuit chip layer are connected and a pixel unit in the pixel chip layer is directly connected to a part of the capacitors in the memory chip layer.
[0145] In an exemplary embodiment, connecting the pixel chip layer, the memory chip layer, and the logic circuit chip layer comprises the following steps:
[0146] thinning the substrate of the memory chip layer;
[0147] turning over the memory chip layer;
[0148] bonding the memory chip layer to the pixel chip layer;
[0149] flipping the bonded assembly of the pixel chip layer and the memory chip layer so that the pixel chip layer is on top of the memory chip layer; and
[0150] The memory chip layer and the logic circuit chip layer are bonded.
[0151] In an exemplary embodiment, connecting the pixel chip layer, the memory chip layer, and the logic circuit chip layer further comprises the following steps:
[0152] The peripheral area of the pixel chip layer, the peripheral area of the memory chip layer and the logic circuit chip layer are connected by means of a plurality of through silicon vias.
[0153] An exemplary embodiment of the present disclosure further provides an electronic device, comprising the chip provided by the exemplary embodiment of the present disclosure.
[0154] In an exemplary embodiment, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.
[0155] Although the embodiments disclosed in the present disclosure are as described above, the above contents are merely examples or implementations adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. It should be noted that the above embodiments or implementations are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to the contents specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the implementation without departing from the scope of the present disclosure.
Claims
1. A chip, comprising: A pixel chip layer, comprising a plurality of pixel units, each pixel unit comprising at least a photoelectric conversion unit, a transfer transistor, a source follower and a floating diffusion portion; A memory chip layer, which is disposed below the pixel chip layer and includes a plurality of memories, each memory including a plurality of vertically stacked transistors and capacitors; as well as A logic circuit chip layer, which is arranged below the memory chip layer and includes a plurality of logic circuits for controlling the reading and writing of the memory; A pixel unit in the pixel chip layer is directly connected to a part of the capacitors in the memory chip layer.
2. The chip according to claim 1, wherein: A pixel unit in the pixel chip layer is directly connected to a capacitor array.
3. The chip according to claim 2, wherein: The source follower in the one pixel unit is directly connected to a capacitor array of the memory chip layer.
4. The chip according to claim 1, wherein: The transistor includes a vertically extending active column located on a substrate; each active column includes a channel layer and a first source / drain located on a side of the channel layer away from the substrate and a second source / drain located on a side of the channel layer close to the substrate; two adjacent columns of active columns are separated by a first groove extending along a second direction, and two adjacent rows of active columns are separated by a second groove extending along the first direction; a groove extending along the second direction is provided in the substrate; and the transistor also includes a gate surrounding the channel layer.
5. The chip according to claim 4, wherein: The memory further includes a plurality of bit lines extending along the second direction and arranged at intervals in the first direction, each of the bit lines being located in the groove and connected to the second source / drain.
6. The chip according to claim 5, wherein: The plurality of bit lines are connected in parallel in the first direction.
7. The chip according to claim 4, wherein: The memory further includes a plurality of word lines extending along the first direction and arranged at intervals in the second direction, a plurality of transistors arranged along the first direction share a word line, and the gate of each transistor is a part of the shared word line.
8. The chip according to claim 4, wherein: The plurality of word lines are connected in parallel in the second direction.
9. The chip according to claim 1, further comprising multi-level through silicon vias to connect the peripheral area of the pixel chip layer, the peripheral area of the memory chip layer and the logic circuit chip layer.
10. A method for manufacturing a chip, comprising the following steps: Manufacturing a pixel chip layer, a memory chip layer, and a logic circuit chip layer respectively; The pixel chip layer, the memory chip layer and the logic circuit chip layer are connected to each other and a pixel unit in the pixel chip layer is directly connected to a part of capacitors in the memory chip layer.
11. The manufacturing method according to claim 10, wherein: Connecting the pixel chip layer, the memory chip layer and the logic circuit chip layer comprises the following steps: thinning the substrate of the memory chip layer; Turning over the memory chip layer; bonding the memory chip layer to the pixel chip layer; Flipping the bonded combination of the pixel chip layer and the memory chip layer so that the pixel chip layer is on top of the memory chip layer; as well as The memory chip layer is bonded to the logic circuit chip layer.
12. The manufacturing method according to claim 10, wherein: Connecting the pixel chip layer, the memory chip layer and the logic circuit chip layer further comprises the following steps: The peripheral area of the pixel chip layer, the peripheral area of the memory chip layer and the logic circuit chip layer are connected by means of a plurality of through silicon vias.
13. An electronic device comprising the chip according to any one of claims 1 to 9.
14. The electronic device according to claim 13, comprising a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a mobile power supply.