Memory and manufacturing method therefor, and electronic device

Abstract

A memory and a manufacturing method therefor, and an electronic device. The memory comprises a substrate and a plurality of memory cells stacked in a direction perpendicular to the substrate. Each memory cell comprises a transistor. The transistor comprises a semiconductor layer (14), a first electrode (11), a second electrode (12), and a gate electrode (13). The first electrode (11) is connected to the second electrode (12) by means of the semiconductor layer (14). The semiconductor layer (14), the first electrode (11), and the second electrode (12) are arranged in the same layer. The gate electrode (13) surrounds the semiconductor layer (14), and a gate insulating layer (21) is arranged between the gate electrode (13) and the semiconductor layer (14). The wrap-around gate can effectively enhance the control capability of the gate electrode on the transistor.

Description

Memory and manufacturing method thereof, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 18, 2023, with application number 202310882038.5 and invention name “Memory and its manufacturing method, electronic device”, the content of which should be understood as incorporated into this application by reference. Technical Field

[0002] The embodiments of the present disclosure relate to, but are not limited to, semiconductor technology, and in particular to a memory and a manufacturing method thereof, and an electronic device. Background Art

[0003] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0004] To minimize product costs, people hope to create as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs.

[0005] Summary of the Invention

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] An embodiment of the present disclosure provides a memory, comprising: a substrate, and a plurality of memory cells stacked in a direction perpendicular to the substrate; the memory cells comprising: a transistor;

[0008] The transistor includes a semiconductor layer, a first electrode, a second electrode, and a gate electrode. The first electrode and the second electrode are connected through the semiconductor layer. The semiconductor layer, the first electrode, and the second electrode are arranged in the same layer. The gate electrode surrounds the semiconductor layer, and a gate insulating layer is arranged between the gate electrode and the semiconductor layer.

[0009] In an exemplary embodiment, the semiconductor layer, the first electrode, and the second electrode form a columnar structure parallel to the substrate.

[0010] In an exemplary embodiment, a cross section of the columnar structure in a direction perpendicular to the substrate is rectangular.

[0011] In an exemplary embodiment, the device further includes a bit line, the bit line being parallel to the substrate and connected to the second electrode of the transistor.

[0012] In an exemplary embodiment, the bit line and the second electrode of the transistor are an integrated structure and include the same conductive material.

[0013] In an exemplary embodiment, the memory cell further includes a capacitor including a first capacitor electrode and a second capacitor electrode insulated from each other, wherein the first capacitor electrode is connected to the first electrode of the transistor.

[0014] In an exemplary embodiment, the first capacitor electrode and the first electrode of the transistor are an integral structure and include the same conductive material.

[0015] In one exemplary embodiment, the material of the semiconductor layer includes metal oxide.

[0016] In an exemplary embodiment, the device further includes an isolation layer, wherein the isolation layer is perpendicular to the substrate and separates gate electrodes of adjacent memory cells.

[0017] In an exemplary embodiment, the device further includes: an insulating dielectric layer and a semiconductor dielectric layer, wherein the insulating dielectric layer is disposed on a side of the storage unit away from the substrate, and the semiconductor dielectric layer is disposed on a side of the insulating dielectric layer away from the substrate.

[0018] In an exemplary embodiment, a transition layer and a capacitor insulating layer are provided between the first capacitor electrode and the second capacitor electrode.

[0019] In an exemplary embodiment, the transition layer contacts the second capacitor electrode, and a material of the transition layer includes titanium or titanium nitride.

[0020] The present disclosure also provides a method for manufacturing a memory, including:

[0021] forming conductive layers and insulating layers alternately arranged in a direction away from the substrate on a substrate;

[0022] Performing patterned etching to form trenches extending in a direction perpendicular to the substrate, wherein each layer of the conductive layer forms a patterned structure stacked on top of each other, and each layer of the patterned structure includes a bit line and a plurality of branches extending in a direction perpendicular to the bit line;

[0023] filling the trench with a dielectric layer;

[0024] Performing patterned etching to form a groove extending in a direction perpendicular to the substrate, wherein a sidewall of the groove exposes portions of the plurality of branches and a portion of the insulating layer;

[0025] Performing selective etching to remove the exposed branches to form a first cavity, and retaining some branches on both sides of the first cavity to form a first electrode and a second electrode respectively;

[0026] forming a semiconductor layer in the first cavity, wherein the semiconductor layer connects the first electrode and the second electrode;

[0027] Performing selective etching to remove the exposed insulating layer and form a second cavity, wherein the second cavity surrounds the sidewall of the semiconductor layer;

[0028] A gate insulating layer and a gate electrode are sequentially formed in the second cavity by adopting an atomic layer deposition process, so that the gate electrode surrounds the semiconductor layer, and the gate insulating layer is located between the gate electrode and the semiconductor layer.

[0029] In an exemplary embodiment, after sequentially forming a gate insulating layer and a gate electrode in the second cavity using an atomic layer deposition process, the method further includes:

[0030] An isolation layer extending in a direction perpendicular to the substrate is formed in the groove, and the isolation layer separates adjacent gate electrodes.

[0031] An embodiment of the present disclosure further provides an electronic device, comprising the aforementioned memory.

[0032] The memory of the disclosed embodiment increases the relative area between the gate electrode and the semiconductor layer by wrapping the gate electrode around the side wall of the semiconductor layer. The wrap-around gate can effectively enhance the control capability of the gate electrode over the transistor and improve the space utilization of the memory.

[0033] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The objects and advantages of the present invention can be realized and obtained through the structures particularly pointed out in the description and the drawings.

[0034] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The technical solutions in the accompanying drawings are preferred implementation methods of the present disclosure, which are used to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation on the technical solutions.

[0036] FIG1a is a schematic cross-sectional view of a memory device provided by an exemplary embodiment along a direction parallel to a substrate;

[0037] FIG1b is a cross-sectional view taken along the aa' direction in FIG1a;

[0038] FIG1c is a cross-sectional view taken along the bb' direction in FIG1a;

[0039] FIG1d is a cross-sectional view taken along the c-c' direction in FIG1a;

[0040] Figure 1e is a cross-sectional view taken along the dd' direction in Figure 1a;

[0041] FIG2 a is a cross-sectional view taken along the aa′ direction during the manufacturing process of the memory device shown in FIG1 a after forming an insulating layer, a conductive layer, and a capacitor;

[0042] FIG2 b is a cross-sectional view taken along the bb′ direction after forming an insulating layer, a conductive layer, and a capacitor during the manufacturing process of the memory shown in FIG1 a ;

[0043] FIG2 c is a cross-sectional view taken along the c-c′ direction after forming an insulating layer, a conductive layer, and a capacitor during the manufacturing process of the memory shown in FIG1 a ;

[0044] FIG3 a is a cross-sectional view taken along the bb′ direction after a groove is formed during the manufacturing process of the memory shown in FIG1 a ;

[0045] FIG3 b is a cross-sectional view taken along the c-c′ direction after a groove is formed during the manufacturing process of the memory shown in FIG1 a ;

[0046] FIG4 a is a cross-sectional view taken along the aa′ direction after a groove is formed during the manufacturing process of the memory shown in FIG1 a ;

[0047] FIG4 b is a cross-sectional view taken along the CC′ direction after a groove is formed during the manufacturing process of the memory shown in FIG1 a ;

[0048] FIG5 a is a cross-sectional view taken along the aa′ direction after a semiconductor thin film is formed during the manufacturing process of the memory device shown in FIG1 a ;

[0049] FIG5 b is a cross-sectional view taken along the bb′ direction after a semiconductor thin film is formed during the manufacturing process of the memory device shown in FIG1 a ;

[0050] FIG5 c is a cross-sectional view taken along the c-c′ direction after a semiconductor thin film is formed during the manufacturing process of the memory device shown in FIG1 a ;

[0051] FIG6 a is a cross-sectional view taken along the bb′ direction after the semiconductor film in the groove is removed during the manufacturing process of the memory shown in FIG1 a ;

[0052] FIG6 b is a cross-sectional view taken along the c-c′ direction after the semiconductor film in the groove is removed during the manufacturing process of the memory shown in FIG1 a ;

[0053] FIG7 a is a cross-sectional view taken along the aa′ direction after the second cavity is formed during the manufacturing process of the memory device shown in FIG1 a ;

[0054] FIG7 b is a cross-sectional view taken along the CC′ direction after the second cavity is formed during the manufacturing process of the memory device shown in FIG1 a ;

[0055] FIG8 a is a cross-sectional view taken along the aa′ direction after forming a gate insulating layer and a gate electrode during the manufacturing process of the memory shown in FIG1 a ;

[0056] FIG8 b is a cross-sectional view taken along the c-c′ direction after forming a gate insulating layer and a gate electrode during the manufacturing process of the memory device shown in FIG1 a ;

[0057] FIG. 9 is a cross-sectional view taken along the CC′ direction of the memory device shown in FIG. 1 a after an isolation layer is formed during the manufacturing process. DETAILED DESCRIPTION

[0058] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Unless there is a conflict, the embodiments of the present disclosure and the features therein may be combined with each other in any manner.

[0059] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs.

[0060] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically illustrate ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0061] In the present disclosure, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0062] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements may be appropriately changed according to the direction in which each constituent element is described. Therefore, the words and phrases described in this disclosure are not limited and may be appropriately replaced according to the circumstances.

[0063] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.

[0064] In this disclosure, a transistor refers to an element comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0065] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. The functions of the "source electrode" and "drain electrode" may be reversed when using transistors with opposite polarities or when the direction of current changes during circuit operation. Therefore, in the present disclosure, the terms "source electrode" and "drain electrode" may be reversed.

[0066] In this disclosure, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0067] In this disclosure, "parallel" means approximately parallel or nearly parallel. For example, the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes the angle of greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular. For example, the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes the angle of greater than 85° and less than 95°.

[0068] In this disclosure, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0069] As used herein, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process. "The orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0070] In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there are no distinct microstructural boundaries, such as gaps or discontinuities. Generally, a film layer patterned to form a connection is considered integrated. For example, A and B may be formed using the same material into a single film layer and simultaneously formed into a connected structure through the same patterning process.

[0071] An embodiment of the present disclosure provides a memory, comprising: a substrate and a plurality of memory cells stacked in a direction perpendicular to the substrate; the memory cells comprising: a transistor;

[0072] The transistor includes a semiconductor layer, a first electrode, a second electrode, and a gate electrode. The first electrode and the second electrode are connected through the semiconductor layer. The semiconductor layer, the first electrode, and the second electrode are arranged in the same layer. The gate electrode surrounds the semiconductor layer, and a gate insulating layer is arranged between the gate electrode and the semiconductor layer.

[0073] The memory disclosed herein is described below by way of some exemplary embodiments.

[0074] Figure 1a is a schematic cross-sectional view of a memory device provided by an exemplary embodiment, taken along a direction parallel to the substrate; Figure 1b is a cross-sectional view taken along the a-a' direction of Figure 1a; Figure 1c is a cross-sectional view taken along the b-b' direction of Figure 1a; Figure 1d is a cross-sectional view taken along the c-c' direction of Figure 1a; and Figure 1e is a cross-sectional view taken along the d-d' direction of Figure 1a. As shown in Figure 1a, the memory device provided by this embodiment may include: multiple layers of memory cells stacked along a direction perpendicular to the substrate, and bit lines 30, wherein the bit lines 30 extend along a direction parallel to the substrate and connect to one or more memory cells in the same layer.

[0075] In one exemplary embodiment, the memory cells in the same layer form an array distributed along a first direction D1 and a second direction D2. The bit line 30 is shared by transistors in the same layer and column, and may be connected to the second electrode of the transistor. The first direction D1 and the second direction D2 are both parallel to the substrate, intersecting the first direction D1 and the second direction D2. In some embodiments, the first direction D1 and the second direction D2 may be perpendicular.

[0076] In an exemplary embodiment, transistors of adjacent memory cells in the same layer share one bit line 30 , and two adjacent memory cells are distributed in a mirror-symmetrical manner.

[0077] In one exemplary embodiment, the bit lines 30 may extend along the second direction D2 .

[0078] In an exemplary embodiment, the bit line 30 may be made of metal, such as tungsten.

[0079] The embodiment of the present disclosure uses metal as a bit line, which is respectively connected to the channel or source / drain of different transistors, so that the contact between the bit line and the channel or source / drain is an ohmic contact.

[0080] In an exemplary embodiment, the memory cell may include a transistor and a data storage element, wherein a first electrode of the transistor is connected to the data storage element.

[0081] In an exemplary embodiment, the data storage element is a capacitor, forming a 1T1C storage structure. However, the present disclosure is not limited thereto and can be combined with other transistors to form a 2T0C storage structure, etc.

[0082] In an exemplary embodiment, as shown in FIG. 1 a and FIG. 1 e , the capacitor may include a first capacitor electrode 41 and a second capacitor electrode 42 , wherein the first capacitor electrode 41 is connected to the first electrode of the transistor.

[0083] In an exemplary embodiment, the first capacitor electrode 41 may extend along the first direction D1 , and a first end of the first capacitor electrode 41 is connected to the first electrode of the transistor.

[0084] In an exemplary embodiment, the capacitor may further include a capacitor dielectric layer positioned between the first capacitor electrode 41 and the second capacitor electrode 42. The capacitor dielectric layer may be a composite film layer and may include a transition layer and a capacitor insulating layer. The transition layer may be made of titanium or titanium nitride. The transition layer contacts the second capacitor electrode 42 and is used to reduce the contact resistance of the second capacitor electrode 42. The capacitor insulating layer may be made of a high-K dielectric material, including but not limited to at least one of the following: silicon oxide, aluminum oxide (Al2O3), and hafnium oxide.

[0085] In an exemplary embodiment, the first capacitor electrode 41 may be made of metal, such as tungsten; and the second capacitor electrode 42 may be made of a conductive material, such as polysilicon.

[0086] In an exemplary embodiment, as shown in Figures 1a, 1b, 1c and 1d, the transistor includes a first electrode 11, a second electrode 12, a gate electrode 13 and a semiconductor layer 14, the first electrode 11 and the second electrode 12 are connected through the semiconductor layer 14, and the gate electrode 13 and the semiconductor layer 14 are insulated from each other.

[0087] In one exemplary embodiment, the semiconductor layer 14, the first electrode 11, and the second electrode 12 form a columnar structure extending along a first direction D1. The semiconductor layer 14, the first electrode 11, and the second electrode 12 are different regions of the columnar structure. The side surfaces of the semiconductor layer 14, the first electrode 11, and the second electrode 12 are substantially flush, forming a columnar structure with substantially flush side surfaces. The first electrode 11 and the second electrode 12 are located on opposite sides of the semiconductor layer 14 in the first direction D1, and the first electrode 11 and the second electrode 12 are made of the same material and produced using the same production process. The material of the semiconductor layer 14 is different from that of the first electrode 11 and the second electrode 12. Alternatively, the semiconductor layer 14, the first electrode 11, and the second electrode 12 are made of the same material, and the first electrode 11 and the second electrode 12 are formed into a conductive material through a doping process.

[0088] In one exemplary embodiment, the cross-section of the columnar structure perpendicular to the substrate is rectangular. In some embodiments, the cross-section of the columnar structure perpendicular to the substrate can adopt other shapes, such as circular, elliptical, diamond, pentagonal, hexagonal, etc.

[0089] In one exemplary embodiment, the first electrode 11 may extend along a first direction D1. The first electrode 11 is located on a side of the semiconductor layer 14 opposite to the first direction D1. A first end of the first electrode 11 is connected to a first end of the semiconductor layer 14, and a second end of the first electrode 11 is connected to a first end of a first capacitor electrode 41 of the capacitor.

[0090] In an exemplary embodiment, the first capacitor electrode 41 and the first electrode 11 may be an integrated structure and formed of the same conductive material, such as tungsten.

[0091] In an exemplary embodiment, the first electrode 11 may be a portion of a first capacitor electrode 41 to which the first electrode 11 is connected, and the first end of the semiconductor layer 14 of the transistor is connected to the first capacitor electrode 41 .

[0092] In an exemplary embodiment, the second electrode 12 may extend along the first direction D1 and is located on one side of the semiconductor layer 14 in the first direction D1. A first end of the second electrode 12 is connected to a second end of the semiconductor layer 14 , and a second end of the second electrode 12 is connected to the bit line 30 .

[0093] In an exemplary embodiment, the bit line 30 and the second electrode 12 may be an integral structure and formed of the same conductive material, such as tungsten.

[0094] In an exemplary embodiment, the second electrode 12 may be a portion of a bit line 30 to which the second electrode 12 is connected, and the second end of the semiconductor layer 14 of the transistor is connected to the bit line 30 .

[0095] In an exemplary embodiment, the second electrodes 12 of the transistors of the memory cells in two adjacent columns in the same layer are connected to the same bit line 30. The second electrodes 12 of the transistors in two adjacent columns in the same layer and the bit line 30 may be an integrated structure.

[0096] In one exemplary embodiment, the first electrode 11 and the second electrode 12 of the same transistor can be located in the same conductive film layer. This can be understood as the first electrode 11 and the second electrode 12 being located in the same conductive film layer and formed by patterning a single conductive film layer, wherein the conductive film layer is approximately parallel to the upper surface of the substrate. The first electrode 11 and the second electrode 12 can be provided in the same layer. That is, the first electrode 11 and the second electrode 12 can be formed simultaneously through the same patterning process, but the embodiments of the present disclosure are not limited thereto. In some embodiments, the first electrode 11 and the second electrode 12 can be manufactured separately through different patterning processes.

[0097] In an exemplary embodiment, the first electrode 11 and the second electrode 12 are made of the same material. The first electrode 11 and the second electrode 12 can both be made of metal, such as tungsten.

[0098] In one exemplary embodiment, the semiconductor layer 14 may extend along a first direction D1. The semiconductor layer 14 is located in the same film layer as the first electrode 11 and the second electrode 12. The semiconductor layer 14 is disposed in the same layer as the first electrode 11 and the second electrode 12. A first end of the semiconductor layer 14 is connected to a first end of the first electrode 11, and a second end of the semiconductor layer 14 is connected to a first end of the second electrode 12. The extension direction of the semiconductor layer 14 is approximately parallel to the upper surface of the substrate.

[0099] In one exemplary embodiment, the material of the semiconductor layer 14 can be a metal oxide. The metal oxide can be indium gallium zinc oxide (IGZO), InGaO, ITO, IZO, or a metal oxide containing In and / or Sn. When the metal oxide material is IGZO, the leakage current of the transistor is low (less than or equal to 1E-15A to 1E-10A), where 1E-15A refers to 10 to the negative 15th power amperes and 1E-10A refers to 10 to the negative 10th power amperes, thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide can also be IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx and other materials, as long as the leakage current of the transistor can meet the requirements, and the specific adjustment can be made according to the actual situation.

[0100] In an exemplary embodiment, the gate electrode 13 may wrap around the sidewall of the semiconductor layer 14. The term "wrap around" may be understood as partially or completely wrapping around the semiconductor layer 14. In some embodiments, the wrapping may be completely wrapped around the entirety, where the cross-section of the gate electrode 13 after wrapping is a closed ring along a direction perpendicular to the substrate, and the ring shape is adapted to the outer contour of the cross section of the semiconductor layer 14. For example, the cross-section of the gate electrode 13 may be a square or other structure. In some embodiments, the wrapping may be partially wrapped around, where the cross-section after wrapping is not closed, but presents a ring shape. For example, a ring with an opening.

[0101] The memory of the disclosed embodiment surrounds the gate electrode 13 on the sidewall of the semiconductor layer 14 to increase the relative area between the gate electrode 13 and the semiconductor layer 14 , thereby effectively enhancing the control capability of the gate electrode 13 .

[0102] In an exemplary embodiment, the memory cell may further include a gate insulating layer 21 . The gate insulating layer 21 is disposed between the gate electrode 13 and a sidewall of the semiconductor layer 14 , and the gate electrode 13 is connected to the semiconductor layer 14 through the gate insulating layer 21 .

[0103] In one exemplary embodiment, the material of the gate insulating layer 21 is not limited and can be a high-K dielectric material, i.e., a dielectric material with a dielectric constant K ≥ 3.9. The high-K dielectric material can include, but is not limited to, at least one of the following: silicon oxide, aluminum oxide (Al2O3), and hafnium oxide.

[0104] In an exemplary embodiment, the memory further includes an isolation layer 61 , which extends in a direction perpendicular to the substrate to separate gate electrodes of adjacent memory cells to prevent short circuits between the gate electrodes of adjacent memory cells.

[0105] In one exemplary embodiment, the memory cell may further include a word line. A word line is a common lead for multiple vertically stacked transistors. A word line extends perpendicular to the substrate and connects to the gate electrodes of each transistor. Gate electrode 13 may be part of the word line. Alternatively, the word line may consist of two lines, one on each side of the channel, approximately perpendicular to the substrate.

[0106] The present disclosure realizes word lines perpendicular to the substrate through a unique process, and enables the gate electrode to surround the channel; because the present disclosure utilizes a stack of insulating layers and metal layers, and punches holes next to the transistor in combination with lateral etching, it can form a space for accommodating word lines and gate insulating layers, thereby forming the above-mentioned structure.

[0107] In an exemplary embodiment, as shown in FIG1e , the memory device further includes a semiconductor dielectric layer 81 and an insulating dielectric layer 82. The semiconductor dielectric layer 81 is disposed on the side of the memory cell away from the substrate, and the insulating dielectric layer 82 is disposed on the side of the semiconductor dielectric layer 81 away from the substrate. The semiconductor dielectric layer 81 can be made of the same semiconductor material as the semiconductor layer 14 and fabricated using the same deposition process; the insulating dielectric layer 82 can be made of the same insulating material as the gate insulating layer 21 and fabricated using the same deposition process.

[0108] The technical solution of this embodiment will be further explained below using the manufacturing process of the memory device of this embodiment. The "patterning process" referred to in this embodiment includes film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, and is a mature manufacturing process in the relevant art. The "photolithography process" referred to in this embodiment includes film coating, mask exposure, and development, and is a mature manufacturing process in the relevant art. Deposition can be achieved using known processes such as sputtering, evaporation, and chemical vapor deposition; coating can use known coating processes; and etching can use known methods, without specific limitations here. In the description of this embodiment, it should be understood that a "thin film" refers to a thin layer of a certain material produced on a substrate using a deposition or coating process. If the "thin film" does not require patterning or photolithography during the entire manufacturing process, it can also be referred to as a "layer." If the "thin film" also requires patterning or photolithography during the entire manufacturing process, it is referred to as a "thin film" before patterning and a "layer" after patterning. The "layer" after patterning or photolithography contains at least one "pattern."

[0109] In this embodiment, each layer includes a plurality of storage units, but the embodiments of the present disclosure are not limited thereto, and each layer may include one storage unit.

[0110] In an exemplary embodiment, the memory may be any of the above-mentioned memories, and the manufacturing process of the memory may include:

[0111] Step 101: forming an insulating layer, a conductive layer, and a capacitor.

[0112] Forming the insulating layer, the conductive layer, and the capacitor includes: forming conductive layers 31 and insulating layers 32 alternately arranged in a direction away from the substrate on the substrate 101, etching the conductive layers 31 and the insulating layers 32 in a patterned manner using a mask to form trenches extending in a direction perpendicular to the substrate, wherein each layer of the insulating layer 32 forms a first patterned structure stacked on top of each other and distributed cyclically, and each layer of the conductive layer 31 forms a second patterned structure stacked on top of each other and distributed cyclically, wherein each layer of the second patterned structure includes a bit line and a plurality of branches extending in a direction perpendicular to the bit line;

[0113] Subsequently, a dielectric layer 33 is deposited on the substrate 101 to fill the trench and cover the conductive layer 31 and the insulating layer 32. The dielectric layer may be made of silicon nitride.

[0114] Subsequently, the insulating layer 32 is patterned and etched to remove a portion of the insulating layer 32, exposing multiple branches of the conductive layer 31 away from one end of the bit line. The exposed multiple branches of the conductive layer 31 form a first capacitor electrode 41. Subsequently, a capacitor insulating layer 43 and a transition layer 44 are formed on the exposed multiple branches of the conductive layer 31 through an atomic layer deposition process. Subsequently, a second capacitor electrode 42 is formed. The second capacitor electrode 42 is connected to the first capacitor electrode 41 through the capacitor insulating layer 43 and the transition layer 44. The first capacitor electrode 41 and the second capacitor electrode 42 form a capacitor, as shown in Figures 2a, 2b, and 2c. Figure 2a is a cross-sectional view taken along the a-a' direction after forming the insulating layer, conductive layer, and capacitor during the manufacturing process of the memory shown in Figure 1a; Figure 2b is a cross-sectional view taken along the b-b' direction after forming the insulating layer, conductive layer, and capacitor during the manufacturing process of the memory shown in Figure 1a; and Figure 2c is a cross-sectional view taken along the c-c' direction after forming the insulating layer, conductive layer, and capacitor during the manufacturing process of the memory shown in Figure 1a.

[0115] In an exemplary embodiment, the dielectric layer 33 may isolate the second capacitor electrode 42 of the capacitor.

[0116] In an exemplary embodiment, the material of the first capacitor electrode 41 can be tungsten, the material of the second capacitor electrode 42 can be polysilicon, the material of the transition layer 44 can be titanium or titanium nitride, and the material of the capacitor insulating layer 43 can be a high-K dielectric material, which can include but is not limited to at least one of the following: silicon oxide, aluminum oxide (Al2O3), and hafnium oxide.

[0117] In one exemplary embodiment, the insulating layer and the conductive layer may be deposited using a chemical vapor deposition method.

[0118] In an exemplary embodiment, the substrate may be a semiconductor substrate, such as a silicon substrate. Of course, it may be any substrate that plays a supporting role, not just a base, but may be a substrate formed by peripheral circuits on the substrate.

[0119] In an exemplary embodiment, the insulating layer serves to isolate devices and may be a low-K dielectric layer, ie, a dielectric layer with a dielectric constant K<3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2).

[0120] Step 102: forming a groove.

[0121] Forming the recess includes: based on the substrate 101 having the aforementioned pattern, patterned etching is performed on the dielectric layer 33 to form a recess 51 extending perpendicular to the substrate. The sidewalls of the recess 51 expose the portions of the multiple branches of the conductive layer 31 located between the bit line 30 and the first capacitor electrode 41, as well as portions of the insulating layer 32. The sidewalls of the recess 51 do not expose the bit line 30, so that the sidewalls of the bit line 30 are covered by the dielectric layer 33, as shown in Figures 3a and 3b. Figure 3a is a cross-sectional view taken along the direction bb' after the recess is formed during the manufacturing process of the memory device shown in Figure 1a; Figure 3b is a cross-sectional view taken along the direction cc' after the recess is formed during the manufacturing process of the memory device shown in Figure 1a.

[0122] Step 103: forming a first cavity.

[0123] Forming the first cavity includes: on the substrate 101 formed with the aforementioned pattern, selectively etching the exposed portions of the multiple branches of the conductive layer 31 located between the bit line 30 and the first capacitor electrode 41 through the groove 51 by wet etching, thereby removing the portions of the multiple branches of the conductive layer 31 located between the bit line 30 and the first capacitor electrode 41 to form a first cavity 52. ​​The multiple branches of the conductive layer 31 between the first cavity 52 and the first capacitor electrode 41 each form the first electrode 11 of a different transistor, and the multiple branches of the conductive layer 31 between the first cavity 52 and the bit line 30 each form the second electrode 12 of a different transistor, as shown in Figures 4a and 4b. Lateral isotropic etching refers to etching the material of the conductive layer 31 along a direction parallel to the substrate 101. Figure 4a is a cross-sectional view taken along the a-a' direction of the memory device shown in Figure 1a after the groove is formed during the manufacturing process; Figure 4b is a cross-sectional view taken along the c-c' direction of the memory device shown in Figure 1a after the groove is formed during the manufacturing process.

[0124] Step 104: forming a semiconductor thin film.

[0125] Forming the semiconductor thin film includes: depositing a semiconductor thin film 53 in the groove and the first cavity based on the substrate 101 formed with the aforementioned pattern, with the semiconductor thin film 53 filling the groove and the first cavity, as shown in Figures 5a, 5b, and 5c. Figure 5a is a cross-sectional view taken along the a-a' direction after the semiconductor thin film is formed during the manufacturing process of the memory device shown in Figure 1a; Figure 5b is a cross-sectional view taken along the b-b' direction after the semiconductor thin film is formed during the manufacturing process of the memory device shown in Figure 1a; and Figure 5c is a cross-sectional view taken along the c-c' direction after the semiconductor thin film is formed during the manufacturing process of the memory device shown in Figure 1a.

[0126] Step 105 , removing the semiconductor film in the groove.

[0127] Removing the semiconductor film in the groove includes: based on the substrate 101 formed with the aforementioned pattern, patterned etching is performed on the semiconductor film 53 in the groove 51, removing the semiconductor film 53 in the groove 51, and retaining the semiconductor film in the first cavity. The semiconductor film in the first cavity forms the semiconductor layer 14, and the groove exposes the sidewalls of the semiconductor layer 14 in the first cavity, as shown in Figures 6a and 6b. Figure 6a is a cross-sectional view taken along the direction bb' after the semiconductor film in the groove is removed during the manufacturing process of the memory shown in Figure 1a; Figure 6b is a cross-sectional view taken along the direction cc' after the semiconductor film in the groove is removed during the manufacturing process of the memory shown in Figure 1a.

[0128] Step 106: forming a second cavity.

[0129] Forming the second cavity includes: on the substrate 101 formed with the aforementioned pattern, selectively etching the exposed insulating layer 32 through the groove 51, removing the insulating layer 32 connected to the semiconductor layer 14 in the first cavity, and forming a second cavity 54. The second cavity 54 surrounds the sidewalls of the semiconductor layer 14 in the first cavity, as shown in Figures 7a and 7b. Figure 7a is a cross-sectional view taken along the a-a' direction after the second cavity is formed during the manufacturing process of the memory shown in Figure 1a; Figure 7b is a cross-sectional view taken along the c-c' direction after the second cavity is formed during the manufacturing process of the memory shown in Figure 1a.

[0130] Step 107: forming a gate insulating layer and a gate electrode.

[0131] Forming the gate insulating layer and gate electrode includes: on the substrate 101 formed with the aforementioned pattern, sequentially depositing a gate insulating film and a conductive film on the inner walls of the groove and the second cavity through an atomic layer deposition process. The conductive film fills the groove and the second cavity. The gate insulating film on the semiconductor layer 14 in the second cavity forms the gate insulating layer 21, and the conductive film on the semiconductor layer 14 in the second cavity forms the gate electrode 13, as shown in Figures 8a and 8b. Figure 8a is a cross-sectional view taken along the a-a' direction after the gate insulating layer and gate electrode are formed during the manufacturing process of the memory shown in Figure 1a; Figure 8b is a cross-sectional view taken along the c-c' direction after the gate insulating layer and gate electrode are formed during the manufacturing process of the memory shown in Figure 1a.

[0132] In one exemplary embodiment, the first electrode 11 , the second electrode 12 , the semiconductor layer 14 , and the gate electrode 13 form a transistor.

[0133] Step 107: forming an isolation layer.

[0134] Forming the isolation layer includes: first, based on the substrate 101 formed with the aforementioned pattern, etching back to remove the conductive film on the side of the pattern away from the substrate; then, selectively etching the conductive film in the groove to remove the conductive film in the groove, and depositing an isolation layer 61 extending perpendicular to the substrate. The isolation layer 61 separates the gate electrodes 13 of adjacent transistors, as shown in Figure 9. Figure 9 is a cross-sectional view taken along the c-c' direction after the isolation layer is formed during the manufacturing process of the memory shown in Figure 1a.

[0135] Step 108: forming an external channel.

[0136] Forming the external channel includes: on the basis of the substrate 101 formed with the aforementioned pattern, forming an external channel 71 extending in a direction perpendicular to the substrate 101 on the dielectric layer 33 on the side away from the substrate 101, wherein a first end of the external channel 71 is connected to the gate electrode 13, and a second end of the external channel 71 extends in a direction away from the substrate and is connected to an external circuit, as described in Figures 1b and 1d.

[0137] The manufacturing method of the memory of the embodiment of the present disclosure forms grooves to expose multiple branches of the conductive layer and the insulating layer, removes the conductive layer by lateral etching to form a first cavity, and forms a semiconductor layer in the first cavity; then removes the insulating layer by lateral etching again to form a second cavity, and uses an atomic deposition process to form a gate insulating layer and a gate electrode in the second cavity, so that the gate electrode surrounds the sidewalls of the semiconductor layer, increasing the relative area between the gate electrode and the semiconductor layer, which can effectively enhance the control capability of the gate electrode and improve the space utilization of the memory.

[0138] The manufacturing method of the memory in the embodiment of the present disclosure has a simple preparation process and low production cost.

[0139] The present disclosure also provides an electronic device comprising the memory device described in any of the preceding embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power bank. The storage device may include, but is not limited to, computer memory.

[0140] Although the embodiments disclosed herein are as described above, the contents described herein are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. Any person skilled in the art may make any modifications and variations in the form and details of the embodiments without departing from the spirit and scope of the present invention. However, the scope of patent protection of the present invention shall remain subject to the scope defined by the appended claims.

Claims

1. A memory, comprising: A substrate, and a plurality of storage units stacked in a direction perpendicular to the substrate; The storage unit comprises: a transistor; The transistor comprises a semiconductor layer, a first electrode, a second electrode and a gate electrode, the first electrode and the second electrode are connected through the semiconductor layer, the semiconductor layer, the first electrode and the second electrode are arranged in the same layer, the gate electrode surrounds the semiconductor layer, and a gate insulating layer is arranged between the gate electrode and the semiconductor layer; The invention also includes a word line, wherein the word line is perpendicular to the substrate, and the gate electrode is a part of the word line.

2. The memory according to claim 1, wherein: The semiconductor layer, the first electrode, and the second electrode form a columnar structure parallel to the substrate.

3. The memory according to claim 2, wherein: The cross section of the columnar structure in a direction perpendicular to the substrate is rectangular.

4. The memory according to claim 1, further comprising: A bit line is parallel to the substrate and connected to the second electrode of the transistor.

5. The memory according to claim 4, wherein: The bit line and the second electrode of the transistor are an integrated structure and include a same conductive material.

6. The memory according to claim 1, wherein: The memory cell further includes a capacitor including a first capacitor electrode and a second capacitor electrode insulated from each other, wherein the first capacitor electrode is connected to the first electrode of the transistor.

7. The memory according to claim 6, wherein: The first capacitor electrode and the first electrode of the transistor are an integrated structure and include a same conductive material.

8. The memory according to any one of claims 1 to 7, wherein: The material of the semiconductor layer includes metal oxide.

9. The memory according to any one of claims 1 to 7, further comprising: The isolation layer is perpendicular to the substrate and separates gate electrodes of adjacent memory cells.

10. The memory according to any one of claims 1 to 7, further comprising: A semiconductor dielectric layer and an insulating dielectric layer, wherein the insulating dielectric layer is arranged on a side of the storage unit away from the substrate, and the semiconductor dielectric layer is arranged on a side of the insulating dielectric layer away from the substrate.

11. The memory according to claim 6, wherein: A transition layer and a capacitor insulating layer are provided between the first capacitor electrode and the second capacitor electrode.

12. The memory according to claim 11, wherein: The transition layer contacts the second capacitor electrode, and a material of the transition layer includes titanium or titanium nitride.

13. A method for manufacturing a memory, comprising: forming conductive layers and insulating layers alternately arranged in a direction away from the substrate on a substrate; Performing patterned etching to form a groove extending in a direction perpendicular to the substrate, wherein each layer of the conductive layer forms a patterned structure stacked on top of each other, and each layer of the patterned structure includes a bit line and a plurality of branches extending in a direction perpendicular to the bit line; filling the trench with a dielectric layer; Performing patterned etching to form a groove extending in a direction perpendicular to the substrate, wherein a sidewall of the groove exposes portions of the plurality of branches and a portion of the insulating layer; Performing selective etching to remove the exposed branches to form a first cavity, and retaining some branches on both sides of the first cavity to form a first electrode and a second electrode respectively; forming a semiconductor layer in the first cavity, wherein the semiconductor layer connects the first electrode and the second electrode; Performing selective etching to remove the exposed insulating layer to form a second cavity, wherein the second cavity surrounds the side wall of the semiconductor layer; An atomic layer deposition process is adopted to sequentially form a gate insulating layer and a gate electrode in the second cavity, so that the gate electrode surrounds the semiconductor layer, and the gate insulating layer is provided between the gate electrode and the semiconductor layer.

14. The method for manufacturing a memory according to claim 11, wherein: After sequentially forming a gate insulating layer and a gate electrode in the second cavity by an atomic layer deposition process, the method further includes: An isolation layer extending in a direction perpendicular to the substrate is formed in the groove, and the isolation layer separates adjacent gate electrodes.

15. An electronic device comprising the memory according to any one of claims 1 to 12.

Images