Method and apparatus for processing hypercomplex numbers

Abstract

Embodiments of the present application provide a method and an apparatus for processing hypercomplex numbers. According to the proposed solution, one of the operands to a first operation such as a subtraction operation, a multiplication operation, or a convolution operation is negated before the first operation is performed. The solution can be applied in any product where subtraction is required without dedicated subtraction logic or subtraction instructions, for example, applied in complex-valued matrix (or 1-dimension vector) multiplication or convolution. By the proposed solution, operations on complex-valued matrices and CVNNs can be emulated with maximum time and area efficiency. Besides, operations on matrices of higher order algebras, where subtraction is needed, can be emulated with maximum time and area efficiency.

Description

METHOD AND APPARATUS FOR PROCESSING HYPERCOMPLEX NUMBERSTECHNICAL FIELD

[0001] Embodiments of the present invention relate to the field of computer technologies, and more specifically, to a method and an apparatus for processing hypercomplex numbers.BACKGROUND

[0002] The implementation of neural networks (NNs) has traditionally focused on real- valued neural networks (RVNNs). Lately, the research has demonstrated that complex-valued NNs (CVNNs) can achieve better accuracy than RVNNs. However, up to this day, most computers cannot work with complex numbers directly. Operations on complex numbers are emulated by multiple operations on real numbers, which represent the components of the complex numbers. The emulation slows down the calculations and increases the cost of using complex numbers, in terms of increased processing time and increased power consumption. Multiplication or convolution of complex numbers is particularly expensive in these aspects. The operations, especially the multiplication operation and the convolution operation, on the complex numbers are inefficient due to the absence of matrix subtraction.SUMMARY

[0003] Embodiments of the present application provide a method and an apparatus for processing hypercomplex numbers, which can be applied in any product where matrix (or vector) subtraction is required. Operations on hypercomplex numbers can be emulated with high efficiency.

[0004] According to a first aspect, provided is a method for processing hypercomplex numbers, including: negating a sign of a first operand to a first operation, where the negating the sign ofthe first operand includes inverting signs of all elements of the first operand, where the first operation includes any one of operations: subtraction operation, multiplication operation, or convolution operation, and operands to the first operation comprise matrices or 1-dimension vectors; performing the first operation based on negation of the sign of the first operand.

[0005] According to the proposed method in the first aspect, the negation of a sign of one operand of the operands to the first operation is performed before the first operation. Operations on the operands, such as matrices (or vectors) of hypercomplex numbers (for example, complex numbers, Quaternions or Octonions), can be emulated with high efficiency in terms of processing time, saved areas, saved power, etc.

[0006] In an embodiment of the first aspect, elements in the matrices or the vectors include hypercomplex numbers, each hypercomplex number includes at least two components, and each element in the matrices or the vectors includes one component of the at least two components.

[0007] Note that, in the present application, each of the matrices (or vectors) represents one component of the hypercomplex numbers. For example, matrix A contains real parts of complex numbers, and matrix B contains imaginary parts of the complex numbers.

[0008] The proposed solution can be applied to any product where subtraction is required, for example, operations on hypercomplex numbers. Operations on hypercomplex numbers can be emulated by a computer with high efficiency.

[0009] In an embodiment of the first aspect, the first operation is the multiplication operation; and the method further includes: performing the multiplication operation on a first input and a second input to obtain products, where the first input is an output of the negation of the sign of the first operand, the first operand is any one of two operands of the multiplication, and the second input is a second operand of the two operands; obtaining a result of the multiplication operation according to the products.

[0010] The proposed solution can be applied to a multiplication operation for hypercomplex matrices or vectors without dedicated subtraction logic or an instruction for subtraction operations. Operations on hypercomplex matrices (or vectors) multiplication have highefficiency.

[0011] In an embodiment of the first aspect, the first operation is the convolution operation; where the method further includes: performing multiplication of the convolution operation on a first input and a second input to obtain products, where the first input is an output of the negation of the sign of the first operand, the first operand is any one of two operands of the convolution operation, and the second input is a second operand of the two operands; obtaining a result of the convolution operation according to accumulation operation and the products.

[0012] The proposed solution can be applied to a convolution operation, where subtraction exists, for hypercomplex matrices or vectors without dedicated subtraction logic or an instruction for subtraction operations. Operations of convolution for matrices (or vectors) can be emulated with high efficiency.

[0013] In an embodiment of the first aspect, the method further includes: receiving an instruction, where the instruction indicates one operand of the operands to the first operation on which the negation is performed; where the negating the sign of the first operation, includes: negating the sign of the first operand in a case that the instruction indicates the first operand on which the negation is performed.

[0014] In this embodiment, the inversion of the sign of the first operand can be controlled by an instruction from a control logic. Another possible way is provided to implement the proposed solution.

[0015] According to a second aspect, provided is a method for processing hypercomplex numbers, including: performing multiplication operation on two operands to obtain an output, where each of the two operands and the output is a matrix or vector, elements in the matrix or the vector include hypercomplex numbers, each hypercomplex number includes at least two components, and each element in the matrix or the vector includes one component of the at least two components; negating a sign of the output, where the negating the sign of the output includesinverting signs of all elements of the output.

[0016] The proposed method in the second aspect can be applied to multiplication or convolution for hypercomplex matrices (or vectors). The inversion of a sign of an output of the multiplication operation can be performed, or inversion of a sign of the output of multiplication part of the convolution before accumulation is performed. Another possible way to implement the subtraction without a dedicated hardware logic or an instruction for the subtraction is provided. The operations of multiplication or convolution on hypercomplex numbers are provided with high efficiency in terms of processing time, saved areas, saved power, etc.

[0017] In an embodiment of the second aspect, the multiplication operation is a multiplication part of convolution operation;

[0018] where the method further includes: obtaining a result of the convolution operation according to accumulation operation and the output.

[0019] The convolution operation has an additional operation that is an accumulation operation compared to the multiplication operation. The convolution operation can be emulated with high efficiency.

[0020] According to a third aspect, provided is a method for processing hypercomplex numbers, including: negating, based on a control instruction, a sign of an operand to a first operation, where the negating the sign of the operand includes inverting signs of all elements of the operand, the first operation involves subtraction or no subtraction, and the control instruction is related to the first operation involving the subtraction or no subtraction; and performing the first operation based on negation of the sign of the operand.

[0021] In an embodiment of the third aspect, where that the control instruction is related to the first operation involving the subtraction or no subtraction, includes: the control instruction indicates negation of two operands to the first operation in a case that the first operation involves no subtraction; where the negating, based on the control instruction, the sign of the operand to the first operation, includes: negating, based on the control instruction, signs of the two operands to the firstoperation.

[0022] In an embodiment of the third aspect, where the control instruction is related to the first operation involving the subtraction or no subtraction, includes: the control instruction indicates negation of one operand of two operands to the first operation in a case that the first operation involves the subtraction; where the negating, based on the control instruction, the sign of the operand to the first operation, includes: negating, based on the control instruction, a sign of a first operand of two operands to the first operation, where the first operand is any one of the two operands.

[0023] The technique effects can refer to that of the first aspect or the second aspect, and it is not repeated herein.

[0024] According to a third aspect, provided is an apparatus for processing hypercomplex numbers. The apparatus has a function of implementing the method in the first aspect and any possible implementation manners of the first aspect. The function may be implemented by using hardware. The hardware includes one or more circuits corresponding to the foregoing function.

[0025] According to a fourth aspect, provided is an apparatus for processing hypercomplex numbers. The apparatus has a function of implementing the method in the second aspect and any possible implementation manners of the second aspect. The function may be implemented by using hardware. The hardware includes one or more circuits corresponding to the forgoing function.

[0026] According to a fifth aspect, provided is a chip (or chip system), the chip includes a first register, a sign inversion circuit, a multiplication circuit, a control logic, and a second register that are configured to implement the method in the first aspect or the second aspect, or any possible implementation manners of the first aspect or the second aspect. Reference can be made to the details in the specification, which will not be repeated herein.DESCRIPTION OF DRAWINGS

[0027] One or more embodiments are exemplarily described by corresponding accompanying drawings, and these exemplary illustrations and accompanying drawingsconstitute no limitation on the embodiments. Elements with the same reference numerals in the accompanying drawings are illustrated as similar elements, and the drawings are not limiting to scale, in which:

[0028] FIG. 1 is an example of a circuit, based on the prior art, for matrix multiplication and matrix convolution.

[0029] FIG. 2 is a flowchart of a method (200) for processing hypercomplex numbers according to the present application.

[0030] FIG. 3 is an example of the method (200) for processing hypercomplex numbers according to the present application.

[0031] FIG. 4 is another example of the method (200) for processing hypercomplex numbers according to the present application.

[0032] FIG. 5 is a flowchart of a method (300) for processing hypercomplex numbers according to the present application.

[0033] FIG. 6 is another example of the method (300) for processing hypercomplex numbers according to the present application.

[0034] FIG. 7 is a flowchart of a method (500) for processing hypercomplex numbers according to the present application.

[0035] FIG. 8 is another example of a method for processing hypercomplex numbers according to the present application.

[0036] FIG. 9 is a schematic block diagram of a chip (or chip system) proposed by the present application.DESCRIPTION OF EMBODIMENTS

[0037] In order to understand features and technical contents of embodiments of the present application in detail, implementations of the embodiments of the present application will be described in detail below with reference to the accompanying drawings, and the attached drawings are only for reference and illustration purposes, and are not intended to limit the embodiments of the present application. In the following technical descriptions, for ease of explanation, numerous details are set forth to provide a thorough understanding of the disclosedembodiments. One or more embodiments, however, may be practiced without these details. In other cases, well-known structures and apparatuses may be shown simplified in order to simplify the drawings.

[0038] A real number consists of one type of value, that is real value. A complex number can be written as in an equation (1):where is the imaginary unit that satisfies the equation.

[0039] Multiplication of two complex numbers can be expressed as in an equation (2) below:

[0040] This implies that values of components f and g can be calculated as in an equation (3) below:

[0041] The same applies if A, B, C, D, E, F, and G are matrices:

[0042] Real-valued matrices F and G can be calculated in the same way as the real- valued numbers f and g calculated in the equation (3).

[0043] Computer programming languages like python, C, C++, and many others, have a special notation for “arithmetic assignment” operators like and For example, someexamples are given blow:

[0044] Multiply-and-accumulate instructions, is also called as “MAC” or “FMA” instructions, are used to perform the following operation:where c is an accumulation register in equation (8).

[0045] Some arithmetic logic units (ALUs) have multiple accumulation registers.

[0046] Calculation (9) can be also expressed as equations in (10) using the “arithmetic assignment” operators:

[0047] The equation (10) does addition or subtraction in (9) by using the accumulation registers. The addition or subtraction happens simultaneously with the multiplication, without the use for a separate “add” or “subtract” instruction. In most cases it also happens within the same clock cycle(s) as the multiplication, and hence it is also faster than to use a separate “add” statement or a separate “subtract” statement. A separate “add” statement or “subtract” statement would lead to a separate “add” instruction or “subtraction” instruction being executed. The “add” instruction or “subtraction” has to be loaded form memory to cache, fetched from cache, decoded, executed, etc. this leads to increased memory utilization, increased requirements for memory bandwidth, reduced performance, increased power consumption, and ultimately increased cost of ownership.

[0048] The combined instructions lead to optimizations in all aspects of operations. In convolutions where many multiplication products are added together, the savings can be significant.

[0049] The problem is that many computer architectures, do not have aoperation.Such an operation has to be emulated in software, as described in an equation (11) below:

[0050] The way shown in equation (l l) is one way to emulate complex-valued convolution. There are many other ways that are similar to complexity to equation (ll). The emulation is transparent to the programmer, but causes extra resource utilization and performance losses.

[0051] Given all this, the present application uses the fact the equations (12) and (13) are valid in commutative algebras like complex numbers and real numbers.

[0052] Equations (12) and (13) imply that if we are negating b before (5), then we are in fact executing (6) instead (5). Exactly what we need, besides from the fact that we have no instruction to negate b, and such instruction would also take up room in the executable code,have to be loaded, fetched, decoded, executed, etc.

[0053] Then multiplication can be expressed as an equation (14) below:

[0054] By combing equations (5), (6), (12), (13) and (14), we notice that, if one, and only one, of the operands of the multiplication is negated before the multiplication, then multiply and add to accumulator becomes a multiply and subtract from accumulator instead. This is the essence of the present application. The details will be explained in embodiments below.

[0055] Another way to represent complex numbers is by use of so called “matrix representation”, as shown in an equation (15):

[0056] The matrix representation, as shown in (15) requires four real values in order to represent one complex number. In matrix representation, the real component x is repeated two times and the imaginary component y is present two times as well, both as y and — y.

[0057] A matrix of complex values, then becomes a large matrix of size n x n withsmaller matrices, each with a size of 2 X 2 elements, embedded inside it, as shown in (16).

[0058] As of today, complex numbers cannot be processed directly in modem SIMD processors for NNs, and these numbers have to be emulated by two real numbers, one real number for the “real” component and the other real number for the “imaginary” component of the complex number. Any real-valued matrix processor can do complex-valued matrix multiplication if the complex values are in matrix representation, as shown in (15) and (16).

[0059] Emulation of complex-valued multiplication like in (4) is known, and requires matrix subtraction, which is indicated in (3). Though (3) is operating on real numbers, not real- valued matrices, the equation (3) for matrices would have been the same.

[0060] Many matrix processors can perform only matrix multiplication and matrixconvolution. The absence of a matrix subtraction and matrix negation implies that operations on complex numbers as in (4) and use of other higher order algebras becomes inefficient. The justification for this is, that it is cheaper to implement only multiplication and accumulation, in terms of saved areas, saved power, and ultimately lower chip cost, and lower cost of ownership. Matrix multiplication processors with a general matrix-ALU functionality, which implement subtraction and negation, have larger area, higher energy consumption, and larger cost, compared to the multiply-and-accumulate only solution.

[0061] General purpose graphics processing units (GPGPUs) have even higher cost in terms of functional logic, higher number of instructions, more complex control logic, higher energy consumption and ultimately higher chip cost, and higher cost of ownership.

[0062] Many matrix processors, can perform complex-valued matrix multiplication today, as shown in (15) and (16). However, the “matrix representation” of the complex number requires four real numbers to represent one complex number. This leads to double memory consumption, and derived requirements for double memory bandwidth. Therefore, the power consumption is roughly doubled for the arithmetic part of the operations. There are also other operations, which do not have their energy consumption doubled, but in e.g. NNs, arithmetic operations amount for the vast majority of all operations. More than 99% of all operations are multiplication and accumulation.

[0063] All that said, instruction for the operation of matrix subtraction is expensive in area to implement, and it is expensive in performance (for example, processing time) not to have it, when working with complex-valued algorithms, and other higher-order algebras or algorithms, which requires subtraction of matrices. These higher order algebras which require subtraction are hypercomplex numbers (HCNs), for example, complex numbers, Quaternions and Octonions.

[0064] Given that, the present application proposes a method and an apparatus to implement convolution or multiplication of hypercomplex numbers (for example, complex numbers, Quaternions, Octonions). In matrix convolution, some of multiplication products can be subtracted from a convolution result, while other multiplication products are added without the need to implement a separate matrix subtraction function and the need to assign neither instructions nor processing time to this subtraction. This implies that in channelizedhypercomplex matrix convolution, which is common in certain types of CVNNs, the channelized hypercomplex matrix convolution (or multiplication) can be implemented fast and efficiently with minimal hardware overhead and no performance overhead stemming from emulation.

[0065] The solution proposed by the present application can be applied to all hardware implementations of hypercomplex matrix convolution (or multiplication), and hypercomplex 1 -dimensional vector convolution (or multiplication).

[0066] For the sake of conciseness, a list of elements, as shown in Table 1 , of figures in the present application are given first. Table 1

[0067] FIG. 1 is an example of a circuit, based on the prior art, for matrix multiplication and matrix convolution. The operand sources 101 and 102 can be separate registers with one matrix in each, they can be separate register files with multiple registers in each, or they can be a common register file with several matrices, and the register file has the ability to read out two operands at the same time, etc. Elements 101 and 102 also can be first input first output (FIFO)- type queues, which can pump matrices into a matrix multiplier 105. Therefore, elements 101 and 102 should be understood as the sources of the operands, not necessarily as the storagepoint of the operand matrices. An element 107 is an accumulation register at the output. A control logic 108 generates an output signal(s) based on decoding of instruction code of matrix operation instructions. Matrix multiplication will cause the accumulator to load the matrix product into the accumulator, overwriting the existing value. Matrix convolution will cause the accumulator to add the matrix product to the accumulation value, which is already in the accumulator.

[0068] In addition, FIG. 1 does not make any assumptions about how and where the result is stored, and the present application should be independent of that.

[0069] FIG. 2 is a flowchart of a method (200) for processing hypercomplex numbers according to the present application. The method (200) can be applied to any product where subtraction is required. For example, the method (200) is applied to matrix subtraction, vector subtraction, matrix multiplication, matrix convolution, 1 -dimensional vector multiplication, or 1 -dimensional vector convolution. Elements in the matrices or vectors include hypercomplex numbers (for example, complex numbers, Quaternions, or Octonions). One hypercomplex number includes at least two components, and each element in the matrices or the vectors includes one component of at least two components.

[0070] It should be understood that, in the present application, the hypercomplex numbers includes the complex numbers, quaternions, octonions and numbers of the form. In other words, the “hypercomplex number” includesall algebras of order higher than 1st order (real numbers).

[0071] In addition, the proposed solution can be used in many areas where hypercomplex numbers are involved. Some of the applications of the proposed solution includes signal processing, communication systems, image processing, quantum computing, antenna design, control systems, etc. These are just a few examples, and the application of hypercomplex numbers also can be used in different domains to solve practical problems.

[0072] The method (200) specifically includes the following steps.

[0073] Step 210: a sign of a first operand to a first operation is negated, where negation of the sign of the first operand includes inverting signs of all elements of the first operand so that each of the elements has a negative sign, the first operand includes any one of operations: a subtraction operation, a multiplication operation, a convolution operation, or the like. Operandsto the first operation include matrices or 1 -dimensional vectors.

[0074] Step 220: the first operation is performed based on the negation of the sign of the first operand.

[0075] As an example, the elements in the matrices or the vectors include hypercomplex numbers, because emulation of the hypercomplex numbers requires subtraction. In other words, the first operation is performed on matrices of hypercomplex numbers, or the first operation is performed on vectors of hypercomplex numbers.

[0076] As an embodiment, the first operation includes matrix subtraction or vector subtraction. It should be understood that, the subtraction can be implemented as addition by negating a sign of a subtrahend. For example, an operation of subtracting matrix A from matrix B is performed. Negation of a sign of matrix A is performed firstly to obtain a negation result, and then an addition operation is performed on the negation result and matrix B to obtain an output of the matrix subtraction.

[0077] As another embodiment, the first operation includes matrix multiplication, a sign of the first operand is negated to obtain a first input to the matrix multiplication, where the first operand is any one of two operands to the matrix multiplication. The matrix multiplication is performed on the first input and a second input to obtain products (or called as multiplication products), where the second input is a second operand of the two operands. A result of the multiplication operation can be obtained according to the products. The vector multiplication is similar to the matrix multiplication, and is not repeated here. Each element of the two operands and the result of the multiplication operation includes one component of the at least two components of the hypercomplex numbers.

[0078] In another embodiment, the first operation includes matrix convolution. A multiplication part of the matrix convolution is the same as the matrix multiplication as described above, and an additional operation is an accumulation operation that is performed on the products to obtain a result of the matrix convolution. The vector convolution is similar to the matrix convolution, and is not repeated here.

[0079] Some hardware implementations of the method (200) will be given below.

[0080] FIG. 3 is an example of a method (200) for processing hypercomplex numbers according to the present application. Specifically, FIG. 3 shows a matrix multiplication andconvolution circuit with sign inversion module 103 on operand A. The element 103 is controlled by the control logic 108. A control signal from 108 to 103, tells the element 103 to invert (or inverse) the sign of the operand A or not invert (or inverse) the sign of the operand A. The control circuit 108 generates the control signal based on information in the instruction code of the matrix instruction.

[0081] FIG. 4 is another example of a method (200) for processing hypercomplex numbers according to the present application. In FIG. 4, an element 104 is a sign inversion module on operand B. The element 104 is identical to the element 103 in FIG. 3, but the element 103 inverts the sign on operand A, and the element 104 inverts the sign on operand B.

[0082] According to the present application, it is not necessary to inverse the signs on both A and B. It is enough to inverse the sign on one, and only one, operand. It makes no sense if negation is performed on both operands A and B. The result is in a case that the signs of all the elements of a result of the matrix multiplication are inverted. This again implies that the result of the matrix multiplication will be subtracted from the accumulator register as in equation (6), and not added to the accumulator register, otherwise in equation (5).

[0083] If the first operation is the matrix multiplication, matrix convolution, vector multiplication, or vector convolution, it is possible to negate an output of a multiplication part of the convolution directly, which refers to FIG. 5.

[0084] FIG. 5 is a flowchart of a method (300) for processing hypercomplex numbers according to the present application. The method (300) includes the following steps.

[0085] Step 310: a multiplication operation is performed on two operands to obtain an output, where each of the two operands and the output is a matrix or vector, and elements in the matrix or the vector include hypercomplex numbers (for example, complex numbers, Quaternions or Octonions). One hypercomplex number includes at least two components, and each element in the matrix or the vector includes one component of the at least two components. The output of the multiplication operation includes products generated by the multiplication operation.

[0086] Step 320: negation of a sign of the output is performed, where the negation of the sign of the output includes inverting signs of all elements of the output.

[0087] The products are loaded to an accumulator, overwriting the existing values in a casethat the method (300) is applied in the matrix multiplication or the vector multiplication.

[0088] In another embodiment, if the method (300) is applied to the matrix convolution or vector convolution, the multiplication operation is a multiplication part of the convolution operation. The method (300) further includes a step 330 described below.

[0089] Step 330 : a result of the convolution operation is obtained according to accumulation operation and the output.

[0090] Specifically, the products of the multiplication part of the convolution operation are added to accumulation values correspondingly to obtain a result of the convolution operation.

[0091] FIG. 6 is an example of a method (300) for processing hypercomplex numbers according to the present application. A sign inversion module 106 is provided at the output of an element 105. This may be obvious, but in fact, in many circumstances, the timing budget is more limited in the location of the element 106, compared to the locations of the element 103 and the element 104.

[0092] FIG. 7 is a flowchart of a method (500) for processing hypercomplex numbers according to the present application. The method (500) includes the following steps.

[0093] Step 510: negation, based on a control instruction, of a sign of an operand to a first operation is performed, where the negation of the sign of the operand includes inverting signs of all elements of the operand, the first operation involves subtraction or no subtraction, and the control instruction is related to the first operation involving the subtraction or no subtraction.

[0094] Step 520: the first operation is performed base on the negation of the sign of the operand.

[0095] An explanation of the operand to the first operation, a matrix, a 1 -dimensional vector and the elements in the matrix (or the vector) is similar to that of the method (200) or the method (300), which can refer to the embodiments of the method (200) or the method (300), and is not repeated here.

[0096] Another embodiment shown in FIG. 8 is provided. This embodiment refers to a hardware structure that is applicable to both the method (200) and the method (500). It depends on a specific control method that the hardware structure performs the method (200) or the method (500), and details about this embodiment will be given below.

[0097] FIG. 8 is another example of a method for processing hypercomplex numbersaccording to the present application.

[0098] Note that, two embodiments are included in FIG.8. As another embodiment of the method (200), it is possible to choose to invert a sign on either operand A or operand B according to the control logic 108. The embodiment of the method (200) is a first embodiment, of FIG. 8, where subtraction is needed. In the first embodiment of FIG.8, it is not necessary to have the sign inversion module on both the operands A and B, but it is possible to add the signs inversion modules on both operands A and B, and the control logic 108 can choose to invert the sign on either operand A or operand B. Specifically, the control logic 108 sends instructions to the element 103 and the element 104, respectively, and one of the instructions indicates inversion of a sign of the corresponding operand, and the other indicates skipping inversion of a sign of the corresponding operand. For example, if an instruction sent to the element 103 indicates inversion of the sign of the operand 101, then an instruction sent to the element 104 indicates skipping inversion of the sign of the operand 102. The instructions sent to the elements 103 and 104 could be exchanged, which is not limited. It should be noted that, it doesn’t matter how the control logic 108 chooses an operand on which sign inversion is performed, and what matters is that the element 108 can choose one operand of the two operands 101 and 102 to be inverted. Besides, the present application covers one or more schemes for choosing an operand on which sign inversion is performed, and the schemes include, but are not limited to the following ones:Controlling by the instruction code;Controlling by a control bit in a different data register or control register;Controlling by an external logic signal;Permanently choosing to inverse the sign on either operand A or operand B;Alternating inversion of the sign of either operand A or operand B, and the alternating can be any concept of alternation, including and not limited to:Round-robin alternation;Pseudo-random algorithms of any kind;Random-number generation;Any repeating patterns of alternation (i.e. anything based on output from a counter, final state machine, or similar construction, with a finite number of states).

[0099] A second embodiment of FIG. 8 is an embodiment of the method (500). In the second embodiment, inversion of signs of operands both A and B is performed in a normal case (that is to say, by default) that the first operation involves no subtraction, and inversion of a sign of one operand is performed in a case that the first operation involves subtraction. For example, in the normal case, the control logic 108 sends a first instruction and a second instruction to the elements 103 and 104 respectively, the first instruction indicates inversion of the sign of the operand A, and the second instruction indicates inversion of the sign of the operand B. Outputs are obtained as -A and -B from the elements 103 and 104 respectively.

[0100] In another case, that excludes the normal case, where subtraction is needed, the control logic 108 chooses to perform inversion of a sign of either operand A or operand B. For example, the control log 108 sends a first instruction to indicate inversion of a sign of the operand A, and sends a second instruction to indicate skipping inversion of a sign of the operand B. thus, outputs are obtained as —A and B from the elements 103 and 104 respectively. Alternatively, the instructions sent to the elements 103 and 104 can be exchanged, and outputs A and— B are obtained respectively.

[0101] That is to say, the second embodiment of FIG. 8 includes a normal case and a case that excludes the normal case, the signs of the two operands A and B are inverted in the normal case, and the sign of only one operand is inverted in the case (for example, a case where the subtraction is needed) that excludes the normal case.

[0102] FIG. 8 shows a hardware structure of two embodiments described above. It can be seen that, the two embodiments are the same in terms of the hardware structure, and they are different in terms of a control way inside. It is controlled by the control logic 108 that the inversion is performed on one operand or on both the two operands. In other words, it is controlled by whether the subtraction is involved in the first operation to some extent that the inversion is performed on only one operand or both the two operands.

[0103] It doesn’t matter if a control logic for the element 103 is physically integrated or separate from a control logic for the element 104. For example, the control logic for the element 103 and the control logic for the element 104 are integrated as the control logic 108 in FIG. 8, which is only an example. In either case, the control logic 108 symbolizes the control functions for the elements 103 and 104, no matter the control functions for the elements 103 and 104 arephysically combined or not in the implementation.

[0104] In another embodiment, in FIGS. 3, 4 and 8, inputs of the element 105 are 1- dimensional vectors of a certain length n, n is a positive integer. In other words, inputs of the element 105 are vectors containing n elements, but not matrices of a size of n x n elements. In this embodiment, the element 105 also can be called as a vector multiplication circuit. This embodiment covers a situation where one of the operands A and B inputted to the vector multiplication 105 is sign inverted by either the element 103 or 104.

[0105] In another embodiment, in FIG. 6, an output of the element 105 is a 1 -dimensional vector of a certain length n, n is a positive integer. This embodiment covers a situation where the output of the vector multiplication circuit 105 is sign inverted by the element 106, before entering the vector accumulation register 107.

[0106] According to the present application, the multiplication product will be subtracted from the accumulation register by negating one of the operands to the multiplication part of the convolution before the multiplication, or negating the output of the multiplication part of the convolution before the accumulation. The proposed method is implemented without the need for dedicated subtraction logic or a subtraction operation. On this basis, operations on hypercomplex matrices and CVNNs can be emulated with high efficiency in terms of processing time, saved areas, saved power, etc. Besides, operations on matrices (or vectors) of other higher order algebras, where subtraction is needed, can be emulated with high efficiency.

[0107] The above is an introduction about the embodiments of method, and embodiments of an apparatus will be described below.

[0108] In an embodiment of the present application, a chip (or a chip system) is provided. The chip may include a first register, a sign inversion circuit, an operation circuit and a second register. The first register is configured to provide two operands to a first operation, where the first operation includes any one of operations: a subtraction operation, a multiplication operation, or a convolution operation, and each of the two operands includes a matrix or 1- dimensional vector. The sign inversion circuit is configured to negate a sign of a first operand of the two operands, where negation of the sign of the first operand includes inverting signs of all elements of the first operand. The operation circuit is configured to perform the first operation based on the negation of the sign of the first operand to obtain an output, and thesecond register is configured to cache or store the output. The chip has a function of implementing any one of the methods or any possible implementation manners of any one method proposed by the application. The function may be implemented by using hardware. The hardware includes one or more circuits corresponding to the foregoing function.

[0109] FIG. 9 is an example of a schematic block diagram of a chip (or a chip system) 10 proposed by the present application. As shown in FIG. 9, the chip (or the chip system) may include some or all of the following hardware: a first register 11, a sign inversion circuit 12, a multiplication circuit 13, a control logic 14, and a second register 15.

[0110] The first register 11 is configured to provide two operands. The sign inversion circuit 12 is configured to perform a sign inversion operation on a corresponding operand of the two operands. The multiplication circuit 13 is configured to perform matrix multiplication or vector multiplication. The control logic 14 is configured to send instructions to the sign inversion circuit 12 and the second register 15. The second register 15 is configured to receive an instruction from the control logic 14, load an output, which includes multiplication products, of the multiplication circuit 13, and overwrite existing values in a case that the instruction from the control logic 14 indicates a multiplication operation, for example, a matrix multiplication operation or a vector multiplication operation. The second register 15 is configured to receive an instruction from the control logic 14, load an output, which includes multiplication products, of the multiplication circuit 13, and perform an accumulation operation on the multiplication products to obtain a result of a convolution operation in a case that the instruction from the control logic 14 indicates the convolution operation, for example, a matrix convolution operation or a vector convolution operation.

[0111] In short, the first register is used to provide operands to the multiplication operation or the convolution operation, and the second register is configured to cache or store an output of the multiplication operation or the convolution operation. The number of the first register 11 may be one or more, and the number of the second register may be one or more, and that is not limited in the present application.

[0112] For example, the first register includes the elements 101 and 102, the second register is the element 107. The sign inversion circuit includes the element 103, 104, or 106. The multiplication circuit is the element 105. The control logic is the element 108, as shown in theforegoing embodiments.

[0113] Besides, the number of the sign inversion circuit 12 may be one or two, and that is not limited in the present application. For example, the sign inversion circuit 12 can be the element 103 in FIG. 3, or the element 104 in FIG. 4, or the element 106 in FIG. 6, and the number of the sign inversion circuit 12 is one in these cases. Alternatively, the sign inversion circuit 12 can be the elements 103 and 104 in FIG. 8, and the number of the sign inversion circuit 12 is two in this case. The reference can be made to the details of the embodiments of the method, and is not repeated herein.

[0114] The foregoing descriptions are merely specific implementations of this application, but are not intended to limit the protection scope of this application. Any variation or replacement readily figured out by a person skilled in the art within the technical scope disclosed in this application shall fall within the protection scope of this application. Therefore, the protection scope of this application shall be subject to the protection scope of the claims.

Claims

CLAIMSWhat is claimed is:

1. A method for processing hypercomplex numbers, comprising: negating a sign of a first operand to a first operation, wherein the negating the sign of the first operand comprises inverting signs of all elements of the first operand, the first operation comprises any one of operations: a subtraction operation, a multiplication operation, or a convolution operation, and operands to the first operation comprise matrices or 1 -dimensional vectors; and performing the first operation based on negation of the sign of the first operand.

2. The method according to claim 1, wherein elements in the matrices or the vectors comprise hypercomplex numbers, each hypercomplex number comprises at least two components, and each element in the matrices or the vectors comprises one component of the at least two components.

3. The method according to claim 1 or 2, wherein the first operation is the multiplication operation; and the method further comprises: performing the multiplication operation on a first input and a second input to obtain products, wherein the first input is an output of the negation of the sign of the first operand, the first operand is any one of two operands of the multiplication operation, and the second input is a second operand of the two operands; and obtaining a result of the multiplication operation according to the products.

4. The method according to claim 1 or 2, wherein the first operation is the convolution operation; and the method further comprises: performing multiplication of the convolution operation on a first input and a second input to obtain products, wherein the first input is an output of the negation of the sign of the first operand, the first operand is any one of two operands of the convolution operation, and the second input is a second operand of the two operands; and obtaining a result of the convolution operation according to an accumulation operation and the products.

5. The method according to any one of claims 1 to 4, wherein the method further comprises: receiving an instruction, wherein the instruction indicates one operand of the operands to the first operation on which the negation is performed; and wherein the negating the sign of the first operation, comprises: negating the sign of the first operand in a case that the instruction indicates the first operand on which the negation is performed.

6. A method for processing hypercomplex numbers, comprising: performing a multiplication operation on two operands to obtain an output, wherein each of the two operands and the output comprises a matrix or vector, elements in the matrix or the vector comprise hypercomplex numbers, each hypercomplex number comprises at least two components, and each element in the matrix or the vector comprises one component of the at least two components; and negating a sign of the output, wherein the negating the sign of the output comprises inverting signs of all elements of the output.

7. The method according to claim 6, wherein the multiplication operation is a multiplication part of a convolution operation; and the method further comprises: obtaining a result of the convolution operation according to an accumulation operation and the output.

8. A method for processing hypercomplex numbers, comprising: negating, based on a control instruction, a sign of an operand to a first operation, wherein the negating the sign of the operand comprises inverting signs of all elements of the operand, the first operation involves subtraction or no subtraction, and the control instruction is related to the first operation involving the subtraction or no subtraction; and performing the first operation based on negation of the sign of the operand.

9. The method according to claim 8, wherein the operand to first operation comprises a matrix or 1 -dimensional vector, elements in the matrix or the vector comprise hypercomplex numbers, each hypercomplex number comprises at least two components, and each element in the matrix or the vector comprises one component of the at least two components.

10. The method according to claim 8 or 9, wherein that the control instruction is related to the first operation involving the subtraction or no subtraction, comprises:the control instruction indicates negation of two operands to the first operation in a case that the first operation involves no subtraction; wherein the negating, based on the control instruction, the sign of the operand to the first operation, comprises: negating, based on the control instruction, the signs of the two operands to the first operation.

11. The method according to claim 8 or 9, wherein that the control instruction is related to the first operation involving the subtraction or no subtraction, comprises: the control instruction indicates negation of one operand of two operands to the first operation in a case that the first operation involves the subtraction; wherein the negating, based on the control instruction, the sign of the operand to the first operation, comprises: negating, based on the control instruction, the sign of a first operand of two operands to the first operation, wherein the first operand is any one of the two operands.

12. An apparatus for processing hypercomplex numbers, comprising: a first register, configured to provide two operands to a first operation, wherein the first operation comprises any one of operations: a subtraction operation, a multiplication operation, or a convolution operation, and each of the two operands comprises a matrix or 1 -dimensional vector; a sign inversion circuit, configured to negate a sign of a first operand of the two operands, wherein negation of the sign of the first operand comprises inverting signs of all elements of the first operand; and an operation circuit, configured to perform the first operation based on negation of the sign of the first operand.

13. The apparatus according to claim 11, wherein the elements in the matrices or the vectors comprise hypercomplex numbers, each hypercomplex number comprises at least two components, and each element in the matrices or the vectors comprises one component of the at least two components.

14. The apparatus according to claim 12 or 13, wherein the first operation is the multiplication operation; and the operation circuit comprises:a multiplication circuit, configured to: perform the multiplication operation on a first input and a second input to obtain products, wherein the first input is an output of the negation of the sign of the first operand, the first operand is any one of two operands of the multiplication operation, and the second input is a second operand of the two operands; and obtain a result of the multiplication operation according to the products; and a second register, configured to: receive the result of the multiplication operation from the multiplication circuit; and cache or store the result of the multiplication operation.

15. The apparatus according to claim 12 or 13, wherein the first operation is the convolution operation; and the operation circuit comprises: a multiplication circuit, configured to: perform multiplication of the convolution operation on a first input and a second input to obtain products, wherein the first input is an output of the negation of the sign of the first operand, the first operand is any one of two operands of the convolution operation, and the second input is a second operand of the two operands; obtain a result of the convolution operation according to an accumulation operation and the products; and a second register, configured to: receive the result of the convolution operation from the multiplication circuit, and cache or store the result of the convolution operation.

16. The apparatus according to any one of claims 12 to 15, wherein the sign inversion circuit further comprises a first sign inversion circuit and a second sign inversion circuit; the apparatus further comprises: a control logic, configured to send instructions to the first sign inversion circuit and the second sign inversion circuit respectively, wherein one of the instructions sent to the first sign inversion circuit indicates inversion of a sign of the first operand, and the other instruction sent to the second sign inversion circuit indicates skipping inversion of a sign of the second operand; and the first sign inversion circuit and the second sign inversion circuit, further configured to:invert or skip inverting a sign of the corresponding operand according to an instruction from the control logic respectively.

17. An apparatus for processing hypercomplex numbers, comprising: a first register, configured to provide two operands; a multiplication circuit, configured to perform a multiplication operation on the two operands to obtain an output, wherein each of the two operands and the output is a matrix or vector, elements in the matrix or the vector comprise hypercomplex numbers, each hypercomplex number comprises at least two components, and each element in the matrix or the vector comprises one component of the at least two components; a sign inversion circuit, configured to negate a sign of the output, wherein negation of the sign of the output comprises inverting signs of all elements of the output; and a second register, configured to cache or store the output.

18. The apparatus according to claim 17, wherein the multiplication operation is a multiplication part of a convolution operation; wherein the second register further is configured to: obtaining a result of the convolution operation according to an accumulation operation and the output; cache or store the result of the convolution operation.

19. An apparatus for processing hypercomplex numbers, comprising: a first register, configured to provide an operand to a first operation; a sign inversion circuit, configured to negate, based on a control instruction, a sign of the operand, wherein negation of the sign of the operand comprises inverting the sign of all elements of the operand, and the first operation involves subtraction or no subtraction; a control logic, configured to send the control instruction to the sign inversion circuit, wherein the control instruction is related to the first operation involving the subtraction or no subtraction; and an operation circuit, configured to perform the first operation based on the negation of the sign of the operand.

20. The apparatus according to claim 19, wherein the operand to first operation comprises a matrix or 1 -dimensional vector, elements in the matrix or the vector comprise hypercomplexnumbers, each hypercomplex number comprises at least two components, and each element in the matrix or the vector comprises one component of the at least two components.

21. The apparatus according to claim 19 or 20, wherein the sign inversion circuit is further configured to: negate, based on the control instruction, signs of the two operands in a case that the control instruction indicates negation of the two operands, wherein the first operation involves no subtraction.

22. The apparatus according to claim 19 or 20, wherein the sign inversion circuit is further configured to: negate, based on the control instruction, a sign of a first operand of the two operands in a case that the control instruction indicates negation of one operand of the two operands, wherein the first operation involves the subtraction, and the first operand is any one of the two operands.

23. A chip or a chip system, comprising an apparatus according to any one of claims 8 to14.