Display panel, manufacturing method therefor and display apparatus

Abstract

The present disclosure relates to a display panel. The display panel is provided with a partition recess, the partition recess penetrating through a second conductive part and an insulation layer group, a light-emitting material layer and a common electrode being disconnected at a side wall of the partition recess, and the common electrode extending from a side surface of the light-emitting material layer to be in contact with the second conductive part. A pixel current generated during light emission can flow to the second conductive part via the common electrode and then enters a first conductive part by means of a first via hole, and the first conductive part has a relatively small impedance, thus achieving an effect of reducing a voltage drop, and achieving effect of an auxiliary electrode. The second conductive part can use an integrated structure, thereby reducing short circuit and dark point defects generated due to breakage of the second conductive part. Further provided in the present disclosure are a manufacturing method for said display panel and a display apparatus comprising said display panel. (FIG. 1)

Description

Display panel, manufacturing method thereof, and display device

[0001] Cross-references

[0002] This disclosure claims priority to Chinese patent application number 202310947807.5 filed on July 27, 2023, entitled “Display panel, manufacturing method thereof and display device”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel, a manufacturing method thereof, and a display device. Background Art

[0004] Currently, large-size vapor-deposited OLED top-emitting display devices require transparent materials for the cathode, resulting in large sheet resistance and a large voltage drop, which limits the development of large-size OLED display devices.

[0005] In order to disconnect the common electrode, the second conductive part is set to a stacked structure, and a gap is formed between the first layer and the third layer around the second layer. The third layer is prone to breakage, causing short circuits and dark spots in the display panel.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0007] Summary of the Invention

[0008] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and to provide a display panel, a manufacturing method thereof, and a display device.

[0009] According to one aspect of the present disclosure, a display panel is provided, which includes a base substrate, a first conductive part, an insulating layer group, a second conductive part, a pixel definition layer, a light-emitting material layer and a common electrode, wherein the first conductive part is arranged on one side of the base substrate; the insulating layer group is arranged on a side of the first conductive part away from the base substrate; the second conductive part is arranged on a side of the insulating layer group away from the base substrate, and the second conductive part is connected to the first conductive part through a first via hole; the pixel definition layer is arranged on a side of the second conductive part away from the base substrate, and the pixel definition layer is provided with a first opening exposing the second conductive part; the light-emitting material layer is arranged on a side of the pixel definition layer away from the base substrate; the common electrode is provided on a side of the light-emitting material layer away from the base substrate; a partition groove is provided on one side of the first via hole, the partition groove passes through the second conductive part and at least part of the insulating layer group, the light-emitting material layer and the common electrode are disconnected at the side wall of the partition groove, and the common electrode extends from the side of the light-emitting material layer to contact the second conductive part.

[0010] In one embodiment of the present disclosure, the common electrode extends from a side surface of the light-emitting material layer and a side surface of the second conductive portion to a surface of the second conductive portion close to the base substrate.

[0011] In one embodiment of the present disclosure, the partition groove includes a first groove segment and a second groove segment that are sequentially away from the substrate, and the orthographic projection of at least part of the second groove segment on the substrate is located within the orthographic projection of the first groove segment on the substrate.

[0012] In one embodiment of the present disclosure, the second slot section is an opening penetrating the second conductive portion, and the first slot section is a groove at least partially passing through the insulating layer group.

[0013] In one embodiment of the present disclosure, the insulating layer group includes a protective layer and a first planarization layer, and the first planarization layer is provided on a side of the protective layer away from the base substrate.

[0014] In one embodiment of the present disclosure, a second opening is provided in the first planarization layer area within the first opening, the orthographic projection of the second opening on the base substrate is located within the orthographic projection of the first opening on the base substrate, the orthographic projection of the first groove section on the base substrate is located within the orthographic projection of the second opening on the base substrate, the first groove section is a groove that at least partially passes through the protective layer, and the first via is located on the protective layer between the second opening and the first groove section.

[0015] In one embodiment of the present disclosure, the first slot segment includes an opening penetrating the first planarization layer and a groove at least partially penetrating the protective layer, and the first via hole penetrates the protective layer and the first planarization layer between the first opening and the first slot segment.

[0016] In one embodiment of the present disclosure, the first groove segment penetrates the protective layer and exposes the first conductive portion, the light-emitting material layer forms a light-emitting material portion on the first conductive portion, and the common electrode forms a third conductive portion in the light-emitting material portion, and the third conductive portion covers the side surface of the light-emitting material portion and the side away from the base substrate.

[0017] In one embodiment of the present disclosure, the second slot section is a rectangular opening, a circular opening, or an elliptical opening provided on the second conductive portion.

[0018] In one embodiment of the present disclosure, the second slot section passes through two opposite sides of the second conductive portion along the first direction, dividing the second conductive portion into two sub-second conductive portions that are symmetrical about the first direction.

[0019] In one embodiment of the present disclosure, a portion of the second slot section close to the two first via holes is provided with a plurality of protrusions arranged at intervals, and a groove is formed between two adjacent protrusions.

[0020] In one embodiment of the present disclosure, the display panel has a display area and a non-display area located outside the display area. The display area includes a pixel light-emitting area and a non-light-emitting area between adjacent pixel light-emitting areas. The partition structure is provided in the non-light-emitting area.

[0021] In one embodiment of the present disclosure, the display panel has a display area and a non-display area located outside the display area, and the partition groove is provided in the non-display area.

[0022] In one embodiment of the present disclosure, the display panel further includes a thin film transistor, which is disposed in the display area. The thin film transistor has a first source and a drain, and the first conductive portion is disposed in the same layer and material as the first source and drain.

[0023] In one embodiment of the present disclosure, the display panel also includes a pixel electrode, which is arranged in the display area, the pixel electrode is connected to the first source electrode through a second via hole, the pixel electrode and the common electrode, and the light-emitting material layer located between the pixel electrode and the common electrode form a sub-pixel, and the pixel electrode and the second conductive part are arranged in the same layer and material.

[0024] In one embodiment of the present disclosure, the display panel also includes a light-shielding layer, which is arranged between the base substrate and the thin film transistor. The orthographic projection of the light-shielding layer on the base substrate overlaps with the orthographic projection of the channel region of the thin film transistor on the base substrate, and the light-shielding layer is connected to the first source electrode of the thin film transistor.

[0025] According to another aspect of the present disclosure, a method for manufacturing a display panel is provided, the method comprising:

[0026] providing a substrate;

[0027] forming a first conductive portion on one side of the base substrate, wherein the first conductive portion is located in a non-display area;

[0028] forming an insulating layer group on one side of the base substrate, and performing a first etching on the insulating layer group to form a first via hole;

[0029] A second conductive portion is formed on a side of the insulating layer group away from the base substrate, the second conductive portion is located in the non-display area, and the second conductive portion is connected to the first conductive portion through a first via hole;

[0030] patterning the second conductive portion to form a second groove segment;

[0031] forming a pixel definition layer on a side of the second conductive portion away from the base substrate, and forming a first opening in the pixel definition layer to expose the second conductive portion;

[0032] Using the patterned first conductive portion as a mask, the insulating layer group is etched a second time to form a first groove segment, wherein the first groove segment and the second groove segment form a partition groove;

[0033] forming a light-emitting material layer on a side of the pixel definition layer away from the base substrate, wherein the light-emitting material layer is disconnected at a sidewall of the partition groove;

[0034] A common electrode is formed on the side of the light-emitting material layer away from the base substrate. The common electrode is disconnected at the side wall of the partition groove and extends from the side of the light-emitting material layer and the side of the second conductive part to the side of the second conductive part close to the base substrate.

[0035] According to yet another aspect of the present disclosure, a display device is provided, including the display panel provided in one aspect of the present disclosure.

[0036] The display panel disclosed herein is provided with a partition groove that extends through the second conductive portion and the insulating layer group. The light-emitting material layer and the common electrode are disconnected at the sidewalls of the partition groove, and the common electrode extends from the side of the light-emitting material layer to contact the second conductive portion. The pixel current generated during light emission can flow through the common electrode to the second conductive portion, and then enter the first conductive portion through the first via. The first conductive portion has a low impedance, thereby reducing voltage drop and achieving an auxiliary electrode effect. The second conductive portion can adopt a monolithic structure, reducing short circuits and dark spot defects caused by fractures in the second conductive portion.

[0037] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0039] FIG1 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure when a first groove section partially passes through a protective layer.

[0040] FIG2 is a schematic cross-sectional view of the display panel according to an embodiment of the present disclosure when the first groove segment penetrates the protective layer.

[0041] FIG3 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure when a first planarization layer and a second planarization layer are provided.

[0042] FIG4 is a schematic cross-sectional view of the display panel according to an embodiment of the present disclosure when the first via hole penetrates the protective layer and the first planarization layer.

[0043] FIG5 is a partial plan view of a display panel according to an embodiment of the present disclosure when the second slot segment is a rectangular opening.

[0044] FIG6 is a plan view of the second conductive portion according to an embodiment of the present disclosure when the second slot segment is a rectangular opening.

[0045] FIG7 is a partial plan view of a display panel according to an embodiment of the present disclosure when the second groove segment is a circular opening.

[0046] FIG8 is a planar schematic diagram of the second conductive portion involved in an embodiment of the present disclosure when the second slot segment is a circular opening.

[0047] FIG9 is a partial plan view of a display panel according to an embodiment of the present disclosure when the second conductive portion comprises two sub-second conductive portions.

[0048] FIG10 is a planar schematic diagram of the second conductive portion involved in an embodiment of the present disclosure when the second conductive portion is composed of two sub-second conductive portions.

[0049] 11 is a partial plan view of a display panel according to an embodiment of the present disclosure, when the second slot segment is a rectangular opening and a portion of the second slot segment close to the two first via holes is provided with a plurality of spaced protrusions.

[0050] FIG12 is a plan view of the second conductive portion according to an embodiment of the present disclosure when the second slot segment is a rectangular opening and a portion of the second slot segment close to the two first via holes is provided with a plurality of spaced protrusions.

[0051] 13 is another partial plan view of the display panel according to an embodiment of the present disclosure, when the second slot segment is a rectangular opening and a portion of the second slot segment close to the two first via holes is provided with a plurality of spaced protrusions.

[0052] 14 is another planar schematic diagram of the second conductive portion involved in an embodiment of the present disclosure when the second slot segment is a rectangular opening and a portion of the second slot segment close to the two first via holes is provided with a plurality of spaced protrusions.

[0053] FIG15 is a flow chart of a method for manufacturing a display panel according to an embodiment of the present disclosure.

[0054] FIG16 is a schematic cross-sectional view of the display panel after the second groove segment is formed during the manufacturing process of the embodiment of the present disclosure.

[0055] FIG17 is a cross-sectional view showing the second conductive portion being patterned to form a first groove segment during the manufacturing process of the display panel according to the embodiment of the present disclosure.

[0056] FIG18 is a cross-sectional schematic diagram of a light-emitting material layer after being broken in a partition groove during the manufacturing process of the display panel according to an embodiment of the present disclosure.

[0057] FIG19 is a schematic cross-sectional view of a common electrode after being disconnected in a partition groove during the manufacturing process of the display panel according to an embodiment of the present disclosure.

[0058] Explanation of the accompanying symbols: 1-substrate, 2-functional layer group, 21-light shielding layer, 22-buffer layer, 23-driving circuit layer, 231-thin film transistor, 2311-active layer, 2312-gate insulating layer, 2313-gate, 2315-interlayer dielectric layer, 2316-first source, 2317-drain, 2318-protective layer, 2319-second source, 232-first conductive portion, 233-first groove segment, 234-second opening, 235-first via hole, 24-planarization layer group, 241-first planarization layer, 242-second planarization layer, 25-pixel definition layer, 251-pixel opening, 25 2-first opening, 26-pixel layer, 261-pixel electrode, 262-luminescent material layer, 2621-luminescent material portion, 263-common electrode, 2631-third conductive portion, 264-second conductive portion, 2641-second groove segment, 2642-sub-second conductive portion, 27-encapsulation layer, 271-first inorganic encapsulation layer, 272-organic encapsulation layer, 273-second inorganic encapsulation layer, 28-partitioning groove, 100-display area, 1001-pixel luminescent area, 1002-non-luminescent area. DETAILED DESCRIPTION

[0059] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0060] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0061] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0062] Currently, large-scale vapor-deposited OLED top-emission displays require a transparent cathode material, resulting in a large sheet resistance and voltage drop. This requires an increase in the power supply voltage, which increases the power consumption of the display device. Currently, the anode undergoes a double Dep (deposition) reverse etching process to form a stacked structure. The stacked structure includes a first layer, a second layer, and a third layer stacked in a direction away from the substrate. The area of ​​the third layer is larger than that of the second layer, and a gap is formed between the third layer and the first layer. The third layer is an ITO2 layer, which is prone to falling off from the second layer, forming particulate impurities, which makes the display panel prone to short circuits and dark spots.

[0063] Based on this, the embodiment of the present disclosure provides a display panel. As shown in Figures 1 to 13, the display panel includes a base substrate 1, a first conductive portion 232, an insulating layer group, a second conductive portion 264, a pixel definition layer 25, a light-emitting material layer 262, and a common electrode 263. The first conductive portion 232 is provided on one side of the base substrate 1; the insulating layer group is provided on the side of the first conductive portion 232 away from the base substrate 1; the second conductive portion 264 is provided on the side of the insulating layer group away from the base substrate 1, and the second conductive portion 264 is connected to the first conductive portion 232 through a first via 235; the pixel definition layer 25 is provided on the side of the second conductive portion 264 away from the base substrate 1. On the side, the pixel definition layer 25 is provided with a first opening 252 exposing the second conductive part 264; the light-emitting material layer 262 is provided on the side of the pixel definition layer 25 away from the base substrate 1; the common electrode 263 is provided on the side of the light-emitting material layer 262 away from the base substrate 1; a partition groove 28 is provided on one side of the first via 235, and the partition groove 28 passes through the second conductive part 264 and at least part of the insulating layer group, the light-emitting material layer 262 and the common electrode 263 are disconnected at the side wall of the partition groove 28, and the common electrode 263 extends from the side of the light-emitting material layer 262 to contact the second conductive part 264.

[0064] The display panel is provided with a partition groove 28, which passes through the second conductive portion 264 and the insulating layer group. The light-emitting material layer 262 and the common electrode 263 are disconnected at the sidewalls of the partition groove 28. The common electrode 263 extends from the side of the light-emitting material layer 262 to contact the second conductive portion 264. The pixel current generated during light emission can flow through the common electrode 263 to the second conductive portion 264, and then enter the first conductive portion 232 through the first via 235. The material impedance of the first conductive portion 232 is lower than that of the common electrode 263. The low impedance of the first conductive portion 232 reduces voltage drop and achieves the auxiliary electrode effect. The second conductive portion 264 can adopt a monolithic structure to reduce short circuits and dark spot defects caused by fractures in the second conductive portion 264.

[0065] The display panel involved in the embodiment of the present disclosure is described in detail below with reference to specific examples.

[0066] As shown in Figures 1 to 4, the display panel includes a base substrate 1 and a functional layer group 2 arranged on one side of the base substrate 1. The display panel has a display area 100 and a non-display area located outside the display area 100. The functional layer group 2 includes a driving circuit layer 23 and a pixel layer. The driving circuit layer 23 is arranged on one side of the base substrate 1, and the pixel layer is arranged on the side of the driving circuit layer 23 away from the base substrate 1.

[0067] The functional layer group 2 includes a first planarization layer group 24 , which is disposed between the driving circuit layer 23 and the pixel layer. The first planarization layer group 24 may include a first planarization layer, which is disposed on a side of the driving circuit layer 23 away from the base substrate 1 .

[0068] The driving circuit layer 23 may include a plurality of thin film transistors 231. The thin film transistors 231 may be top-gate or bottom-gate. Taking the top-gate thin film transistor 231 as an example, the thin film transistor 231 may include an active layer 2311, a gate insulating layer 2312, a gate electrode 2313, and a first conductive layer, wherein:

[0069] The active layer 2311 is disposed on one side of the substrate 1 , and its material may be polysilicon, amorphous silicon, etc. The active layer 2311 may include a channel region and two doping regions of different doping types located on both sides of the channel region.

[0070] The gate insulating layer 2312 may cover the active layer 2311 and the base substrate 1 , and the material of the gate insulating layer 2312 is an insulating material such as silicon oxide.

[0071] The gate 2313 is arranged on the side of the gate insulation layer 2312 away from the base substrate 1 and is opposite to the active layer 2311, that is, the projection of the gate 2313 on the base substrate 1 is located within the projection range of the active layer 2311 on the base substrate 1. For example, the projection of the gate 2313 on the base substrate 1 coincides with the projection of the channel region of the active layer 2311 on the base substrate 1.

[0072] The thin film transistor 231 further includes an interlayer dielectric layer 2315 . The interlayer dielectric layer 2315 covers the gate electrode 2313 and the gate insulating layer 2312 . The interlayer dielectric layer 2315 is made of an insulating material.

[0073] The first conductive layer is arranged on the surface of the interlayer dielectric layer 2315 away from the base substrate 1. The first conductive layer includes a first source 2316 and a drain 2317. The first source 2316 and the drain 2317 are connected to the active layer 2311. For example, the first source 2316 and the drain 2317 are respectively connected to the two doped regions of the corresponding active layer 2311 through vias.

[0074] A protective layer 2318 is provided on the side of the first source electrode 2316 away from the base substrate 1. The protective layer 2318 covers the first source electrode 2316 and the drain electrode 2317. A first planarization layer 24 is provided on the side of the first conductive layer away from the base substrate 1. The first planarization layer 24 is provided on the side of the protective layer 2318 away from the base substrate 1. The first planarization layer 24 covers the protective layer 2318, and the surface of the first planarization layer 24 away from the base substrate 1 is flat.

[0075] In other feasible embodiments, the thin film transistor 231 may further include a fourth conductive layer, the fourth conductive layer includes a second source electrode 2319, a second planarization layer 242 is provided on the side of the second source electrode 2319 away from the substrate 1, the second planarization layer covers the second source electrode 2319 and the first planarization layer 24, and the second source electrode 2319 is connected to the first source electrode 2316 through a via.

[0076] It should be noted that a buffer layer 22 is usually provided between the base substrate 1 and the driving circuit layer 23 .

[0077] A pixel definition layer 25 and a pixel layer 26 may be provided on the side of the driving backplane away from the base substrate 1. The pixel definition layer 25 has a plurality of pixel openings 251, and the pixel layer 26 includes a plurality of sub-pixels, each of which is disposed within the plurality of pixel openings 251. The plurality of sub-pixels are arranged in an array on the side of the driving backplane away from the base substrate 1. Specifically, the sub-pixels may be located on the side of the first planarization layer 24 or the second planarization layer away from the base substrate 1. It should be noted that the sub-pixels may include red, green, or blue sub-pixels, depending on the color of the emitted light.

[0078] Each sub-pixel may include a pixel electrode 261, a light-emitting material layer 262, and a common electrode 263. The pixel electrode 261 is provided on the second conductive layer, which is located on the surface of the driving backplane away from the base substrate 1. The light-emitting material layer 262 is provided on the surface of the pixel electrode 261 away from the base substrate 1. The common electrode 263 is provided on the third conductive layer, which is provided on the surface of the light-emitting material layer 262 away from the base substrate 1. The pixel layer can be driven to emit light through the pixel electrode 261 and the common electrode 263 to display an image.

[0079] The pixel electrode 261 is connected to the first source electrode 2316 or the second source electrode 2319. When the thin film transistor 231231 includes only the first source electrode 2316, the pixel electrode 261 is connected to the first source electrode 2316, and a pixel definition layer 25 is provided to cover the pixel electrode 261 and the first planarization layer 24. When the thin film transistor 231 also includes the second source electrode 2319, the pixel electrode 261 is connected to the second source electrode 2319, and a pixel definition layer 25 is provided to cover the pixel electrode 261 and the first planarization layer.

[0080] The first conductive layer may further include a first conductive portion 232. The first conductive portion 232 is provided in the same layer and material as the first source electrode 2316, that is, the first conductive portion 232 is provided between the interlayer dielectric layer 2315 and the protective layer 2318. Of course, the first conductive portion 232 may also be provided in the same layer and material as the second source electrode 2319. The second conductive layer may further include a second conductive portion 264. The second conductive portion 264 is provided in the same layer and material as the pixel electrode 261, that is, the second conductive portion 264 is provided between the pixel definition layer 25 and the first planarization layer. The second conductive portion 264 is connected to the first conductive portion 232 through a first via, forming an auxiliary electrode.

[0081] In this embodiment, the display area 100 may include a pixel light-emitting area 1001 and a non-light-emitting area 1002 between adjacent pixel light-emitting areas 1001. The auxiliary electrode is typically disposed in the non-light-emitting area 1002, which does not increase the width of the non-display area and is suitable for narrow-frame display devices. In other implementations, the auxiliary electrode may also be disposed in the non-display area to maintain pixel density in the display area, thereby ensuring a good display effect.

[0082] The pixel definition layer 25 is provided with a first opening 252, which exposes the first planarization layer. A partition groove 28 is provided within the first opening 252. The partition groove 28 is located between the two first vias and extends through the second conductive portion 264, the first planarization layer, and at least a portion of the protective layer 2318. It is understood that the first planarization layer and the protective layer 2318 constitute the aforementioned insulating layer group. The partition groove 28 includes a first groove segment 233 and a second groove segment 2641, which are located away from the substrate. The orthographic projection of the second groove segment 2641 on the substrate is located within the orthographic projection of the first groove segment 233 on the substrate. The first groove segment 233 and the second groove segment 2641 form an inverted T-shaped partition groove 28.

[0083] As shown in Figures 1 to 3, a second opening 234 is provided in the first planarization layer region within the first opening 252. The orthographic projection of the second opening 234 on the substrate is located within the orthographic projection of the first opening 252 on the substrate. A first groove section 233 is provided in the protective layer 2318 region within the second opening 234. The orthographic projection of the first groove section 233 on the substrate is located within the orthographic projection of the second opening 234 on the substrate. As shown in Figure 1, the first groove section can partially pass through the protective layer 2318. As shown in Figure 2, the first groove section can penetrate the protective layer 2318. As shown in Figure 3, when the second opening 234 penetrates the first planarization layer 241 and the second planarization layer 242 located within the first opening 252.

[0084] The portion of the protective layer 2318 between the second opening 234 and the first slot section 233 constitutes the first opening region. The portion of the first planarization layer between the first opening 252 and the second opening 234 constitutes the second opening region. The orthographic projection of the second conductive portion 264 on the substrate covers a portion of the orthographic projection of the second opening region, the orthographic projection of the first opening region, and the outer edge of the orthographic projection of the first slot section 233. The second conductive portion 264 is provided with a second slot section 2641 extending through it. A first via is provided in the first opening region.

[0085] As shown in Figure 4, the orthographic projection of the first groove section 233 on the base substrate is located within the orthographic projection of the first opening 252 on the base substrate. The first groove section 233 includes an opening that passes through the first planarization layer and a groove that at least partially passes through the protective layer 2318. The orthographic projection of the opening on the base substrate can coincide with the orthographic projection of the groove on the base substrate. The first via hole passes through the protective layer 2318 and the first planarization layer between the first opening 252 and the first groove section 233.

[0086] Whether shown in Figures 1, 2, 3, or 4, the first groove segment 233 can penetrate the protective layer 2318 and expose the first conductive portion 232, thereby ensuring a sufficiently large gap between the side of the second conductive portion 264 close to the substrate and the side of the first conductive portion 232 away from the substrate, thereby effectively disconnecting the light-emitting material layer 262 and the common electrode 263. The light-emitting material layer 262 disconnected within the partition groove 28 forms a light-emitting material portion 262 on the first conductive portion 232, and the common electrode 263 disconnected within the partition groove 28 forms a third conductive portion 2631 on the light-emitting material portion 262. The third conductive portion 2631 covers the side surface of the light-emitting material portion 262 and the side away from the substrate.

[0087] Figure 5 is a schematic plan view of a portion of a display panel according to an embodiment of the present disclosure, when the second groove segment 2641 is a rectangular opening. As shown in Figures 5 and 6, the second groove segment 2641 is a rectangular opening formed on the second conductive portion 264. The second conductive portion 264 overlaps the first conductive portion 232 through the first via 235 to form an auxiliary electrode. The pixel electrode layer and the first planarization layer wrap around the auxiliary electrode to prevent damage to the common electrode 263 and the light-emitting layer within the inverted T-shaped partition groove 28 during brush and air knife cleaning, which could cause dark spots.

[0088] Figure 7 is a schematic plan view of a portion of a display panel according to an embodiment of the present disclosure, when the second slot segment 2641 is a circular opening. As shown in Figures 7 and 8, the second slot segment 2641 is a circular or elliptical opening provided on the second conductive portion 264. This reduces the area of ​​the second conductive portion 264 where the second slot segment 2641 is provided, thereby increasing the contact area between the common electrode 263 and the second conductive portion 264. This reduces the contact resistance between the common electrode 263 and the second conductive portion 264, thereby enhancing the auxiliary electrode's ability to reduce IR drop.

[0089] Figure 9 is a schematic plan view of a portion of a display panel according to an embodiment of the present disclosure, where the second conductive portion comprises two sub-second conductive portions 2642. As shown in Figures 9 and 10, a second slot 2641 extends along the first direction through two opposing sides of the second conductive portion 264, dividing the second conductive portion 264 into two sub-second conductive portions 2642 symmetrical about the first direction. The two sub-second conductive portions 2642 are rectangular in shape, and their area is half that of the second conductive portion 264.

[0090] It should be noted that the first direction is the x-direction shown in Figures 9 and 10. Because the two sub-second conductive portions 2642 are respectively connected to the first conductive portion 232 through the first via 235, the first conductive portion 232 is a continuous whole. Therefore, dividing the second conductive portion 264 into two independent sub-second conductive portions 2642 does not affect the auxiliary electrode's ability to reduce voltage drop.

[0091] Figures 11 and 13 are schematic plan views of a portion of a display panel according to an embodiment of the present disclosure, wherein the second slot segment is a rectangular opening and the portion of the second slot segment near the two first vias 235 is provided with a plurality of spaced-apart protrusions 2643. As shown in Figures 11 and 12, based on Figure 5, the portion of the second slot segment 2641 near the two first vias 235 is provided with a plurality of spaced-apart sawtooth-shaped protrusions 2643, with a sawtooth-shaped groove formed between adjacent sawtooth-shaped protrusions 2643. This further reduces the area of ​​the second conductive portion 264 where the second slot segment 2641 is provided, thereby increasing the contact area between the common electrode 263 and the second conductive portion 264 and reducing the contact resistance between the common electrode 263 and the second conductive portion 264.

[0092] As shown in FIG13 and FIG14 , the difference from FIG11 and FIG12 is that a portion of the second slot section 2641 close to the two first via holes 235 is provided with a plurality of spaced arc-shaped protrusions 2643 , and an arc-shaped groove is formed between two adjacent arc-shaped protrusions 2643 .

[0093] Referring to Figures 12 and 14 , the shape of the second groove segment 2641 is designed to maximize the contact area between the common electrode 263 and the second conductive portion 264. The larger the contact area between the common electrode 263 and the second conductive portion 264, the lower the contact resistance between the common electrode 263 and the second conductive portion 264. The lower the contact resistance between the common electrode 263 and the second conductive portion 264, the more effective the auxiliary electrode is in reducing voltage drop.

[0094] In addition, the display panel of the present disclosure may further include an encapsulation layer 27. Encapsulation layer 27 is disposed on the side of pixel layer 26 away from base substrate 1, thereby encapsulating pixel layer 26 and preventing corrosion by water and oxygen. Encapsulation layer 27 may have a single-layer or multi-layer structure, and the material of encapsulation layer 27 may include organic or inorganic materials, without particular limitation herein.

[0095] In this embodiment, the encapsulation layer 27 may include a first inorganic encapsulation layer 271, an organic encapsulation layer 272, and a second inorganic encapsulation layer 273. The first inorganic encapsulation layer 271 is provided on a side of the pixel layer 26 away from the base substrate 1, the organic encapsulation layer 272 is provided on a side of the first inorganic encapsulation layer 271 away from the base substrate 10, and the second inorganic encapsulation layer 273 is provided on a side of the organic encapsulation layer 272 away from the base substrate 1. The inorganic encapsulation layer 271 and the second inorganic encapsulation layer 273 may be formed by vapor deposition, and the organic encapsulation layer 272 may be formed by inkjet printing and leveling.

[0096] The display panel also includes a light-shielding layer 21, which is disposed between the base substrate and the thin-film transistor 231. Specifically, the light-shielding layer 21 is disposed between the base substrate 1 and the buffer layer 22. The orthographic projection of the light-shielding layer 21 on the base substrate can overlap with the orthographic projection of the channel region of the thin-film transistor 231 on the base substrate, thereby shielding light from the thin-film transistor 231 and stabilizing the electrical characteristics of the thin-film transistor 231. The light-shielding layer 21 is connected to the first source electrode of the thin-film transistor 231 to conduct static electricity away from the light-shielding layer 21, preventing electrostatic discharge from damaging the thin-film transistor 231.

[0097] The present disclosure also provides a method for manufacturing a display panel. As shown in Figures 15 to 19, the method includes:

[0098] Step S10: providing a base substrate.

[0099] In step S20 , a first conductive portion 232 is formed on one side of the base substrate.

[0100] Step S30 , forming an insulating layer group on one side of the base substrate, and performing a first etching on the insulating layer group to form a first via hole.

[0101] In step S40 , a second conductive portion 264 is formed on a side of the insulating layer group away from the base substrate. The second conductive portion 264 is connected to the first conductive portion 232 through a first via hole.

[0102] In step S50 , the second conductive portion 264 is patterned to form a second groove section 2641 .

[0103] In step S60 , a pixel definition layer 25 is formed on a side of the second conductive portion 264 away from the base substrate, and a first opening 252 is formed on the pixel definition layer 25 to expose the second conductive portion 264 .

[0104] In step S70 , the insulating layer group is etched a second time using the patterned first conductive portion 232 as a mask to form a first groove segment 233 . The first groove segment 233 and the second groove segment 2641 form a partition groove 28 .

[0105] In step S80 , a light-emitting material layer 262 is formed on a side of the pixel definition layer 25 away from the base substrate. The light-emitting material layer 262 is disconnected at the sidewall of the partition groove 28 .

[0106] In step S90, a common electrode 263 is formed on the side of the light-emitting material layer 262 away from the base substrate. The common electrode 263 is disconnected at the side wall of the partition groove 28 and extends from the side of the light-emitting material layer 262 and the side of the second conductive part 264 to the side of the second conductive part 264 close to the base substrate.

[0107] The beneficial effects of this method can be referenced to the beneficial effects of the display panel. In addition, in this method, the protective layer 2318 is first etched to form a first via hole, connecting the second conductive portion 264 to the first conductive portion 232. After the second conductive portion 264 is patterned to form the second groove segment 2641, the pixel definition layer 25 is first formed to expose the first groove segment 233. The protective layer 2318 is then etched a second time to form the first groove segment 233, and then the light-emitting material layer 262 is directly formed. When the first groove segment 233 penetrates the protective layer 2318, the risk of oxidation caused by the first conductive portion 232 being exposed for too long is avoided.

[0108] In other feasible embodiments, steps S60 and S70 may be interchanged. Using the patterned first conductive portion 232 as a mask, the insulating layer assembly is etched a second time to form the second groove segment 2641. A pixel definition layer 25 is then formed on the side of the second conductive portion 264 facing away from the substrate, and a first opening 252 is formed in the pixel definition layer 25, exposing the second conductive portion 264. However, in this method, when the first groove segment 233 penetrates the protective layer 2318, the first conductive layer remains exposed during the process of forming the pixel definition layer 25, posing a risk of oxidation.

[0109] Between step S10 and step S20 , the method may further include: forming a light shielding layer 21 on one side of the base substrate.

[0110] The method may further include: forming a thin film transistor 231 layer on a side of the light shielding layer 21 away from the base substrate.

[0111] Forming a thin film transistor 231 layer on the side of the light-shielding layer 21 away from the base substrate may include: forming a buffer layer 22 on one side of the base substrate, forming an active layer on the side of the buffer layer 22 away from the base substrate, and the orthographic projection of the active layer on the base substrate may be located within the orthographic projection of the light-shielding layer 21 on the base substrate; forming a gate insulating layer on the side of the active layer away from the base substrate; forming a gate on the side of the gate insulating layer away from the base substrate; and forming an interlayer dielectric layer on the side of the gate away from the base substrate.

[0112] In step S20, while forming the first conductive part 232, the first source and drain of the thin film transistor 231 can also be formed. The first source is connected to the active layer through the interlayer dielectric layer, and the first source is connected to the light shielding layer 21 through the interlayer dielectric layer and the buffer layer 22.

[0113] In step S30 , when forming the first via hole, a second via hole may also be formed on the insulating layer group.

[0114] In step S40 , while forming the second conductive portion 264 , a pixel electrode may also be formed. The pixel electrode is connected to the first source of the thin film transistor 231 through the second via hole.

[0115] The present disclosure also provides a display device. The display device may include any of the display panels described above. The specific structure and beneficial effects of the display panel have been described in detail above and are therefore not further elaborated here.

[0116] It should be noted that, in addition to the display panel, the display device also includes other necessary components and components, such as circuit boards, power cords, etc. Those skilled in the art can make corresponding supplements based on the specific usage requirements of the display device, which will not be repeated here.

[0117] When the display panel has the structure shown in the figure, the display device can be a traditional electronic device, such as a mobile phone, a computer, a television, and a camcorder, or it can be an emerging wearable device, such as a virtual reality device and an augmented reality device, which are not listed here one by one.

[0118] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A display panel, characterized in that: include: substrate substrate; A first conductive portion is provided on one side of the base substrate; An insulating layer group, provided on a side of the first conductive portion away from the base substrate; A second conductive portion is provided on a side of the insulating layer group away from the base substrate, and the second conductive portion is connected to the first conductive portion through a first via hole; A pixel definition layer is provided on a side of the second conductive portion away from the base substrate, and the pixel definition layer is provided with a first opening exposing the second conductive portion; A light emitting material layer is disposed on a side of the pixel definition layer away from the base substrate; A common electrode is provided on a side of the light emitting material layer away from the base substrate; A partition groove is provided on one side of the first via hole, and the partition groove passes through the second conductive part and at least part of the insulating layer group. The light-emitting material layer and the common electrode are disconnected at the side wall of the partition groove, and the common electrode extends from the side of the light-emitting material layer to contact the second conductive part.

2. The display panel according to claim 1, characterized in that: The common electrode extends from the side surface of the light emitting material layer and the side surface of the second conductive portion to a surface of the second conductive portion close to the base substrate.

3. The display panel according to claim 1, characterized in that: The partition groove comprises a first groove section and a second groove section which are sequentially away from the substrate, and the orthographic projection of at least a portion of the second groove section on the substrate is located within the orthographic projection of the first groove section on the substrate.

4. The display panel according to claim 3, characterized in that: The second slot section is an opening penetrating through the second conductive portion, and the first slot section is a groove at least partially penetrating through the insulating layer group.

5. The display panel according to claim 4, characterized in that: The insulating layer group includes a protective layer and a first planarization layer, and the first planarization layer is arranged on a side of the protective layer away from the base substrate.

6. The display panel according to claim 5, characterized in that: A second opening is provided in the first planarization layer area within the first opening, the orthographic projection of the second opening on the substrate is located within the orthographic projection of the first opening on the substrate, the orthographic projection of the first groove section on the substrate is located within the orthographic projection of the second opening on the substrate, the first groove section is a groove that at least partially passes through the protective layer, and the first via is located on the protective layer between the second opening and the first groove section.

7. The display panel according to claim 5, characterized in that: The first groove section includes an opening penetrating the first planarization layer and a groove at least partially penetrating the protection layer, and the first via hole penetrates the protection layer and the first planarization layer between the first opening and the first groove section.

8. The display panel according to claim 6 or 7, characterized in that: The first groove segment penetrates the protective layer and exposes the first conductive part. The light-emitting material layer forms a light-emitting material part on the first conductive part. The common electrode forms a third conductive part on the light-emitting material part. The third conductive part covers the side surface of the light-emitting material part and the side away from the base substrate.

9. The display panel according to claim 3, characterized in that: The second slot section is a rectangular opening, a circular opening or an elliptical opening provided on the second conductive portion.

10. The display panel according to claim 3, characterized in that: The second slot section passes through two opposite sides of the second conductive portion along the first direction, dividing the second conductive portion into two sub-second conductive portions that are symmetrical with respect to the first direction.

11. The display panel according to claim 3, characterized in that: A portion of the second slot section close to the two first via holes is provided with a plurality of protrusions arranged at intervals, and a groove is formed between two adjacent protrusions.

12. The display panel according to claim 1, characterized in that: The display panel has a display area and a non-display area located outside the display area. The display area includes a pixel light-emitting area and a non-light-emitting area between adjacent pixel light-emitting areas. The partition structure is arranged in the non-light-emitting area.

13. The display panel according to claim 1, characterized in that: The display panel has a display area and a non-display area located outside the display area, and the partition groove is arranged in the non-display area.

14. The display panel according to claim 12 or 13, characterized in that: The display panel further includes a thin film transistor, which is disposed in the display area. The thin film transistor has a first source and a drain, and the first conductive portion is disposed in the same layer and material as the first source and the drain.

15. The display panel according to claim 14, characterized in that: The display panel also includes a pixel electrode, which is arranged in the display area. The pixel electrode is connected to the first source electrode through a second via hole. The pixel electrode and the common electrode, as well as a light-emitting material layer located between the pixel electrode and the common electrode form a sub-pixel. The pixel electrode and the second conductive part are arranged in the same layer and material.

16. The display panel according to claim 14, characterized in that: The display panel also includes a light-shielding layer, which is arranged between the base substrate and the thin film transistor. The orthographic projection of the light-shielding layer on the base substrate overlaps with the orthographic projection of the channel region of the thin film transistor on the base substrate. The light-shielding layer is connected to the first source electrode of the thin film transistor.

17. A method for manufacturing a display panel, characterized in that: The method comprises: providing a substrate base plate; forming a first conductive portion on one side of the base substrate; forming an insulating layer group on one side of the base substrate, and performing a first etching on the insulating layer group to form a first via hole; A second conductive portion is formed on a side of the insulating layer group away from the base substrate, wherein the second conductive portion is connected to the first conductive portion through a first via hole; Patterning the second conductive portion to form a second groove segment; forming a pixel definition layer on a side of the second conductive portion away from the base substrate, and forming a first opening on the pixel definition layer to expose the second conductive portion; Using the patterned first conductive portion as a mask, etching the insulating layer group for a second time to form a first groove segment, wherein the first groove segment and the second groove segment constitute a partition groove; forming a light-emitting material layer on a side of the pixel definition layer away from the base substrate, wherein the light-emitting material layer is disconnected at a side wall of the partition groove; A common electrode is formed on a side of the light emitting material layer away from the base substrate. The common electrode is disconnected at the side wall of the partition groove and extends from the side of the light emitting material layer and the side of the second conductive part to a side of the second conductive part close to the base substrate.

18. A display device, characterized in that: A display panel comprising any one of claims 1 to 16.

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