Display panel and control method therefor

Abstract

A display panel and a control method therefor. The control method comprises: during the process of switching the refresh frequency of a first display partition (AA1), setting a plurality of transition frames, wherein the refresh frequency of the first display partition (AA1) in the plurality of transition frames is between the refresh frequency of the first display partition (AA1) before switching and the refresh frequency of the first display partition (AA1) after switching; and / or, during the process of switching the refresh frequency of the first display partition (AA1), making configurations in the plurality of transition frames, such that the positions where pixel circuits corresponding to the adjacent boundary of the first display partition (AA1) and a second display partition (AA2) are located are different (S120).

Description

Display panel and control method thereof

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on August 23, 2023, with application number 202311069548.7. The entire contents of the above application are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of display technology, for example, to a display panel and a control method thereof. Background Art

[0003] With the development of display technology, people have higher and higher requirements on the display quality of display panels.

[0004] Currently, display panels have uneven display brightness, which results in an uneven visual effect and seriously reduces display quality.

[0005] Summary of the Invention

[0006] Embodiments of the present application provide a display panel and a control method thereof to improve display quality.

[0007] According to one aspect of the present application, a method for controlling a display panel is provided. The display panel includes at least two display partitions, wherein the at least two display partitions include a first display partition and a second display partition that are adjacent and have different refresh rates. The display panel includes:

[0008] A plurality of pixel circuits arranged in an array;

[0009] The control method of the display panel includes:

[0010] During the process of switching the refresh frequency of the first display partition, multiple transition frames are set, and the refresh frequency of the first display partition in the multiple transition frames is between the refresh frequency before the switching of the first display partition and the refresh frequency after the switching; and / or, in the multiple transition frames, the positions of the pixel circuits corresponding to the adjacent boundaries of the first display partition and the second display partition are different.

[0011] According to another aspect of the present application, a method for controlling a display panel is provided. The display panel includes at least two display partitions, the at least two display partitions including a first display partition and a second display partition that are adjacent and have different refresh rates. The display panel includes: a plurality of pixel circuits arranged in an array; at least one driving circuit, the driving circuit including a scanning circuit, at least two clock signal lines, a gating module, and a gating signal line. The scanning circuit includes a multi-stage shift unit, and the scanning circuit is connected to the at least two clock signal lines.

[0012] The control method of the display panel includes:

[0013] The selection module responds to the signal on the selection signal line, causing the shift unit to output a scanning signal to the corresponding pixel circuit, so as to achieve different refresh frequencies corresponding to at least two display partitions; the transition edge of the signal on the selection signal line is aligned in time with the transition edge of the clock signal on one of at least two clock signal lines, or the difference is less than or equal to 2 crystal oscillator cycles, wherein the crystal oscillator is set in the clock circuit used to generate the clock signal.

[0014] According to another aspect of the present application, a display panel is provided. The display panel is controlled by the display panel control method provided by any embodiment of the present application.

[0015] The technical solution provided by the embodiment of the present application is to set multiple transition frames during the process of switching the refresh frequency of the first display partition. The refresh frequency of the first display partition in the multiple transition frames is between the refresh frequency before the switching and the refresh frequency after the switching of the first display partition, so that the display brightness at the boundary position changes slowly during the frequency switching process, thereby avoiding the situation where the abnormal display of the boundary line is caused by excessive brightness changes when the display images with different refresh frequencies are switched. And / or, during the process of switching the refresh frequency of the first display partition, in the multiple transition frames, by setting the positions of the pixel circuits corresponding to the adjacent boundaries of the first display partition and the second display partition to be different, for example, changing with time, the brightness difference of the boundary line between the first display partition and the second display partition in the multiple transition frames is balanced, thereby improving the situation where the boundary line is displayed abnormally. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIG1 is a schematic structural diagram of a display device provided in an embodiment of the present application;

[0017] FIG2 is a schematic structural diagram of a display panel provided in an embodiment of the present application;

[0018] FIG3 is a flow chart of a method for controlling a display panel provided in an embodiment of the present application;

[0019] FIG4 is a schematic structural diagram of a pixel circuit provided in an embodiment of the present application;

[0020] FIG5 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

[0021] FIG6 is a schematic diagram of a driving timing sequence of a pixel circuit provided in an embodiment of the present application;

[0022] FIG7 is a timing diagram of a strobe signal on a strobe signal line in the time domain provided by an embodiment of the present application;

[0023] FIG8 is a timing diagram of another strobe signal on a strobe signal line in the time domain provided by an embodiment of the present application;

[0024] FIG9 is a schematic structural diagram of a display panel corresponding to a display panel spatial space adjustment method provided in an embodiment of the present application;

[0025] FIG10 is a schematic diagram of a driving timing sequence of a scanning signal during a frequency switching process provided by an embodiment of the present application;

[0026] FIG11 is a schematic diagram of a driving timing sequence of a scanning signal during another frequency switching process provided by an embodiment of the present application;

[0027] FIG12 is a flowchart of another method for controlling a display panel provided by an embodiment of the present application;

[0028] FIG13 is a schematic structural diagram of a shift unit provided in an embodiment of the present application;

[0029] FIG14 is a schematic diagram of a driving timing sequence of a shift unit provided in this embodiment;

[0030] FIG15 is a schematic structural diagram of another shift unit provided in an embodiment of the present application;

[0031] FIG16 is a schematic diagram of a driving timing of another shift unit provided in an embodiment of the present application;

[0032] FIG17 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

[0033] FIG18 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

[0034] FIG19 is a schematic diagram of a driving timing of another shift unit provided in an embodiment of the present application;

[0035] FIG20 is a schematic structural diagram of another display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0037] FIG1 is a schematic diagram of the structure of a display device provided in an embodiment of the present application. The display device includes a display panel 11 and a display driver module 300. The display driver module 300 may be a driver chip. The display panel 11 may include a display area AA and a non-display area NAA. The display area AA may include a plurality of pixel circuits PX arranged in an array. The display panel 11 may also include a plurality of scan lines GL1 and a driver circuit 12. The plurality of scan lines GL1 extend along the X direction and are arranged in sequence along the Y direction. Each scan line GL1 is connected to a corresponding row of pixel circuits PX. The driver circuit 12 is connected to the corresponding scan lines GL1. The driver circuit 12 is located in the non-display area NAA. The display panel 11 also includes a plurality of data lines DL extending along the Y direction and arranged along the X direction. Each data line DL is connected to a corresponding column of pixel circuits PX. The X direction (which may be the row direction) and the Y direction (which may be the column direction) intersect, for example, and may be perpendicular.

[0038] FIG2 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application. Referring to FIG1 and FIG2 , the display area AA of the display panel 11 provided in this embodiment includes at least two display partitions, such as a first display partition AA1 and a second display partition AA2, adjacent to each other. The first display partition AA1 and the second display partition AA2 correspond to different refresh frequencies. For example, the first display partition AA1 corresponds to a low refresh frequency, and the second display partition AA2 corresponds to a high refresh frequency; alternatively, the first display partition AA1 corresponds to a high refresh frequency, and the second display partition AA2 corresponds to a low refresh frequency. The first display partition AA1 and the second display partition AA2 can be arranged along the Y direction.

[0039] FIG3 is a flow chart of a method for controlling a display panel provided in an embodiment of the present application. Referring to FIG1 to FIG3 , the method for controlling a display panel provided in this embodiment includes:

[0040] S120. During the process of switching the refresh frequency of the first display partition, a plurality of transition frames are set, and the refresh frequency of the first display partition in the plurality of transition frames is between the refresh frequency before the switching and the refresh frequency after the switching of the first display partition; and / or, in the plurality of transition frames, the positions of the pixel circuits corresponding to the adjacent boundaries of the first display partition and the second display partition are different.

[0041] During the display process of the display panel 11, the refresh frequencies switched between different display partitions are not necessarily the same. The refresh frequency of the first display partition AA1 in multiple transition frames may be greater than the smaller of the refresh frequencies before and after the switching of the first display partition AA1, and less than the larger of the refresh frequencies before and after the switching of the first display partition AA1.

[0042] Taking the display panel 11 shown in FIG2 as an example, which includes a first display partition AA1 and a second display partition AA2, for example, the refresh frequency of the first display partition AA1 before switching is 60Hz, and the refresh frequency to be switched of the first display partition AA1 is obtained to be 30Hz, then a transition frame with a refresh frequency of 40Hz can be inserted during the refresh frequency switching process of the first display partition AA1. In other words, during the refresh frequency switching process of the first display partition AA1, the refresh frequency of the first display partition AA1 can be first switched to 40Hz, and then switched from 40Hz to 30Hz, so as to reduce the brightness difference when the refresh frequency is switched each time. Compared with the method of directly switching from the current refresh frequency (60Hz) to the target refresh frequency (30Hz), this solution gradually transitions the refresh frequency of the first display partition to the target refresh frequency to be switched by inserting a transition frame, so that the display brightness of the dividing line position changes slowly during the frequency switching process, avoiding the situation where the brightness change is too large when the display screens with different refresh frequencies are switched, causing abnormal display of the dividing line.

[0043] In one embodiment, the number of transition frames can be set to be greater than 1. During the refresh frequency switching process of the first display partition AA1, the refresh frequencies of the multiple transition frames inserted in sequence are increased or decreased in sequence to improve the brightness difference during the refresh frequency switching process. The number of transition frames can be determined based on the difference between the refresh frequencies before and after the display partition is switched. If the difference between the refresh frequencies before and after the switch is too large, the gradient of the transition frames can be reduced, thereby increasing the number of transition frames; if the difference between the refresh frequencies before and after the switch is small, the gradient of the transition frames can be appropriately increased, thereby reducing the number of transition frames. Here, the gradient of the transition frame represents the difference in refresh frequency between two adjacent transition frames.

[0044] Optionally, in multiple transition frames, the position of the pixel circuit corresponding to the adjacent boundary between the first display partition AA1 and the second display partition AA2 is variable. That is, in multiple transition frames, the position of the pixel circuit corresponding to the adjacent boundary between the first display partition AA1 and the second display partition AA2 is different. That is, the position of the boundary line between the first display partition AA1 and the second display partition AA2 is adjustable. For example, during the refresh frequency switching process of the first display partition AA1, in the first transition frame, the adjacent boundary between the first display partition AA1 and the second display partition AA2 corresponds to the Qth row of pixel circuits, and in the second transition frame, the adjacent boundary between the first display partition AA1 and the second display partition AA2 corresponds to the Q±qth row of pixel circuits, where Q and q are both positive integers. Similarly, in other transition frames, the number of rows of pixel circuits corresponding to the adjacent boundary between the first display partition AA1 and the second display partition AA2 is also different from the position of the boundary line in the first transition frame and the second transition frame. By changing the position of the pixel circuits corresponding to the adjacent boundary between the first display partition AA1 and the second display partition AA2 in each transition frame, the boundary between the first display partition AA1 and the second display partition AA2 changes spatially over time, thereby balancing the brightness difference between the boundary line between the first display partition AA1 and the second display partition AA2 across multiple transition frames, thereby improving the display of abnormal boundary lines. During the refresh rate switching process of the first display partition AA1, 1-255 transition frames can be set, or the transition frames at each transition refresh frequency can be greater than or equal to 1 frame and less than or equal to 255 frames. During the refresh rate switching process of the first display partition AA1, the transition frames can include one or more of the following: at least a portion of the frames at the frequency before the switch, at least a portion of the frames at the frequency after the switch, and transition frames at a frequency between the frequencies before and after the switch. The refresh rate of the first display partition AA1 is switched when the refresh rate switching conditions for the first display partition AA1 are met or when a refresh rate switching instruction for the first display partition AA1 is received.

[0045] The technical solution provided by the embodiment of the present application is to set multiple transition frames during the process of switching the refresh frequency of the first display partition. The refresh frequency of the first display partition in the multiple transition frames is between the refresh frequency before the switching and the refresh frequency after the switching of the first display partition, so that the display brightness at the boundary position changes slowly during the frequency switching process, thereby avoiding the situation where the abnormal display of the boundary line is caused by excessive brightness changes when the display images with different refresh frequencies are switched. And / or, during the process of switching the refresh frequency of the first display partition, in the multiple transition frames, by setting the positions of the pixel circuits corresponding to the adjacent boundaries of the first display partition and the second display partition to be different, for example, changing with time, the brightness difference of the boundary line between the first display partition and the second display partition in the multiple transition frames is balanced, thereby improving the situation where the boundary line is displayed abnormally.

[0046] Optionally, in this embodiment, the refresh frequency of the first display area AA1 gradually increases or decreases over multiple transition frames, and is between the refresh frequency of the first display area AA1 before switching and the refresh frequency after switching. That is, the refresh frequencies corresponding to the multiple transition frames gradually change according to a positive gradient or a negative gradient, respectively, so that the first display area AA1 gradually switches from the current refresh frequency to the refresh frequency to be switched in a step-by-step manner. This results in a regular change in brightness caused by each refresh frequency switch within the transition frame, making the brightness change at the boundary location difficult for the human eye to perceive.

[0047] For example, if the refresh rate of the first display partition AA1 before switching is 1Hz and the refresh rate after switching is 60Hz, then when the refresh rate of the first display partition AA1 switches from 1Hz to 60Hz, transition frames corresponding to transition refresh rates of 12Hz, 15Hz, 20Hz, 24Hz, 30Hz, and 40Hz are sequentially inserted. The brightness of the display screen corresponding to the transition frames at each transition refresh rate gradually changes (e.g., increases or decreases), which helps improve the display condition caused by the brightness difference at the partition boundary position when the first display partition AA1 switches from 1Hz to 60Hz. Conversely, if the refresh rate of the first display partition AA1 before switching is 60Hz and the refresh rate after switching is 1Hz, then when the refresh rate of the first display partition AA1 switches from 60Hz to 1Hz, transition frames corresponding to transition refresh rates of 40Hz, 30Hz, 24Hz, 20Hz, 15Hz, and 12Hz are sequentially inserted. The brightness of the display screen corresponding to the transition frames at each transition refresh rate gradually decreases. The number and gradient of transition refresh rates can be set as needed.

[0048] Continuing to refer to Figures 1 and 2, the driving circuit 12 includes a scanning circuit 100, a gating module 200, and a gating signal line SE1, wherein the scanning circuit 100 includes a multi-stage shift unit 10. The carry signal output terminal CR of the current stage shift unit 10 (in some embodiments, it can also be multiplexed as the output terminal O1) is connected to the input terminal IN of the next stage shift unit 10. The shift unit 10 is used to output the scanning signal step by step according to the first clock signal and / or the second clock signal. Exemplarily, in a plurality of cascaded shift units 10, the first clock signal SCK2 connected to the odd-stage shift unit 10 and the second clock signal SCK1 connected to the even-stage shift unit 10 are both provided by the second clock signal line CLK2, and the second clock signal SCK1 connected to the odd-stage shift unit 10 and the first clock signal SCK2 connected to the even-stage shift unit 10 are both provided by the first clock signal line CLK1. For example, in two adjacent stages of shift units 10, the first clock signal terminal CK2 of the shift unit 10 of the current stage is connected to the first clock signal line CLK1, and the second clock signal terminal CK1 is connected to the second clock signal line CLK2; the first clock signal terminal CK2 of the shift unit 10 of the next stage is connected to the second clock signal line CLK2, and the second clock signal terminal CK1 is connected to the first clock signal line CLK1, so as to realize the shift output of the scanning circuit 100.

[0049] Optionally, the output end of the scanning circuit 100 is connected to a gating module 200. For example, the gating module 200 includes multiple gating units 20. The output end O1 of each shift unit 10 is connected to a gating unit 20. The control end of the gating unit 20 is connected to a gating signal line SE1. Each gating unit 20 can be connected to the same gating signal line SE1. The output end O2 of the gating unit 20 is connected to the scanning line GL1 of the corresponding row, that is, to the pixel circuit PX of the corresponding row. The gating unit 20 is used to select whether the scanning signal output by the shift unit 10 of the corresponding stage is transmitted to the corresponding scanning line GL1. Optionally, the gating unit 20 may include a logic gate circuit.

[0050] Optionally, the gating unit 20 may include a first transistor and a second transistor, the first end of the first transistor being connected to the output end O1 of the corresponding shift unit 10, the second end of the first transistor being connected to the second end of the second transistor, and the first end of the second transistor being connected to a first power signal line (the voltage of which may be an invalid level of the scan signal). The control end of the first transistor and the control end of the second transistor may be connected to the same gating signal line, and the channel type of the first transistor and the second transistor may be the same. The control end of the first transistor and the control end of the second transistor may be connected to different gating signal lines, and the channel type of the first transistor and the second transistor is different. The first transistor is turned on and the second transistor is turned off, so that the scan signal output by the shift unit 10 can be transmitted to the corresponding pixel circuit PX. The first transistor is turned off and the second transistor is turned on, so that the scan signal output by the shift unit 10 cannot be transmitted to the corresponding pixel circuit PX.

[0051] Optionally, the gating unit 20 may include a cascade control switch for controlling whether the carry signal outputted from the carry signal output terminal of the preceding shift unit 10 is outputted to the input terminal of the succeeding shift unit 10, thereby preventing the succeeding shift unit 10 from generating a scan signal. The cascade control switch may be connected between the carry signal output terminal of the preceding shift unit 10 and the input terminal of the succeeding shift unit 10 of two adjacent shift units 10. The specific structure of the gating unit 20 may be set as required, and is not limited in this embodiment of the present application.

[0052] In this embodiment, the multiple transition frames include a first-type refresh frame and a second-type refresh frame. The gating module 200 is configured to be turned on or off in response to a signal on the gating signal line SE1. The display area AA of the display panel 11 includes at least a first display subarea AA1 and a second display subarea AA2. The gating module 200 is configured to, in response to a signal on the gating signal line SE1, prevent the shift unit 10 from outputting a scan signal to the pixel circuit PX corresponding to the first display subarea AA1 during the first-type refresh frame. Preventing the shift unit 10 from outputting a scan signal to the corresponding pixel circuit PX may include: the shift unit generates a scan signal, but the scan signal is blocked by the gating module 200 (e.g., comprising a logic gate circuit) in a turned-off state and cannot be transmitted to the corresponding pixel circuit PX; or the shift unit 10 is unable to generate a scan signal under the action of the gating module 200 (e.g., comprising a cascade control switch) in a turned-off state, and thus no scan signal is transmitted to the corresponding pixel circuit PX.

[0053] The gating module 200 is configured to, in response to a signal on the gating signal line SE1, cause the shift unit 10 to output a scan signal to the pixel circuit PX corresponding to the first display subarea AA1 during a second-type refresh frame. The gating module 200 is in an on state, equivalent to an enabled state, so that the shift unit 10 generates a scan signal and transmits it to the pixel circuit PX corresponding to the first display subarea AA1. Causing the shift unit 10 to output a scan signal to the pixel circuit PX corresponding to the first display subarea AA1 includes: the shift unit 10 outputting the scan signal directly to the pixel circuit PX corresponding to the first display subarea AA1; or the shift unit 10 outputs a previous scan signal, which, after passing through the gating module 200, is converted into a final scan signal, which is then transmitted to the pixel circuit PX corresponding to the first display subarea AA1.

[0054] In this embodiment, during the refresh rate switching process of the first display area AA1, first type refresh frames are inserted between multiple second type refresh frames, and the number of first type refresh frames between two adjacent second type refresh frames gradually increases or decreases.

[0055] The refresh frequency of the first display partition AA1 before switching is greater than the refresh frequency after switching. During the process of switching the refresh frequency of the first display partition AA1, the number of first-type refresh frames inserted between two adjacent second-type refresh frames gradually increases; the refresh frequency of the first display partition AA1 gradually decreases. For example, the refresh frequency of the first display partition AA1 before switching is 60Hz, and the refresh frequency after switching is 1Hz. Then, during the process of switching the refresh frequency of the first display partition AA1, transition frames corresponding to transition refresh frequencies of 40Hz, 30Hz, 24Hz, 20Hz, 15Hz, and 12Hz can be inserted in sequence. Since the first display partition AA1 is not refreshed in the first-type refresh frame, the number of first-type refresh frames in the multiple transition frames increases in sequence to reduce the refresh frequency of the first display partition AA1, thereby meeting the refresh frequency requirements of the first display partition AA1 and the second display partition AA2.

[0056] Optionally, in at least two transition frames, the pixel circuits corresponding to the adjacent boundaries of the first display partition AA1 and the second display partition AA2 are located in different rows. In the aforementioned multiple transition frames, the pixel circuits corresponding to the adjacent boundaries of the first display partition AA1 and the second display partition AA2 may be located in different rows, or the pixel circuits corresponding to the adjacent boundaries of the first display partition AA1 and the second display partition AA2 may be located in different rows in only some of the multiple transition frames.

[0057] Optionally, in at least two first-type refresh frames, the pixel circuits corresponding to the adjacent boundaries between the first display subarea AA1 and the second display subarea AA2 are located in different rows. Optionally, in at least two second-type refresh frames, the pixel circuits corresponding to the adjacent boundaries between the first display subarea AA1 and the second display subarea AA2 are located in different rows. Optionally, in at least one first-type refresh frame and at least one second-type refresh frame, the pixel circuits corresponding to the adjacent boundaries between the first display subarea AA1 and the second display subarea AA2 are located in different rows.

[0058] Specifically, in at least two transition frames, the row position of the pixel circuit corresponding to the adjacent boundary between the first display partition AA1 and the second display partition AA2 can be changed in an increasing row number manner. For example, when the refresh rate of the first display partition AA1 is switched from 60 Hz to 1 Hz, in the transition frame with a transition refresh rate of 40 Hz, the row position of the pixel circuit corresponding to the adjacent boundary between the first display partition AA1 and the second display partition AA2 is the Nth row. In the transition frame with a transition refresh rate of 30 Hz, the row position of the pixel circuit corresponding to the adjacent boundary between the first display partition AA1 and the second display partition AA2 is the N+2th row. In the transition frame with a transition refresh rate of 24 Hz, In the transition frame with a transition refresh frequency of 20 Hz, the row position of the pixel circuit corresponding to the adjacent boundary of the first display partition AA1 and the second display partition AA2 is the N+4th row. In the transition frame with a transition refresh frequency of 15 Hz, the row position of the pixel circuit corresponding to the adjacent boundary of the first display partition AA1 and the second display partition AA2 is the N+8th row. In the transition frame with a transition refresh frequency of 12 Hz, the row position of the pixel circuit corresponding to the adjacent boundary of the first display partition AA1 and the second display partition AA2 is the N+10th row.

[0059] Alternatively, the row position of the pixel circuit corresponding to the adjacent boundary between the first display partition AA1 and the second display partition AA2 can be changed in a manner of decreasing row numbers. For example, when the refresh rate of the first display partition AA1 switches from 60 Hz to 1 Hz, in a transition frame with a transition refresh rate of 40 Hz, the row position of the pixel circuit corresponding to the adjacent boundary between the first display partition AA1 and the second display partition AA2 is the Nth row; in a transition frame with a transition refresh rate of 30 Hz, the row position of the pixel circuit corresponding to the adjacent boundary between the first display partition AA1 and the second display partition AA2 is the N-2th row; in a transition frame with a transition refresh rate of 24 Hz, the row position of the pixel circuit corresponding to the adjacent boundary between the first display partition AA1 and the second display partition AA2 is the N-2th row. The row position of the circuit is the N-4th row. In the transition frame with a transition refresh frequency of 20Hz, the row position of the pixel circuit corresponding to the adjacent boundary of the first display partition AA1 and the second display partition AA2 is the N-6th row. In the transition frame with a transition refresh frequency of 15Hz, the row position of the pixel circuit corresponding to the adjacent boundary of the first display partition AA1 and the second display partition AA2 is the N-8th row. In the transition frame with a transition refresh frequency of 12Hz, the row position of the pixel circuit corresponding to the adjacent boundary of the first display partition AA1 and the second display partition AA2 is the N-10th row.

[0060] Alternatively, the row positions of the pixel circuits corresponding to the adjacent boundaries between the first display area AA1 and the second display area AA2 may be changed in a manner that the row number first increases and then decreases, or in a manner that the row number first decreases and then increases. For example, when the refresh rate of the first display partition AA1 switches from 60 Hz to 1 Hz, in a transition frame with a transition refresh rate of 40 Hz, the row position of the pixel circuit corresponding to the adjacent boundary between the first display partition AA1 and the second display partition AA2 is the Nth row; in a transition frame with a transition refresh rate of 30 Hz, the row position of the pixel circuit corresponding to the adjacent boundary between the first display partition AA1 and the second display partition AA2 is the N-2th row; in a transition frame with a transition refresh rate of 24 Hz, the row position of the pixel circuit corresponding to the adjacent boundary between the first display partition AA1 and the second display partition AA2 is the N-4th row; in a transition frame with a transition refresh rate of 20 Hz, the row position of the pixel circuit corresponding to the adjacent boundary between the first display partition AA1 and the second display partition AA2 is the N-6th row; in a transition frame with a transition refresh rate of 15 Hz, the row position of the pixel circuit corresponding to the adjacent boundary between the first display partition AA1 and the second display partition AA2 is the N-4th row; and in a transition frame with a transition refresh rate of 12 Hz, the row position of the pixel circuit corresponding to the adjacent boundary between the first display partition AA1 and the second display partition AA2 is the N-2th row.

[0061] Alternatively, the positions of the rows of pixel circuits corresponding to the adjacent boundaries between the first display area AA1 and the second display area AA2 may be randomly changed, and the change may be set according to actual needs. For example, when the refresh rate of the first display partition AA1 switches from 60 Hz to 1 Hz, in a transition frame with a transition refresh rate of 40 Hz, the row position of the pixel circuit corresponding to the adjacent boundary between the first display partition AA1 and the second display partition AA2 is the Nth row; in a transition frame with a transition refresh rate of 30 Hz, the row position of the pixel circuit corresponding to the adjacent boundary between the first display partition AA1 and the second display partition AA2 is the N-2th row; in a transition frame with a transition refresh rate of 24 Hz, the row position of the pixel circuit corresponding to the adjacent boundary between the first display partition AA1 and the second display partition AA2 is the N-6th row; in a transition frame with a transition refresh rate of 20 Hz, the row position of the pixel circuit corresponding to the adjacent boundary between the first display partition AA1 and the second display partition AA2 is the N-4th row; in a transition frame with a transition refresh rate of 15 Hz, the row position of the pixel circuit corresponding to the adjacent boundary between the first display partition AA1 and the second display partition AA2 is the Nth row; and in a transition frame with a transition refresh rate of 12 Hz, the row position of the pixel circuit corresponding to the adjacent boundary between the first display partition AA1 and the second display partition AA2 is the N-2th row.

[0062] In some embodiments, during the refresh rate switching process of the first display area AA1, the row positions of the pixel circuits corresponding to the adjacent boundaries between the first display area AA1 and the second display area AA2 are changed by a fixed number of rows each time. For example, during the refresh rate switching process of the first display area AA1, multiple transition frames are set, and in each transition frame, the row positions of the pixel circuits corresponding to the adjacent boundaries between the display areas are changed by a fixed number of rows, or by a fixed number of multiples of 2.

[0063] Optionally, during the refresh frequency switching process of the first display partition AA1, multiple transition frames are set. In the multiple transition frames, the position of the row of pixel circuits corresponding to the adjacent boundaries between the first display partition AA1 and the second display partition AA2 changes, and the refresh frequency of the transition frames is the refresh frequency before the switch or the refresh frequency after the switch. For example, if the refresh frequency of the first display partition AA1 before the switch is 1 Hz and the refresh frequency after the switch is 60 Hz, then when the refresh frequency of the first display partition AA1 switches from 1 Hz to 60 Hz, a display cycle of the first display partition AA1 at the refresh frequency of 1 Hz may include 120 frames, for example, corresponding to 119 first-type refresh frames and 1 second-type refresh frame. When the first display partition AA1 switches its refresh frequency, at least some of the 120 frames of the last display cycle in which the refresh frequency before the switch was 1 Hz are transition frames. In at least some of the transition frames, the position of the row of pixel circuits corresponding to the adjacent boundaries between the first display partition AA1 and the second display partition AA2 changes. And / or, when the refresh rate of the first display partition AA1 switches from 1 Hz to 60 Hz, a display cycle of the first display partition AA1 at a refresh rate of 60 Hz may include two frames, for example, corresponding to one first-type refresh frame and one second-type refresh frame. When the first display partition AA1 switches its refresh rate, the two frames of the first display cycle and the two frames of the second display cycle after the switch to a refresh rate of 60 Hz are transition frames. In the multiple transition frames, the positions of the rows of pixel circuits corresponding to the adjacent boundaries of the first display partition AA1 and the second display partition AA2 vary. And / or, at least a portion of the 120 frames of the last display cycle before the switch to a refresh rate of 1 Hz are transition frames, and at least a portion of the two frames of the first display cycle after the switch to a refresh rate of 60 Hz are transition frames. In the multiple transition frames, the positions of the rows of pixel circuits corresponding to the adjacent boundaries of the first display partition AA1 and the second display partition AA2 vary (i.e., are different).

[0064] Optionally, during the process of switching the refresh frequency of the first display partition AA1, multiple transition frames are set, and the refresh frequency of the first display partition AA1 in the multiple transition frames is between the refresh frequency before the switching of the first display partition AA1 and the refresh frequency after the switching. The refresh frequency gradually increases or decreases, and the position of the pixel circuit corresponding to the adjacent boundary of the first display partition AA1 and the second display partition AA2 is fixed.

[0065] As an optional technical solution provided by this embodiment, during the refresh frequency switching process of the first display subarea AA1, the row positions of the pixel circuits corresponding to the adjacent boundaries between the first display subarea AA1 and the second display subarea AA2 vary with the refresh frequency of the first display subarea AA1, for example, varying by a fixed number of rows. In other words, during the refresh frequency switching process of the first display subarea AA1, while controlling the transition refresh frequencies of multiple transition frames, the row positions of the pixel circuits corresponding to the adjacent boundaries of the display subareas are also controlled to vary synchronously with the refresh frequency of the transition frames, and each variation may vary by a fixed number of rows or a non-fixed number of rows.

[0066] In this embodiment, the purpose of setting the row positions of the pixel circuits corresponding to the adjacent boundaries of the first display partition AA1 and the second display partition AA2 to change according to a fixed number of rows is to ensure the uniformity of the position changes of the dividing lines of the display partitions in multiple transition frames, so as to improve the uniformity of the display brightness at the dividing line positions, which is conducive to improving the color cast at the dividing line.

[0067] Alternatively, with continued reference to FIG. 2 , in another embodiment, the gating module 200, in response to the signal on the gating signal line SE1, causes the shift unit 10 to output a scan signal to the pixel circuits of the second display partition AA2 during a first-type refresh frame, and prevents the shift unit 10 from outputting a scan signal to the pixel circuits of the first display partition AA1; and causes the shift unit 10 to output a scan signal to the pixel circuits of the first display partition AA1 and the second display partition AA2 during a second-type refresh frame. In other words, the second display partition AA2 is in a refresh state during both the first-type and second-type refresh frames, while the first display partition AA1 is refreshed only during the second-type refresh frame. This means that the second display partition AA2 is in a high refresh state, while the first display partition AA1 is in a low refresh state, and the refresh frequency of the first display partition AA1 is lower than that of the second display partition AA2.

[0068] Optionally, in each of the above technical solutions, the refresh frequency may be switched in the second display area AA2 , or the refresh frequency may be switched in both the first display area AA1 and the second display area AA2 .

[0069] Optionally, in any two transition frames, the change in the position of the row of pixel circuits PX corresponding to the adjacent boundary between the first display partition AA1 and the second display partition AA2 is less than or equal to 20 rows, so as to ensure that the normal human eye is subjectively imperceptible to the change in the position of the dividing line while improving the abnormal brightness of the dividing line during frequency switching, so as to prevent the human eye from perceiving the change in the position of the dividing line due to excessive change in the position of the dividing line during the refresh frequency switching. Optionally, in any two transition frames, the change in the position of the row of pixel circuits PX corresponding to the adjacent boundary between the first display partition AA1 and the second display partition AA2 is less than or equal to 10 rows. During the frequency switching process, the range of change in the position of the dividing line cannot be too large or too small, otherwise it will not be possible to balance the improvement of the abnormal brightness of the dividing line and the visual effect of the change in the position of the dividing line to the human eye.

[0070] Optionally, in multiple first-type refresh frames (e.g., partial refresh frames) between two adjacent second-type refresh frames (e.g., full refresh frames), the positions of the rows of pixel circuits corresponding to the adjacent boundaries of the first display partition AA1 and the second display partition AA2 are the same or different. That is, in transition frames corresponding to the same refresh frequency, for multiple inserted first-type refresh frames, the positions of the rows of pixel circuits corresponding to the adjacent boundaries of the first display partition AA1 and the second display partition AA2 can be the same, that is, in multiple first-type refresh frames, the positions of the boundaries of the display partitions are not changed; or, the positions of the rows of pixel circuits corresponding to the adjacent boundaries of the first display partition AA1 and the second display partition AA2 can be different, that is, in multiple first-type refresh frames, the positions of the boundaries of the display partitions are changed while inserting the first-type refresh frames, so as to further improve the situation where the positions of the boundaries are displayed abnormally.

[0071] Of course, in other embodiments, the refresh rate of the first display partition AA1 before switching is lower than the refresh rate after switching. During the process of switching the refresh rate of the first display partition AA1, the number of first-type refresh frames inserted between two adjacent second-type refresh frames gradually decreases, and the refresh rate of the first display partition AA1 gradually increases. In this embodiment, the specific control method of the display panel is opposite to the control method described above in which the refresh rate of the first display partition AA1 before switching is higher than the refresh rate after switching. For details, please refer to the relevant description in the above embodiment and will not be repeated here.

[0072] FIG4 is a schematic diagram of the structure of a pixel circuit provided by an embodiment of the present application. Referring to FIG4 , the pixel circuit includes a driver module, a data write module, and a threshold compensation module. The data write module is connected between a data line and a first end of the driver module. The control end of the data write module is electrically connected to a second driver circuit. The threshold compensation module is connected between a second end and a control end of the driver module. The control end of the threshold compensation module is electrically connected to the first driver circuit. The effective level of the scanning signal SN1 output by the first driver circuit can be the conduction level of the compensation module. The effective level of the scanning signal SP1 output by the second driver circuit can be the conduction level of the data write module.

[0073] Optionally, the pixel circuit further includes a first initialization module, the first initialization module being connected between the first initialization signal line Vref2 and the control terminal of the driving module, the control terminal of the first initialization module being electrically connected to the third driving circuit. The effective level of the scanning signal SN2 output by the third driving circuit may be the on-level of the first initialization module.

[0074] Specifically, the driving module includes a driving transistor M3 , the data writing module includes a data writing transistor M4 , the threshold compensation module includes a threshold compensation transistor M5 , and the first initialization module includes a third initialization transistor M6 .

[0075] Optionally, the data writing module includes a P-type transistor. Optionally, the threshold compensation module includes an N-type transistor. Optionally, the first initialization module includes an N-type transistor.

[0076] Optionally, the pixel circuit further includes part or all of a first initialization transistor M1, a second initialization transistor M2, a storage capacitor C, a first emission control transistor M7, and a second emission control transistor M8. The first initialization transistor M1 is connected between the second initialization signal line Vref1 and the first electrode of the light-emitting diode D1. The second initialization transistor M2 is connected between the third initialization signal line Vcom and the first electrode S (or second electrode D) of the third transistor M3. The storage capacitor C is connected between the first power line L1 and the gate G of the driving transistor M3. The first emission control transistor M7 is connected between the first power line L1 and the first electrode S of the driving transistor M3. The second emission control transistor M8 is connected between the second electrode D of the driving transistor M3 and the first electrode of the light-emitting diode D1. The second electrode of the light-emitting diode D1 is connected to the second power line L2. Optionally, the gate of the first initialization transistor M1 and the gate of the second initialization transistor M2 are connected to a fourth driving circuit. The effective level of the scanning signal SP2 output by the fourth driving circuit can be the on-state level of the first initialization transistor M1 and the second initialization transistor M2, such as a low level. The gates of the first and second emission control transistors M7 and M8 may be connected to the fifth driving circuit. The effective level of the scanning signal EM output by the fifth driving circuit may be the conduction level of the first and second emission control transistors M7 and M8, such as a high level.

[0077] In FIG. 4 , VDD represents the power supply potential of the first power supply line L1 , and VSS represents the power supply potential of the second power supply line L2 .

[0078] Optionally, the scan line GL1 can be connected to the gate of the data write transistor M4 in the pixel circuit PX to control the switching state of the data write transistor M4. During the display process of the image, a scan signal SP1 is provided to the scan line GL1 in each row of the pixel circuit PX in a row-by-row scanning manner. During the duration of the on-pulse of the corresponding scan signal SP1 (the duration of the active level of the scan signal SP1), the data voltage Vdata on the data line DL is transmitted to the corresponding pixel circuit PX, implementing data writing and refreshing the sub-pixels in the display area AA.

[0079] Optionally, the threshold compensation transistor M5 is an N-type transistor. Optionally, the third initialization transistor M6 is an N-type transistor.

[0080] The technical solution provided in this embodiment is also applicable to panel structures with more than two display partitions. Figure 5 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application. Referring to Figure 5, based on the above technical solutions, the display area AA optionally further includes a third display partition AA3, and the first display partition AA1, the second display partition AA2, and the third display partition AA3 are adjacent to each other in sequence. The refresh rates of adjacent display partitions in the first display partition AA1, the second display partition AA2, and the third display partition AA3 are different.

[0081] Optionally, during the refresh rate switching process of the third display subarea AA3, multiple transition frames are provided, wherein the refresh rate of the third display subarea AA3 in the multiple transition frames is between the refresh rate before and after the switching of the third display subarea AA3; and / or, in the multiple transition frames, the pixel circuits corresponding to the adjacent boundaries between the third display subarea AA3 and the second display subarea AA2 are located at different positions, for example, they are shifted. The principles of the refresh rate switching process of the third display subarea AA3 are the same or similar to those of the first display subarea AA1, and are not further described here.

[0082] The positions of the pixel circuits corresponding to the adjacent boundaries of the first, second, and third display subareas AA1, AA2, and AA3 are adjustable to significantly change the area and / or position of at least one display subarea, for example, upon receiving a user instruction to adjust the size or position of a display subarea window. The first, second, and third display subareas AA1, AA2, and AA3 can be arranged along the Y direction.

[0083] Optionally, the refresh frequency of the first display area AA1 is lower than the refresh frequency of the second display area AA2, and the refresh frequency of the third display area AA3 is lower than the refresh frequency of the second display area AA2. Optionally, the refresh frequencies of the first display area AA1 and the third display area AA3 are the same. That is, the first display area AA1 and the third display area AA3 are low-frequency areas, and the second display area AA2 is high-frequency area.

[0084] During the refresh frequency switching process of the first display partition AA1 and the third display partition AA3, the selection module 200 responds to the signal on the selection signal line SE1, and in the first type of refresh frame, enables the shift unit 10 to output the scan signal to the pixel circuit PX of the second display partition AA2, and does not enable the shift unit 10 to output the scan signal to the pixel circuit PX of the first display partition AA1 and the third display partition AA3; in the second type of refresh frame, enables the shift unit 10 to output the scan signal to the pixel circuit PX of the first display partition AA1, the second display partition AA2 and the third display partition AA3.

[0085] Optionally, the refresh frequencies of the first display partition and the third display partition are the same, and the refresh frequency of the first display partition is greater than the refresh frequency of the second display partition. The display driving method further includes:

[0086] The selection module responds to the signal on the selection signal line. In the first type of refresh frame, the shift unit is not enabled to output the scan signal to the pixel circuit of the second display partition, but is enabled to output the scan signal to the pixel circuits of the first display partition and the third display partition; in the second type of refresh frame, the shift unit is enabled to output the scan signal to the pixel circuits of the first display partition, the second display partition and the third display partition.

[0087] Figure 6 is a schematic diagram of the driving timing of a pixel circuit provided in an embodiment of the present application, which is applicable to the pixel circuit shown in Figure 4. Referring to Figure 6, a display cycle of pixel circuit PX includes a write frame and a hold frame. During a write frame, the shift unit 10 provides a scan signal SP1 to pixel circuit PX, and data voltages are written to pixel circuit PX. During a hold frame, the shift unit 10 does not provide a scan signal SP1 to pixel circuit PX, and data voltages cannot be written to pixel circuit PX. The refresh rate can be understood as the number of write frames per unit time. For example, if the refresh rate is 120 Hz, the display panel includes 120 frames per second, all of which are write frames. When the refresh rate is reduced to 60 Hz, a hold frame is inserted between two adjacent write frames. Thus, within a second, 60 write frames are included, and the remaining 60 frames are hold frames, thereby reducing the refresh rate to 60 Hz. During the first type of refresh frame, the pixel circuits PX in the first display subarea AA1 operate in the hold frame, while the pixel circuits PX in the second display subarea AA2 operate in the write frame. During the second type refresh frame, it is equivalent to that the pixel circuit PX of the first display partition AA1 operates in a writing frame, and the pixel circuit PX of the second display partition AA2 operates in a writing frame.

[0088] FIG7 is a timing diagram of a strobe signal on a strobe signal line provided in an embodiment of the present application in the time domain, and FIG8 is a timing diagram of another strobe signal on a strobe signal line provided in an embodiment of the present application in the time domain, wherein the timing shown in FIG7 is a separate timing diagram under each transition frame, and FIG8 is a continuous timing diagram under multiple transition frames. FIG7 and FIG8 are explained using the example of the effective level of the strobe signal on the strobe signal line SE1 being a high level. Referring to FIG7 and FIG8, based on the above technical solution, taking the example of the refresh frequency of the first display partition AA1 and the third display partition AA3 before switching being 60 Hz and the refresh frequency of the second display partition AA2 being 120 Hz, the refresh frequency of the first display partition AA1 and the third display partition AA3 after switching is 1 Hz.

[0089] Specifically, during the refresh frequency switching process between the first display partition AA1 and the third display partition AA3 at 60 Hz, during the second type refresh frame F2, the signal on the strobe signal line SE1 is at its own active level when scanning the first display partition AA1, the second display partition AA2, and the third display partition AA3, controlling the strobe unit 20 to be turned on, causing the shift units 10 corresponding to the pixel circuits PX of the first display partition AA1, the second display partition AA2, and the third display partition AA3 to output scan signals to the pixel circuits PX of the first display partition AA1, the second display partition AA2, and the third display partition AA3, thereby writing data to the pixel circuits PX of the first display partition AA1, the second display partition AA2, and the third display partition AA3. During the first type refresh frame F1, the signal on the strobe signal line SE1 is at its own active level when scanning the time period corresponding to the second display partition AA2, controlling the strobe unit 20 to be turned on, causing the shift units 10 corresponding to the pixel circuits PX of the second display partition AA2 to output scan signals to the pixel circuits PX of the second display partition AA2, thereby writing data to the pixel circuits corresponding to the second display partition AA2. The signal on the strobe signal line SE1 is at an inactive level during the scanning period corresponding to the first display subarea AA1 and the third display subarea AA3. This controls the strobe unit 20 to be turned off, preventing the shift unit 10 from outputting a scan signal to the corresponding pixel circuits PX of the first display subarea AA1 and the third display subarea AA3. Consequently, no data is written to the corresponding pixel circuits PX of the first display subarea AA1 and the third display subarea AA3. Therefore, for the first display subarea AA1 and the third display subarea AA3, the first-type refresh frame is a hold frame, and the second-type refresh frame is a write frame. For the second display subarea AA2, both the second-type refresh frame and the first-type refresh frame are write frames.

[0090] At 60Hz, one first-type refresh frame F1 is inserted between two adjacent second-type refresh frames F2. For the first display subarea AA1 and the third display subarea AA3, one second-type refresh frame F2 is a write frame, and one first-type refresh frame F1 is a hold frame. For the second display subarea AA2, one second-type refresh frame F2 and one first-type refresh frame F1 are both write frames. The refresh frequencies of the three display subareas are 60Hz-120Hz-60Hz, respectively.

[0091] At 1 Hz, 119 first-type refresh frames F1 are inserted between two adjacent second-type refresh frames F2. For the first display subarea AA1 and the third display subarea AA3, one second-type refresh frame F2 is a write frame, and all 119 first-type refresh frames F1 are hold frames. For the second display subarea AA2, one second-type refresh frame F2 and 119 first-type refresh frames F1 are write frames.

[0092] During the switching process of the refresh rates of the first display partition AA1 and the third display partition AA3, transition frames corresponding to transition refresh rates of 40 Hz, 30 Hz, 24 Hz, 20 Hz, 15 Hz and 12 Hz are set to gradually switch the refresh rates of the first display partition AA1 and the third display partition AA3 from 60 Hz to 1 Hz.

[0093] In a transition frame with a transition refresh frequency of 40 Hz, two first-type refresh frames F1 are inserted between two adjacent second-type refresh frames F2. In the second-type refresh frame F2, the shift unit 10 is controlled to output scan signals to the pixel circuits PX corresponding to the first display partition AA1, the second display partition AA2, and the third display partition AA3. In each of the two first-type refresh frames F1, the shift unit 10 outputs scan signals to the pixel circuits PX corresponding to the second display partition AA2, and does not output scan signals to the pixel circuits PX corresponding to the first display partition AA1 and the third display partition AA3, thereby achieving a refresh frequency of 40 Hz for the first display partition AA1 and the third display partition AA3. The refresh frequencies of the three display partitions are 40 Hz-120 Hz-40 Hz, respectively. Optionally, during the frequency switching process, at 40 Hz, the position of the boundary between the two first-type refresh frames F1, the first display partition AA1, and the second display partition AA2 may change or remain unchanged.

[0094] In a transition frame with a transition refresh frequency of 30 Hz, three first-type refresh frames F1 are inserted between two adjacent second-type refresh frames F2. In the second-type refresh frames F2, the shift unit 10 is controlled to output scan signals to the pixel circuits PX corresponding to the first display partition AA1, the second display partition AA2, and the third display partition AA3. In each of the three first-type refresh frames F1, the shift unit 10 outputs scan signals to the pixel circuits PX corresponding to the second display partition AA2, and does not output scan signals to the pixel circuits PX corresponding to the first display partition AA1 and the third display partition AA3, thereby achieving a refresh frequency of 30 Hz for the first display partition AA1 and the third display partition AA3. The refresh frequencies of the three display partitions are 30 Hz-120 Hz-30 Hz, respectively. Optionally, during the frequency switching process, at 30 Hz, the position of the boundary between the first display partition AA1 and the second display partition AA2 may change or remain unchanged in at least some of the three first-type refresh frames F1.

[0095] In a transition frame with a transition refresh frequency of 24 Hz, four first-type refresh frames F1 are inserted between two adjacent second-type refresh frames F2. In the second-type refresh frames F2, the shift unit 10 is controlled to output scan signals to the pixel circuits PX corresponding to the first display partition AA1, the second display partition AA2, and the third display partition AA3. In each of the four first-type refresh frames F1, the shift unit 10 outputs scan signals to the pixel circuits PX corresponding to the second display partition AA2, and does not output scan signals to the pixel circuits PX corresponding to the first display partition AA1 and the third display partition AA3, thereby achieving a refresh frequency of 24 Hz for the first display partition AA1 and the third display partition AA3. The refresh frequencies of the three display partitions are 24 Hz-120 Hz-24 Hz, respectively. Optionally, during the frequency switching process, at 24 Hz, the position of the boundary between the first display partition AA1 and the second display partition AA2 changes or remains unchanged in at least some of the four first-type refresh frames F1.

[0096] In a transition frame with a transition refresh frequency of 20 Hz, five first-type refresh frames F1 are inserted between two adjacent second-type refresh frames F2. In the second-type refresh frames F2, the shift unit 10 is controlled to output scan signals to the pixel circuits PX corresponding to the first display partition AA1, the second display partition AA2, and the third display partition AA3. In each of the five first-type refresh frames F1, the shift unit 10 outputs scan signals to the pixel circuits PX corresponding to the second display partition AA2, and does not output scan signals to the pixel circuits PX corresponding to the first display partition AA1 and the third display partition AA3, thereby achieving a refresh frequency of 20 Hz for the first display partition AA1 and the third display partition AA3. The refresh frequencies of the three display partitions are 20 Hz-120 Hz-20 Hz, respectively. Optionally, during the frequency switching process, at 20 Hz, the position of the boundary between the first display partition AA1 and the second display partition AA2 changes or remains unchanged in at least some of the five first-type refresh frames F1.

[0097] In a transition frame with a transition refresh frequency of 15 Hz, seven first-type refresh frames F1 are inserted between two adjacent second-type refresh frames F2. In the second-type refresh frames F2, the shift unit 10 is controlled to output scan signals to the pixel circuits PX corresponding to the first display partition AA1, the second display partition AA2, and the third display partition AA3. In each of the seven first-type refresh frames F1, the shift unit 10 outputs scan signals to the pixel circuits PX corresponding to the second display partition AA2, and does not output scan signals to the pixel circuits PX corresponding to the first display partition AA1 and the third display partition AA3, thereby achieving a refresh frequency of 15 Hz for the first display partition AA1 and the third display partition AA3. The refresh frequencies of the three display partitions are 15 Hz-120 Hz-15 Hz, respectively. Optionally, during the frequency switching process, at 15 Hz, the position of the boundary between the first display partition AA1 and the second display partition AA2 changes or remains unchanged in at least some of the seven first-type refresh frames F1.

[0098] In a transition frame with a transition refresh frequency of 12 Hz, nine first-type refresh frames F1 are inserted between two adjacent second-type refresh frames F2. In the second-type refresh frames F2, the shift unit 10 is controlled to output scan signals to the pixel circuits PX corresponding to the first display partition AA1, the second display partition AA2, and the third display partition AA3. In each of the nine first-type refresh frames F1, the shift unit 10 outputs scan signals to the pixel circuits PX corresponding to the second display partition AA2, and does not output scan signals to the pixel circuits PX corresponding to the first display partition AA1 and the third display partition AA3, thereby achieving a refresh frequency of 12 Hz for the first display partition AA1 and the third display partition AA3. The refresh frequencies of the three display partitions are 12 Hz-120 Hz-12 Hz, respectively. Optionally, during the frequency switching process, at 12 Hz, the position of the boundary between the first display partition AA1 and the second display partition AA2 changes or remains unchanged in at least some of the nine first-type refresh frames F1.

[0099] In a transition frame with a refresh frequency of 1 Hz, 119 first-type refresh frames F1 are inserted between two adjacent second-type refresh frames F2. In the second-type refresh frames F2, the shift unit 10 is controlled to output a scan signal to the pixel circuits PX corresponding to the first display partition AA1, the second display partition AA2, and the third display partition AA3. In each of the 119 first-type refresh frames F1, the shift unit 10 is controlled to output a scan signal to the pixel circuits PX corresponding to the second display partition AA2, and the shift unit 10 is not caused to output a scan signal to the pixel circuits PX corresponding to the first display partition AA1 and the third display partition AA3, thereby achieving a refresh frequency of 1 Hz for the first display partition AA1 and the third display partition AA3. The refresh frequencies of the three display partitions are 1 Hz-120 Hz-1 Hz, respectively. Optionally, during the frequency switching process, at 1 Hz, the position of the boundary between the first display partition AA1 and the second display partition AA2 may change or remain unchanged in at least some of the 119 first-type refresh frames F1.

[0100] In this embodiment, in a plurality of transition frames, the number of first-type refresh frames F1 inserted between two adjacent second-type refresh frames F2 gradually increases.

[0101] Figure 9 is a structural schematic diagram of a display panel corresponding to a display panel spatial domain adjustment method provided in an embodiment of the present application. Referring to Figure 9, on the basis of the above-mentioned technical solution, optionally, during the switching process of the refresh frequency of the first display partition AA1 and the third display partition AA3, under the corresponding transition frame, the row position of the pixel circuit PX corresponding to the dividing line between adjacent display partitions is adjusted so that the row position of the pixel circuit PX corresponding to the dividing line between adjacent display partitions under different transition frames is different.

[0102] In conjunction with Figures 5 and 9 , before the refresh rate of the display panel is switched, before the refresh rate of at least one display partition (e.g., one or more of the first display partition AA1, the second display partition AA2, and the third display partition AA3) is switched, or after the refresh rate is switched, the first display partition AA1 corresponds to the pixel circuits PX in rows 1 to W, the second display partition AA2 corresponds to the pixel circuits PX in rows W+1 to J, and the third display partition AA3 corresponds to the pixel circuits PX in rows J+1 to Z, where W, J, and Z are all positive integers greater than 1 and not equal to each other. W, J, and Z increase in sequence. During the refresh frequency switching process between the first display area AA1 and the third display area AA3, the gating module 200, in response to the signal on the gating signal line SE1, prevents the shift unit 10 from outputting scan signals to the pixel circuits PX in rows 1 to W+P*n and rows 1 to Z of the pixel circuits PX, but instead causes the shift unit 10 to output scan signals to rows 1 to Z of the pixel circuits PX in rows 1 to W+P*n+1. During at least one second-type refresh frame, the shift unit 10 outputs scan signals to the pixel circuits PX in rows 1 to Z. Wherein, P is a positive integer, such as a fixed step size, and n is a positive or negative integer. During the refresh frequency switching process between the first display area AA1 and the third display area AA3, the values ​​of P*n in at least two first-type refresh frames F1 are different.

[0103] For example, before the refresh frequencies of the first display partition AA1 and the third display partition AA3 are switched, when the refresh frequency is 60 Hz, the row positions of the pixel circuits PX corresponding to the first display partition AA1 are 1 to 786H (H represents: row), and the row positions of the pixel circuits PX corresponding to the second display partition AA2 are 787 to 2014H. The row number after 2014H is the row position of the pixel circuits PX corresponding to the third display partition AA3.

[0104] Specifically, in a transition frame with a transition refresh frequency of 40 Hz, during a first-type refresh frame F1, the shift unit 10 outputs scan signals to pixel circuits 789 to 2012H, but does not output scan signals to pixel circuits 1 to 788H (786+2*1=788) and pixel circuits 2013 (2015-2*1=2013) to ZH (for example, Z may be 2800). During a second-type refresh frame F2, the shift unit 10 outputs scan signals to pixel circuits 1 to ZH.

[0105] In a transition frame with a transition refresh frequency of 30 Hz, during a first-type refresh frame F1, the shift unit 10 outputs scan signals to pixel circuits 791 to 2010H, but does not output scan signals to pixel circuits 1 to 790H (788+2*1=790) and pixel circuits 2011 (2013-2*1=2011) to ZH (for example, Z may be 2800). During a second-type refresh frame F2, the shift unit 10 outputs scan signals to pixel circuits 1 to ZH.

[0106] In a transition frame with a transition refresh frequency of 24 Hz, during a first-type refresh frame F1, the shift unit 10 outputs scan signals to pixel circuits 793 to 2008H, but does not output scan signals to pixel circuits 1 to 792H (790+2*1=792) and pixel circuits 2009 (2011-2*1=2009) to ZH (for example, Z may be 2800). During a second-type refresh frame F2, the shift unit 10 outputs scan signals to pixel circuits 1 to ZH.

[0107] In a transition frame with a transition refresh frequency of 20 Hz, during a first-type refresh frame F1, the shift unit 10 outputs scan signals to the 795-2006H pixel circuits PX, but does not output scan signals to the 1st-794th (792+2*1=794)th pixel circuits PX and the 2007th (2009-2*1=2007)-ZH pixel circuits PX (for example, Z may be 2800). During a second-type refresh frame F2, the shift unit 10 outputs scan signals to the 1st-ZH pixel circuits PX.

[0108] In a transition frame with a transition refresh frequency of 15 Hz, during a first-type refresh frame F1, the shift unit 10 outputs scan signals to pixel circuits 797 to 2004H, but does not output scan signals to pixel circuits 1 to 796H (794+2*1=796) and pixel circuits 2005 (2007-2*1=2005) to ZH (for example, Z may be 2800). During a second-type refresh frame F2, the shift unit 10 outputs scan signals to pixel circuits 1 to ZH.

[0109] In a transition frame with a transition refresh frequency of 12 Hz, during a first-type refresh frame F1, the shift unit 10 outputs scan signals to pixel circuits 799 to 2002H, but does not output scan signals to pixel circuits 1 to 798H (796+2*1=798) and pixel circuits 2003 (2005-2*1=2003) to ZH (for example, Z may be 2800). During a second-type refresh frame F1, the shift unit 10 outputs scan signals to pixel circuits 1 to ZH.

[0110] In a transition frame with a refresh frequency of 1 Hz, during a first-type refresh frame F1, the shift unit 10 outputs scan signals to the 801-2000H pixel circuits PX, but does not output scan signals to the 1st-800H (798+2*1=800) pixel circuits PX and the 2001st (2003-2*1=2001)-ZH pixel circuits PX (for example, Z may be 2800). During a second-type refresh frame F2, the shift unit 10 outputs scan signals to the 1st-ZH pixel circuits PX.

[0111] To facilitate understanding of the present solution, FIG10 is a schematic diagram of a driving timing sequence of a scan signal during a frequency switching process provided by an embodiment of the present application. Taking the refresh frequency of 1 Hz in FIG9 as an example, during a second-type refresh frame F2, the select signal CSP1 on the select signal line SE1 in the second drive circuit is at an active level, such as a low level. Scan signals SP1 (i.e., SP1-1 to SP1-2800) are output to the pixel circuits corresponding to the first display area AA1, the second display area AA2, and the third display area AA3 in rows 1 to 2800. The scan signal SP1 is written to the pixel circuits PX corresponding to the first display area AA1, the second display area AA2, and the third display area AA3. During the first-type refresh frame F1, the select signal CSP1 on the select signal line SE1 jumps to an active level at time tp corresponding to the scanning of row 801, and jumps to an inactive level, such as a high level, at time tp' corresponding to the scanning of row 2000. Consequently, the shift unit 10 outputs scan signals to the pixel circuits PX in rows 801 to 2000.

[0112] FIG11 is a schematic diagram of another drive timing sequence for a scan signal during a frequency switching process according to an embodiment of the present application. Taking the refresh frequency of 1 Hz shown in FIG9 as an example, during the second refresh frame F2, the select signal CSN1 on the select signal line SE1 in the first drive circuit is at an active level, such as a high level. Scan signals SN1 (i.e., SN1-1 to SN1-2800) are output to the pixel circuits PX corresponding to the first display partition AA1, the second display partition AA2, and the third display partition AA3, respectively. The scan signal SN1 is written to the pixel circuits PX corresponding to the first display partition AA1, the second display partition AA2, and the third display partition AA3. During the first refresh frame F1, the select signal CSN1 on the select signal line SE1 jumps to an active level at time tn corresponding to the scanning of row 801, and jumps to an inactive level, such as a low level, at time tn' corresponding to the scanning of row 2000. Consequently, the shift unit 10 outputs scan signals to the pixel circuits PX in rows 801 to 2000.

[0113] Continuing to refer to FIG10 and FIG11, during the refresh frequency switching process of the first display subarea AA1, in the first type refresh frame F1, the pulse width TP1 (or TN1) of the signal on the strobe signal line SE1 at its own effective level is smaller than the pulse width TP2 (or TN2) of the signal on the strobe signal line SE1 at its own effective level in the second type refresh frame F2. That is, TP1 <TP2,TN1<TN2。

[0114] Optionally, with continued reference to FIG. 10 , during the refresh frequency switching process of the first display subarea AA1, in at least two first-type refresh frames F1, the transition time tp (or tn) of the signal CSP1 (or CSN1) on the selection signal line SE1 in the first-type refresh frame F1 varies. Specifically, the transition time tp (or tn) of the signal on the selection signal line SE1 in the first-type refresh frame F1 corresponds to the position of the row of pixel circuits corresponding to the boundary between the first display subarea AA1 and the second display subarea AA2. As the position of the boundary between the first display subarea AA1 and the second display subarea AA2 changes, the transition time tp (or tn) of the signal on the selection signal line SE1 in the first-type refresh frame F1 will also change.

[0115] For example, in conjunction with Figures 9 to 11, it can be seen that during the refresh rate switching process of the first display subarea AA1, tp at 12 Hz corresponds to the transition edge of the effective clock signal of the shift unit 10 corresponding to the 799th row of pixel circuits PX jumping to its own effective level, and tp at 15 Hz corresponds to the transition edge of the effective clock signal of the shift unit 10 corresponding to the 797th row of pixel circuits PX jumping to its own effective level. Therefore, tp at 12 Hz and tp at 15 Hz are in different positions in their respective first-type refresh frames F1, which is equivalent to changing. Similarly, tn at 12 Hz and tn at 15 Hz are in different positions in their respective first-type refresh frames F1, which is equivalent to changing.

[0116] Optionally, in a transition frame with a refresh frequency of 1 Hz, in the 119 first type refresh frames F1 between two adjacent second type refresh frames F2, the jump time tp (or tn) of the signal on the selection signal line SE1 in the 119 first type refresh frames F1 is changed, that is, the position of tp (or tn) at 1 Hz in the first type refresh frame F1 is different.

[0117] During the refresh frequency switching process of the first display subarea AA1, in at least two first-type refresh frames F1, the transition time tp (or tn) of the signal on the strobe signal line SE1 in the first-type refresh frames F1 changes in an increasing or decreasing manner, or changes in a manner of first increasing and then decreasing, or changes in a manner of first decreasing and then increasing, or changes randomly. The transition time tp (or tn) changes in the same or similar manner as the row position of the pixel circuit PX corresponding to the boundary between the display subareas.

[0118] In any two first-type refresh frames F1 , the change amount of the signal on the selection signal line SE1 at the transition time tp (or tn) in the first-type refresh frame F1 is less than or equal to the scanning time of 20 rows of pixel circuits.

[0119] Optionally, during the refresh frequency switching process of the first display subarea AA1, the transition time tp (or tn) of the signal on the selection signal line SE1 in the first type refresh frame varies with the refresh frequency of the first display subarea AA1. For example, the transition time tp (or tn) varies at a fixed time interval with the refresh frequency of the first display subarea AA1. The fixed time interval may be equal to an integer multiple of the scanning time of the pixel circuits PX in the R row.

[0120] In summary, during the process of switching from 60 Hz to 1 Hz in the first display partition AA1 and the third display partition AA3, the row positions of the pixel circuits PX corresponding to the adjacent boundaries of the first display partition AA1 and the second display partition AA2 change in an increasing row number manner, and the row positions of the pixel circuits PX corresponding to the adjacent boundaries of the third display partition AA3 and the second display partition AA2 change in a decreasing row number manner, with the number of rows changing each time being P*n rows. Here, P can be determined by the drive architecture of the scanning circuit 100. For example, if the drive architecture of the scanning circuit 100 is a single shift unit 10 driving two rows of pixel circuits PX simultaneously, then P = 2; if the drive architecture of the scanning circuit 100 is a single shift unit 10 driving one row of pixel circuits PX, then P = 1.

[0121] Of course, in other embodiments, the position of the row of pixel circuits PX corresponding to the boundary position between adjacent display partitions may also be changed in other ways. For details, please refer to the above description of the display area AA including the first display partition AA1 and the second display partition AA2, which will not be repeated here.

[0122] Optionally, during the first type refresh frame, when the shift unit corresponding to the pixel circuit of the second display subarea outputs the scan signal, the signal on the selection signal line is at its own valid level, and the selection unit is controlled to be turned on to control the shift unit to output the scan signal to part of the pixel circuits in the second display area;

[0123] During the second type of refresh frame, when the shift units corresponding to the pixel circuits of the first display partition and the second display partition output scan signals, the signal on the selection signal line jumps to its own valid level, controlling the selection unit to be turned on, so as to control the shift unit to output scan signals to the pixel circuits of the first display partition and the second display partition.

[0124] Optionally, during the switching of the refresh frequency of the first display partition, in a plurality of transition frames, a change in the position of the pixel circuit corresponding to the adjacent boundary between the first display partition and the second display partition is an integer multiple of R rows.

[0125] FIG12 is a flow chart of another method for controlling a display panel provided in an embodiment of the present application. Referring to FIG12 , the method for controlling a display panel includes:

[0126] S210, the selection module responds to the signal on the selection signal line, causing the shift unit to output a scan signal to the corresponding pixel circuit, so as to achieve different refresh frequencies corresponding to at least two display partitions; the transition edge of the signal on the selection signal line is aligned in time with the transition edge of the clock signal on one of the at least two clock signal lines, or the difference is less than or equal to 2 crystal oscillator cycles, wherein the crystal oscillator is set in the clock circuit for generating the clock signal.

[0127] Specifically, the timing of the conduction of the gating module 200 is associated with the timing of the occurrence of the conduction pulse of the scanning signal output by the shift unit 10. Therefore, the alignment of the transition edge of the signal on the gating signal line SE1 that controls the conduction of the gating module 20 will also affect the display effect of the display partition boundary position. In this embodiment, the alignment of the transition edge of the signal on the gating signal line SE1 is associated with the clock signal (including at least the first clock signal and the second clock signal) corresponding to the current stage shift unit 10. The transition edge of the signal on the gating signal line SE1 is controlled to be aligned in time with the transition edge of at least one of the two clock signals, or the difference is less than or equal to 2 crystal oscillator cycles, so as to achieve precise timing control of different display partitions, thereby improving the brightness abnormality that occurs at the boundary between each display partition when switching the frequency.

[0128] Optionally, the transition edge at which the signal on the selection signal line SE1 jumps to its own valid level is aligned in time with the transition edge at which the clock signal on one of at least two clock signal lines jumps to its own valid level, or the difference is less than or equal to 2 crystal oscillator cycles.

[0129] Optionally, the clock signal on one of the at least two clock signal lines serves as the effective clock signal for the corresponding shift unit 10. The transition time of the scanning signal output by the shift unit 10 to its own effective level is determined by the corresponding effective clock signal. The effective clock signals corresponding to two adjacent shift units 10 are clock signals on different clock signal lines. The transition time of the scanning signal output by the shift unit 10 to its own effective level is determined by the transition time of the corresponding effective clock signal to its own effective level.

[0130] Optionally, during the first type refresh frame, the control shift unit outputs a scan signal to the pixel circuit of the second display area, and during the second type refresh frame, the control shift unit outputs a scan signal to the pixel circuits of the first display partition and the second display area.

[0131] Figure 13 is a structural schematic diagram of a shift unit provided in an embodiment of the present application. Optionally, the shift unit includes a first output transistor M15, and the first output transistor M15 is connected between the carry signal output terminal CR and the first clock signal terminal CK2 (for transmitting the first clock signal SCK2) of the shift unit. In two adjacent shift units 10, the carry signal output terminal CR of the previous shift unit 10 is electrically connected to the input terminal IN (SINP in Figure 13) of the next shift unit 10; in two adjacent shift units 10, the first clock signal terminal CK2 of the previous shift unit 10 and the first clock signal terminal CK2 of the next shift unit 10 are electrically connected to different clock signal lines, and the clock signal on the clock signal line electrically connected to the first clock signal terminal CK2 of the shift unit 10 is used as a valid clock signal.

[0132] When the first output transistor M15 is turned on, the valid pulse of the valid clock signal connected to the first clock signal terminal CK2 can be output to the carry signal output terminal CR (which can be multiplexed as the output terminal O1), which is equivalent to the scan signal.

[0133] FIG13 specifically illustrates a case where the shift unit 10 is a PScan circuit. Referring to FIG13 , the shift unit 10 may include a first input transistor M9, a second input transistor M10, a third input transistor M11, a first output control transistor M12, a second output control transistor M13, a first output transistor M15, a second output transistor M14, a protection transistor M16, a first capacitor C1, and a second capacitor C2. The first electrode of the first input transistor M9 is connected to the first potential signal line VGH, the second electrode of the first input transistor M9 is connected to the second electrode of the third input transistor M11 via the second input transistor M10, the first electrode of the third input transistor M11 is connected to the input terminal SINP of the shift unit 10, the gate of the third input transistor M11 is connected to the second clock signal terminal CK1, and the gate of the second input transistor M10 is connected to the first clock signal terminal CK2. The first electrode of the first output control transistor M12 is connected to the second clock signal terminal CK1, the second electrode of the first output control transistor M12 is connected to the gate of the first input transistor M9, and the gate of the first output control transistor M12 is connected to the second electrode of the third input transistor M11. The first electrode of the second output control transistor M13 is connected to the second potential signal line VGL, the second electrode of the second output control transistor M13 is connected to the gate of the second output transistor M14, and the gate of the second output control transistor M13 is connected to the second clock signal terminal CK1. The first electrode of the first output transistor M15 is connected to the first clock signal terminal CK2, and the gate of the first output transistor M15 is connected to the second electrode of the third output transistor M11 via the protection transistor M16. The second electrodes of the second output transistor M14 and the second electrodes of the first output transistor M15 are both connected to the output terminal O1 of the shift unit 10 (which can be multiplexed as the carry signal output terminal CR). The first electrode of the second output transistor M14 can be connected to the first potential signal line VGH, and the gate of the protection transistor M16 can be connected to the second potential signal line VGL. The first capacitor C1 is connected between the gate of the first output transistor M15 and the output terminal O1 of the shift unit 10 (which can be multiplexed as the carry signal output terminal CR). The second capacitor C2 is connected between the gate of the second output transistor M14 and the first potential signal line VGH. The structure, operation process, and principle of the circuit of Figure 13 are the same or similar to those in the related art and will not be repeated here.

[0134] Figure 14 is a schematic diagram of a driving timing of a shift unit provided in this embodiment. Combined with Figure 13 and Figure 14, on the basis of the above technical solution, at least two clock signal lines include a first clock signal line CLK1 and a second clock signal line CLK2, and the clock signals transmitted on the first clock signal line CLK1 and the second clock signal line CLK2 have the same frequency and opposite phases.

[0135] In combination with Figures 13 and 14, taking the clock signal on the second clock signal line CLK2 as the effective clock signal SCK2 of the shift unit 10 as an example, the transition moment of the scanning signal SP1 output by the shift unit 10 of this level jumps to its own effective level (for example, a low level) is determined by the corresponding effective clock signal SCK2, that is, the transition moment of the effective level of the scanning signal SP1 is the same as the transition moment of the first clock signal SCK2, or the difference is less than or equal to 2 crystal oscillator cycles.

[0136] Continuing to refer to Figure 14, the transition moment (such as tp) when the signal on the selection signal line SE1 (such as CSP1) jumps to its own valid level is the same as the transition moment when the valid clock signal SCK2 of the shift unit 10 corresponding to the first row of pixel circuits that need to be refreshed (for example, it can be the first row of pixel circuits PX that need to be refreshed in the entire display panel, or, along the refresh direction, the first row of pixel circuits PX of the display partition that needs to be refreshed and is adjacent to the previous display partition that does not need to be refreshed, such as the 801st row of pixel circuits PX at 1 Hz in Figures 9 and 10) jumps to its own valid level. In other words, still taking the clock signal on the second clock signal line CLK2 as the effective clock signal of the odd-numbered shift unit 10 as an example, the transition moment of the effective level of the scanning signal output by the shift unit 10 corresponding to the pixel circuit of the first row that needs to be refreshed is determined by the transition moment of the effective clock signal of the shift unit 10 to its own effective level. For example, the transition moment of the effective level of the scanning signal is determined by the transition moment of the first clock signal SCK2. The clock signal is the input signal, and the scanning signal is the output signal. There will be a certain delay in the output signal responding to the input signal. Therefore, the transition moment of the effective clock signal (first clock signal SCK2) of the shift unit 10 corresponding to the pixel circuit of the first row that needs to be refreshed to its own effective level (e.g., low level) is used as the transition moment of the signal on the selection signal line SE1 to its own effective level (e.g., low level). Compared with using the transition moment of the scanning signal output from the output terminal O1 as the transition moment of the signal on the selection signal line SE1, the timing can be controlled more accurately.

[0137] In the first type of refresh frame F1, the first row of pixel circuits PX of the second display partition AA2 can be regarded as the first row of pixel circuits PX that need to be refreshed, such as the 801st row of pixel circuits PX at 1 Hz in Figures 9 and 10. In the second type of refresh frame F2, the first row of pixel circuits PX of the first display partition AA1 can be regarded as the first row of pixel circuits PX that need to be refreshed, such as the 1st row of pixel circuits PX at 1 Hz in Figures 9 and 10. If there are other display partitions on the side of the first display partition AA1 away from the second display partition AA2, the refresh areas of various types of refresh frames and the first row refresh position of the display panel can be set as needed, and this application does not limit this. The more display partitions there are, the more types of refresh frames there are. In the same refresh frame, there will be multiple transition edges for the signal on the selection signal line SE1 to jump to its own valid level. Therefore, the setting method of the other transition edges for the signal on the selection signal line SE1 to jump to its own valid level is the same or similar to the setting method for the first transition edge for the signal on the selection signal line SE1 to jump to its own valid level.

[0138] In other embodiments, since parameters such as the period and accuracy of the clock signal are related to the crystal oscillator of the clock circuit, the moment when the signal on the selection signal line SE1 jumps to its own valid level and the moment when the effective clock signal of the shift unit 10 corresponding to the first row of pixel circuits PX that need to be refreshed jumps to its own valid level can differ by 1 to 2 crystal oscillator cycles to ensure precise timing control.

[0139] Optionally, when the shift unit 10 corresponding to the pixel circuit PX in the first row to be refreshed is an odd-numbered shift unit, a transition edge of the signal on the selection signal line SE1 (e.g., a transition edge at which the signal transitions to its own valid level) is aligned with a transition edge of the clock signal on the second clock signal line CLK2 (e.g., a transition edge at which the signal transitions to its own valid level), or a difference between the transition edges is less than or equal to two crystal oscillator cycles. The clock signal on the second clock signal line CLK2 may be the valid clock signal of the odd-numbered shift unit.

[0140] And / or, when the shift unit 10 corresponding to the pixel circuit PX in the first row to be refreshed is an even-numbered shift unit, a transition edge of the signal on the selection signal line SE1 (e.g., a transition edge at which the signal transitions to its own valid level) is aligned with a transition edge of the clock signal on the first clock signal line CLK1 (e.g., a transition edge at which the signal transitions to its own valid level), or a difference between the transition edges is less than or equal to two crystal oscillator cycles. The clock signal on the first clock signal line CLK1 may be the valid clock signal of the even-numbered shift unit.

[0141] Among them, the transition edge specifically includes a rising edge and a falling edge. In this control method, whether the transition edge of the signal on the selection signal line SE1 is aligned with the rising edge of the clock signal or the falling edge of the clock signal can be determined by the specific circuit principle and structure of the shift unit 10, the driving architecture of the scanning circuit 100, and at least one of the driving type of the scanning signal output by the scanning circuit 100.

[0142] The driving architecture of the scanning circuit 100 includes "one drive one", "one drive two", "one drive three", etc., among which "one drive one" means that there is a one-to-one correspondence between a shift unit 10 in the scanning circuit 100 and the scanning line GL1, that is, one shift unit 10 drives a row of pixel circuits; "one drive two" means that the same shift unit 10 in the scanning circuit 100 corresponds to two scanning lines GL1, that is, one shift unit 10 drives two rows of pixel circuits. Similarly, "one drive three" means that the same shift unit 10 in the scanning circuit 100 corresponds to three scanning lines GL1, that is, one shift unit 10 drives three rows of pixel circuits.

[0143] The driving type of the scanning signal is determined by the type of the scanning circuit 100. If the scanning circuit 100 is an NScan circuit, it can be electrically connected to the gate of the N-type transistor in the pixel circuit PX to control the conduction or shutdown of the N-type transistor, and the scanning signal is a high-level valid signal (the high level is the conduction level of the N-type transistor connected to the NScan circuit); if the scanning circuit 100 is a PScan circuit, it can be electrically connected to the gate of the P-type transistor in the pixel circuit PX to control the conduction or shutdown of the P-type transistor, and the scanning signal is a low-level valid signal (the low level is the conduction level of the P-type transistor connected to the PScan circuit).

[0144] Continuing with reference to FIG. 13 and FIG. 14 , FIG. 14 specifically illustrates a scanning circuit 100 that is a PScan circuit and employs a "one-drive-one" drive timing scheme. The PScan circuit may be electrically connected to the gate of the data write transistor M4. As shown in FIG. 14 , the low level of the input signal SINP of the shift unit 10 included in the scanning circuit 100 is a valid signal, the low level of the scanning signal SP1 is a conduction level or a valid level, the pulse width of the scanning signal SP1 is the same as the pulse width of the first clock signal SCK2, and the low level of the signal CSP1 on the selection signal line SE1 is a conduction signal or a valid level. This controls the falling edge of the signal CSP1 on the selection signal line SE1 to be aligned with the falling edge of the first clock signal SCK2. Half the period of the clock signal on the clock signal line to which the PScan circuit is connected may be equal to the scanning time required to scan a row of pixel circuits PX. If the NScan circuit is a one-drive-two architecture, the boundary line between the first display partition AA1 and the second display partition AA2 changes according to two rows of pixel circuits PX, while the PScan circuit is a one-drive-one architecture. The first row of pixel circuits PX corresponding to the boundary line between the first display partition AA1 and the second display partition AA2 is always an odd-numbered row of pixel circuits PX, corresponding to the odd-numbered shift unit 10, and the falling edge (corresponding to time tp) of the signal CSP1 on the selection signal line SE1 is aligned with the falling edge of the clock signal on the same clock signal line, and the corresponding clock signal line does not change with the change of the boundary line between the first display partition AA1 and the second display partition AA2.

[0145] If the scanning circuit 100 is an NScan circuit, the high level of the signal on the selection signal line SE1 is a conduction signal or an active level. The high level of the scanning signal S1 is a conduction level or an active level. When M=Rm+1, and m is an even number, it is equivalent to the shift unit corresponding to the pixel circuit PX in the first row to be refreshed being an even-numbered shift unit 10, and the rising edge of the signal on the selection signal line SE1 is controlled to be aligned with the rising edge or falling edge of the clock signal on the first clock signal line CLK1. If m is an odd number, it is equivalent to the shift unit corresponding to the pixel circuit PX in the first row to be refreshed being an odd-numbered shift unit 10, and the rising edge of the signal on the selection signal line SE1 is controlled to be aligned with the rising edge or falling edge of the clock signal on the second clock signal line CLK2. For example, the 0th-level shift unit 10 corresponds to the pixel circuit PX in the first and second rows, the 1st-level shift unit 10 corresponds to the pixel circuit PX in the third and fourth rows, and so on. For example, the first-stage shift unit 10 may correspond to the first and second-row pixel circuits PX, the second-stage shift unit 10 may correspond to the third and fourth-row pixel circuits PX, and so on.

[0146] Wherein, M is the corresponding row number of the first row of pixel circuits of the refreshed display partition, m is the number of stages of the shift unit 10, and R is the number of rows of pixel circuits PX driven by one shift unit.

[0147] In this embodiment, whether the rising edge of the signal on the selection signal line SE1 is aligned with the rising edge or the falling edge of the clock signal can be determined according to the valid level of the signal SIN (for example, SINN1) at the input end of the shift unit 10.

[0148] For example, FIG15 is a schematic diagram of the structure of another shift unit provided in an embodiment of the present application, specifically illustrating the case where the shift unit 10 is an NScan circuit. FIG16 is a schematic diagram of the driving timing of another shift unit provided in an embodiment of the present application, specifically illustrating the driving timing of a reverse NScan circuit in a "one-drive-two" driving architecture when the scanning circuit 100 is a scanning circuit 100, which is applicable to the NScan circuit shown in FIG15. The low level of the input signal SINN1 of the shift unit 10 is a valid level. Since the scanning circuit 100 adopts a "one-drive-two" driving architecture, one shift unit 10 is connected to two rows of pixel circuits, i.e., R=2. The circuit of FIG15 is equivalent to the circuit of FIG13 , with an inverting circuit added to the output terminal. The inverting circuit may include a third output transistor M17 and a fourth output transistor M18. The third output transistor M17 is connected between the first potential signal line VGH and the output terminal O1, and the fourth output transistor M18 is connected between the second potential signal line VGL and the output terminal O1. The gates of the third output transistor M17 and the fourth output transistor M18 are electrically connected to the carry signal output terminal CR. The structure and operating principle of the circuit of FIG15 are the same or similar to those of the circuit of FIG13 . The scanning signal at the output terminal O1 of the circuit of FIG15 is equivalent to the scanning signal at the output terminal O1 of the circuit of FIG13 being inverted.

[0149] Figure 17 is a structural schematic diagram of another display panel provided by an embodiment of the present application, which specifically shows the cascade of the shift units shown in Figure 15. In combination with Figures 15 and 17, the shift unit 10 includes a first output transistor M15, and the first output transistor M15 is connected between the carry signal output terminal CR and the first clock signal terminal CK2 of the shift unit 10. In two adjacent shift units 10, the carry signal output terminal CR of the previous shift unit 10 is electrically connected to the input terminal IN (SINN1) of the next shift unit 10; in two adjacent shift units 10, the first clock signal terminal CK2 of the previous shift unit 10 and the first clock signal terminal CK2 of the next shift unit 10 are electrically connected to different clock signal lines, and the clock signal on the clock signal line electrically connected to the first clock signal terminal CK2 of the shift unit 10 is used as a valid clock signal.

[0150] As shown in FIG16 , when the high level of the scan signal SN1 is at a conduction level or an active level, if the low level of the input signal SINN1 of the shift unit 10 is at an active level, the rising edge of the signal CSN1 on the selection signal line SE1 is controlled to be aligned with the falling edge of the clock signal on the first clock signal line CLK1 or the clock signal on the second clock signal line CLK2. The scan circuit 100 may be a first NScan circuit electrically connected to the gate of the threshold compensation transistor M5 in the pixel circuit.

[0151] Taking the first row of pixel circuits PX that need to be refreshed in the second display partition AA2 during the first type of refresh frame F1 as an example, if the first row of pixel circuits in the second display partition AA2 is the 677th row, then according to 677=M=2m+1, it can be seen that m=338, m is an even number, which is equivalent to the shift unit 10 corresponding to the first row of pixel circuits PX that need to be refreshed being an even-level shift unit. Therefore, the rising edge of the signal CSN1 on the control selection signal line SE1 (for example, corresponding to time tn) is aligned with the falling edge of the clock signal on the first clock signal line CLK1 (as shown by the solid line portion of the signal CSN1 in Figure 16).

[0152] Taking the first row of pixel circuits that need to be refreshed in the second display partition AA2 during the first type of refresh frame F1 as an example, if the first row of pixel circuits PX in the second display partition AA2 is the 675th row, then according to 675=M=2m+1, it can be seen that m=337, m is an odd number, which is equivalent to the shift unit 10 corresponding to the first row of pixel circuits PX that need to be refreshed being an odd-level shift unit. Therefore, the rising edge of the signal CSN1 on the control selection signal line SE1 (for example, corresponding to time tn") is aligned with the falling edge of the clock signal on the second clock signal line CLK2 (as shown by the dotted line portion of the signal CSN1 in Figure 16).

[0153] In the two examples shown in FIG16 , the row number of the first row of pixel circuits PX in the second display partition AA2 in the latter example is two greater than the row number of the first row of pixel circuits PX in the second display partition AA2 in the former example. Therefore, the time interval T is equal to the two-row scanning time, which is equivalent to T=tn″-tn. Half the period of the clock signal on the clock signal line connected to the NScan circuit can be equal to the scanning time required to scan two rows of pixel circuits PX. Optionally, when the high level of the input signal SIN of the shift unit 10 is an effective level, the alignment method of the rising edge of the signal CS1 on the selection signal line SE1 is opposite to that shown in FIG16 .

[0154] FIG18 is a schematic diagram of the structure of another display panel provided by an embodiment of the present application, specifically showing the case where the shift unit 10 is an NScan circuit, wherein each stage of the shift unit 10 is connected to a clock signal line, and the effective clock signal of the shift unit 10 is the clock signal on the clock signal line connected thereto, and the clock signal lines connected to the two adjacent stages of the shift unit 10 are different. FIG19 is a schematic diagram of the driving timing of another shift unit provided by an embodiment of the present application, and specifically shows the driving timing of the second NScan circuit under the "one drive two" driving architecture of the scanning circuit 100, wherein the high level of the input signal SIN of the shift unit 10 is an effective level, and the rising edge of the signal CSN2 on the selection signal line SE1 is aligned with the rising edge of the clock signal. Specifically, as shown in FIG19, when the high level of the scan signal SN2 is a conduction level or an effective level, if the high level of the input signal SIN (for example, SINN2) of the shift unit 10 is an effective level, the rising edge of the signal CSN2 on the selection signal line SE1 is controlled to be aligned with the rising edge of the clock signal on the first clock signal line CLK1 or the second clock signal line CLK2. The scanning circuit 100 may be a second NScan circuit, which is electrically connected to the gate of the third initialization transistor M6 in the pixel circuit.

[0155] Referring to Figure 19, for example, taking the first row of pixel circuits PX that need to be refreshed in the second display partition AA2 during the first type of refresh frame F1 as an example, if the first row of pixel circuits in the second display partition AA2 is the 677th row, then according to M=2m+1, it can be seen that m=338, m is an even number, which is equivalent to the shift unit 10 corresponding to the first row of pixel circuits PX that need to be refreshed being an even-level shift unit. Therefore, the rising edge of the signal CSN2 on the control selection signal line SE1 (corresponding to the moment tn) is aligned with the rising edge of the clock signal on the first clock signal line CLK1 (as shown by the solid line portion of the signal CSN2 on the selection signal line SE1 in Figure 19).

[0156] Taking the first row of pixel circuits PX that need to be refreshed in the second display partition AA2 during the first type of refresh frame F1 as an example, the high level of the input signal SIN of the shift unit 10 is a valid level. If the first row of pixel circuits in the second display partition AA2 is the 679th row, then according to M=2m+1, it can be seen that m=339, m is an odd number, which is equivalent to the shift unit 10 corresponding to the first row of pixel circuits PX that need to be refreshed being an odd-level shift unit. Therefore, the rising edge of the signal CSN2 on the control selection signal line SE1 (corresponding to the moment tn") is aligned with the rising edge of the clock signal on the second clock signal line CLK2 (as shown by the dotted line portion of the signal CSN2 on the selection signal line SE1 in FIG19 ).

[0157] Optionally, the rising edge of the clock signal on the second clock signal line CLK2 is aligned with the falling edge of the clock signal on the first clock signal line CLK1. Optionally, the falling edge of the clock signal on the second clock signal line CLK2 is aligned with the rising edge of the clock signal on the first clock signal line CLK1. Optionally, m is an even number, which is equivalent to the shift unit 10 corresponding to the pixel circuit PX in the first row that needs to be refreshed being an even-level shift unit, and the rising edge (corresponding to the moment tn) of the signal CSN2 on the control selection signal line SE1 is aligned with the falling edge of the clock signal on the second clock signal line CLK2. Optionally, m is an odd number, which is equivalent to the shift unit 10 corresponding to the pixel circuit PX in the first row that needs to be refreshed being an odd-level shift unit, and the rising edge (corresponding to the moment tn”) of the signal CSN2 on the control selection signal line SE1 is aligned with the falling edge of the clock signal on the first clock signal line CLK1.

[0158] Optionally, the rising edge of the clock signal on the second clock signal line CLK2 is not aligned with the falling edge of the clock signal on the first clock signal line CLK1. Optionally, the falling edge of the clock signal on the second clock signal line CLK2 is not aligned with the rising edge of the clock signal on the first clock signal line CLK1.

[0159] In the above-mentioned technical solutions, when the number of rows corresponding to the first row of pixel circuits in the second display partition AA2 changes, for example, the row number increases, in Figure 16 (or Figure 19), the signal CSN1 or CSN2 on the selection signal line SE1 changes to the timing shown by the dotted line, and when it shifts back by T time, the scanning signal SN1 or SN2 of the current-stage shift unit will not be output to the corresponding pixel circuit PX, and the scanning signal SN1 or SN2 of the subsequent-stage shift unit will be output to the corresponding pixel circuit PX.

[0160] This solution synchronizes the signal on the selection signal line SE1 and the scan signal by precisely controlling the alignment of the transition edges of the signals CSP, CSN1, or CSN2 on the selection signal line SE1 with the transition edges of the corresponding clock signals. This is beneficial for precisely controlling the refresh frequencies of multiple display partitions, improving the abnormal display of the boundary position when multiple display partitions switch refresh frequencies, and reducing power consumption.

[0161] FIG20 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application. Referring to FIG20 , optionally, at least one driving circuit includes a first driving circuit 121, the first driving circuit 121 includes a first scanning circuit and a first gating module, and the first scanning circuit includes a plurality of first shift units. R rows of pixel circuits PX correspond to the same first shift unit in the first driving circuit 121, where R is an integer greater than or equal to 2. When R=2, the number of first shift units 11 is Z / 2. The figure only shows the connection between the first-stage first shift unit and the last-stage first shift unit and the pixel circuit PX. Specifically, the first-stage first shift unit corresponds to driving the first-row pixel circuit PX and the second-row pixel circuit PX, and the last-stage first shift unit corresponds to driving the Z-th row (last row) pixel circuit PX and the Z-1-th row (second to last row) pixel circuit PX.

[0162] And / or, at least one driving circuit includes a second driving circuit 122, the second driving circuit 122 includes a second scanning circuit and a second gating module, and the second scanning circuit includes multiple stages of second shift units. A row of pixel circuits PX corresponds to one second shift unit in the second driving circuit 122, and pixel circuits PX in different rows correspond to different second shift units in the second driving circuit 122. The number of second shift units 12 is Z.

[0163] And / or, at least one driving circuit includes a third driving circuit 123, which includes a third scanning circuit and a third gating module, and the third scanning circuit includes a multi-stage third shift unit. K rows of pixel circuits PX correspond to the same shift unit in the third driving circuit 123, where K is an integer greater than or equal to 2. When K = 2, the number of third shift units is Z / 2, and their specific connection method can refer to the connection method of the first driving circuit 121. Optionally, R = K.

[0164] The input terminals IN of the first shift units in different scanning circuits receive different input signals (e.g. SIN1, SIN2, SIN3). The pixel circuit sp1 terminal is the input terminal of the scanning signal SP1, sn1 terminal is the input terminal of the scanning signal SN1, and sn2 terminal is the input terminal of the scanning signal SN2.

[0165] Optionally, in combination with the pixel circuit shown in Figure 4, the second driving circuit 122 can be used to provide a scan signal SP1 to the data writing transistor M4, the first driving circuit 121 can be used to provide a scan signal SN1 to the threshold compensation transistor M5, and the third driving circuit 123 can be used to provide a scan signal SN2 to the third initialization transistor M6.

[0166] The first gating module, the second gating module and the third gating module are respectively connected to different gating signal lines, and different driving circuits are connected to different clock signal lines, that is, each driving circuit is connected to its corresponding first clock signal line CLK1 and second clock signal line CLK2, and the corresponding signals on each gating signal line can be set using the alignment method in the above-mentioned technical solutions.

[0167] By separately controlling the transition edge of the signal on the selection signal line to be aligned in time with the transition edge of the clock signal on one of at least two clock signal lines, the abnormal display of the display partition boundary position can also be improved.

[0168] Alternatively, in the technical solutions provided in the above embodiments, the shift unit 10 may be a shift register, which may be an 8T2C architecture. For details, please refer to the description of the shift register in the relevant technical solutions. The gating module 200 may be composed of transistors or logic gate circuits, as long as they can realize the gating function.

[0169] Optionally, an embodiment of the present application further provides a display panel that can be controlled by the display panel control method provided in any embodiment of the present application. The display panel can be not only a mobile phone panel, but also a display panel in electronic devices such as tablets, mobile phones, watches, wearable devices, and in-vehicle displays, camera displays, televisions, and computer screens. Because the display panel is controlled by the display panel control method provided in any embodiment of the present application, the display panel provided in the embodiment of the present application also has the beneficial effects described in any embodiment of the present application.

[0170] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this application can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of this application can be achieved. This is not limited herein.

[0171] The above specific embodiments do not constitute a limitation on the scope of protection of this application. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application shall be included within the scope of protection of this application.

Claims

1. A method for controlling a display panel, wherein the display panel comprises at least two display partitions, wherein the at least two display partitions comprise a first display partition and a second display partition that are adjacent and have different refresh frequencies, and the display panel comprises: A plurality of pixel circuits arranged in an array; The control method of the display panel includes: During the process of switching the refresh frequency of the first display partition, multiple transition frames are set, and the refresh frequency of the first display partition in the multiple transition frames is between the refresh frequency before the switching of the first display partition and the refresh frequency after the switching; and / or, in the multiple transition frames, the positions of the pixel circuits corresponding to the adjacent boundaries of the first display partition and the second display partition are different.

2. The control method of the display panel according to claim 1, wherein: The refresh frequency of the first display partition in the plurality of transition frames gradually increases or decreases, and is between the refresh frequency before switching and the refresh frequency after switching of the first display partition.

3. The control method of the display panel according to claim 1, wherein: The display panel further includes: at least one driving circuit, the driving circuit comprising a scanning circuit, a gating module and a gating signal line, the scanning circuit comprising a multi-stage shifting unit; The plurality of transition frames include a first type refresh frame and a second type refresh frame; The gating module, in response to the signal on the gating signal line, does not enable the shift unit to output a scan signal to the pixel circuit of the first display partition during the first type refresh frame, and enables the shift unit to output a scan signal to the pixel circuit of the first display partition during the second type refresh frame; During the process of switching the refresh frequency of the first display partition, the first type refresh frame is inserted between multiple second type refresh frames, and the number of the first type refresh frames inserted between two adjacent second type refresh frames gradually increases or decreases; and / or, in at least two transition frames, the row positions of the pixel circuits corresponding to the adjacent boundaries of the first display partition and the second display partition are different.

4. The control method of the display panel according to claim 3, wherein: In at least two of the first-type refresh frames, the pixel circuits corresponding to the boundaries between the first display partition and the second display partition are located in different rows.

5. The control method of the display panel according to claim 3, wherein: In a plurality of the first-type refresh frames between two adjacent second-type refresh frames, the positions of the rows of pixel circuits corresponding to the adjacent boundaries of the first display partition and the second display partition are the same or different.

6. The control method of the display panel according to claim 3, wherein: When the refresh frequency before the first display partition is switched is greater than the refresh frequency after the switching, during the process of switching the refresh frequency of the first display partition, the number of the first type of refresh frames inserted between two adjacent second type refresh frames gradually increases; and the refresh frequency of the first display partition gradually decreases; and / or, when the refresh frequency before the first display partition is switched is lower than the refresh frequency after the switching, During the process of switching the refresh frequency of the display partition, the number of the first type refresh frames inserted between two adjacent second type refresh frames gradually decreases; and the refresh frequency of the first display partition gradually increases.

7. The control method of the display panel according to claim 1, wherein: In at least two transition frames, the row position of the pixel circuit corresponding to the boundary between the first display partition and the second display partition changes in a manner of increasing row number or decreasing row number, or changes in a manner of first increasing and then decreasing row number, or changes in a manner of first decreasing and then increasing row number, or changes randomly.

8. The control method of the display panel according to claim 1, wherein: In any two transition frames, the change in the position of the row where the pixel circuits corresponding to the adjacent boundaries between the first display partition and the second display partition are located is less than or equal to 20 rows.

9. The control method of the display panel according to claim 1, wherein: During the switching of the refresh frequency of the first display partition, the row position of the pixel circuit corresponding to the boundary between the first display partition and the second display partition changes by a fixed number of rows each time; Alternatively, during the switching of the refresh frequency of the first display partition, the position of the row where the pixel circuits corresponding to the boundary between the first display partition and the second display partition are located changes with the change of the refresh frequency of the first display partition; Alternatively, during the switching of the refresh frequency of the first display partition, the row position of the pixel circuit corresponding to the boundary between the first display partition and the second display partition changes by a fixed number of rows as the refresh frequency of the first display partition changes.

10. The control method of the display panel according to claim 3, wherein: The gating module, in response to the signal on the gating signal line, enables the shift unit to output a scan signal to the pixel circuit of the second display partition and does not enable the shift unit to output a scan signal to the pixel circuit of the first display partition during the first type refresh frame; In the second type refresh frame, the shift unit outputs a scan signal to the pixel circuits of the first display partition and the second display partition; and / or, in the process of switching the refresh frequency of the first display partition, the first type refresh frame is inserted between multiple second type refresh frames, and the number of the first type refresh frames inserted between two adjacent second type refresh frames gradually increases or gradually decreases; and / or, in at least two first type refresh frames, the row positions of the pixel circuits corresponding to the boundaries adjacent to the first display partition and the second display partition are different; and / or, during the switching of the refresh frequency of the first display partition, in the first type refresh frame, the pulse width of the signal on the selection signal line being its own effective level is smaller than the pulse width of the signal on the selection signal line being its own effective level in the second type refresh frame; And / or, during the switching of the refresh frequency of the first display partition, in at least two of the first type refresh frames, the transition time of the signal on the strobe signal line in the first type refresh frame is changed; The transition time of the signal on the line in the first type refresh frame corresponds to the row position of the pixel circuit corresponding to the boundary between the first display partition and the second display partition; and / or, in the process of switching the refresh frequency of the first display partition, in at least two of the first type refresh frames, the signal on the selection signal line changes in an increasing manner or a decreasing manner at a transition time in the first type refresh frame, or changes in a manner of first increasing and then decreasing, or changes in a manner of first decreasing and then increasing, or changes randomly; and / or, in any two first-type refresh frames, a change in the signal on the selection signal line at a transition time in the first-type refresh frame is less than or equal to a scanning time of 20 pixel lines; And / or, during the switching of the refresh frequency of the first display partition, the transition timing of the signal on the selection signal line in the first type refresh frame changes with the change of the refresh frequency of the first display partition.

11. The control method of the display panel according to claim 1, wherein: The display panel further includes a third display partition, the first display partition, the second display partition and the third display partition are adjacent to each other in sequence, and the refresh frequencies of two adjacent display partitions among the first display partition, the second display partition and the third display partition are different, During the switching of the refresh frequency of the third display partition, the refresh frequency of the third display partition in the plurality of transition frames is between the refresh frequency before the switching and the refresh frequency after the switching of the third display partition; and / or, in the plurality of transition frames, the positions of the pixel circuits corresponding to the adjacent boundaries of the third display partition and the second display partition are different; The display panel further includes: at least one driving circuit, the driving circuit comprising a scanning circuit, a gating module and a gating signal line, the scanning circuit comprising a multi-stage shifting unit; The plurality of transition frames include a first type refresh frame and a second type refresh frame; The refresh frequencies of the first display partition and the third display partition are the same, and the refresh frequency of the first display partition is lower than the refresh frequency of the second display partition, and the display driving method further includes: The gating module, in response to the signal on the gating signal line, enables the shift unit to output a scan signal to the pixel circuit of the second display partition in the first type refresh frame, and does not enable the shift unit to output a scan signal to the pixel circuits of the first display partition and the third display partition; and enables the shift unit to output a scan signal to the pixel circuits of the first display partition, the second display partition, and the third display partition in the second type refresh frame; Alternatively, the refresh frequencies of the first display partition and the third display partition are the same, and the refresh frequency of the first display partition is greater than the refresh frequency of the second display partition, and the display driving method further includes: The gating module responds to the signal on the gating signal line, in the first type refresh frame, not causing the shift unit to output a scan signal to the pixel circuit of the second display partition, but causing the shift unit to output a scan signal to the pixel circuits of the first display partition and the third display partition; in the second type refresh frame, causing the The shift unit outputs a scan signal to the pixel circuits of the first display partition, the second display partition, and the third display partition.

12. The control method of the display panel according to claim 11, wherein: Before the refresh frequencies of the first display partition and the third display partition are switched, the first display partition corresponds to the 1st to Wth rows of pixel circuits, the second display partition corresponds to the W+1th to Jth rows of pixel circuits, and the third display partition corresponds to the J+1th to Zth rows of pixel circuits, where W, J, and Z are all positive integers greater than 1 and not equal to each other; During the switching of the refresh frequencies of the first display partition and the third display partition, the gating module responds to the signal on the gating signal line, and in at least one of the first type refresh frames, does not enable the shift unit to output a scan signal to the pixel circuits in the 1st to W+P*n rows and the pixel circuits in the J+P*n+1 to Z rows, and enables the shift unit to output a scan signal to the pixel circuits in the W+P*n+1 to J+P*n rows; In the second type refresh frame, the shift unit outputs a scan signal to the pixel circuits in rows 1 to Z; wherein P is a positive integer, and n is a positive integer or a negative integer.

13. The control method of the display panel according to claim 3, wherein: The gating module comprises a plurality of gating units, each stage of the shifting unit is connected to the pixel circuit of the corresponding row through the gating unit, and the control ends of the plurality of gating units are connected to the gating signal line; In the first type refresh frame, when the shift unit corresponding to the pixel circuit of the second display partition outputs a scan signal, the signal on the selection signal line is at its own effective level, and the selection unit is controlled to be turned on, so as to control the shift unit to output the scan signal to the pixel circuit of the second display partition; In the second type refresh frame, when the shift units corresponding to the pixel circuits of the first display partition and the second display partition output scan signals, the signal on the selection signal line jumps to its own valid level, controlling the selection unit to be turned on, so as to control the shift unit to output scan signals to the pixel circuits of the first display partition and the second display partition.

14. The control method of the display panel according to claim 1, wherein: The display panel further includes: at least one driving circuit, the driving circuit comprising a scanning circuit, at least two clock signal lines, a gating module and a gating signal line, the scanning circuit comprising a multi-stage shift unit; The control method of the display panel further includes: The selection module controls the shift unit to output a scanning signal to the corresponding pixel circuit in response to the signal on the selection signal line, so as to achieve different refresh frequencies corresponding to at least two of the display partitions; the transition edge of the signal on the selection signal line is aligned in time with the transition edge of the clock signal on one of the at least two clock signal lines, or the difference is less than or equal to 2 crystal oscillator cycles, wherein the crystal oscillator is arranged in a clock circuit for generating the clock signal.

15. The method for controlling a display panel according to claim 14, wherein: The clock signal on one of the at least two clock signal lines serves as an effective clock signal corresponding to the shift unit. The transition time when the scanning signal output by the shift unit jumps to its own effective level is determined by the corresponding effective clock signal, and the effective clock signals corresponding to the two adjacent shift units are clock signals on different clock signal lines; The transition time when the signal on the selection signal line jumps to its own effective level is the same as the transition time when the effective clock signal of the shift unit corresponding to the pixel circuit of the first row to be refreshed jumps to its own effective level; And / or, the shift unit includes a first output transistor, which is connected between a carry signal output terminal and a first clock signal terminal of the shift unit; in two adjacent shift units, the carry signal output terminal of the previous shift unit is electrically connected to the input terminal of the next shift unit; in two adjacent shift units, the first clock signal terminal of the previous shift unit and the first clock signal terminal of the next shift unit are electrically connected to different clock signal lines, and the clock signal on the clock signal line to which the first clock signal terminal of the shift unit is electrically connected serves as a valid clock signal.

16. The method for controlling a display panel according to claim 14, wherein: The at least two clock signal lines include a first clock signal line and a second clock signal line; the clock signals on the first clock signal line and the second clock signal line have the same frequency and opposite phase; When the shift unit corresponding to the pixel circuit of the first row to be refreshed is an odd-numbered shift unit, the transition edge of the signal on the selection signal line is aligned with the transition edge of the clock signal on the second clock signal line; and / or, when the shift unit corresponding to the pixel circuit of the first row to be refreshed is an even-numbered shift unit, the transition edge of the signal on the selection signal line is aligned with the transition edge of the clock signal on the first clock signal line; And / or, at least one driving circuit includes a first driving circuit, R rows of pixel circuits correspond to the same shift unit in the first driving circuit, and R is an integer greater than or equal to 2; And / or, at least one driving circuit includes a second driving circuit, a row of the pixel circuits corresponds to one of the shift units in the second driving circuit, and different rows of the pixel circuits correspond to different shift units in the second driving circuit; And / or, at least one driving circuit includes a third driving circuit, K rows of pixel circuits correspond to the same shift unit in the third driving circuit, and K is an integer greater than or equal to 2; And / or, the pixel circuit includes a driving module, a data writing module and a threshold compensation module, the data writing module is connected between the data line and the first end of the driving module, the control end of the data writing module is electrically connected to the second driving circuit, the threshold compensation module is connected between the second end and the control end of the driving module, and the control end of the threshold compensation module is electrically connected to the first driving circuit; The pixel circuit further includes a first initialization module, the first initialization module is connected between the first initialization signal line and the control end of the driving module, and the control end of the first initialization module is electrically connected to the third driving circuit; The data writing module includes a P-type transistor, the threshold compensation module includes an N-type transistor, and the first initialization module includes an N-type transistor; And / or, during the switching of the refresh frequency of the first display partition, in a plurality of the transition frames, a change in the position of the pixel circuit corresponding to the boundary between the first display partition and the second display partition is an integer multiple of R rows.

17. A method for controlling a display panel, wherein the display panel comprises at least two display partitions, wherein the at least two display partitions comprise a first display partition and a second display partition that are adjacent and have different refresh frequencies; the display panel comprises: A plurality of pixel circuits arranged in an array; At least one driving circuit, the driving circuit comprising a scanning circuit, at least two clock signal lines, a gating module and a gating signal line, the scanning circuit comprising a multi-stage shift unit, the scanning circuit being connected to the at least two clock signal lines; The control method of the display panel includes: The selection module responds to the signal on the selection signal line, causing the shift unit to output a scanning signal to the corresponding pixel circuit, so as to achieve different refresh frequencies corresponding to at least two of the display partitions; the transition edge of the signal on the selection signal line is aligned in time with the transition edge of the clock signal on one of the at least two clock signal lines, or the difference is less than or equal to 2 crystal oscillator cycles, wherein the crystal oscillator is arranged in a clock circuit for generating the clock signal.

18. The control method of the display panel according to claim 17, wherein: The clock signal on one of the at least two clock signal lines is used as the effective clock signal corresponding to the shift unit, and the transition time when the scanning signal output by the shift unit jumps to its own effective level is determined by the corresponding effective clock signal, and the effective clock signals corresponding to the two adjacent shift units are clock signals on different clock signal lines; The transition time when the signal on the selection signal line jumps to its own effective level is the same as the transition time when the effective clock signal of the shift unit corresponding to the pixel circuit of the first row to be refreshed jumps to its own effective level; And / or, the shift unit includes a first output transistor, the first output transistor is connected between a carry signal output terminal and a first clock signal terminal of the shift unit, and in two adjacent stages of the shift units, the carry signal output terminal of the shift unit of the previous stage is electrically connected to the input terminal of the shift unit of the next stage; in two adjacent stages of the shift units, the first clock signal terminal of the shift unit of the previous stage and the first clock signal terminal of the shift unit of the next stage are electrically connected to different clock signal lines, and the clock signal on the clock signal line electrically connected to the first clock signal terminal of the shift unit is used as a valid clock signal; And / or, in a first type refresh frame, the shift unit is controlled to output a scan signal to the pixel circuit of the second display partition, and in a second type refresh frame, the shift unit is controlled to output a scan signal to the pixel circuits of the first display partition and the second display partition.

19. The control method of the display panel according to claim 17, wherein: The at least two clock signal lines include a first clock signal line and a second clock signal line; the first clock signal line and the second clock signal line have the same frequency and opposite phase; When the shift unit corresponding to the pixel circuit of the first row to be refreshed is an odd-numbered shift unit, the selection signal line The transition edge of the signal of the first clock signal line is aligned with the transition edge of the clock signal on the first clock signal line; And / or, when the shift unit corresponding to the pixel circuit of the first row to be refreshed is an even-numbered shift unit, the transition edge of the signal on the selection signal line is aligned with the transition edge of the clock signal on the second clock signal line.

20. A display panel controlled by the display panel control method according to any one of claims 1 to 19.

Images