Shift register unit, display panel, display device and driving method

Abstract

Provided in the embodiments of the present disclosure are a shift register unit, a display panel, a display device and a driving method. The shift register unit comprises: a shift register, which is configured to output a cascade signal by means of a cascade output end; and an output circuit, which is electrically connected to the shift register and is configured to control a driving output end to output a gate scanning signal on the basis of a signal of an output control signal end and a signal of a reference signal end.

Description

Shift register unit, display panel, display device and driving method TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to a shift register unit, a display panel, a display device and a driving method. BACKGROUND

[0002] With the rapid development of display technology, display panels show a development trend of high integration and low cost. Among them, the array substrate row driving technology (Gate Driver on Array, GOA) integrates the driving control circuit on the array substrate of the display panel to form the scanning driving of the display panel. At present, the driving control circuit is usually composed of a plurality of cascaded shift register units.

[0003] SUMMARY

[0004] Some embodiments of the present disclosure provide a shift register unit, comprising:

[0005] a shift register configured to output a cascade signal through a cascade output terminal;

[0006] an output circuit electrically connected with the shift register, the output circuit being configured to control a driving output terminal to output a gate scanning signal according to a signal of a first voltage signal terminal and a signal of a reference signal terminal;

[0007] The shift register comprises a first control sub-circuit.

[0008] The first control sub-circuit is electrically connected with a first node, a second node, a second voltage signal terminal and a first clock signal terminal in the shift register; and the first control circuit is configured to control a voltage of the second node according to a voltage of the first node and a signal of the first clock signal terminal.

[0009] In some possible implementation manners provided by the present disclosure, the shift register comprises:

[0010] an input sub-circuit configured to provide a signal of an input signal terminal to the first node in response to a signal of a second clock signal terminal.

[0011] In some possible implementation manners provided by the present disclosure, the input sub-circuit comprises a first transistor.

[0012] A first pole of the first transistor is electrically connected with the input signal terminal, a second pole of the first transistor is electrically connected with the first node, and a third pole of the first transistor is electrically connected with the second clock signal terminal.

[0013] In some possible implementation provided by the present disclosure, the first control sub-circuit comprises a second transistor, a third transistor, a fourth transistor and a first capacitor.

[0014] The first electrode of the second transistor is electrically connected with the first clock signal end, the second electrode of the second transistor is electrically connected with the second node, and the third electrode of the second transistor is electrically connected with a third node.

[0015] The first electrode of the third transistor is electrically connected with the second voltage signal end, the second electrode of the third transistor is electrically connected with the third node, and the third electrode of the third transistor is electrically connected with the first node.

[0016] The first electrode of the fourth transistor is electrically connected with the second voltage signal end, the second electrode of the fourth transistor is electrically connected with the second node, and the third electrode of the fourth transistor is electrically connected with the first node.

[0017] The first electrode of the first capacitor is electrically connected with the first clock signal end, and the second electrode of the first capacitor is electrically connected with the third node.

[0018] In some possible implementation provided by the present disclosure, the shift register comprises:

[0019] A second control sub-circuit is electrically connected with the first node, the second node, the second voltage signal end and the first clock signal end, and the second control sub-circuit is configured to transmit a signal from the second voltage signal end to the first node according to the voltage of the second node and the signal of the first clock signal end.

[0020] In some possible implementation provided by the present disclosure, the second control sub-circuit comprises a fifth transistor and a sixth transistor.

[0021] The first electrode of the fifth transistor is electrically connected with the second voltage signal end, the second electrode of the fifth transistor is electrically connected with the first electrode of the sixth transistor, and the third electrode of the fifth transistor is electrically connected with the second node.

[0022] The second electrode of the sixth transistor is electrically connected with the first node, and the third electrode of the sixth transistor is electrically connected with the first clock signal end.

[0023] In some possible implementation provided by the present disclosure, the shift register comprises:

[0024] A voltage stabilizing sub-circuit is electrically connected with the first node, a fourth node and a first voltage signal end, and the voltage stabilizing sub-circuit is configured to transmit the voltage from the first node to the fourth node according to the signal of the first voltage signal end.

[0025] In some possible implementation provided by the present disclosure, the voltage stabilizing sub-circuit comprises a seventh transistor.

[0026] The first electrode of the seventh transistor is electrically connected with the first node, the second electrode of the seventh transistor is electrically connected with the fourth node, and the third electrode of the seventh transistor is electrically connected with the first voltage signal terminal.

[0027] In some possible implementation provided by the present disclosure, the shift register comprises:

[0028] A cascading sub-circuit is electrically connected with the second node, the fourth node, the first clock signal terminal and the second voltage signal terminal, and the cascading sub-circuit is configured to output the cascading signal to the cascading output terminal in response to the voltages of the second node and the fourth node.

[0029] In some possible implementation provided by the present disclosure, the cascading sub-circuit comprises an eighth transistor, a ninth transistor and a second capacitor.

[0030] The first electrode of the eighth transistor is electrically connected with the first clock signal terminal, the second electrode of the eighth transistor is electrically connected with the cascading output terminal, and the third electrode of the eighth transistor is electrically connected with the fourth node.

[0031] The first electrode of the ninth transistor is electrically connected with the second voltage signal terminal, the second electrode of the ninth transistor is electrically connected with the cascading output terminal, and the third electrode of the ninth transistor is electrically connected with the second node.

[0032] The first electrode of the second capacitor is electrically connected with the fourth node, and the second electrode of the second capacitor is electrically connected with the cascading output terminal.

[0033] In some possible implementation provided by the present disclosure, the cascading sub-circuit comprises a third capacitor.

[0034] The first electrode of the third capacitor is electrically connected with the second voltage signal terminal, and the second electrode of the third capacitor is electrically connected with the cascading output terminal.

[0035] In some possible implementation provided by the present disclosure, the shift register comprises:

[0036] A pull-down sub-circuit is electrically connected with the third voltage signal terminal and the first node, and is configured to transmit the signal from the third voltage signal terminal to the first node.

[0037] In some possible implementation provided by the present disclosure, the third voltage signal end has a voltage signal with an amplitude greater than that of the first voltage signal end.

[0038] In some possible implementation provided by the present disclosure, the pull-down sub-circuit comprises a twelfth transistor.

[0039] The first pole of the twelfth transistor is electrically connected with the third voltage signal end, the second pole of the twelfth transistor is electrically connected with the first node, and the third pole of the twelfth transistor is electrically connected with the fourth node.

[0040] In some possible implementation provided by the present disclosure, the pull-down sub-circuit comprises a twelfth transistor.

[0041] The first pole of the twelfth transistor is electrically connected with the third voltage signal end, the second pole of the twelfth transistor is electrically connected with the first node, and the third pole of the twelfth transistor is electrically connected with the first node.

[0042] In some possible implementation provided by the present disclosure, the output circuit comprises a tenth transistor and an eleventh transistor.

[0043] The first pole of the tenth transistor is electrically connected with the reference signal end, the second pole of the tenth transistor is electrically connected with the driving output end, and the third pole of the tenth transistor is electrically connected with the first node.

[0044] The first pole of the eleventh transistor is electrically connected with the first voltage signal end, the second pole of the eleventh transistor is electrically connected with the driving output end, and the third pole of the eleventh transistor is electrically connected with the second node.

[0045] In some possible implementation provided by the present disclosure, the output circuit comprises a tenth transistor, an eleventh transistor and a thirteenth transistor.

[0046] The first pole of the tenth transistor is electrically connected with the reference signal end, the second pole of the tenth transistor is electrically connected with the driving output end, and the third pole of the tenth transistor is electrically connected with the second pole of the thirteenth transistor.

[0047] The first pole of the eleventh transistor is electrically connected with the first voltage signal end, the second pole of the eleventh transistor is electrically connected with the driving output end, and the third pole of the eleventh transistor is electrically connected with the second node.

[0048] The first pole of the thirteenth transistor is electrically connected with the first node, and the third pole of the thirteenth transistor is electrically connected with the first voltage signal end.

[0049] In some possible implementation provided by the present disclosure, the output circuit further includes a fourth capacitor.

[0050] The first electrode of the fourth capacitor is electrically connected with the first voltage signal terminal, and the second electrode of the fourth capacitor is electrically connected with the second node.

[0051] In some possible implementation provided by the present disclosure, the signal of the reference signal terminal and the signal of the first clock signal terminal are inverse signals.

[0052] In some possible implementation provided by the present disclosure, the signal of the first clock signal terminal and the signal of the second clock signal terminal are not active level signals at the same time.

[0053] Some embodiments of the present disclosure provide a display panel, comprising:

[0054] A substrate substrate including a display area and a non-display area;

[0055] The display area includes:

[0056] A plurality of sub-pixels;

[0057] A plurality of scan lines, a row of the sub-pixels in the plurality of sub-pixels corresponding to electrically connecting at least one of the scan lines in the plurality of scan lines;

[0058] The non-display area includes:

[0059] A gate drive circuit including a plurality of the above-mentioned shift register units, and a driving output terminal of each of the plurality of shift register units corresponding to electrically connecting at least one of the scan lines in the plurality of scan lines.

[0060] In some possible implementation provided by the present disclosure, further comprising: an input signal line electrically connected with the gate drive circuit and arranged in the non-display area, a first voltage signal line away from the display area, a first clock signal line and a second clock signal line;

[0061] Any one of the input signal line, the first voltage signal line away from the display area, the first clock signal line and the second clock signal line extends along a first direction, and the gate line extends along a second direction, and the first direction intersects the second direction.

[0062] In some possible implementation provided by the present disclosure, the input signal line, the first clock signal line, the second clock signal line and the first voltage signal line away from the display area are sequentially arranged in a direction close to the display area on the orthographic projection of the substrate substrate, and located on the side of the shift register unit away from the display area.

[0063] In some possible implementation modes provided by the present disclosure, the input signal line, the first clock signal line, the second clock signal line and the first voltage signal line away from the display area are arranged on the same layer.

[0064] In some possible implementation modes provided by the present disclosure, the input signal line, the first voltage signal line away from the display area, the first clock signal line and the second clock signal line are arranged in sequence along the direction close to the display area in the orthographic projection on the substrate, and are arranged on the side of the shift register unit away from the display area.

[0065] In some possible implementation modes provided by the present disclosure, the input signal line and the first voltage signal line away from the display area are arranged on the same layer, the first clock signal line and the second clock signal line are arranged on the same layer, and the input signal line, the first voltage signal line away from the display area and the first clock signal line, the second clock signal line are arranged on different layers.

[0066] In some possible implementation modes provided by the present disclosure, further comprising: a second voltage signal line electrically connected with the gate drive circuit and arranged on the non-display area, the second voltage signal line extending along the first direction.

[0067] In some possible implementation modes provided by the present disclosure, the second voltage signal line is arranged on the side of the first voltage signal line away from the display area close to the display area.

[0068] In some possible implementation modes provided by the present disclosure, further comprising: a third voltage signal line electrically connected with the gate drive circuit and arranged on the non-display area, the third voltage signal line extending along the first direction.

[0069] In some possible implementation modes provided by the present disclosure, the third voltage signal line is arranged on the side of the second voltage signal line close to the display area.

[0070] In some possible implementation modes provided by the present disclosure, further comprising: a third clock signal line, a fourth clock signal line and a first voltage signal line close to the display area electrically connected with the gate drive circuit and arranged on the non-display area, the third clock signal line, the fourth clock signal line and the first voltage signal line close to the display area extending along the first direction.

[0071] In some possible implementation modes provided by the present disclosure, any one of the third clock signal line and the fourth clock signal line is arranged on the side of the third voltage signal line close to the display area;

[0072] The first voltage signal line close to the display area is located on one side of any one of the third clock signal line and the fourth clock signal line close to the display area.

[0073] In some possible implementation modes provided by the present disclosure, the reference signal end of the i-th stage shift register unit is electrically connected to one of the third clock signal line and the fourth clock signal line, and the reference signal end of the i+1-th stage shift register unit is electrically connected to the other of the third clock signal line and the fourth clock signal line.

[0074] In some possible implementation modes provided by the present disclosure, the first clock signal end of the i-th stage shift register unit is electrically connected to one of the first clock signal line and the second clock signal line, and the second clock signal end of the i-th stage shift register unit is electrically connected to the other of the first clock signal line and the second clock signal line.

[0075] The signal line to which the first clock signal end of the adjacent shift register unit is connected is different from the signal line to which the second clock signal end of the adjacent shift register unit is connected.

[0076] In some possible implementation modes provided by the present disclosure, any one of the input signal line, the first voltage signal line, the second voltage signal line and the third voltage signal line has a width along the second direction smaller than that of any one of the first clock signal line, the second clock signal line, the third clock signal line and the fourth clock signal line.

[0077] In some possible implementation modes provided by the present disclosure, the shift register unit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a seventh transistor and a first capacitor.

[0078] At least part of any one of the first transistor, the second transistor, the third transistor, the fourth transistor, the seventh transistor and the first capacitor is located between the first voltage signal line and the second voltage signal line.

[0079] In some possible implementation modes provided by the present disclosure, the shift register unit comprises a fifth transistor, a sixth transistor, an eighth transistor, a ninth transistor, a twelfth transistor and a second capacitor.

[0080] At least part of any one of the fifth transistor, the sixth transistor, the eighth transistor, the ninth transistor, the twelfth transistor and the second capacitor is located between the second voltage signal line and the third voltage signal line.

[0081] In some possible implementation provided by the present disclosure, the active layer of the twelfth transistor extends along a first direction, at least part of any one of the first electrode and the second electrode of the twelfth transistor extends along a second direction, and the third electrode of the twelfth transistor extends along the second direction.

[0082] In some possible implementation provided by the present disclosure, the shift register unit comprises a tenth transistor, an eleventh transistor and a third capacitor.

[0083] At least part of any one of the tenth transistor, the eleventh transistor and the third capacitor is located on the side of the first voltage signal line close to the display area.

[0084] The orthogonal projection of the first voltage signal line close to the display area on the substrate substrate partially overlaps the orthogonal projection of the third capacitor on the substrate substrate.

[0085] In some possible implementation provided by the present disclosure, the channel width of the active layer of the tenth transistor is greater than the channel width of the active layer of the eighth transistor.

[0086] In some possible implementation provided by the present disclosure, the channel width of the active layer of the tenth transistor is not less than 90 microns.

[0087] In some possible implementation provided by the present disclosure, the channel width of the active layer of the eighth transistor is not greater than 50 microns.

[0088] In some possible implementation provided by the present disclosure, the channel width of the active layer of the eleventh transistor is greater than the channel width of the active layer of the ninth transistor.

[0089] In some possible implementation provided by the present disclosure, the channel width of the active layer of the eleventh transistor is not less than 90 microns.

[0090] In some possible implementation provided by the present disclosure, the channel width of the active layer of the ninth transistor is not greater than 50 microns.

[0091] The display device provided by some embodiments of the present disclosure comprises the display panel described above.

[0092] The driving method provided by some embodiments of the present disclosure comprises:

[0093] The input sub-circuit provides the signal of the input signal terminal to the first node under the control of the signal of the second clock signal terminal.

[0094] The first control sub-circuit controls the voltage of the second node under the control of the voltage of the first node and the signal of the first clock signal terminal.

[0095] a second control sub-circuit, under control of a voltage at the second node and a signal at the first clock signal terminal, providing a signal at the second voltage signal terminal to the first node;

[0096] a voltage stabilizing sub-circuit, under control of a signal at the first voltage signal terminal, providing a voltage at the first node to the fourth node;

[0097] a cascading sub-circuit, under control of voltages at the second node and the fourth node, providing a signal at the second voltage signal terminal or the first clock signal terminal to a cascading output terminal;

[0098] an output circuit, under control of voltages at the first node and the second node, providing a signal at the reference signal terminal or the first voltage signal terminal to a driving output terminal.

[0099] In some possible embodiments provided by the present disclosure, the shift register unit further comprises a pull-down sub-circuit.

[0100] The method further comprises: under control of a voltage at the first node or the fourth node, the pull-down sub-circuit providing a signal at the third voltage signal terminal to the first node.

[0101] Other aspects can become apparent from the following detailed description, when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0102] The accompanying drawings are included to provide a further understanding of the present application, and constitute a part of this application. The drawings illustrate embodiments of the present application and, together with the description, serve to explain the present application. However, the present application is not limited to the specific embodiments disclosed in the drawings.

[0103] FIG. 1 is a structural schematic diagram of a shift register unit according to some embodiments of the present disclosure;

[0104] FIG. 2 is another structural schematic diagram of a shift register unit according to some embodiments of the present disclosure;

[0105] FIG. 3 is an equivalent circuit diagram of a shift register unit according to some embodiments of the present disclosure;

[0106] FIG. 4 is yet another structural schematic diagram of a shift register unit according to some embodiments of the present disclosure;

[0107] FIG. 5 is a second equivalent circuit diagram of a shift register unit according to some embodiments of the present disclosure;

[0108] FIG. 6 is a third equivalent circuit diagram of a shift register unit according to some embodiments of the present disclosure;

[0109] FIG. 7 is a fourth equivalent circuit diagram of a shift register unit according to some embodiments of the present disclosure;

[0110] FIG. 8 is a fifth equivalent circuit diagram of a shift register unit according to an embodiment of the present disclosure;

[0111] FIG. 9 is a sixth equivalent circuit diagram of a shift register unit according to an embodiment of the present disclosure;

[0112] FIG. 10 is a signal timing simulation diagram of the shift register units of FIGS. 3, 5-9;

[0113] FIG. 11 is a signal comparison diagram of driving output terminals of different shift register units;

[0114] FIG. 12 is a structural schematic diagram of a display device;

[0115] FIG. 13 is a plan structural schematic diagram of a display substrate;

[0116] FIG. 14 is an equivalent circuit schematic diagram of a pixel driving circuit;

[0117] FIG. 15 is a working timing diagram of the pixel driving circuit of FIG. 14;

[0118] FIG. 16 is a cascade schematic diagram of a gate driving circuit of a display device;

[0119] FIG. 17 is a layout structural schematic diagram of a shift register unit according to an embodiment of the present disclosure;

[0120] FIG. 18 is a structural schematic diagram after forming a semiconductor layer pattern of FIG. 17;

[0121] FIG. 19 is a structural schematic diagram of a first conductive layer pattern of FIG. 17;

[0122] FIG. 20 is a structural schematic diagram after forming the first conductive layer pattern of FIG. 17;

[0123] FIG. 21 is a structural schematic diagram of a second conductive layer pattern of FIG. 17;

[0124] FIG. 22 is a structural schematic diagram after forming the second conductive layer pattern of FIG. 17;

[0125] FIG. 23 is a structural schematic diagram of a third insulating layer pattern of FIG. 17;

[0126] FIG. 24 is a structural schematic diagram after forming the third insulating layer pattern of FIG. 17;

[0127] FIG. 25 is a structural schematic diagram of a third conductive layer pattern of FIG. 17;

[0128] FIG. 26 is a structural schematic diagram after forming the third conductive layer pattern of FIG. 17;

[0129] FIG. 27 is a structural schematic diagram of a fourth insulating layer pattern of FIG. 17;​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​

[0130] Fig. 28 is a schematic view of the structure of Fig. 17 after forming a fourth insulating layer pattern;

[0131] Fig. 29 is a schematic view of the structure of Fig. 17 of a fourth conductive layer pattern;

[0132] Fig. 30 is a schematic view of the structure of Fig. 17 after forming a fourth conductive layer pattern;

[0133] Fig. 31 is a schematic view of the layout structure of another shift register unit according to an embodiment of the present disclosure;

[0134] Fig. 32 is a schematic view of the structure of Fig. 31 of a first conductive layer pattern;

[0135] Fig. 33 is a schematic view of the structure of Fig. 31 after forming a first conductive layer pattern;

[0136] Fig. 34 is a schematic view of the structure of Fig. 31 of a second conductive layer pattern;

[0137] Fig. 35 is a schematic view of the structure of Fig. 31 after forming a second conductive layer pattern;

[0138] Fig. 36 is a schematic view of the structure of Fig. 31 of a third insulating layer pattern;

[0139] Fig. 37 is a schematic view of the structure of Fig. 31 after forming a third insulating layer pattern;

[0140] Fig. 38 is a schematic view of the structure of Fig. 31 of a third conductive layer pattern;

[0141] Fig. 39 is a schematic view of the structure of Fig. 31 after forming a third conductive layer pattern;

[0142] Fig. 40 is a schematic view of the structure of Fig. 31 of a fourth insulating layer pattern;

[0143] Fig. 41 is a schematic view of the structure of Fig. 31 after forming a fourth insulating layer pattern;

[0144] Fig. 42 is a schematic view of the structure of Fig. 31 of a fourth conductive layer pattern;

[0145] Fig. 43 is a schematic view of the structure of Fig. 31 after forming a fourth conductive layer pattern. DETAILED DESCRIPTION

[0146] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will be combined with the drawings of the embodiments of the present disclosure to clearly and completely describe the technical solutions of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. And the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present disclosure.

[0147] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning understood by a person of ordinary skill in the art to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not represent any order, number or importance, but are only used to distinguish different components. "Include" or "contain" and similar words mean that the elements or objects before the words cover the elements or objects listed after the words and their equivalents, without excluding other elements or objects. "Electrically connected" or "connected" and similar words are not limited to physical or mechanical electrical connection, but can include electrical connection, whether direct or indirect.

[0148] It should be noted that the size and shape of each figure in the drawings do not reflect the true proportions, but only serve to illustrate the present disclosure. And the same or similar reference numbers represent the same or similar elements or elements with the same or similar functions throughout.

[0149] In the present specification, for the convenience of description, the words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like are used to describe the positional relationship of the components with reference to the drawings, only for the convenience of the description of the present specification and the simplification of the description, and do not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0150] In the present specification, "disposed in the same layer" means that two (or more) structures are patterned by the same patterning process to form structures, and the materials thereof can be the same or different. For example, the materials of the precursors forming the multiple structures disposed in the same layer are the same, and the final materials can be the same or different.

[0151] The triangles, rectangles, trapezoids, pentagons or hexagons in the specification are not strictly in the sense, and can be approximate triangles, rectangles, trapezoids, pentagons or hexagons, and there can be some small deformation caused by tolerance, and there can be guide angles, arc edges and deformation.

[0152] The display substrate includes a pixel driving circuit, a light emitting element, and a gate driving circuit, wherein the gate driving circuit is configured to provide a third electrode signal to the pixel driving circuit, so that the pixel driving circuit can drive the light emitting element to emit light. The display substrate uses a low temperature poly-silicon (LTPS) technology, which has the advantages of high resolution, high response speed, high brightness, high aperture ratio, etc. Although it is popular in the market, LTPS technology also has some defects, such as high production cost, high power consumption, etc. At this time, the low temperature polycrystalline oxide (LTPO) technology scheme emerges as the times require. Compared with the LTPS technology, the pixel driving circuit includes a low temperature poly-silicon transistor, and the LTPO technology includes a low temperature poly-silicon transistor and a metal oxide transistor in the pixel driving circuit. The metal oxide transistor has smaller leakage current, so that the pixel point reacts faster, and the display substrate adds an oxide layer, which can reduce the energy consumption required to excite the pixel point, thereby reducing the power consumption when the screen is displayed. The development of the LTPO technology requires the gate driving circuit to provide a third electrode signal that meets the potential requirement.

[0153] The shift register unit provided by the embodiments of the present disclosure, as shown in FIG. 1, includes:

[0154] The shift register 100 is configured to output a cascade signal through a cascade output terminal OUT1;

[0155] The output circuit 200 is electrically connected with the shift register 100, and the output circuit 200 is configured to control a driving output terminal OUT2 to output a gate scanning signal according to a signal of a reference signal terminal VREF and a signal of a first voltage signal terminal V1.

[0156] In some embodiments of the present disclosure, as shown in FIG. 2, the shift register 100 includes:

[0157] The input sub-circuit 110 is configured to provide a signal from an input signal terminal IN to a first node N1 according to a signal of a second clock signal terminal CK2;

[0158] a first control sub-circuit 120, where the first control sub-circuit 120 is electrically connected with the first clock signal terminal CK1, the second voltage signal terminal V2, the first node N1 and the second node N2 respectively, and is configured to control the voltage of the second node N2 according to the voltage of the first node N1 and the signal of the first clock signal terminal CK1;

[0159] a second control sub-circuit 130, configured to transmit the signal from the second voltage signal terminal V2 to the first node N1 according to the voltage of the second node N2 and the signal of the first clock signal terminal CK1;

[0160] a potential stabilizing circuit 140, configured to transmit the voltage from the first node N1 to the fourth node N4 according to the signal of the first voltage signal terminal V1;

[0161] a cascaded sub-circuit 150, configured to control the cascaded output terminal OUT1 to output a cascaded signal according to the voltages of the second node N2 and the fourth node N4.

[0162] In some embodiments of the present disclosure, as shown in FIG. 3, the input sub-circuit 110 includes a first transistor T1, where the first electrode of the first transistor T1 is electrically connected with the input signal terminal IN, the second electrode of the first transistor T1 is electrically connected with the first node N1, and the third electrode of the first transistor T1 is electrically connected with the second clock signal terminal CK2.

[0163] In some embodiments of the present disclosure, as shown in FIG. 3, the first control sub-circuit 120 includes a second transistor T2, a third transistor T3, a fourth transistor T4 and a first capacitor C1.

[0164] The first electrode of the second transistor T2 is electrically connected with the first clock signal terminal CK1, the second electrode of the second transistor T2 is electrically connected with the second node N2, and the third electrode of the second transistor T2 is electrically connected with the third node N3; the first electrode of the third transistor T3 is electrically connected with the second voltage signal terminal V2, the second electrode of the third transistor T3 is electrically connected with the third node N3, and the third electrode of the third transistor T3 is electrically connected with the first node N1; the first electrode of the fourth transistor T4 is electrically connected with the second voltage signal terminal V2, the second electrode of the fourth transistor T4 is electrically connected with the second node N2, and the third electrode of the fourth transistor T4 is electrically connected with the first node N1; the first electrode of the first capacitor C1 is electrically connected with the third node N3, and the second electrode of the first capacitor C1 is electrically connected with the first clock signal terminal CK1.

[0165] In some embodiments of the present disclosure, the first capacitor C1 can couple the signal of the first clock signal terminal to the third node N3.

[0166] In some embodiments of the present disclosure, as shown in FIG. 3, the second control sub-circuit 130 includes a fifth transistor T5 and a sixth transistor T6.

[0167] The first electrode of the fifth transistor T5 is electrically connected with the second voltage signal terminal V2, the second electrode of the fifth transistor T5 is electrically connected with the first electrode of the sixth transistor T6, the third electrode of the fifth transistor T5 is electrically connected with the second node N2; the second electrode of the sixth transistor T6 is electrically connected with the first node N1, and the third electrode of the sixth transistor T6 is electrically connected with the first clock signal terminal CK1.

[0168] In some embodiments of the present disclosure, as shown in FIG. 3, the voltage stabilizing sub-circuit 140 comprises a seventh transistor T7; wherein the first electrode of the seventh transistor T7 is electrically connected with the first node N1, the second electrode of the seventh transistor T7 is electrically connected with the fourth node N4, and the third electrode of the seventh transistor T7 is electrically connected with the first voltage signal terminal V1.

[0169] In some embodiments of the present disclosure, as shown in FIG. 3, the cascade sub-circuit 150 comprises an eighth transistor T8, a ninth transistor T9 and a second capacitor C2;

[0170] The first electrode of the eighth transistor T8 is electrically connected with the first clock signal terminal CK1, the second electrode of the eighth transistor T8 is electrically connected with the cascade output terminal OUT1, and the third electrode of the eighth transistor T8 is electrically connected with the fourth node N1; the first electrode of the ninth transistor T9 is electrically connected with the second voltage signal terminal V2, the second electrode of the ninth transistor T9 is electrically connected with the cascade output terminal OUT1, and the third electrode of the ninth transistor T9 is electrically connected with the second node N2; the first electrode of the second capacitor C2 is electrically connected with the fourth node N4, and the second electrode of the second capacitor C2 is electrically connected with the cascade output terminal OUT1.

[0171] In some embodiments of the present disclosure, the second capacitor C2 can maintain the voltage difference between the fourth node N4 and the cascade output terminal OUT1 signal.

[0172] In some embodiments of the present disclosure, as shown in FIG. 3, the output circuit 200 comprises a tenth transistor T10 and an eleventh transistor T11;

[0173] The first electrode of the tenth transistor T10 is electrically connected with the reference signal terminal VREF, the second electrode of the tenth transistor T10 is electrically connected with the driving output terminal OUT2, and the third electrode of the tenth transistor T10 is electrically connected with the first node N1; the first electrode of the eleventh transistor T11 is electrically connected with the first voltage signal terminal V1, the second electrode of the eleventh transistor T11 is electrically connected with the driving output terminal OUT2, and the third electrode of the eleventh transistor T11 is electrically connected with the second node N2.

[0174] In some embodiments of the present disclosure, as shown in FIG. 4, the shift register 100 further includes a pull-down sub-circuit 160 configured to transmit a signal from a third voltage signal terminal V3 to the first node N1. Wherein, the amplitude of the voltage signal of the third voltage signal terminal V3 is greater than the amplitude of the voltage signal of the first voltage signal terminal V1. That is, the absolute value of the voltage value of the signal of the third voltage signal terminal V3 is greater than the absolute value of the voltage value of the signal of the first voltage signal terminal V1.

[0175] In some embodiments of the present disclosure, as shown in FIG. 5, the pull-down sub-circuit 160 includes a twelfth transistor T12. Wherein, the first electrode of the twelfth transistor T12 is electrically connected with the third voltage signal terminal V3, the second electrode of the twelfth transistor T12 is electrically connected with the first node N1, and the third electrode of the twelfth transistor T12 is electrically connected with the fourth node N4.

[0176] In some embodiments of the present disclosure, as shown in FIG. 6, the pull-down sub-circuit 160 includes a twelfth transistor T12. Wherein, the first electrode of the twelfth transistor T12 is electrically connected with the third voltage signal terminal V3, the second electrode of the twelfth transistor T12 is electrically connected with the first node N1, and the third electrode of the twelfth transistor T12 is electrically connected with the first node N1.

[0177] The shift register unit provided by the present disclosure can pull down the signal of the first node N1 to a low-level signal with a lower voltage value, so that some transistors in the shift register unit can be fully turned on, and thus the voltage of the output signal of the shift register unit can reach a predetermined voltage, improving the driving capability of the shift register unit, ensuring the conduction capability of the transistors in the pixel driving circuit, and thus improving the performance of the pixel driving circuit and the display effect of the display substrate.

[0178] In some embodiments of the present disclosure, as shown in FIG. 7, the cascade sub-circuit 150 further includes a third capacitor C3. Wherein, the first electrode of the third capacitor C3 is electrically connected with the second voltage signal terminal V2, and the second electrode of the third capacitor C3 is electrically connected with the cascade output terminal OUT1.

[0179] In the present disclosure, the signal output by the cascade output terminal OUT1 is a cascade signal, that is, the signal line connected with the cascade output terminal OUT1 does not flow through the display area where the pixel driving circuit is located, that is, the load of the signal line connected with the cascade output terminal OUT1 is small, which is easily affected by the parasitic capacitance of some transistors in the output circuit, thereby causing the signal of the cascade output terminal OUT1 to fluctuate. The present disclosure can make the signal output by the cascade output terminal OUT1 more stable by setting the third capacitor C3, thereby improving the performance of the shift register unit.

[0180] In some embodiments of the present disclosure, as shown in FIG. 8, the output circuit 200 can further include a fourth capacitor C4, wherein a first electrode of the fourth capacitor C4 is electrically connected with the second node N2, and a second electrode of the fourth capacitor C4 is electrically connected with the first voltage signal terminal V1.

[0181] In some embodiments of the present disclosure, the fourth capacitor C4 can ensure the stability of the signal of the second node N2.

[0182] In some embodiments of the present disclosure, as shown in FIG. 9, the output circuit 200 further includes a thirteenth transistor T13, wherein a first electrode of the thirteenth transistor T13 is electrically connected with the first node N1, a second electrode of the thirteenth transistor T13 is electrically connected with the third electrode of the tenth transistor T10, and a third electrode of the thirteenth transistor T13 is electrically connected with the first voltage signal terminal V1.

[0183] In some embodiments of the present disclosure, the thirteenth transistor T13 is a continuously turned-on transistor, which can ensure the signal stability of the third electrode of the tenth transistor T10, avoid the output signal of the shift register unit from deviating greatly, and ensure the stability of the output signal of the shift register unit.

[0184] In some embodiments of the present disclosure, according to the characteristics of the transistors, the transistors can be divided into N-type transistors and P-type transistors. When the transistor is a P-type transistor, the on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltage), and the off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltage). When the transistor is an N-type transistor, the on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltage), and the off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltage).

[0185] In some embodiments of the present disclosure, the first transistor T1 to the thirteenth transistor T13 can all be P-type transistors.

[0186] In some embodiments of the present disclosure, the first voltage signal terminal V1 and the third voltage signal terminal V3 continuously provide low-level signals, and the second voltage signal terminal V2 continuously provides a high-level signal.

[0187] In some embodiments of the present disclosure, the amplitude of the voltage signal of the third voltage signal terminal V3 is greater than the amplitude of the voltage signal of the first voltage signal terminal V1.

[0188] In some embodiments of the present disclosure, the signal of any one of the reference signal terminal VREF, the first clock signal terminal CK1 and the second clock signal terminal CK2 can be a periodic pulse signal.

[0189] In some embodiments of the present disclosure, the signal of any one of the reference signal terminal VREF, the first clock signal terminal CK1 and the second clock signal terminal CK2 can be a clock signal.

[0190] In some embodiments of the present disclosure, the signal of the reference signal terminal VREF and the signal of the first clock signal terminal CK1 are complementary signals, or can not be complementary signals. When the signal of the reference signal terminal VREF and the signal of the first clock signal terminal CK1 are complementary signals, the signal of the reference signal terminal VREF is a valid level signal, and the signal of the first clock signal terminal CK1 is an invalid level signal; the signal of the reference signal terminal VREF is an invalid level signal, and the signal of the first clock signal terminal CK1 is a valid level signal.

[0191] In some embodiments of the present disclosure, the signal of the first clock signal terminal CK1 and the signal of the second clock signal terminal CK2 are not valid level signals at the same time. For example, when the signal of the first clock signal terminal CK1 is a valid level signal, the signal of the second clock signal terminal CK2 is an invalid level signal; when the signal of the second clock signal terminal CK2 is a valid level signal, the signal of the first clock signal terminal CK1 is an invalid level signal.

[0192] In some embodiments of the present disclosure, the signals of the cascade output terminal OUT1 and the driving output terminal OUT2 can be single pulse signals, and the signals of the cascade output terminal OUT1 and the driving output terminal OUT2 can be complementary signals, i.e., when the signal of the cascade output terminal OUT1 is a high level signal, the signal of the driving output terminal OUT2 is a low level signal; when the signal of the cascade output terminal OUT1 is a low level signal, the signal of the driving output terminal OUT2 is a high level signal.

[0193] In some embodiments of the present disclosure, the cascade output terminal OUT1 is configured to output a cascade signal, and the cascade signal can be a low level signal; the driving output terminal OUT2 is configured to output a gate scanning signal, and the gate scanning signal is a high level signal.

[0194] FIG. 10 is a signal timing simulation diagram of the shift register unit provided in FIGS. 3, 5-9. FIG. 10 is described by taking an example in which all the transistors in the shift register unit are P-type transistors. It can be understood that at this time, the first voltage signal terminal V1 provides a first low level signal VGL1, the second voltage signal terminal V2 provides a high level signal VGH, and the third voltage signal terminal V3 provides a second low level signal VGL2. At this time, the second low level signal VGL2 provided by the third voltage signal terminal V3 is lower than the first low level signal VGL1 provided by the first voltage signal terminal V1.

[0195] In some embodiments of the present disclosure, for the shift register unit provided in FIG. 3, FIG. 5 to FIG. 9, the seventh transistor T7 is always turned on due to the third electrode of the seventh transistor T7 being electrically connected to the first power supply terminal V1.

[0196] In combination with FIG. 5 and FIG. 10, the working process of controlling the shift register unit provided in FIG. 5 includes the following stages:

[0197] In the first stage t1, i.e., the input stage, the input signal terminal IN, the reference signal terminal VREF, and the second clock signal terminal CK2 provide low-level signals, and the first clock signal terminal CK1 provides a high-level signal. At this time, the first transistor T1 is turned on, and the low-level signal provided by the input signal terminal IN is written to the first node N1. Since the first voltage signal terminal V1 continuously provides a low-level signal VGL1, the seventh transistor T7 is continuously turned on. At this time, the low-level signal of the first node N1 is written to the fourth node N4 via the seventh transistor T7, the eighth transistor T8 is turned on, and the high-level signal provided by the first clock signal terminal CK1 is written to the cascade output terminal OUT1. The low-level signal of the first node N1 is written to the third electrode of the tenth transistor T10 via the thirteenth transistor T13, the tenth transistor T10 is turned on, and the low-level signal provided by the reference signal terminal VREF is written to the driving output terminal OUT2. At the same time, the twelfth transistor T12 is turned on, the second low-level signal VGL2 provided by the third voltage signal terminal V3 is written to the first node N1, and the signal of the first node N1 is maintained as a low-level signal. The third transistor T3 and the fourth transistor T4 are turned on, and the high-level signal VGH provided by the second voltage signal terminal V2 is written to the second node N2 and the third node N3, respectively. At this time, the second transistor T2, the fifth transistor T5, the ninth transistor T9, and the eleventh transistor T11 are all turned off. The first clock signal terminal CK1 provides a high-level signal, and the sixth transistor T6 is turned off. The first capacitor C1 can couple the high-level signal provided by the first clock signal terminal CK1 to the third node N3, and the second capacitor C2 can maintain the voltage difference between the fourth node N4 and the cascade output terminal OUT1. At this time, the cascade output terminal OUT1 outputs the high-level signal provided by the first clock signal terminal CK1, and the driving output terminal OUT2 outputs the low-level signal provided by the reference signal terminal VREF.

[0198] In the second stage t2, i.e. the output stage, the first clock signal terminal CK1 provides a low level signal, the input signal terminal IN, the reference signal terminal VREF and the second clock signal terminal CK2 provide high level signals. At this time, the first transistor T1 is off, the second capacitor C2 can discharge, and the voltage of the first node N1 is maintained at a low level. Since the first voltage signal terminal V1 continuously provides a low level signal VGL1, the seventh transistor T7 is continuously turned on. At this time, the low level signal of the first node N1 is written to the fourth node N4 through the seventh transistor T7, the eighth transistor T8 is turned on, and the low level signal provided by the first clock signal terminal CK1 is written to the cascade output terminal OUT1. The low level signal of the first node N1 is written to the third electrode of the tenth transistor T10, the tenth transistor T10 is turned on, and the high level signal provided by the reference signal terminal VREF is written to the driving output terminal OUT2. At the same time, the twelfth transistor T12 is turned on, the second low level signal VGL2 provided by the third voltage signal terminal V3 is written to the first node N1, and the voltage of the first node N1 is further pulled down, so that the eighth transistor T8 and the tenth transistor T10 are completely turned on. The third transistor T3 and the fourth transistor T4 are turned on, and the high level signal VGH provided by the second voltage signal terminal V2 is written to the second node N2 and the third node N3 respectively, at this time, the second transistor T2, the fifth transistor T5, the ninth transistor T9 and the eleventh transistor T11 are all off. The third transistor T3 is turned on, and the high level signal VGH provided by the second voltage signal terminal V2 is written to the third node N3, at this time, the first clock signal terminal CK1 will still be coupled to the third node N3 through the first capacitor C1, but the voltage of the third node N3 is still controlled by the second voltage signal terminal V2. In the output stage, the cascade output terminal OUT1 outputs the low level signal provided by the first clock signal terminal CK1, and the driving output terminal OUT2 outputs the high level signal provided by the reference signal terminal VREF.

[0199] In the third stage t3, the input signal terminal IN and the first clock signal terminal CK1 provide high level signals, the reference signal terminal VREF provides a low level signal, and the second clock signal terminal CK2 first maintains a high level signal and then jumps to a low level signal. In the stage when the second clock signal terminal CK2 maintains a high level signal, the first transistor T1 is cut off, the first node N1 is in a floating state, and the voltage at the first node N1 is a low level at this time. The low level signal is written into the fourth node N4 through the continuously conducting seventh transistor T7, the eighth transistor T8 and the tenth transistor T10 are turned on, the high level signal provided by the first clock signal terminal CK1 is written into the cascade output terminal OUT1, and the low level signal provided by the reference signal terminal VREF is written into the driving output terminal OUT2. The third transistor T3 and the fourth transistor T4 are turned on, and the high level VGH signal provided by the second voltage signal terminal V2 is written into the second node N2 and the third node N3 respectively. At this time, the second transistor T2, the fifth transistor T5, the ninth transistor T9 and the eleventh transistor T11 are all cut off. The first clock signal terminal CK1 provides a high level signal, and the sixth transistor T6 is cut off. Therefore, in the stage when the second clock signal terminal CK2 maintains a high level signal, the cascade output terminal OUT1 outputs the high level signal provided by the first clock signal terminal CK1, and the driving output terminal OUT2 outputs the low level signal provided by the reference signal terminal VREF. When the second clock signal terminal CK2 jumps to a low level signal, the first transistor T1 is turned on, and the high level signal provided by the input signal terminal IN is written into the first node N1. At this time, the third transistor T3 and the fourth transistor T4 are cut off, and the high level signal of the first node N1 is written into the fourth node N4 through the continuously conducting seventh transistor T7. The eighth transistor T8, the tenth transistor T10 and the twelfth transistor T12 are cut off. Since the first clock signal terminal CK1 jumps from a low level signal to a high level signal, and due to the coupling effect of the first capacitor C1, the voltage at the third node N3 remains a high level signal, and the second transistor T2 is cut off. The second node N2 is in a floating state, and the voltage at the second node N2 is a high level at this time. The fifth transistor T5, the ninth transistor T9 and the eleventh transistor T11 are cut off. Therefore, in the stage when the second clock signal terminal CK2 jumps to a low level signal, the cascade output terminal OUT1 and the driving output terminal OUT2 are both in a floating state. At this time, the cascade output terminal OUT1 outputs a high level signal, and the driving output terminal OUT2 outputs a low level signal.

[0200] In the fourth stage t4, the input signal terminal IN, the reference signal terminal VREF and the second clock signal terminal CK2 provide high level signals, and the first clock signal terminal CK1 provides a low level signal. At this time, the first transistor T1 is turned off, the first node N1 is in a floating state, and the voltage at the first node N1 is high. The third transistor T3 and the fourth transistor T4 are turned off. The high level signal at the first node N1 is written to the fourth node N4 through the continuously turned-on seventh transistor T7, and the eighth transistor T8, the tenth transistor T10 and the twelfth transistor T12 are turned off. Since the first clock signal terminal CK1 jumps from high level to low level, and due to the coupling effect of the first capacitor C1, the voltage at the third node N3 is low at this time, and the second transistor T2 is turned on. The low level signal provided by the first clock signal terminal CK1 is written to the second node N2 through the second transistor T2, and the fifth transistor T5, the ninth transistor T9 and the eleventh transistor T11 are turned on at this time. The sixth transistor T6 is also turned on at this time. The high level signal VGH provided by the second voltage signal terminal V2 is written to the first node N1 through the fifth transistor T5 and the sixth transistor T6, and is written to the cascade output terminal OUT1 through the ninth transistor T9. The low level signal VGL1 provided by the first voltage signal terminal V1 is written to the driving output terminal OUT2 through the eleventh transistor T11. In this stage, the cascade output terminal OUT1 outputs the high level signal provided by the second voltage signal terminal V2, and the driving output terminal OUT2 outputs the low level signal provided by the first voltage signal terminal V1.

[0201] The working process of the shift register unit includes a plurality of third stages t3 and fourth stages t4, and the third stages t3 and the fourth stages t4 work alternately.

[0202] The shift register unit provided in FIG. 3 is different from the shift register unit provided in FIG. 5 in that the shift register unit provided in FIG. 5 includes the twelfth transistor T12, and the shift register unit provided in FIG. 3 does not include the twelfth transistor T12. In addition, the working process of the shift register unit provided in FIG. 3 is the same as the working process of the shift register unit provided in FIG. 5.

[0203] The twelfth transistor T12 in the present disclosure can be configured such that the first node N1 can be pulled low to the signal of the third voltage signal terminal V3 with a lower voltage value, thereby improving the on degree of the eighth transistor T8 and the tenth transistor T10, so that the eighth transistor T8 and the tenth transistor T10 can be fully turned on.

[0204] Figure 6 provides a shift register unit different from the shift register unit provided in Figure 5 in that the node to which the third electrode of the twelfth transistor T12 is connected is different. Figure 5 illustrates that the third electrode of the twelfth transistor T12 is connected to the fourth node N4, while Figure 6 illustrates that the third electrode of the twelfth transistor T12 is connected to the first node N1. Since the signals of the first node N1 and the fourth node N4 are high signals at the same time or low signals at the same time, the twelfth transistor T12 in the shift register unit provided in Figure 5 and the shift register unit provided in Figure 6 is turned on at the same time or turned off at the same time. Therefore, the working process of the shift register unit provided in Figure 5 is the same as the working process of the shift register unit provided in Figure 6.

[0205] Figure 7 provides a shift register unit different from the shift register unit provided in Figure 5 in that the shift register unit provided in Figure 7 further comprises a third capacitor C3. The third capacitor C3 can be used to maintain the stability of the signal of the cascade output end OUT1, and will not have other effects on the working process of the shift register unit. Therefore, the working process of the shift register unit provided in Figure 5 is the same as the working process of the shift register unit provided in Figure 7.

[0206] Figure 8 provides a shift register unit different from the shift register unit provided in Figure 5 in that the shift register unit provided in Figure 8 further comprises a fourth capacitor C4. The fourth capacitor C4 can be used to maintain the stability of the voltage of the second node N2, and will not have other effects on the working process of the shift register unit. Therefore, the working process of the shift register unit provided in Figure 8 is the same as the working process of the shift register unit provided in Figure 7.

[0207] Figure 9 provides a shift register unit different from the shift register unit provided in Figure 8 in that the shift register unit provided in Figure 9 further comprises a thirteenth transistor T13. Since the third electrode of the thirteenth transistor T13 is electrically connected to the first voltage signal end V1, the thirteenth transistor T13 is continuously turned on. Therefore, the thirteenth transistor T13 can be equivalent to a piece of wire, and will not affect the working process of other transistors of the shift register unit. Therefore, the working process of the shift register unit provided in Figure 9 is the same as the working process of the shift register unit provided in Figure 5.

[0208] It can be understood that, in some embodiments of the present disclosure, the shift register unit can comprise the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4; or can comprise the first capacitor C1 and the second capacitor C2; or can comprise the first capacitor C1, the second capacitor C2 and the third capacitor C3; or can comprise the first capacitor C1, the second capacitor C2 and the fourth capacitor C4. Those skilled in the art can set it according to actual needs.

[0209] OUT2-0 refers to the signal output by the driving output end in the shift register unit provided in FIG. 3 according to the present application, and OUT2-M refers to the signal output by the driving output end in any one of the shift register units provided in FIGS. 5 to 9 according to the present application. As shown in FIG. 11, in other working stages except the output stage, the voltage value of the signal of OUT2-M is lower than the voltage value of the signal of OUT2-0, and in the output stage, the rising edge duration of the signal of OUT2-M is less than the rising edge duration of the signal of OUT2-0, that is, the shift register unit provided in some embodiments of the present disclosure can pull down the voltage value of the signal output by the driving output end, and the performance of the shift register unit is improved.

[0210] The present disclosure further provides a driving method of a shift register unit, configured to drive the shift register unit, and the driving method of the shift register unit can include the following steps:

[0211] In step 100, the input sub-circuit provides the signal of the input signal end to the first node under the control of the signal of the second clock signal end.

[0212] In step 200, the first control sub-circuit controls the voltage of the second node under the control of the voltage of the first node and the signal of the first clock signal end.

[0213] In step 300, the second control sub-circuit provides the signal of the second voltage signal end to the first node under the control of the voltage of the second node and the signal of the first clock signal end.

[0214] In step 400, the voltage stabilizing sub-circuit provides the voltage of the first node to the fourth node under the control of the signal of the first voltage signal end.

[0215] In step 500, the cascading sub-circuit provides the signal of the second voltage signal end or the first clock signal end to the cascading output end under the control of the voltages of the second node and the fourth node.

[0216] In step 600, the output circuit provides the signal of the reference signal end or the first voltage signal end to the driving output end under the control of the voltages of the first node and the second node.

[0217] The shift register unit is the shift register unit provided in any one of the foregoing embodiments, and the implementation principle and implementation effect are similar, which will not be described here.

[0218] In some embodiments of the present disclosure, the shift register unit can further include a pull-down sub-circuit, and the driving method of the shift register unit can further include that the pull-down sub-circuit provides the signal of the third voltage signal end to the first node under the control of the voltage of the first node or the fourth node.

[0219] The display device can include a timing controller, a data signal driver, a scan signal driver, a light emission signal driver, and a display substrate. The display substrate includes an array of pixels. The timing controller is connected to the data signal driver, the scan signal driver, and the light emission signal driver. The data signal driver is connected to a plurality of data signal lines (D1 to Dn). The scan signal driver is connected to a plurality of scan signal lines (S1 to Sm). The light emission signal driver is connected to a plurality of light emission signal lines (E1 to Eo). The array of pixels can include a plurality of sub-pixels Pij. i and j can be natural numbers. At least one sub-pixel Pij can include a circuit unit and a light emitting device connected to the circuit unit. The circuit unit can include a pixel driving circuit. The pixel driving circuit can be electrically connected to a scan signal line, a light emission signal line, and a data signal line. In some embodiments, the timing controller can provide a grayscale value and a control signal suitable for the specification of the data signal driver to the data signal driver, a clock signal, a scan start signal, and the like suitable for the specification of the scan signal driver to the scan signal driver, and a clock signal, an emission stop signal, and the like suitable for the specification of the light emission signal driver to the light emission signal driver. The data signal driver can generate a data voltage to be provided to the data signal lines D1, D2, D3, …, and Dn using the grayscale value and the control signal received from the timing controller. For example, the data signal driver can sample the grayscale value using the clock signal and apply a data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixels. n can be a natural number. The scan signal driver can generate a scan signal to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan signal driver can sequentially provide the scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan signal driver can be configured in the form of a shift register unit and can generate the scan signal in a manner that sequentially transfers the scan start signal provided in the form of an on-level pulse to a next stage circuit under the control of the clock signal. m can be a natural number. The light emission signal driver can generate an emission signal to be provided to the light emission signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emission signal driver can sequentially provide the emission signal having an off-level pulse to the light emission signal lines E1 to Eo. For example, the light emission signal driver can be configured in the form of a shift register unit and can generate the emission signal in a manner that sequentially transfers the emission stop signal provided in the form of an off-level pulse to a next stage circuit under the control of the clock signal. o can be a natural number.

[0220] In some embodiments of the present disclosure, the display device can be a liquid crystal display (LCD) or an organic light emitting diode (OLED) display device. The display device can be a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any product or component having a display function.

[0221] FIG. 13 is a schematic diagram of a planar structure of a display substrate. As shown in FIG. 13, the display substrate can include a plurality of pixel units P arranged in a matrix manner, each of the plurality of pixel units P including a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and at least one third sub-pixel P3 emitting a third color light, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each including a pixel driving circuit and a light emitting device. The pixel driving circuit in each of the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 is electrically connected to a scan signal line, a data signal line, and a light emitting signal line, respectively, and is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light emitting signal line, and control the pixel driving circuit to output a corresponding current. The light emitting device in each of the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 is electrically connected to the pixel driving circuit of the sub-pixel in which the light emitting device is located, and is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which the light emitting device is located.

[0222] In some embodiments of the present disclosure, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 can be a green sub-pixel (G) emitting green light. In some embodiments of the present disclosure, the shape of the sub-pixel can be rectangular, diamond, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal side-by-side manner, a vertical side-by-side manner, or a triangular manner, which is not limited in the present disclosure.

[0223] In some embodiments of the present disclosure, one pixel unit can include three sub-pixels, and the three sub-pixels can be arranged in a horizontal side-by-side manner, a vertical side-by-side manner, or a triangular manner, which is not limited in the present disclosure. FIG. 13 is described by way of example in a horizontal side-by-side manner.

[0224] In some embodiments of the present disclosure, one pixel unit can further include four sub-pixels, which can be one first sub-pixel, one second sub-pixel, and two third sub-pixels. The four sub-pixels can be arranged in a horizontal parallel, vertical parallel, or square manner, which is not limited in the present disclosure.

[0225] In some embodiments of the present disclosure, the light-emitting device can be an organic electroluminescent diode (OLED) including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked.

[0226] In some embodiments of the present disclosure, the organic light-emitting layer can include a hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL) stacked. In some embodiments of the present disclosure, the hole injection layer of all sub-pixels can be a common layer connected together, the electron injection layer of all sub-pixels can be a common layer connected together, the hole transport layer of all sub-pixels can be a common layer connected together, the electron transport layer of all sub-pixels can be a common layer connected together, the hole block layer of all sub-pixels can be a common layer connected together, the emitting layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated, and the electron block layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated.

[0227] In some embodiments of the present disclosure, the display substrate is an LTPO display substrate.

[0228] FIG. 14 is an equivalent circuit schematic diagram of a pixel driving circuit. In some embodiments of the present disclosure, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in FIG. 14, the pixel driving circuit can include 7 transistors (first transistor M1 to seventh transistor M7) and 1 capacitor C.

[0229] As shown in FIG. 14, the first electrode of the first transistor M1 is electrically connected with the first initial signal line INIT1, the second electrode of the first transistor M1 is electrically connected with the first node Q1, and the third electrode of the first transistor M1 is electrically connected with the reset signal line Reset; the first electrode of the second transistor M2 is electrically connected with the first node Q1, the second electrode of the second transistor M2 is electrically connected with the third node Q3, and the third electrode of the second transistor M2 is electrically connected with the second scan signal line Gate2; the first electrode of the third transistor M3 is electrically connected with the second node Q2, the second electrode of the third transistor M3 is electrically connected with the third node Q3, and the third electrode of the third transistor M3 is electrically connected with the first node Q1; the first electrode of the fourth transistor M4 is electrically connected with the data signal line Data, the second electrode of the fourth transistor M4 is electrically connected with the second node Q2, and the third electrode of the fourth transistor M4 is electrically connected with the first scan signal line Gate1; the first electrode of the fifth transistor M5 is electrically connected with the high-level power supply line VDD, the second electrode of the fifth transistor M5 is electrically connected with the second node Q2, and the third electrode of the fifth transistor M5 is electrically connected with the light-emitting signal line EM; the first electrode of the sixth transistor M6 is electrically connected with the third node Q3, the second electrode of the sixth transistor M6 is electrically connected with the fourth node Q4, and the third electrode of the sixth transistor M6 is electrically connected with the light-emitting signal line EM; the first electrode of the seventh transistor M7 is electrically connected with the second initial signal line INIT2, the second electrode of the seventh transistor M7 is electrically connected with the fourth node Q4, and the third electrode of the seventh transistor M7 is electrically connected with the first scan signal line Gate1; and the first plate of the capacitor C is electrically connected with the first node Q1, and the second plate of the capacitor C is electrically connected with the high-level power supply line VDD.

[0230] In some embodiments of the present disclosure, the first transistor M1 to the seventh transistor M7 in the pixel driving circuit can adopt a low-temperature polysilicon thin film transistor, or can adopt an oxide thin film transistor, or can simultaneously adopt a low-temperature polysilicon thin film transistor and an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor adopts low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor adopts oxide semiconductor (Oxide). The low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. Integrating the low-temperature polysilicon thin film transistor and the oxide thin film transistor on one display substrate forms an LTPO display substrate, which can take advantage of both and can realize low-frequency driving, reduce power consumption, and improve display quality.

[0231] In some embodiments of the present disclosure, the first transistor M1 and the second transistor M2 are opposite to the transistor types of the third transistor M3 to the seventh transistor M7. For example, the first transistor M1 and the second transistor M2 can be N-type transistors, and the third transistor M3 to the seventh transistor M7 can be P-type transistors.

[0232] In some embodiments of the present disclosure, the first transistor M1 and the second transistor M2 can be oxide transistors, and the third transistor M3 to the seventh transistor M7 can be low-temperature polysilicon transistors.

[0233] In some embodiments of the present disclosure, the voltage value of the signal of the first initial signal line INIT1 is constant and is a direct current signal, and the voltage value of the signal of the first initial signal line INIT1 can be -3V.

[0234] In some embodiments of the present disclosure, the voltage value of the signal of the second initial signal line INIT2 is constant and is a direct current signal, and the voltage value of the signal of the second initial signal line INIT2 can be 0V.

[0235] In some embodiments of the present disclosure, the light emitting device L can be electrically connected to the fourth node Q4 and the low-level power supply line VSS, respectively.

[0236] In some embodiments of the present disclosure, the high-level power supply line VDD continuously provides a high-level signal, and the low-level power supply line VSS continuously provides a low-level signal.

[0237] FIG. 15 is a timing diagram of the pixel driving circuit corresponding to FIG. 14. The working process of the pixel driving circuit shown in FIG. 14 in the display stage is described below to illustrate the exemplary embodiments of the present disclosure. FIG. 15 is described by taking the first transistor M1 and the second transistor M2 as N-type transistors and the third transistor M3 to the seventh transistor M7 as P-type transistors as an example. The pixel driving circuit in FIG. 26 includes the first transistor M1 to the seventh transistor M7, one capacitor C, and eight signal lines (a data signal line Data, a first scan signal line Gate1, a second scan signal line Gate2, a reset signal line Reset, a first initial signal line INIT1, a second initial signal line INIT2, a light emitting signal line EM, and a high-level power supply line VDD).

[0238] In combination with FIG. 14 and FIG. 15, the working process of the pixel driving circuit can include:

[0239] In the first stage P1, referred to as the initialization stage, the signal of the reset signal line Reset is a high-level signal, the first transistor M1 is turned on, and the signal of the first initial signal line INIT1 is written to the first node Q1 through the turned-on first transistor M1 to initialize (i.e., reset) the first node Q1 and clear the pre-stored voltage in the first node Q1, thereby completing the initialization.

[0240] The second stage P2, referred to as a data writing stage or threshold compensation stage, the first scan signal line Gate1 is a low level signal, the second scan signal line Gate2 is a high level signal, and the data signal line Data outputs a data voltage. In this stage, the first node Q1 is a low level signal, thus the third transistor M3 is turned on. The signal of the first scan signal line Gate1 is a low level signal, thus the fourth transistor M4 is turned on and the seventh transistor M7 is turned on, the signal of the second scan signal line Gate2 is a high level signal, thus the second transistor M2 is turned on, and the data voltage output by the data signal line Data is provided to the first node N1 through the turned-on fourth transistor M4, the second node Q2, the turned-on third transistor M3, the third node Q3, and the turned-on second transistor M2, and the difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor M3 is charged to the capacitor C until the voltage of the first node Q1 is Vd-|Vth|, Vd is the data voltage output by the data signal line Data, Vth is the threshold voltage of the third transistor M3, the seventh transistor M7 is turned on, and the signal of the second initial signal line INIT2 is written to the fourth node Q4 through the turned-on seventh transistor M7 to initialize (i.e., reset) the first electrode of the light emitting device L and empty the pre-stored voltage in the light emitting device L, thus completing the initialization.

[0241] The third stage P3, referred to as a light emitting stage, the signal of the emitting signal line EM is a low level signal, the fifth transistor M5 and the sixth transistor M6 are turned on, and the power voltage output by the high level power supply line VDD is provided to the first electrode of the light emitting device L through the turned-on fifth transistor M5, the third transistor M3, and the sixth transistor M6 to drive the light emitting device L to emit light.

[0242] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (the driving transistor) is determined by the voltage difference between the third electrode and the first electrode of the third transistor M3. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor M3 is:

[0243] I=K*(Vgs-Vth)2=K*[(Vdd-Vd+|Vth|)-Vth]2=K*(Vdd-Vd)2

[0244] wherein I is the driving current flowing through the third transistor M3, i.e., the driving current for driving the light emitting device L, K is a constant, Vgs is the voltage difference between the third electrode and the first electrode of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output by the data signal line Data, and Vdd is the power voltage output by the high level power supply line VDD.

[0245] The display substrate provided by the embodiments of the present disclosure can include a substrate, a sub-pixel, a gate line and a gate driving circuit disposed on the substrate, the substrate is provided with a display area and a non-display area, the gate driving circuit is located in the non-display area, the sub-pixel and the gate line are located in the display area, and the gate line is electrically connected with the sub-pixel and the gate driving circuit respectively.

[0246] In some embodiments of the present disclosure, the sub-pixel includes a pixel driving circuit and a light emitting device. When the pixel driving circuit is the pixel driving circuit provided in FIG. 14, the gate line can include at least one of a reset signal line, a first scan signal line, a second scan signal line and a light emitting signal line.

[0247] FIG. 16 is a schematic diagram of a cascade of the gate driving circuit. As shown in FIG. 16, the cascade output end OUT1 of the i-th shift register unit GOA(i) is connected with the signal input end IN of the i+1-th shift register unit GOA(i+1), 1≤i<N, and N is the total number of stages of the shift register units.

[0248] In some embodiments of the present disclosure, as shown in FIG. 16, the clock signal is input into the second clock signal end CK2 and the first clock signal end CK1 of the plurality of shift register units through the first clock signal line CLK1 and the second clock signal line CLK2 respectively.

[0249] In some embodiments of the present disclosure, as shown in FIG. 16, the clock signal is input into the reference signal end VREF of the plurality of shift register units through the third clock signal line CLK3 and the fourth clock signal line CLK4 respectively.

[0250] In some embodiments of the present disclosure, as shown in FIG. 16, the driving output end OUT2 of the shift register unit can be electrically connected with the gate line.

[0251] In some embodiments of the present disclosure, as shown in FIG. 16, the second clock signal end CK2 of the i-th stage shift register unit is electrically connected with one of the first clock signal line CLK1 and the second clock signal line CLK2, and the first clock signal end CK1 of the i-th stage shift register unit is electrically connected with the other of the first clock signal line CLK1 and the second clock signal line CLK2; the signal line connected with the second clock signal end of the adjacent shift register unit is different, and the signal line connected with the first clock signal end of the adjacent shift register unit is different. For example, the second clock signal end CK2 of the odd-numbered stage shift register unit can be electrically connected with the first clock signal line CLK1, the first clock signal end CK1 of the odd-numbered stage shift register unit can be electrically connected with the second clock signal line CLK2, the second clock signal end CK2 of the even-numbered stage shift register unit can be electrically connected with the second clock signal line CLK2, the first clock signal end CK1 of the even-numbered stage shift register unit can be electrically connected with the first clock signal line CLK1, or the second clock signal end CK2 of the odd-numbered stage shift register unit can be electrically connected with the second clock signal line CLK2, the first clock signal end CK1 of the odd-numbered stage shift register unit can be electrically connected with the first clock signal line CLK1, the second clock signal end CK2 of the even-numbered stage shift register unit can be electrically connected with the first clock signal line CLK1, and the first clock signal end CK1 of the even-numbered stage shift register unit can be electrically connected with the second clock signal line CLK2. FIG. 16 is an example of the second clock signal end CK2 of the odd-numbered stage shift register unit being electrically connected with the first clock signal line CLK1, the first clock signal end CK1 of the odd-numbered stage shift register unit being electrically connected with the second clock signal line CLK2, the second clock signal end CK2 of the even-numbered stage shift register unit being electrically connected with the second clock signal line CLK2, and the first clock signal end CK1 of the even-numbered stage shift register unit being electrically connected with the first clock signal line CLK1.

[0252] In some embodiments of the present disclosure, as shown in FIG. 16, the reference signal end VREF of the i-th stage shift register unit is electrically connected to one of the third clock signal line CLK3 and the fourth clock signal line CLK4, and the reference signal end VREF of the i+1-th stage shift register unit is electrically connected to the other one of the third clock signal line CLK3 and the fourth clock signal line CLK4. For example, the reference signal end VREF of the odd-numbered stage shift register unit is electrically connected to the third clock signal line CLK3, the reference signal end VREF of the even-numbered stage shift register unit is electrically connected to the fourth clock signal line CLK4, or the reference signal end VREF of the odd-numbered stage shift register unit is electrically connected to the fourth clock signal line CLK4, and the reference signal end VREF of the even-numbered stage shift register unit is electrically connected to the third clock signal line CLK3. FIG. 16 illustrates an example in which the reference signal end VREF of the odd-numbered stage shift register unit is electrically connected to the third clock signal line CLK3, and the reference signal end VREF of the even-numbered stage shift register unit is electrically connected to the fourth clock signal line CLK4.

[0253] In some embodiments of the present disclosure, the substrate can be a rigid substrate or a flexible substrate, wherein the rigid substrate can be, but is not limited to, one or more of glass, conductive foil; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers.

[0254] In some embodiments of the present disclosure, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked. The material of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc., and the material of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx) etc. for improving the water and oxygen resistance of the substrate, and the first and second inorganic material layers are also called barrier layers, and the material of the semiconductor layer can be amorphous silicon (a-si). In some embodiments of the present disclosure, taking the laminated structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, the preparation process can include: first coating a layer of polyimide on a glass carrier plate, and after curing into a film, a first flexible (PI1) layer is formed; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating a layer of polyimide on the amorphous silicon layer, and after curing into a film, a second flexible (PI2) layer is formed; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, and the preparation of the substrate is completed.

[0255] In some embodiments of the present disclosure, FIG. 17 is a structural schematic diagram of a display substrate. FIG. 17 is described taking the shift register unit provided in FIG. 8 as an example. As shown in FIGS. 16-17, the display substrate can further include an input signal line STV, a first clock signal line CLK1, a second clock signal line CLK2, a first voltage signal line VGL1, a second voltage signal line VGH, and a third voltage signal line VGL2 disposed on the substrate and located in the non-display area. The number of the first voltage signal line VGL1 is at least one.

[0256] In some embodiments of the present disclosure, the input signal end IN of the first-stage shift register unit GOA(1) is electrically connected with the input signal line STV, the first voltage signal end V1 of the i-th stage shift register unit is electrically connected with the first voltage signal line VGL1, the second voltage signal end V2 of the i-th stage shift register unit is electrically connected with the second voltage signal line VGH, and the third voltage signal end V3 of the i-th stage shift register unit is electrically connected with the third voltage signal line VGL2.

[0257] In some embodiments of the present disclosure, any one of the input signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, the first voltage signal line VGL1, the second voltage signal line VGH, and the third voltage signal line VGL2 extends along a first direction D1, and the gate line extends along a second direction D2, the first direction D1 intersecting the second direction D2.

[0258] In some embodiments of the present disclosure, as shown in FIG. 17, the input signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, and the first voltage signal line VGL1 are arranged in sequence along a direction close to the display area, and are located on a side of the shift register unit away from the display area.

[0259] In some embodiments of the present disclosure, as shown in FIG. 17, the shift register unit includes a plurality of transistors, the second voltage signal line VGH is located on a side of the first voltage signal line VGL1 close to the display area, and is located between the plurality of transistors of the shift register unit.

[0260] In some embodiments of the present disclosure, as shown in FIG. 17, the third voltage signal line VGL2 is located on a side of the second voltage signal line VGH close to the display area, and the orthographic projection of the third voltage signal line VGL2 on the substrate overlaps with part of the orthographic projection of the shift register unit on the substrate.

[0261] In some embodiments of the present disclosure, as shown in FIG. 17, the shift register unit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a seventh transistor T7, and a first capacitor C1. At least part of any one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the seventh transistor T7, and the first capacitor C1 is located between the first voltage signal line VGL1 and the second voltage signal line VGH.

[0262] In some embodiments of the present disclosure, as shown in FIG. 17, the shift register unit includes a fifth transistor T5, a sixth transistor T6, an eighth transistor T8, a ninth transistor T9, a twelfth transistor T12, and a second capacitor C2. At least part of any one of the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, and the second capacitor C2 is located on a side of the second voltage signal line VGH close to the display area.

[0263] In some embodiments of the present disclosure, as shown in FIG. 17, the orthographic projection of the third voltage signal line VGL2 on the substrate partially overlaps with the orthographic projection of the eighth transistor T8, the ninth transistor T9, and the second capacitor C2 on the substrate.

[0264] In some embodiments of the present disclosure, as shown in FIG. 17, the display substrate can further include: a third clock signal line CLK3 and a fourth clock signal line CLK4 disposed on the base substrate and located in the non-display area, any one of the third clock signal line CLK3 and the fourth clock signal line CLK4 extending along the first direction D1.

[0265] In some embodiments of the present disclosure, as shown in FIG. 17, the number of the first voltage signal lines VGL1 is two, the first voltage signal line VGL1 close to the display area is located on one side of any one of the third clock signal line CLK3 and the fourth clock signal line CLK4 close to the display area, and the first voltage signal line VGL1 away from the display area is located on one side of any one of the first clock signal line CLK1 and the second clock signal line CLK2 close to the display area and on one side of the second voltage signal line VGH away from the display area.

[0266] In some embodiments of the present disclosure, as shown in FIG. 17, the shift register unit further includes: a tenth transistor T10, an eleventh transistor T11 and a fourth capacitor C4. Wherein at least part of any one of the tenth transistor T10, the eleventh transistor T11 and the fourth capacitor C4 is located on one side of the first voltage signal line VGL1 close to the display area.

[0267] In some embodiments of the present disclosure, as shown in FIG. 17, the orthographic projection of the first voltage signal line VGL1 close to the display area on the base substrate and the orthographic projection of the fourth capacitor C4 on the base substrate partially overlap.

[0268] In some embodiments of the present disclosure, as shown in FIG. 17, the active layer T121 of the twelfth transistor T12 extends along the first direction D1, any one of the first electrode and the second electrode of the twelfth transistor T12 extends along the second direction D2, and the third electrode T82 of the twelfth transistor T12 at least partially extends along the second direction D2.

[0269] In some embodiments of the present disclosure, as shown in FIG. 17, the width of any one of the two first voltage signal lines VGL1, the second voltage signal line VGH and the third voltage signal line VGL2 along the second direction D2 is less than the width of any one of the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4 along the second direction D2.

[0270] In some embodiments of the present disclosure, since the signal of the clock signal line is an alternating current signal, the width of any one of the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4 along the second direction D2 is wider, which can effectively reduce the load of the signal line.

[0271] In some embodiments of the present disclosure, the channel width of the active layer of the tenth transistor T10 is greater than the channel width of the active layer of the eighth transistor T8.

[0272] In some embodiments of the present disclosure, the channel width of the active layer of the tenth transistor T10 is not less than 90 microns. Illustratively, the channel width of the active layer of the tenth transistor T10 can be about 100 microns.

[0273] In some embodiments of the present disclosure, the channel length of the active layer of the tenth transistor T10 can be about 3.5 microns, and the channel width-length ratio of the active layer of the tenth transistor T10 can be about 100 / 3.5.

[0274] In some embodiments of the present disclosure, the channel width of the active layer of the eighth transistor T8 is not greater than 50 microns. Illustratively, the channel width of the active layer of the eighth transistor T8 can be about 25 microns.

[0275] In some embodiments of the present disclosure, the channel length of the active layer of the eighth transistor T8 can be about 3.5 microns, and the channel width-length ratio of the active layer of the eighth transistor T8 can be about 25 / 3.5.

[0276] In some embodiments of the present disclosure, the channel width of the active layer of the eleventh transistor T11 is greater than the channel width of the active layer of the fifth transistor.

[0277] In some embodiments of the present disclosure, the channel width of the active layer of the eleventh transistor T11 is not less than 90 microns. Illustratively, the channel width of the active layer of the eleventh transistor T11 can be about 100 microns.

[0278] In some embodiments of the present disclosure, the channel length of the active layer of the eleventh transistor T11 can be about 3.5 microns, and the channel width-length ratio of the active layer of the eleventh transistor T11 can be about 100 / 3.5.

[0279] In some embodiments of the present disclosure, the channel width of the active layer of the ninth transistor T9 is not greater than 50 microns. Illustratively, the channel width of the active layer of the ninth transistor T9 can be about 25 microns.

[0280] In some embodiments of the present disclosure, the channel length of the active layer of the ninth transistor T9 can be about 3.5 microns, and the channel width-length ratio of the active layer of the ninth transistor T9 can be about 25 / 3.5.

[0281] In some embodiments of the present disclosure, the display substrate can further include: a driving structure layer disposed on the substrate substrate; the driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer which are sequentially stacked on the substrate substrate; the shift register unit includes: a plurality of transistors and a plurality of capacitors, any one capacitor includes: a first electrode plate and a second electrode plate;

[0282] The semiconductor layer at least includes: an active layer of the plurality of transistors of the at least one shift register unit;

[0283] The first conductive layer at least includes: a third electrode of the plurality of transistors of the at least one shift register unit and a first electrode plate of the plurality of capacitors;

[0284] The second conductive layer at least includes: a second electrode plate of the plurality of capacitors of the at least one shift register unit;

[0285] The third conductive layer at least includes: an initial signal line, a first clock signal line, a second clock signal line, a first power supply line, a second power supply line, a third clock signal line, a fourth clock signal line and a first electrode and a second electrode of the plurality of transistors of the at least one shift register unit;

[0286] The fourth conductive layer at least includes: a third power supply line.

[0287] In some embodiments of the present disclosure, the driving structure layer can further include: a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer and a planar layer, wherein the first insulating layer is between the semiconductor layer and the first conductive layer, the second insulating layer is between the first conductive layer and the second conductive layer, the third insulating layer is between the second conductive layer and the third conductive layer, the fourth insulating layer is between the third conductive layer and the fourth conductive layer, the fifth insulating layer is on a side of the fourth conductive layer away from the substrate substrate, and the planar layer is on a side of the fifth insulating layer away from the substrate substrate.

[0288] The preparation process of the display substrate is exemplarily illustrated below. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and the like for metal material, inorganic material or transparent conductive material, and includes coating organic material, mask exposure and development and the like for organic material. The deposition can adopt any one or more of sputtering, evaporation, chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating and inkjet printing, and the etching can adopt any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a certain material on a substrate prepared by deposition, coating or other processes. If the "thin film" does not need a patterning process in the entire preparation process, the "thin film" can also be referred to as a "layer". If the "thin film" needs a patterning process in the entire preparation process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0289] The first step is to form a semiconductor pattern on the substrate, including: depositing a semiconductor thin film on the substrate, and patterning the semiconductor thin film by a patterning process to form a semiconductor layer pattern. As shown in FIG. 18, FIG. 18 is a schematic diagram after the semiconductor layer pattern of FIG. 17 is formed.

[0290] In some embodiments of the present disclosure, as shown in FIG. 18, the semiconductor layer can include: an active layer T1a of a first transistor to an active layer T12a of a twelfth transistor of at least one shift register unit.

[0291] In some embodiments of the present disclosure, as shown in FIG. 18, the active layer T1a of the first transistor and the active layer T7a of the seventh transistor are integrally formed; the active layer T2a of the second transistor and the active layer T4a of the fourth transistor are integrally formed; the active layer T5a of the fifth transistor and the active layer T6a of the sixth transistor are integrally formed; the active layer T10a of the tenth transistor and the active layer T11a of the eleventh transistor are integrally formed. The active layer T3a of the third transistor, the active layer T8a of the eighth transistor, the active layer T9a of the ninth transistor and the active layer T12a of the twelfth transistor can be separately arranged.

[0292] In some embodiments of the present disclosure, as shown in FIG. 18, the active layer T1a of the first transistor (also the active layer T7a of the seventh transistor) is located at a side far away from the display area, the active layer T2a of the second transistor (also the active layer T4a of the fourth transistor) is located at a side of the active layer T1a of the first transistor close to the display area, the active layer T3a of the third transistor is located at a side of the active layer T1a of the first transistor close to the display area, and the active layer T3a of the third transistor is located at a side of the active layer T2a of the second transistor (also the active layer T4a of the fourth transistor) of the current stage shift register unit close to the next stage shift register unit. The active layer T5a of the fifth transistor (also the active layer T6a of the sixth transistor) and the active layer T12a of the twelfth transistor are arranged along the first direction D1 and located at a side of the active layer T2a of the second transistor (also the active layer T4a of the fourth transistor) close to the display area. The active layer T9a of the ninth transistor and the active layer T8a of the eighth transistor are arranged along the first direction D1 and located at a side of the active layer T5a of the fifth transistor (also the active layer T6a of the sixth transistor) close to the display area. Among them, the active layer T9a of the ninth transistor of the current stage shift register unit is located at a side of the active layer T8a of the eighth transistor of the current stage shift register unit close to the next stage shift register unit. The active layer T10a of the tenth transistor (also the active layer T11a of the eleventh transistor) is located at a side of the active layer T8a close to the display area.

[0293] In some embodiments of the present disclosure, as shown in FIG. 18, the active layer T1a of the first transistor (also the active layer T7a of the seventh transistor), the active layer T5a of the fifth transistor (also the active layer T6a of the sixth transistor), the active layer T12a of the twelfth transistor, the active layer T8a of the eighth transistor, the active layer T9a of the ninth transistor, and the active layer T10a of the tenth transistor (also the active layer T11a of the eleventh transistor) are all in the shape of a strip and extend along the first direction D1. The active layer T2a of the second transistor (also the active layer T4a of the fourth transistor) and the active layer T3a of the third transistor are in the shape of a strip and extend along the second direction D2.

[0294] In some embodiments of the present disclosure, as shown in FIG. 18, the active layer of each transistor can include a first region, a second region, and a channel region between the first region and the second region. Among them, the first region and the second region will be conductorized after the subsequent formation of the first conductive layer, so they are also called conductive regions. In some embodiments of the present disclosure, the second region T1a-2 of the active layer T1a of the first transistor can simultaneously serve as the first region T7a-1 of the active layer T7a of the seventh transistor, the second region T2a-2 of the active layer T2a of the second transistor can simultaneously serve as the second region T4a-2 of the active layer T4a of the fourth transistor, the second region T5a-2 of the active layer T5a of the fifth transistor can simultaneously serve as the first region T6a-1 of the active layer T6a of the sixth transistor, and the second region T10a-2 of the active layer T10a of the tenth transistor can simultaneously serve as the second region T11a-2 of the active layer T11a of the eleventh transistor. The first region T1a-1 of the active layer T1a of the first transistor, the first region T2a-1 of the active layer T2a of the second transistor, the first region T3a-1 of the active layer T3a of the third transistor, the second region T3a-2 of the active layer T3a of the third transistor, the first region T4a-1 of the active layer T4a of the fourth transistor, the first region T5a-1 of the active layer T5a of the fifth transistor, the second region T6a-2 of the active layer T6a of the sixth transistor, the second region T7a-2 of the active layer T7a of the seventh transistor, the first region T8a-1 of the active layer T8a of the eighth transistor, the second region T8a-2 of the active layer T8a of the eighth transistor, the first region T9a-1 of the active layer T9a of the ninth transistor, the second region T9a-2 of the active layer T9a of the ninth transistor, the first region T10a-1 of the active layer T10a of the tenth transistor, and the first region T11a-1 of the active layer T11a of the eleventh transistor can be separately provided.

[0295] The second step of forming the first conductive pattern includes: depositing a first insulating thin film and a first conductive thin film on the substrate on which the aforementioned pattern is formed, patterning the first insulating thin film and the first conductive thin film by a patterning process, forming a first insulating layer pattern and a first conductive pattern disposed on the first insulating layer pattern, as shown in FIGS. 19 and 20. FIG. 19 is a schematic diagram of the first conductive layer pattern in FIG. 17, and FIG. 20 is a schematic diagram of FIG. 17 after the first conductive layer pattern is formed. In some embodiments of the present disclosure, the first conductive layer can be referred to as the first gate metal (GATE1) layer.

[0296] In some embodiments of the present disclosure, as shown in FIGS. 19 and 20, the first conductive layer pattern can include: the third pole T1b of the first transistor to the third pole T12b of the twelfth transistor of at least one stage of shift register unit, the first plate C1-1 of the first capacitor, the first plate C2-1 of the second capacitor, the first plate C4-1 of the fourth capacitor, and the first connection L1.

[0297] In some embodiments of the present disclosure, as shown in FIGS. 19 and 20, the third electrode T2b of the second transistor and the first plate C1-1 of the first capacitor are an integrally formed structure. The third electrode T3b of the third transistor, the third electrode T4b of the fourth transistor, and the third electrode T10b of the tenth transistor are an integrally formed structure. The third electrode T5b of the fifth transistor, the third electrode T9b of the ninth transistor, the third electrode T11b of the eleventh transistor, and the first plate C4-1 of the fourth capacitor are an integrally formed structure. The third electrode T8b of the eighth transistor, the third electrode T12b of the twelfth transistor, and the first plate C2-1 of the second capacitor are an integrally formed structure. The third electrode T1b of the first transistor, the third electrode T6b of the sixth transistor, the third electrode T7b of the seventh transistor, and the first connection L1 can be separately provided.

[0298] In some embodiments of the present disclosure, as shown in FIGS. 19 and 20, the third electrode T1b of the first transistor includes a first third electrode T1b-1 and a second third electrode T1b-2. The first third electrode T1b-1 of the first transistor is in the shape of a In some embodiments of the present disclosure, as shown in FIGS. 19 and 20, the third electrode T1b of the first transistor includes a first third electrode T1b-1 and a second third electrode T1b-2. The first third electrode T1b-1 of the first transistor is in the shape of a

[0299] In some embodiments of the present disclosure, as shown in FIGS. 19 and 20, the first plate C1-1 of the first capacitor can be in the shape of a square, the third electrode T2b of the second transistor can be in the shape of a strip and extend along the first direction D1. The third electrode T2b of the second transistor is located on the side of the first plate C1-1 of the first capacitor close to the upper stage of the shift register unit.

[0300] In some embodiments of the present disclosure, as shown in FIGS. 19 and 20, the first plate C2-1 of the second capacitor can be in the shape of a In some embodiments of the present disclosure, as shown in FIGS. 19 and 20, the first plate C2-1 of the second capacitor can be in the shape of a

[0301] In some embodiments of the present disclosure, as shown in FIGS. 19 and 20, the first plate C4-1 of the fourth capacitor can be square-shaped and extend along the first direction D1, and the third electrode T11b of the eleventh transistor comprises a plurality of first branch segments T11b-1 extending along the second direction D2, and the plurality of first branch segments T11b-1 are arranged along the first direction D1. The third electrode T9b of the ninth transistor is located on a side of the first plate C4-1 of the fourth capacitor away from the display area, and the third electrode T5b of the fifth transistor is located on a side of the third electrode T9b of the ninth transistor away from the display area. FIGS. 19 and 20 are illustrative examples in which the third electrode T11b of the eleventh transistor comprises two first branch segments T11b-1.

[0302] In some embodiments of the present disclosure, as shown in FIGS. 19 and 20, the third electrode T10b of the tenth transistor comprises a first connecting segment T10b-1 and a plurality of second branch segments T10b-2. The first connecting segment T10b-1 extends along the first direction D1, the plurality of second branch segments T10b-2 extend along the second direction D2, and the plurality of second branch segments T10b-2 are arranged along the first direction D1. The first connecting segment T10b-1 corresponds to a “comb back”, and the plurality of second branch segments T10b-2 correspond to “comb teeth”. FIGS. 19 and 20 are illustrative examples in which the third electrode T10b of the tenth transistor comprises four second branch segments T10b-2. The third electrode T3b of the third transistor and the third electrode T4b of the fourth transistor are located on a side of the third electrode T10b of the tenth transistor away from the display area, and the third electrode T3b of the third transistor is located on a side of the third electrode T4b of the fourth transistor close to the next stage of the shift register unit, and the third electrode T3b of the third transistor and the third electrode T4b of the fourth transistor at least partially extend along the first direction D1.

[0303] In some embodiments of the present disclosure, as shown in FIGS. 19 and 20, the third electrode T6b of the sixth transistor, the third electrode T7b of the seventh transistor, and the first connecting portion L1 can be strip-shaped and at least partially extend along the second direction D2.

[0304] In some embodiments of the present disclosure, as shown in FIGS. 19 and 20, the first third pole portion T1b-1 and the second third pole portion T1b-2 of the third pole T1b of the first transistor are respectively arranged across the active layer T1a of the first transistor; the third pole T2b of the second transistor is arranged across the active layer T2a of the second transistor; the third pole T3b of the third transistor is arranged across the active layer T3a of the third transistor; the third pole T4b of the fourth transistor is arranged across the active layer T4a of the fourth transistor; the third pole T5b of the fifth transistor is arranged across the active layer T5a of the fifth transistor; the third pole T6b of the sixth transistor is arranged across the active layer T6a of the sixth transistor; the third pole T7b of the seventh transistor is arranged across the active layer T7a of the seventh transistor; the third pole T8b of the eighth transistor is arranged across the active layer T8a of the eighth transistor; the third pole T9b of the ninth transistor is arranged across the active layer T9a of the ninth transistor; the plurality of second branch segments T10b-2 of the third pole T10b of the tenth transistor are arranged across the active layer T10a of the tenth transistor; and the plurality of first branch segments T11b-1 of the third pole T11b of the eleventh transistor are arranged across the active layer T11a of the eleventh transistor. That is, the extension direction of the third pole of at least one transistor intersects (perpendicularly intersects) the extension direction of the active layer.

[0305] In some embodiments of the present disclosure, the present process further includes a conductorization process. The conductorization process is performed after the formation of the first conductive layer. The conductorization process uses the third pole of the plurality of transistors to shield the corresponding semiconductor layer (i.e., the region where the semiconductor layer and the third pole overlap) as the channel region of the transistor. The semiconductor layer not shielded by the first conductive layer is processed into a conductorized layer to form an electrode connection portion of the transistor.

[0306] The third step of forming a second conductive layer pattern includes: depositing a second insulating thin film and a second conductive thin film on the substrate with the aforementioned pattern, and patterning the second insulating thin film and the second conductive thin film by a patterning process to form a second insulating layer pattern and a second conductive layer pattern on the second insulating layer pattern. As shown in FIGS. 21 and 22, FIG. 21 is a schematic diagram of the second conductive layer pattern in FIG. 17, and FIG. 22 is a schematic diagram of FIG. 17 after the formation of the second conductive layer pattern. In some embodiments of the present disclosure, the second conductive layer can be referred to as a second gate metal (GATE2) layer.

[0307] In some embodiments of the present disclosure, as shown in FIGS. 21 and 22, the second conductive layer pattern can include: the second plate C1-2 of the first capacitor, the second plate C2-2 of the second capacitor, the second plate C4-2 of the fourth capacitor, the second connection portion L2, the third connection portion L3, the fourth connection portion L4, the fifth connection portion L5, and the sixth connection portion L6 of at least one stage of the shift register unit.

[0308] In some embodiments of the present disclosure, as shown in FIGS. 21 and 22, the second plate C1-2 of the first capacitor, the third connection L3, the fourth connection L4, and the fifth connection L5 can be an integrated structure. The second plate C2-2 of the second capacitor, the second plate C4-2 of the fourth capacitor, the second connection L2, and the sixth connection L6 can be separately provided.

[0309] In some embodiments of the present disclosure, as shown in FIGS. 21 and 22, the shape of the second plate C1-2 of the first capacitor can be square, and the orthographic projection of the second plate C1-2 on the substrate substrate at least partially overlaps the orthographic projection of the first plate C1-1 of the first capacitor on the substrate substrate.

[0310] In some embodiments of the present disclosure, as shown in FIGS. 21 and 22, the shape of the second plate C2-2 of the second capacitor can be square, and the orthographic projection of the second plate C2-2 on the substrate substrate at least partially overlaps the orthographic projection of the first plate C2-1 of the second capacitor on the substrate substrate.

[0311] In some embodiments of the present disclosure, as shown in FIGS. 21 and 22, the shape of the second plate C4-2 of the fourth capacitor can be square, and the orthographic projection of the second plate C4-2 on the substrate substrate at least partially overlaps the orthographic projection of the first plate C4-1 of the fourth capacitor on the substrate substrate.

[0312] In some embodiments of the present disclosure, as shown in FIGS. 21 and 22, the shape of the second connection L2, the fourth connection L4, and the fifth connection L5 can be strip-shaped, and at least partially extend along the second direction D2. The shape of the third connection L3 and the sixth connection L6 can be strip-shaped, and at least partially extend along the first direction D1.

[0313] The fourth step is to form a third insulating layer pattern, including: depositing a third insulating thin film on the substrate substrate formed with the aforementioned pattern, and patterning the third insulating thin film by a patterning process to form a third insulating layer pattern covering the aforementioned structure, the third insulating layer being provided with a plurality of via patterns, as shown in FIGS. 23 and 24, FIG. 23 is a schematic diagram of the first via pattern in FIG. 17, and FIG. 24 is a schematic diagram after the third insulating layer pattern is formed in FIG. 17.

[0314] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the plurality of via patterns can include: a first via V1 to a thirty-seventh via V37.

[0315] ​In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the first via V1 is located within the range of the third electrode of the first transistor on the substrate substrate, and the second insulating layer under the first via V1 is etched to expose the surface of the third electrode of the first transistor. The first via V1 is configured to electrically connect one of the first clock signal line and the second clock signal line formed in the subsequent process to the third electrode of the first transistor.

[0316] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the second via V2 is located within the range of the first region of the active layer of the first transistor on the substrate substrate, and the first insulating layer and the second insulating layer under the second via V2 are etched to expose the surface of the first region of the active layer of the first transistor. The second via V2 is configured to electrically connect the first electrode of the first transistor to the first region of the active layer of the first transistor through the via formed in the subsequent process.

[0317] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the third via V3 is located within the range of the second connection L2 on the substrate substrate, and the third via V3 exposes the surface of the second connection L2. The third via V3 is configured to electrically connect the first electrode of the first transistor of the current stage shift register unit to the second connection L2 through the via formed in the subsequent process.

[0318] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the fourth via V4 is located within the range of the second connection L2 on the substrate substrate, and the fourth via V4 exposes the surface of the second connection L2. The fourth via V4 is configured to electrically connect the second electrode of the eighth transistor (also the second electrode of the ninth transistor) of the previous stage shift register unit to the second connection L2 through the via formed in the subsequent process.

[0319] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the fifth via V2 is located within the range of the second region of the active layer of the first transistor on the substrate substrate, and the first insulating layer and the second insulating layer under the fifth via V2 are etched to expose the surface of the second region of the active layer of the first transistor. The fifth via V5 is configured to electrically connect the second electrode of the first transistor (also the first electrode of the seventh transistor) to the second region of the active layer of the first transistor through the via formed in the subsequent process.

[0320] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the sixth via V6 is located within the range of the orthogonal projection of the third electrode of the seventh transistor on the substrate substrate, and the second insulating layer under the sixth via V6 is etched to expose the surface of the third electrode of the seventh transistor. The sixth via V6 is configured to electrically connect the first voltage signal line formed in the subsequent process to the third electrode of the seventh transistor.

[0321] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the seventh via V7 is located within the range of the orthogonal projection of the second region of the active layer of the seventh transistor on the substrate substrate, and the first insulating layer and the second insulating layer under the seventh via V7 are etched to expose the surface of the second region of the active layer of the seventh transistor. The seventh via V7 is configured to electrically connect the second electrode of the seventh transistor formed in the subsequent process to the second region of the active layer of the seventh transistor through the via.

[0322] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the eighth via V8 is located within the range of the orthogonal projection of the fifth connection L5 on the substrate substrate, and the eighth via V8 exposes the surface of the fifth connection L5. The eighth via V8 is configured to electrically connect the other one of the first clock signal line and the second clock signal line formed in the subsequent process to the second plate of the first capacitor.

[0323] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the ninth via V9 is located within the range of the orthogonal projection of the third connection L3 on the substrate substrate, and the ninth via V9 exposes the surface of the third connection L3. The ninth via V9 is configured to electrically connect the first electrode of the second transistor formed in the subsequent process to the second plate of the first capacitor.

[0324] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the tenth via V10 is located within the range of the orthogonal projection of the first region of the active layer of the second transistor on the substrate substrate, and the first insulating layer and the second insulating layer under the tenth via V10 are etched to expose the surface of the first region of the active layer of the second transistor. The tenth via V10 is configured to electrically connect the first electrode of the second transistor formed in the subsequent process to the first region of the active layer of the second transistor through the via.

[0325] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the orthogonal projection of the eleventh via V11 on the substrate substrate is located within the range of the orthogonal projection of the second region of the active layer of the second transistor on the substrate substrate, and the first insulating layer and the second insulating layer under the eleventh via V11 are etched away, exposing the surface of the second region of the active layer of the second transistor. The eleventh via V11 is configured to enable the second electrode of the second transistor (also the second electrode of the fourth transistor) formed in a subsequent process to be electrically connected to the second region of the active layer of the second transistor through the via.

[0326] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the orthogonal projection of the twelfth via V12 on the substrate substrate is located within the range of the orthogonal projection of the third electrode of the second transistor on the substrate substrate, and the second insulating layer under the twelfth via V12 is etched away, exposing the surface of the third electrode of the second transistor. The twelfth via V12 is configured to enable the second electrode of the third transistor formed in a subsequent process to be electrically connected to the third electrode of the second transistor (also the first electrode plate of the first capacitor).

[0327] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the orthogonal projection of the thirteenth via V13 on the substrate substrate is located within the range of the orthogonal projection of the second region of the active layer of the third transistor on the substrate substrate, and the first insulating layer and the second insulating layer under the thirteenth via V13 are etched away, exposing the surface of the second region of the active layer of the third transistor. The thirteenth via V13 is configured to enable the second electrode of the third transistor formed in a subsequent process to be electrically connected to the second region of the active layer of the third transistor through the via.

[0328] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the orthogonal projection of the fourteenth via V14 on the substrate substrate is located within the range of the orthogonal projection of the first region of the active layer of the third transistor on the substrate substrate, and the first insulating layer and the second insulating layer under the fourteenth via V14 are etched away, exposing the surface of the first region of the active layer of the third transistor. The fourteenth via V14 is configured to enable the first electrode of the third transistor formed in a subsequent process to be electrically connected to the first region of the active layer of the third transistor through the via.

[0329] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the orthogonal projection of the fifteenth via V15 on the substrate substrate is located within the range of the orthogonal projection of the third electrode of the third transistor on the substrate substrate, and the second insulating layer under the fifteenth via V15 is etched away, exposing the surface of the third electrode of the third transistor. The fifteenth via V15 is configured to enable the first electrode of the seventh transistor formed in a subsequent process to be electrically connected to the third electrode of the third transistor (also the third electrode of the fourth transistor) through the via.

[0330] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the orthogonal projection of the sixteenth via V16 on the substrate substrate is located within the orthogonal projection of the third electrode of the third transistor on the substrate substrate, and the second insulating layer under the sixteenth via V16 is etched to expose the surface of the third electrode of the third transistor. The sixteenth via V16 is configured to enable the second electrode of the sixth transistor formed in a subsequent process to be electrically connected to the third electrode of the third transistor (also the third electrode of the fourth transistor) through the via. At the same time, the sixteenth via V16 is also configured to enable the second electrode of the twelfth transistor formed in a subsequent process to be electrically connected to the third electrode of the third transistor (also the third electrode of the fourth transistor) through the via.

[0331] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the orthogonal projection of the seventeenth via V17 on the substrate substrate is located within the orthogonal projection of the second region of the active layer of the sixth transistor on the substrate substrate, and the first insulating layer and the second insulating layer under the seventeenth via V17 are etched to expose the surface of the second region of the active layer of the sixth transistor. The seventeenth via V17 is configured to enable the second electrode of the sixth transistor formed in a subsequent process to be electrically connected to the second region of the active layer of the sixth transistor through the via.

[0332] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the orthogonal projection of the eighteenth via V18 on the substrate substrate is located within the orthogonal projection of the third electrode of the sixth transistor on the substrate substrate, and the second insulating layer under the eighteenth via V18 is etched to expose the surface of the third electrode of the sixth transistor. The eighteenth via V18 is configured to enable the first electrode of the eighth transistor formed in a subsequent process to be electrically connected to the third electrode of the sixth transistor.

[0333] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the orthogonal projection of the nineteenth via V19 on the substrate substrate is located within the orthogonal projection of the first region of the active layer of the fifth transistor on the substrate substrate, and the first insulating layer and the second insulating layer under the nineteenth via V19 are etched to expose the surface of the first region of the active layer of the fifth transistor. The nineteenth via V19 is configured to enable the first electrode of the fifth transistor formed in a subsequent process to be electrically connected to the first region of the active layer of the fifth transistor through the via.

[0334] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the orthogonal projection of the twentieth via V20 on the substrate substrate is located within the orthogonal projection of the second region of the active layer of the eighth transistor on the substrate substrate, and the first insulating layer and the second insulating layer under the twentieth via V20 are etched to expose the surface of the second region of the active layer of the eighth transistor. The twentieth via V20 is configured to enable the second electrode of the eighth transistor formed in a subsequent process to be electrically connected to the second region of the active layer of the eighth transistor through the via.

[0335] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the orthogonal projection of the twenty-first via V21 on the substrate substrate is located within the range of the orthogonal projection of the first region of the active layer of the eighth transistor on the substrate substrate, and the first insulating layer and the second insulating layer under the twenty-first via V21 are etched away, exposing the surface of the first region of the active layer of the eighth transistor. The twenty-first via V21 is configured to enable the first electrode of the eighth transistor formed in the subsequent process to be electrically connected to the first region of the active layer of the eighth transistor through the via.

[0336] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the orthogonal projection of the twenty-second via V22 on the substrate substrate is located within the range of the orthogonal projection of the fourth connection L4 on the substrate substrate, and the twenty-second via V22 exposes the surface of the fourth connection L4. The twenty-second via V22 is configured to enable the first electrode of the eighth transistor formed in the subsequent process to be electrically connected to the second plate of the first capacitor through the via.

[0337] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the orthogonal projection of the twenty-third via V23 on the substrate substrate is located within the range of the orthogonal projection of the third electrode of the twelfth transistor on the substrate substrate, and the second insulating layer under the twenty-third via V23 is etched away, exposing the surface of the third electrode of the twelfth transistor. The twenty-third via V23 is configured to enable the second electrode of the seventh transistor formed in the subsequent process to be electrically connected to the third electrode of the twelfth transistor through the via.

[0338] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the orthogonal projection of the twenty-fourth via V24 on the substrate substrate is located within the range of the orthogonal projection of the first region of the active layer of the ninth transistor on the substrate substrate, and the first insulating layer and the second insulating layer under the twenty-fourth via V24 are etched away, exposing the surface of the first region of the active layer of the ninth transistor. The twenty-fourth via V24 is configured to enable the first electrode of the ninth transistor formed in the subsequent process to be electrically connected to the first region of the active layer of the ninth transistor through the via.

[0339] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the orthogonal projection of the twenty-fifth via V25 on the substrate substrate is located within the range of the orthogonal projection of the second region of the active layer of the ninth transistor on the substrate substrate, and the first insulating layer and the second insulating layer under the twenty-fifth via V25 are etched away, exposing the surface of the second region of the active layer of the ninth transistor. The twenty-fifth via V25 is configured to enable the second electrode of the ninth transistor formed in the subsequent process to be electrically connected to the second region of the active layer of the ninth transistor through the via.

[0340] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the second sixthteenth via V26 is located within the range of the second plate of the second capacitor on the substrate substrate, and the second sixthteenth via V26 exposes the surface of the second plate of the second capacitor. The second sixthteenth via V26 is configured to electrically connect the second electrode of the eighth transistor (also the second electrode of the ninth transistor) formed in the subsequent process with the second plate of the second capacitor.

[0341] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the second seventhteenth via V27 is located within the range of the second region of the active layer of the twelfth transistor on the substrate substrate, and the first insulating layer and the second insulating layer below the second seventhteenth via V27 are etched to expose the surface of the second region of the active layer of the twelfth transistor. The second seventhteenth via V27 is configured to electrically connect the second electrode of the active layer of the twelfth transistor formed in the subsequent process with the second region of the active layer of the twelfth transistor through the via.

[0342] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the second eighthteenth via V28 is located within the range of the first region of the active layer of the twelfth transistor on the substrate substrate, and the first insulating layer and the second insulating layer below the second eighthteenth via V28 are etched to expose the surface of the first region of the active layer of the twelfth transistor. The second eighthteenth via V28 is configured to electrically connect the first electrode of the twelfth transistor formed in the subsequent process with the first region of the active layer of the twelfth transistor through the via.

[0343] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the second ninthteenth via V29 is located within the range of the third electrode of the fifth transistor on the substrate substrate, and the second insulating layer below the second ninthteenth via V29 is etched to expose the surface of the third electrode of the fifth transistor. The second ninthteenth via V29 is configured to electrically connect the second electrode of the second transistor (also the second electrode of the fourth transistor) formed in the subsequent process with the third electrode of the fifth transistor through the via.

[0344] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the third tenthteenth via V30 is located within the range of the first region of the active layer of the eleventh transistor on the substrate substrate, and the first insulating layer and the second insulating layer below the third tenthteenth via V30 are etched to expose the surface of the first region of the active layer of the eleventh transistor. The third tenthteenth via V30 is configured to electrically connect the first electrode of the eleventh transistor formed in the subsequent process with the first region of the active layer of the eleventh transistor through the via.

[0345] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the third thirty-one via V31 is located within the range of the second region of the active layer of the eleventh transistor on the substrate substrate, and the first insulating layer and the second insulating layer under the third thirty-one via V31 are etched to expose the surface of the second region of the active layer of the eleventh transistor. The third thirty-one via V31 is configured to electrically connect the second electrode of the eleventh transistor (also the second electrode of the tenth transistor) formed by subsequent processes to the second region of the active layer of the eleventh transistor (also the second region of the active layer of the tenth transistor) through the via.

[0346] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the third thirty-two via V32 is located within the range of the first region of the active layer of the tenth transistor on the substrate substrate, and the first insulating layer and the second insulating layer under the third thirty-two via V32 are etched to expose the surface of the first region of the active layer of the tenth transistor. The third thirty-two via V32 is configured to electrically connect the first electrode of the tenth transistor formed by subsequent processes to the first region of the active layer of the tenth transistor through the via.

[0347] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the third thirty-three via V33 is located within the range of the first connection L1 on the substrate substrate, and the second insulating layer under the third thirty-three via V33 is etched to expose the surface of the first connection L1. The third thirty-three via V33 is configured to electrically connect one of the third clock signal line and the fourth clock signal line formed by subsequent processes to the first connection L1.

[0348] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the third thirty-four via V34 is located within the range of the first connection L1 on the substrate substrate, and the second insulating layer under the third thirty-four via V34 is etched to expose the surface of the first connection L1. The third thirty-four via V34 is configured to electrically connect the first electrode of the tenth transistor formed by subsequent processes to the first connection L1.

[0349] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the third thirty-five via V35 is located within the range of the sixth connection L6 on the substrate substrate, and the third thirty-five via V35 exposes the surface of the sixth connection L6. The third thirty-five via V35 is configured to electrically connect the second electrode of the tenth transistor (also the second electrode of the eleventh transistor) formed by subsequent processes to the sixth connection L6.

[0350] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the third thirty-sixth via hole V36 is located within the range of the normal projection of the second plate of the fourth capacitor on the substrate substrate, and the third thirty-sixth via hole V36 exposes the surface of the second plate of the fourth capacitor. The third thirty-sixth via hole V36 is configured to electrically connect the first voltage signal line formed by the subsequent process to the second plate of the fourth capacitor.

[0351] In some embodiments of the present disclosure, as shown in FIGS. 23 and 24, the third thirty-seventh via hole V37 is located within the range of the normal projection of the first region of the active layer of the fourth transistor on the substrate substrate, and the first insulating layer and the second insulating layer below the third thirty-seventh via hole V37 are etched to expose the surface of the first region of the fourth transistor. The third thirty-seventh via hole V37 is configured to electrically connect the first electrode of the fourth transistor formed by the subsequent process to the first region of the active layer of the fourth transistor through the via hole.

[0352] In the fifth step, the third conductive pattern is formed, including: depositing a third conductive thin film on the substrate substrate on which the aforementioned pattern is formed, and patterning the third conductive thin film through a patterning process to form a third conductive layer pattern, as shown in FIGS. 25 and 26, FIG. 25 is a schematic diagram of the third conductive layer pattern in FIG. 17, and FIG. 29 is a schematic diagram of FIG. 17 after the third conductive pattern is formed. In some embodiments of the present disclosure, the third conductive layer can be referred to as a first source-drain metal (SD1) layer.

[0353] In some embodiments of the present disclosure, as shown in FIGS. 25 and 26, the third conductive layer pattern can include: an input signal line STV, a first clock signal line CLK1, a second clock signal line CLK2, two first voltage signal lines VGL1, a second voltage signal line VGH, a third clock signal line CLK3, a fourth clock signal line CLK4, and the first electrode T1c-1 and the second electrode T1c-2 of the first transistor of the shift register unit at the present level to the first electrode T12c-1 and the second electrode T12c-2 of the twelfth transistor.

[0354] In some embodiments of the present disclosure, as shown in FIGS. 25 and 26, the input signal line, the first clock signal line, the second clock signal line, and the first voltage signal line away from the display area are arranged in the same layer.

[0355] In some embodiments of the present disclosure, as shown in FIGS. 25 and 26, the second electrode T1c-2 of the first transistor and the first electrode T7c-1 of the seventh transistor are integrally formed; the second electrode T2c-2 of the second transistor and the second electrode T4c-2 of the fourth transistor are integrally formed; the second voltage signal line VGH, the first electrode T5c-1 of the fifth transistor and the first electrode T9c-1 of the ninth transistor are integrally formed; the second electrode T6c-2 of the sixth transistor and the second electrode T12c-2 of the twelfth transistor are integrally formed; the second electrode T8c-2 of the eighth transistor and the second electrode T9c-2 of the ninth transistor are integrally formed; the first electrode T10c-1 of the tenth transistor and the first electrode T11c-1 of the eleventh transistor are integrally formed; and the first voltage signal line VGL1 close to the display area and the second electrode T11c-2 of the eleventh transistor are integrally formed. The first electrode T1c-1 of the first transistor, the first electrode T2c-1 of the second transistor, the second electrode T3c-2 of the third transistor, the second electrode T7c-2 of the seventh transistor, the first electrode T8c-1 of the eighth transistor, the first electrode T12c-1 of the twelfth transistor, and the second electrode T10c-2 of the tenth transistor can be separately provided.

[0356] In some embodiments of the present disclosure, as shown in FIGS. 25 and 26, the input signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, the first voltage signal line VGL1 away from the display area, the second voltage signal line VGH, the third clock signal line CLK3, the fourth clock signal line CLK4, and the first voltage signal line VGL1 close to the display area are sequentially arranged along the side close to the display area. Any one of the input signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, the first voltage signal line VGL1 away from the display area, the second voltage signal line VGH, the third clock signal line CLK3, the fourth clock signal line CLK4, and the first voltage signal line VGL1 close to the display area extends along the first direction D1.

[0357] In some embodiments of the present disclosure, as shown in FIGS. 25 and 26, the shape of the first electrode T1c-1 of the first transistor can be strip-shaped and extends along the second direction D2. The first electrode T1c-1 of the first transistor is located between the first voltage signal line VGL1 away from the display area and the second voltage signal line VGH. The first electrode T1c-1 of the first transistor is electrically connected to the first region T1a-1 of the active layer of the first transistor through the second via V2 and electrically connected to the second connection portion L2 of the shift register unit at the present level through the third via V3.

[0358] In some embodiments of the present disclosure, as shown in FIGS. 25 and 26, the second electrode T1c-2 of the first transistor (also the first electrode T7c-1 of the seventh transistor) can be in a strip shape and extend along the second direction D2. The second electrode T1c-2 of the first transistor (also the first electrode T7c-1 of the seventh transistor) is located between the first voltage signal line VGL1 and the second voltage signal line VGH away from the display area. The second electrode T1c-2 of the first transistor (also the first electrode T7c-1 of the seventh transistor) is electrically connected to the second region T1a-2 of the active layer of the first transistor (also the first region T7a-1 of the active layer of the seventh transistor) through the fifth via V5, and electrically connected to the third electrode T3b of the third transistor (also the third electrode T4b of the fourth transistor) through the fifteenth via V15.

[0359] In some embodiments of the present disclosure, as shown in FIGS. 25 and 26, the first electrode T2c-1 of the second transistor can be in a strip shape and extend along the first direction D1. The first electrode T2c-1 of the second transistor is located between the first voltage signal line VGL1 and the second voltage signal line VGH away from the display area. The first electrode T2c-1 of the second transistor is electrically connected to the first region T2a-1 of the active layer of the second transistor through the tenth via V10, and electrically connected to the second plate C1-2 of the first capacitor through the ninth via V9.

[0360] In some embodiments of the present disclosure, as shown in FIGS. 25 and 26, the second electrode T2c-2 of the second transistor (also the second electrode T4c-2 of the fourth transistor) can be in a strip shape and extend along the first direction D1. The second electrode T2c-2 of the second transistor (also the second electrode T4c-2 of the fourth transistor) is located between the first voltage signal line VGL1 and the second voltage signal line VGH away from the display area. The second electrode T2c-2 of the second transistor (also the second electrode T4c-2 of the fourth transistor) is electrically connected to the second region T2a-2 of the active layer of the second transistor (also the second region T4a-2 of the active layer of the fourth transistor) through the eleventh via V11, and electrically connected to the third electrode T5b of the fifth transistor through the twenty-ninth via V29.

[0361] In some embodiments of the present disclosure, as shown in FIGS. 25 and 26, the second electrode T3c-2 of the third transistor can be in a strip shape and extend along the second direction D2. The second electrode T3c-2 of the third transistor is located between the first voltage signal line VGL1 and the second voltage signal line VGH away from the display area. The second electrode T3c-2 of the third transistor is electrically connected to the second region T3a-2 of the active layer of the third transistor through the thirteenth via V13, and electrically connected to the third electrode T2b of the second transistor (also the first plate C1-1 of the first capacitor) through the twelfth via V12.

[0362] In some embodiments of the present disclosure, as shown in FIGS. 25 and 26, the second electrode T7c-2 of the seventh transistor can be in a strip shape and extend along the second direction D2. The second electrode T7c-2 of the seventh transistor is located between the first voltage signal line VGL1 and the second voltage signal line VGH away from the display area. The second electrode T7c-2 of the seventh transistor is electrically connected with the second region T7a-2 of the active layer of the seventh transistor through the seventh via V7, and electrically connected with the third electrode T12b of the twelfth transistor through the twenty-third via V23.

[0363] In some embodiments of the present disclosure, as shown in FIGS. 25 and 26, the first electrode T5c-1 of the fifth transistor (also the first electrode T9c-1 of the ninth transistor) can be in a strip shape and extend along the second direction D2. The first electrode T5c-1 of the fifth transistor (also the first electrode T9c-1 of the ninth transistor) is located between the second voltage signal line VGH and the third clock signal line CLK3. The first electrode T5c-1 of the fifth transistor is electrically connected with the first electrode T5a-1 of the active layer of the fifth transistor through the nineteenth via V19, and the first electrode T9c-1 of the ninth transistor is electrically connected with the first electrode T9a-1 of the active layer of the ninth transistor through the twenty-fourth via V24.

[0364] In some embodiments of the present disclosure, as shown in FIGS. 25 and 26, the second electrode T6c-2 of the sixth transistor (also the second electrode T12c-2 of the twelfth transistor) can be in a strip shape and extend along the first direction D1. The second electrode T6c-2 of the sixth transistor (also the second electrode T12c-2 of the twelfth transistor) is located between the second voltage signal line VGH and the third clock signal line CLK3. The second electrode T6c-2 of the sixth transistor is electrically connected with the second electrode T6a-2 of the active layer of the sixth transistor through the seventeenth via V17, and electrically connected with the third electrode T3b of the third transistor (also the third electrode T4b of the fourth transistor) through the sixteenth via V16. The second electrode T12c-2 of the twelfth transistor is electrically connected with the second electrode T12a-2 of the active layer of the twelfth transistor through the twenty-seventh via V27.

[0365] In some embodiments of the present disclosure, as shown in FIGS. 25 and 26, the first electrode T12c-1 of the twelfth transistor can be in a character shape. The first electrode T12c-1 of the twelfth transistor is located between the second voltage signal line VGH and the third clock signal line CLK3. The first electrode T12c-1 of the twelfth transistor is electrically connected with the first electrode T12a-1 of the active layer of the twelfth transistor through the twenty-eighth via V28.

[0366] In some embodiments of the present disclosure, as shown in FIGS. 25 and 26, the first electrode T8c-1 of the eighth transistor can be in a The first electrode T8c-1 of the eighth transistor is located between the second voltage signal line VGH and the third clock signal line CLK3. The first electrode T8c-1 of the eighth transistor is electrically connected with the first region T8a-1 of the active layer of the eighth transistor through the twenty-first via V21, electrically connected with the fourth connection L4 through the twenty-second via V22, and electrically connected with the third electrode T6b of the sixth transistor through the eighteenth via V18.

[0367] In some embodiments of the present disclosure, as shown in FIGS. 25 and 26, the shape of the second electrode T8c-2 of the eighth transistor (also the second electrode T9c-2 of the ninth transistor) can be an “F” shape. The second electrode T8c-2 of the eighth transistor (also the second electrode T9c-2 of the ninth transistor) is located between the second voltage signal line VGH and the third clock signal line CLK3. The second electrode T8c-2 of the eighth transistor can be electrically connected with the second region T8a-2 of the active layer of the eighth transistor through the twentieth via V20, the second electrode T9c-2 of the ninth transistor can be electrically connected with the second region T9a-2 of the active layer of the ninth transistor through the twenty-fifth via V25, and the second electrode T8c-2 of the eighth transistor (also the second electrode T9c-2 of the ninth transistor) is electrically connected with the second plate C2-2 of the second capacitor through the twenty-sixth via V26.

[0368] In some embodiments of the present disclosure, as shown in FIGS. 25 and 26, the shape of the second electrode T11c-2 of the eleventh transistor can be a strip shape and extend along the second direction D2. The second electrode T11c-2 of the eleventh transistor is located on the side of the first voltage signal line VGL1 close to the display area. The second electrode T11c-2 of the eleventh transistor can be electrically connected with the second region T11a-2 of the active layer of the eleventh transistor through the thirty-first via V31.

[0369] In some embodiments of the present disclosure, as shown in FIGS. 25 and 26, the shape of the second electrode T10c-2 of the tenth transistor can be an “F” shape. The second electrode T10c-2 of the tenth transistor is located on the side of the first voltage signal line VGL1 close to the display area. The second electrode T10c-2 of the tenth transistor can be electrically connected with the second region T10-2 of the active layer of the tenth transistor through the thirty-second via V32.

[0370] In some embodiments of the present disclosure, as shown in FIGS. 25 and 26, the shape of the first electrode T10c-1 of the tenth transistor (also the first electrode T11c-1 of the eleventh transistor) can be comb-shaped, with the "comb teeth" located on the side of the "comb back" away from the display area. The first electrode T10c-1 of the tenth transistor (also the first electrode T11c-1 of the eleventh transistor) is located on the side of the first voltage signal line VGL1 close to the display area. The first electrode T10c-1 of the tenth transistor is electrically connected to the first region T10a-1 of the active layer of the tenth transistor through the thirty-second via V32, and the first electrode T11c-1 of the eleventh transistor is electrically connected to the first region T11a-1 of the active layer of the eleventh transistor through the thirtieth via V30. The first electrode T10c-1 of the tenth transistor (also the first electrode T11c-1 of the eleventh transistor) is electrically connected to the sixth connection portion L6 through the thirty-fifth via V35.

[0371] In some embodiments of the present disclosure, as shown in FIG. 26, the orthographic projection of the first voltage signal line VGL1VGL1 close to the display area on the substrate is partially overlapped with the orthographic projection of the fourth capacitor on the substrate.

[0372] The sixth step of forming a fourth insulating layer pattern includes: depositing a fourth insulating thin film on the substrate with the aforementioned pattern, and patterning the fourth insulating thin film through a patterning process to form a fourth insulating layer pattern covering the aforementioned structure, the fourth insulating layer being provided with a via pattern. As shown in FIGS. 27 and 28, FIG. 27 is a schematic diagram of the second via pattern in FIG. 17, and FIG. 28 is a schematic diagram of FIG. 17 after forming the fourth insulating layer pattern.

[0373] In some embodiments of the present disclosure, as shown in FIGS. 27 and 28, the via pattern can include a thirty-eighth via V38.

[0374] In some embodiments of the present disclosure, as shown in FIGS. 27 and 28, the orthographic projection of the thirty-eighth via V38 on the substrate is within the range of the orthographic projection of the first electrode T12c-1 of the twelfth transistor on the substrate, and the thirty-eighth via V38 exposes the surface of the first electrode T12c-1 of the twelfth transistor. The thirty-eighth via V38 is configured to allow the third voltage signal line VGL2 formed by a subsequent process to be electrically connected to the first electrode T12c-1 of the twelfth transistor through the via.

[0375] The seventh step, forming a fourth conductive layer pattern, includes depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film through a patterning process to form a fourth conductive layer pattern. As shown in Figures 29 and 30, Figure 29 is a schematic diagram of the fourth conductive layer pattern in Figure 17, and Figure 30 is a schematic diagram of Figure 17 after the fourth conductive layer pattern is formed. In some embodiments of the present disclosure, the fourth conductive layer may be referred to as a second source / drain metal layer (SD2).

[0376] In some embodiments of the present disclosure, as shown in FIG. 29 and FIG. 30 , the fourth conductive layer pattern may include: a third voltage signal line VGL2 .

[0377] In some embodiments of the present disclosure, as shown in Figures 29 and 30, the third voltage signal line VGL2 can be linear and extend along the first direction D1. The orthographic projection of the third voltage signal line VGL2 on the substrate is located between the second voltage signal line VGH and the third clock signal line CLK3, and the orthographic projection on the substrate partially overlaps with the orthographic projections of the eighth transistor, the ninth transistor, and the second capacitor on the substrate.

[0378] In some embodiments of the present disclosure, as shown in FIG. 29 and FIG. 30 , the third voltage signal line VGL2 is electrically connected to the first electrode T12 c - 1 of the twelfth transistor through the thirty-eighth via V38 .

[0379] The eighth step is to form a planar layer pattern, including: depositing a fifth insulating film on the base substrate with the aforementioned pattern, coating a planar film, and patterning the fifth insulating film and the planar film through a patterning process to form a fifth insulating layer pattern and a planar layer pattern covering the aforementioned pattern.

[0380] At this point, the drive structure layer is completed on the base substrate. In a plane parallel to the display substrate, the drive structure layer may include multiple shift register units, and the drive structure layer may be disposed on the base substrate. The drive structure layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer, and a planar layer disposed sequentially on the base substrate.

[0381] In some embodiments of the present disclosure, as shown in FIG. 31, the first clock signal line CLK1 and the second clock signal line CLK2 can be arranged in the same layer as the third voltage signal line VGL2. At this time, the input signal line, the first voltage signal line away from the display area, and the first clock signal line and the second clock signal line are arranged in different layers. In some embodiments of the present disclosure, the driving structure layer arranged on the substrate substrate includes: a semiconductor layer, a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer and a planar layer which are sequentially laminated on the substrate substrate. The following is exemplarily described by the preparation process of the display substrate.

[0382] In the first step, a semiconductor layer pattern is formed on the substrate substrate, and the process is similar to the foregoing preparation process, which will not be described here again.

[0383] In the second step, the first conductive layer is formed, including: depositing a first insulating film and a first conductive film on the substrate substrate on which the foregoing pattern is formed, and patterning the first insulating film and the first conductive film by a patterning process to form a first insulating layer pattern and a first conductive pattern arranged on the first insulating layer pattern, as shown in FIG. 32 and FIG. 33, FIG. 32 is a schematic diagram of the first conductive layer pattern in FIG. 31, and FIG. 33 is a schematic diagram after the first conductive layer pattern in FIG. 31 is formed. In some embodiments of the present disclosure, the first conductive layer can be referred to as a first gate metal (GATE1) layer.

[0384] In some embodiments of the present disclosure, as shown in FIG. 32 and FIG. 33, the third electrode T1b' of the first transistor includes: a first third electrode part T1b'-1 and a second third electrode part T1b'-2. The third electrode T1b' of the first transistor is in the shape of “ㄈ”, the first third electrode part T1b'-1 and the second third electrode part T1b'-2 of the first transistor both extend along the second direction D2, and the end of the first third electrode part T1b'-1 of the first transistor is connected with the end of the second third electrode part T1b'-2 of the first transistor.

[0385] In some embodiments of the present disclosure, the preparation process of the first conductive layer is similar to the foregoing preparation process, which will not be described here again.

[0386] The third step of forming the second conductive layer pattern includes: depositing a second insulating film and a second conductive film on the substrate with the aforementioned pattern, and patterning the second insulating film and the second conductive film by a patterning process to form a second insulating layer pattern and a second conductive layer pattern on the second insulating layer pattern. As shown in FIG. 21 and FIG. 22, FIG. 21 is a schematic diagram of the second conductive layer pattern in FIG. 17, and FIG. 22 is a schematic diagram of FIG. 17 after the second conductive layer pattern is formed. In some embodiments of the present disclosure, the second conductive layer can be referred to as a second gate metal (GATE2) layer.

[0387] In some embodiments of the present disclosure, as shown in FIG. 34 and FIG. 35, the second conductive layer pattern can include: a second plate C1-2 of a first capacitor, a second plate C2-2 of a second capacitor, a second plate C4-2 of a fourth capacitor, a second connection L2, a third connection L3, a fourth connection L4, and a sixth connection L6 of at least one stage of shift register unit.

[0388] In some embodiments of the present disclosure, the preparation process of the second conductive layer is similar to the aforementioned preparation process, which will not be described here.

[0389] The fourth step of forming the third insulating layer pattern includes: depositing a third insulating film on the substrate with the aforementioned pattern, and patterning the third insulating film by a patterning process to form a third insulating layer pattern covering the aforementioned structure, the third insulating layer being provided with a plurality of via patterns, as shown in FIG. 36 and FIG. 37, FIG. 36 is a schematic diagram of the third insulating layer via pattern in FIG. 31, and FIG. 37 is a schematic diagram of FIG. 31 after the third insulating layer pattern is formed.

[0390] In some embodiments of the present disclosure, as shown in FIG. 23 and FIG. 24, the plurality of via patterns can include: a second via V2 to a seventh via V7, a ninth via V9 to a thirty-seventh via V37.

[0391] In some embodiments of the present disclosure, the preparation process of the third insulating layer is similar to the aforementioned preparation process, which will not be described here.

[0392] The fifth step of forming the third conductive layer pattern includes: depositing a third conductive film on the substrate with the aforementioned pattern, and patterning the third conductive film by a patterning process to form a third conductive layer pattern, as shown in FIG. 38 and FIG. 39, FIG. 38 is a schematic diagram of the third conductive layer pattern in FIG. 31, and FIG. 39 is a schematic diagram of FIG. 31 after the third conductive layer pattern is formed. In some embodiments of the present disclosure, the third conductive layer can be referred to as a first source-drain metal (SD1) layer.

[0393] In some embodiments of the present disclosure, as shown in FIGS. 38 and 39, the third conductive layer pattern can include: an input signal line STV, two first voltage signal lines VGL1, a second voltage signal line VGH, a third clock signal line CLK3, a fourth clock signal line CLK4, a seventh connection part L7, an eighth connection part L8, and the first pole T1c-1 and the second pole T1c-2 of the first transistor to the first pole T12c-1 and the second pole T12c-2 of the twelfth transistor of the current stage shift register unit.

[0394] In some embodiments of the present disclosure, the preparation process of the third conductive layer is similar to the foregoing preparation process, which will not be described here again.

[0395] In the sixth step, the fourth insulating layer pattern is formed, including: depositing a fourth insulating thin film on the substrate with the foregoing pattern, and patterning the fourth insulating thin film by a patterning process to form a fourth insulating layer pattern covering the foregoing structure, and the fourth insulating layer is provided with a via pattern. As shown in FIGS. 40 and 41, FIG. 40 is a schematic diagram of the second via pattern in FIG. 31, and FIG. 42 is a schematic diagram of FIG. 31 after the fourth insulating layer pattern is formed.

[0396] In some embodiments of the present disclosure, as shown in FIGS. 40 and 41, the via pattern can include: a first via V1', an eighth via V8', and a thirty-eighth via V38.

[0397] In some embodiments of the present disclosure, as shown in FIGS. 40 and 41, the orthographic projection of the first via V1' on the substrate is within the range of the orthographic projection of the third pole of the first transistor on the substrate, and the second insulating layer, the third insulating layer, and the third conductive layer below the first via V1' are etched to expose the surface of the third pole of the first transistor. The first via V1' is configured to electrically connect one of the first clock signal line and the second clock signal line formed in the subsequent process to the third pole of the first transistor.

[0398] In some embodiments of the present disclosure, as shown in FIGS. 40 and 41, the orthographic projection of the eighth via V8' on the substrate is within the range of the orthographic projection of the second pole plate of the first capacitor on the substrate, and the third insulating layer and the third conductive layer below the eighth via V8' are etched to expose the surface of the second pole plate of the first capacitor. The eighth via V8' is configured to electrically connect the other of the first clock signal line and the second clock signal line formed in the subsequent process to the second pole plate of the first capacitor.

[0399] In some embodiments of the present disclosure, the preparation process of the fourth insulating layer is similar to the foregoing preparation process, which will not be described here again.

[0400] The seventh step is forming a fourth conductive layer pattern, which includes depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film through a patterning process to form a fourth conductive layer pattern. As shown in Figures 42 and 43, Figure 42 is a schematic diagram of the fourth conductive layer pattern in Figure 31, and Figure 42 is a schematic diagram of Figure 31 after the fourth conductive layer pattern is formed. In some embodiments of the present disclosure, the fourth conductive layer may be referred to as a second source / drain metal layer (SD2).

[0401] In some embodiments of the present disclosure, as shown in FIG. 42 and FIG. 43 , the fourth conductive layer pattern may include: a first clock signal line CLK1 , a second clock signal line CLK2 , and a third voltage signal line VGL2 .

[0402] In some embodiments of the present disclosure, as shown in Figures 42 and 43, the first clock signal line CLK1 can be linear and extend along a first direction D1. The orthographic projection of the first clock signal line CLK1 on the substrate is located between the first voltage signal line VGL1 and the second voltage signal line VGH, which are located away from the display area. The orthographic projection of the first clock signal line CLK1 on the substrate partially overlaps with the orthographic projections of the first transistor, the seventh transistor, and the first capacitor on the substrate.

[0403] In some embodiments of the present disclosure, as shown in FIG. 42 and FIG. 43 , the first clock signal line CLK1 is electrically connected to the third electrode T1 b of the first transistor through a first via V1 ′.

[0404] In some embodiments of the present disclosure, as shown in Figures 42 and 43, the second clock signal line CLK2 can be linear and extend along a first direction D1. The orthographic projection of the second clock signal line CLK2 on the substrate is located between the first voltage signal line VGL1 and the second voltage signal line VGH, which are located away from the display area. The orthographic projection of the second clock signal line CLK2 on the substrate partially overlaps with the orthographic projections of the second transistor and the first capacitor on the substrate.

[0405] In some embodiments of the present disclosure, as shown in FIG. 42 and FIG. 43 , the second clock signal line CLK2 is electrically connected to the second plate C2 - 2 of the first capacitor through an eighth via V8 ′.

[0406] In some embodiments of the present disclosure, as shown in Figures 42 and 43, the third voltage signal line VGL2 can be linear and extend along the first direction D1. The orthographic projection of the third voltage signal line VGL2 on the substrate is located between the second voltage signal line VGH and the third clock signal line CLK3, and the orthographic projection on the substrate partially overlaps with the orthographic projection of the second capacitor on the substrate.

[0407] In some embodiments of the present disclosure, as shown in FIGS. 42 and 43, the third voltage signal line VGL2 is electrically connected with the first electrode T12c-1 of the twelfth transistor through the thirty-eighth via hole V38.

[0408] In the eighth step, a planar layer pattern is formed. The process is similar to the aforementioned preparation process, and thus will not be described here again.

[0409] In some embodiments of the present disclosure, the first clock signal line CLK1, the second clock signal line CLK2 and the third voltage signal line VGL2 are arranged on the same layer, which can reduce the size of the shift register unit in the first direction by about 25 microns, effectively reducing the size of the shift register unit, further reducing the frame length of the non-display area, and facilitating narrow frame design.

[0410] In some embodiments of the present disclosure, the semiconductor layer can be an amorphous silicon layer or a polysilicon layer, or can be a metal oxide layer. The metal oxide layer can be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer can be a single layer, or can be a double layer, or can be a multi-layer.

[0411] In some embodiments of the present disclosure, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can adopt a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), which can be a single layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0412] In some embodiments of the present disclosure, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer can adopt any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), which can be a single layer, a multi-layer or a composite layer.

[0413] In some embodiments of the present disclosure, the planar layer can adopt an organic material, such as resin, etc.

[0414] In some embodiments of the present disclosure, after the preparation of the driving structure layer is completed, a light-emitting structure layer is prepared on the driving structure layer. The preparation process of the light-emitting structure layer can include the following operations.

[0415] On the substrate on which the aforementioned pattern is formed, an anode conductive thin film is deposited, the anode conductive thin film is patterned by a patterning process to form an anode conductive layer pattern disposed on the planar layer, on the substrate on which the aforementioned pattern is formed, a pixel definition thin film is deposited, the pixel definition thin film is patterned by a patterning process to form a pixel definition layer pattern exposing the anode conductive layer pattern, on the substrate on which the pixel definition layer pattern is formed, an organic light emitting material is coated, the organic light emitting material is patterned by a patterning process to form an organic structure layer pattern, on the substrate on which the organic material layer pattern is formed, a cathode conductive thin film is deposited, the cathode conductive thin film is patterned by a patterning process to form a cathode conductive layer.

[0416] At this point, the light emitting structure layer is prepared on the substrate.

[0417] In some embodiments of the present disclosure, the subsequent preparation process can include forming an encapsulation structure layer on the cathode conductive layer, the encapsulation structure layer can include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked, the first encapsulation layer and the third encapsulation layer can be made of inorganic material, the second encapsulation layer can be made of organic material, the second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer, which can prevent external moisture from entering the light emitting structure layer.

[0418] In some embodiments of the present disclosure, the anode conductive layer includes at least a plurality of anode patterns.

[0419] In some embodiments of the present disclosure, the anode conductive layer can be a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or can be a multi-layer composite structure, such as ITO / Ag / ITO, etc.

[0420] In some embodiments of the present disclosure, the organic structure layer can include at least an organic light emitting layer of the light emitting device.

[0421] In some embodiments of the present disclosure, the cathode conductive layer can include at least a cathode of a plurality of light emitting devices.

[0422] In some embodiments of the present disclosure, the cathode layer can be made of metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or the above-mentioned conductive alloy material, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. Exemplarily, the fourth conductive layer can be a three-layer stacked structure of titanium, aluminum and titanium.

[0423] The display substrate prepared by the embodiments of the present disclosure can be applied to any resolution display product.

[0424] The drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure, and other structures may refer to general designs.

[0425] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0426] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A shift register unit, comprising: The shift register is configured to output a cascade signal through a cascade output terminal; an output circuit electrically connected to the shift register, wherein the output circuit is configured to control the driving output terminal to output a gate scanning signal according to a signal at the first voltage signal terminal and a signal at the reference signal terminal; Wherein, the shift register comprises: a first control subcircuit; The first control sub-circuit is electrically connected to the first node, the second node, the second voltage signal terminal, and the first clock signal terminal in the shift register; the first control circuit is configured to control the voltage of the second node according to the voltage of the first node and the signal of the first clock signal terminal.

2. The shift register unit according to claim 1, wherein: The shift register further includes: an input subcircuit; The input sub-circuit is configured to provide a signal at an input signal terminal to the first node according to a signal at a second clock signal terminal.

3. The shift register unit according to claim 2, wherein: The input subcircuit includes: a first transistor; A first electrode of the first transistor is electrically connected to the input signal terminal, a second electrode of the first transistor is electrically connected to the first node, and a third electrode of the first transistor is electrically connected to the second clock signal terminal.

4. The shift register unit according to claim 1, wherein: The first control subcircuit includes: a second transistor, a third transistor, a fourth transistor and a first capacitor; A first electrode of the second transistor is electrically connected to the first clock signal terminal, a second electrode of the second transistor is electrically connected to the second node, and a third electrode of the second transistor is electrically connected to the third node; The first electrode of the third transistor is electrically connected to the second voltage signal terminal, the second electrode of the third transistor is electrically connected to the third node, and the third electrode of the third transistor is electrically connected to the first node; A first electrode of the fourth transistor is electrically connected to the second voltage signal terminal, a second electrode of the fourth transistor is electrically connected to the second node, and a third electrode of the fourth transistor is electrically connected to the first node; A first electrode of the first capacitor is electrically connected to the first clock signal terminal, and a second electrode of the first capacitor is electrically connected to the third node.

5. The shift register unit according to claim 1, wherein: The shift register further includes: a second control subcircuit; The second control subcircuit is electrically connected to the first node, the second node, the second voltage signal terminal and the first clock signal terminal; the second control subcircuit is configured to transmit the signal from the second voltage signal terminal to the first node based on the voltage of the second node and the signal of the first clock signal terminal.

6. The shift register unit according to claim 5, wherein: The second control subcircuit includes: a fifth transistor and a sixth transistor; a first electrode of the fifth transistor is electrically connected to the second voltage signal terminal, a second electrode of the fifth transistor is electrically connected to the first electrode of the sixth transistor, and a third electrode of the fifth transistor is electrically connected to the second node; A second electrode of the sixth transistor is electrically connected to the first node, and a third electrode of the sixth transistor is electrically connected to the first clock signal terminal.

7. The shift register unit according to claim 1, wherein: The shift register further includes: a voltage stabilization subcircuit; The voltage stabilization subcircuit is electrically connected to the first node, the fourth node and the first voltage signal terminal. The voltage stabilization circuit is configured to transmit the voltage from the first node to the fourth node according to the signal of the first voltage signal terminal.

8. The shift register unit according to claim 7, wherein: The voltage stabilization subcircuit includes: a seventh transistor; A first electrode of the seventh transistor is electrically connected to the first node, a second electrode of the seventh transistor is electrically connected to the fourth node, and a third electrode of the seventh transistor is electrically connected to the first voltage signal terminal.

9. The shift register unit according to claim 1, wherein: The shift register further comprises: a cascade subcircuit; The cascade sub-circuit is electrically connected to the second node, the fourth node, the first clock signal terminal and the second voltage signal terminal. The cascade sub-circuit is configured to enable the cascade output terminal to output the cascade signal according to the voltages of the second node and the fourth node.

10. The shift register unit according to claim 9, wherein: The cascade sub-circuit includes: an eighth transistor, a ninth transistor and a second capacitor; A first electrode of the eighth transistor is electrically connected to the first clock signal terminal, a second electrode of the eighth transistor is electrically connected to the cascade output terminal, and a third electrode of the eighth transistor is electrically connected to the fourth node; a first electrode of the ninth transistor is electrically connected to the second voltage signal terminal, a second electrode of the ninth transistor is electrically connected to the cascade output terminal, and a third electrode of the ninth transistor is electrically connected to the second node; A first electrode of the second capacitor is electrically connected to the fourth node, and a second electrode of the second capacitor is electrically connected to the cascade output terminal.

11. The shift register unit according to claim 10, wherein: The cascade sub-circuit includes: a third capacitor; A first electrode of the third capacitor is electrically connected to the second voltage signal terminal, and a second electrode of the third capacitor is electrically connected to the cascade output terminal.

12. The shift register unit according to claim 7, wherein: The shift register further includes: a pull-down sub-circuit; The pull-down sub-circuit is electrically connected to the third voltage signal terminal and the first node, and is configured to transmit a signal from the third voltage signal terminal to the first node.

13. The shift register unit according to claim 12, wherein: The amplitude of the voltage signal at the third voltage signal terminal is greater than the amplitude of the voltage signal at the first voltage signal terminal.

14. The shift register unit according to claim 13, wherein: The pull-down sub-circuit includes: a twelfth transistor; The first electrode of the twelfth transistor is electrically connected to the third voltage signal terminal, the second electrode of the twelfth transistor is electrically connected to the first node, and the third electrode of the twelfth transistor is electrically connected to the fourth node.

15. The shift register unit according to claim 13, wherein: The pull-down sub-circuit includes: a twelfth transistor; A first electrode of the twelfth transistor is electrically connected to the third voltage signal terminal, a second electrode of the twelfth transistor is electrically connected to the first node, and a third electrode of the twelfth transistor is electrically connected to the first node.

16. The shift register unit according to claim 1, wherein: The output circuit includes: a tenth transistor and an eleventh transistor; A first electrode of the tenth transistor is electrically connected to the reference signal terminal, a second electrode of the tenth transistor is electrically connected to the driving output terminal, and a third electrode of the tenth transistor is electrically connected to the first node; A first electrode of the eleventh transistor is electrically connected to the first voltage signal terminal, a second electrode of the eleventh transistor is electrically connected to the driving output terminal, and a third electrode of the eleventh transistor is electrically connected to the second node.

17. The shift register unit according to claim 1, wherein: The output circuit includes: a tenth transistor, an eleventh transistor and a thirteenth transistor; a first electrode of the tenth transistor is electrically connected to the reference signal terminal, a second electrode of the tenth transistor is electrically connected to the driving output terminal, and a third electrode of the tenth transistor is electrically connected to the second electrode of the thirteenth transistor; A first electrode of the eleventh transistor is electrically connected to the first voltage signal terminal, a second electrode of the eleventh transistor is electrically connected to the driving output terminal, and a third electrode of the eleventh transistor is electrically connected to the second node. A first electrode of the thirteenth transistor is electrically connected to the first node, and a third electrode of the thirteenth transistor is electrically connected to the first voltage signal terminal.

18. The shift register unit according to claim 16 or 17, wherein: The output circuit further includes: a fourth capacitor; A first electrode of the fourth capacitor is electrically connected to the first voltage signal terminal, and a second electrode of the fourth capacitor is electrically connected to the second node.

19. The shift register unit according to claim 1, wherein: The signal at the reference signal end and the signal at the first clock signal end are inverted signals.

20. The shift register unit according to claim 2, wherein: The signal at the first clock signal terminal and the signal at the second clock signal terminal are not valid level signals at the same time.

21. A display panel comprising: A base substrate, comprising a display area and a non-display area; The display area includes: multiple sub-pixels; a plurality of scan lines, wherein a row of the sub-pixels in the plurality of sub-pixels is electrically connected to at least one of the scan lines; The non-display area includes: A gate drive circuit comprises a plurality of shift register units according to any one of claims 1 to 20, wherein a drive output end of each of the plurality of shift register units is electrically connected to at least one of the plurality of scan lines.

22. The display panel according to claim 21, wherein: It also includes: an input signal line electrically connected to the gate drive circuit and arranged in the non-display area, a first voltage signal line away from the display area, a first clock signal line, and a second clock signal line; Any one of the input signal line, the first voltage signal line away from the display area, the first clock signal line and the second clock signal line extends along a first direction, the gate line extends along a second direction, and the first direction intersects the second direction.

23. The display panel according to claim 22, wherein: The input signal line, the first clock signal line, the second clock signal line and the first voltage signal line away from the display area are arranged in sequence on the substrate along the direction close to the display area and are located on the side of the shift register unit away from the display area.

24. The display panel according to claim 23, wherein: The input signal line, the first clock signal line, the second clock signal line and the first voltage signal line away from the display area are arranged in the same layer.

25. The display panel according to claim 22, wherein: The input signal line, the first voltage signal line away from the display area, the first clock signal line and the second clock signal line are arranged in sequence along the direction close to the display area on the substrate, and are set on the side of the shift register unit away from the display area.

26. The display panel according to claim 25, wherein: The input signal line and the first voltage signal line away from the display area are arranged on the same layer, the first clock signal line and the second clock signal line are arranged on the same layer, and the input signal line, the first voltage signal line away from the display area and the first clock signal line, the second clock signal line are arranged on different layers.

27. The display panel according to claim 22, wherein: Also includes: A second voltage signal line is electrically connected to the gate driving circuit and disposed in the non-display area, wherein the second voltage signal line extends along a first direction.

28. The display panel according to claim 27, wherein: The second voltage signal line is disposed on a side of the first voltage signal line that is away from the display area and close to the display area.

29. The display panel according to claim 27, wherein: The display device further includes a third voltage signal line electrically connected to the gate driving circuit and disposed in the non-display area, wherein the third voltage signal line extends along the first direction.

30. The display panel according to claim 29, wherein: The third voltage signal line is arranged on a side of the second voltage signal line close to the display area.

31. The display panel according to claim 29, wherein It also includes: a third clock signal line, a fourth clock signal line, and a first voltage signal line close to the display area, which are electrically connected to the gate drive circuit and arranged in the non-display area, and the third clock signal line, the fourth clock signal line, and the first voltage signal line close to the display area extend along the first direction.

32. The display panel according to claim 31, wherein: Any one of the third clock signal line and the fourth clock signal line is arranged on a side of the third voltage signal line close to the display area; The first voltage signal line close to the display area is located on a side of any one of the third clock signal line and the fourth clock signal line close to the display area.

33. The display panel according to claim 31, wherein: The reference signal end of the i-th stage shift register unit is electrically connected to one of the third clock signal line and the fourth clock signal line, and the reference signal end of the i+1-th stage shift register unit is electrically connected to the other of the third clock signal line and the fourth clock signal line.

34. The display panel according to claim 22, wherein: The first clock signal terminal of the i-th stage shift register unit is electrically connected to one of the first clock signal line and the second clock signal line, and the second clock signal terminal of the i-th stage shift register unit is electrically connected to the other of the first clock signal line and the second clock signal line; The first clock signal terminals of adjacent shift register units are connected to different signal lines, and the second clock signal terminals of adjacent shift register units are connected to different signal lines.

35. The display panel according to claim 31, wherein The width of any one of the input signal line, the first voltage signal line, the second voltage signal line and the third voltage signal line along the second direction is smaller than the width of any one of the first clock signal line, the second clock signal line, the third clock signal line and the fourth clock signal line along the second direction.

36. The display panel according to claim 31, wherein: The shift register unit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a seventh transistor and a first capacitor; At least a portion of any one of the first transistor, the second transistor, the third transistor, the fourth transistor, the seventh transistor and the first capacitor is located between the first voltage signal line and the second voltage signal line.

37. The display panel according to claim 31, wherein: The shift register unit includes: a fifth transistor, a sixth transistor, an eighth transistor, a ninth transistor, a twelfth transistor and a second capacitor; At least a portion of any one of the fifth transistor, the sixth transistor, the eighth transistor, the ninth transistor, the twelfth transistor and the second capacitor is located between the second voltage signal line and the third voltage signal line.

38. The display panel according to claim 37, wherein: The active layer of the twelfth transistor extends along the first direction, at least a portion of either the first electrode or the second electrode of the twelfth transistor extends along the second direction, and the third electrode of the twelfth transistor extends along the second direction.

39. The display panel according to claim 31, wherein: The shift register unit includes: a tenth transistor, an eleventh transistor and a third capacitor; At least a portion of any one of the tenth transistor, the eleventh transistor and the third capacitor is located on a side of the first voltage signal line close to the display area close to the display area; An orthographic projection of the first voltage signal line close to the display area on the base substrate partially overlaps with an orthographic projection of the third capacitor on the base substrate.

40. The display panel according to any one of claims 21 to 39, wherein: A channel width of the active layer of the tenth transistor is greater than a channel width of the active layer of the eighth transistor.

41. The display panel according to claim 40, wherein: The channel width of the active layer of the tenth transistor is not less than 90 micrometers.

42. The display panel according to claim 40, wherein: The channel width of the active layer of the eighth transistor is no greater than 50 micrometers.

43. The display panel according to any one of claims 21 to 39, wherein: A channel width of the active layer of the eleventh transistor is greater than a channel width of the active layer of the ninth transistor.

44. The display panel according to claim 43, wherein The channel width of the active layer of the eleventh transistor is not less than 90 micrometers.

45. The display panel according to claim 43, wherein The channel width of the active layer of the ninth transistor is no greater than 50 micrometers.

46. ​​A display device comprising: A display panel as described in any one of claims 21 to 45.

47. A shift register driving method, comprising: The input sub-circuit provides the signal of the input signal terminal to the first node under the control of the signal of the second clock signal terminal; a first control subcircuit, controlling the voltage of the second node under the control of the voltage of the first node and the signal of the first clock signal terminal; a second control subcircuit, under the control of the voltage of the second node and the signal of the first clock signal terminal, providing a signal of a second voltage signal terminal to the first node; a voltage stabilization subcircuit, under control of a signal from the first voltage signal terminal, providing the voltage of the first node to a fourth node; a cascade sub-circuit, under the control of the voltages of the second node and the fourth node, providing a signal from the second voltage signal terminal or the first clock signal terminal to the cascade output terminal; The output circuit provides a signal from a reference signal terminal or a first voltage signal terminal to a driving output terminal under the control of the voltages of the first node and the second node.

48. The method of claim 47, wherein The shift register unit further includes: a pull-down sub-circuit; The method further includes: the pull-down sub-circuit providing a signal from a third voltage signal terminal to the first node under control of the voltage of the first node or the fourth node.

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