Pixel driving circuit and driving method therefor, and display panel

Abstract

Disclosed are a pixel driving circuit and a driving method therefor, and a display panel. The pixel driving circuit comprises a drive transistor, a first reset sub-circuit, a second reset sub-circuit, a light emission control sub-circuit, a data writing sub-circuit, a gating sub-circuit and an energy storage element. The first reset sub-circuit is configured to, in response to a first reset signal, write a first initialization voltage signal to a control electrode of the driving transistor. The second reset sub-circuit is configured to, in response to a second reset signal, write a second initialization voltage signal to a first electrode of at least one of a plurality of light-emitting devices. The light emission control sub-circuit is configured to, in response to one of a first light emission control signal and a second light emission control signal, electrically connect a first power line and a first electrode of the driving transistor. The gating sub-circuit is configured to, in response to different light emission control signals, electrically connect a second electrode of the driving transistor and different light-emitting devices.

Description

Pixel driving circuit and driving method thereof, and display panel Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel driving circuit and a driving method thereof, and a display panel. Background Art

[0002] Organic light-emitting diode (OLED) displays have become a popular emerging flat-panel display product both domestically and internationally due to their self-luminescence, wide viewing angle, short response time, high luminous efficiency, wide color gamut, low operating voltage, and thin panels. In OLED displays, the pixel circuit provides the driving current to the light-emitting device, driving it to emit light.

[0003] Summary of the Invention

[0004] In a first aspect, the present disclosure provides a pixel driving circuit, comprising: a driving transistor, a first reset subcircuit, a second reset subcircuit, a light emitting control subcircuit, a data writing subcircuit, a gating subcircuit, and an energy storage element; the energy storage element is connected between the control electrode and the first electrode of the driving transistor; wherein,

[0005] The first reset sub-circuit is configured to write a first initialization voltage signal to the control electrode of the driving transistor in response to a first reset signal;

[0006] The second reset subcircuit is configured to write a second initialization voltage signal to the first electrode of at least one of the plurality of light emitting devices in response to a second reset signal;

[0007] The data writing sub-circuit is configured to write a data voltage signal and a threshold voltage signal of the driving transistor into the energy storage element in response to a scan signal;

[0008] The light emitting control subcircuit is configured to connect the first power line to the first electrode of the driving transistor in response to one of the first light emitting control signal and the second light emitting control signal;

[0009] The gating subcircuit is configured to connect the second electrode of the driving transistor to different light-emitting devices in response to different light-emitting control signals.

[0010] In some embodiments, the light emitting control subcircuit includes:

[0011] A fifth transistor, wherein the control electrode of the fifth transistor is electrically connected to the first light emitting control line, the first electrode is electrically connected to the first power line, and the second electrode is electrically connected to the first electrode of the driving transistor.

[0012] In some embodiments, the gating subcircuit includes: a sixth transistor, an eighth transistor, and a ninth transistor, wherein:

[0013] The control electrode of the sixth transistor is electrically connected to the first light emitting control line, and the first electrode of the sixth transistor is electrically connected to the second electrode of the driving transistor;

[0014] The control electrode of the eighth transistor is electrically connected to the second light emitting control line, the first electrode of the eighth transistor is electrically connected to the second electrode of the sixth transistor, and the second electrode of the eighth transistor is electrically connected to the first light emitting device;

[0015] The control electrode of the ninth transistor is electrically connected to the third light emitting control line, the first electrode of the ninth transistor is electrically connected to the second electrode of the sixth transistor, and the second electrode of the ninth transistor is electrically connected to the second light emitting device.

[0016] In some embodiments, the control electrode of the fifth transistor is electrically connected to the first light emitting control line, the first electrode is electrically connected to the first power line, and the second electrode is electrically connected to the first electrode of the driving transistor;

[0017] The control electrode of the ninth transistor is electrically connected to the second light emitting control line, the first electrode is electrically connected to the first power line, and the second electrode is electrically connected to the first electrode of the driving transistor.

[0018] In some embodiments, the gating subcircuit includes: a sixth transistor and an eighth transistor; wherein,

[0019] The control electrode of the sixth transistor is electrically connected to the first light emitting control line, the first electrode is electrically connected to the second electrode of the driving transistor, and the second electrode is electrically connected to the first light emitting device;

[0020] The control electrode of the eighth transistor is electrically connected to the second light emitting control line, the first electrode is electrically connected to the second electrode of the driving transistor, and the second electrode is electrically connected to the second light emitting device.

[0021] In some embodiments, the first reset sub-circuit includes: a first transistor, a control electrode of the first transistor is electrically connected to the first reset signal line, a first electrode is electrically connected to the first initialization voltage line, and a second electrode is electrically connected to the control electrode of the driving transistor.

[0022] In some embodiments, the second reset subcircuit includes: a seventh transistor, wherein the control electrode of the seventh transistor is electrically connected to the second reset signal line, the first electrode is electrically connected to the second initialization voltage line, and the second electrode is electrically connected to the first electrode of the first light-emitting device.

[0023] In some embodiments, the second reset subcircuit further includes: a tenth transistor, wherein the control electrode of the tenth transistor is electrically connected to the second reset signal line, the first electrode is electrically connected to the second initialization voltage line, and the second electrode is electrically connected to the first electrode of the second light-emitting device.

[0024] In some embodiments, the data writing sub-circuit includes: a fourth transistor and a second transistor,

[0025] The control electrode of the fourth transistor is electrically connected to the scan line, the first electrode is electrically connected to the data line, and the second electrode is electrically connected to the first electrode of the driving transistor;

[0026] The control electrode of the second transistor is electrically connected to the scan line, the first electrode is electrically connected to the second electrode of the driving transistor, and the second electrode is electrically connected to the control electrode of the driving transistor.

[0027] In some embodiments, the energy storage element includes a storage capacitor, and the storage capacitor includes a first plate and a second plate, the first plate is electrically connected to the control electrode of the driving transistor, and the second plate is electrically connected to the first electrode of the driving transistor.

[0028] In a second aspect, the present disclosure further provides a driving method for the pixel driving circuit as described above, comprising multiple working stages, wherein:

[0029] In the reset sub-phase of each working phase, the first reset sub-circuit writes a first initialization voltage signal into the control electrode of the driving transistor in response to a first reset signal;

[0030] In the data writing sub-phase of each working phase, the second reset sub-circuit writes a second initialization voltage signal to the first electrode of at least one of the plurality of light-emitting devices in response to a second reset signal; the data writing sub-circuit writes a data voltage signal and a threshold voltage signal of the driving transistor to the energy storage element in response to a scan signal;

[0031] In the light-emitting sub-stage of each working stage, the light-emitting control sub-circuit responds to at least one of the first light-emitting control signal and the second light-emitting control signal to connect the first power line to the first electrode of the driving transistor; and in the light-emitting sub-stages of different working stages, the selection sub-circuit responds to different light-emitting control signals to connect the second electrode of the driving transistor to different light-emitting devices.

[0032] In a third aspect, the present disclosure further provides a display panel, comprising: a substrate and a plurality of pixel driving circuits disposed on the substrate, wherein each of the plurality of pixel driving circuits is electrically connected to a plurality of light-emitting devices; the pixel driving circuit comprises: a driving transistor, a light-emitting control subcircuit, and a gating subcircuit; wherein,

[0033] The light emitting control subcircuit is configured to connect the first power line to the first electrode of the driving transistor in response to a first light emitting control signal on the first light emitting control line or a second light emitting control signal on the second light emitting control line;

[0034] The gating subcircuit is configured to connect the second electrode of the driving transistor to different light-emitting devices in response to different light-emitting control signals;

[0035] In which, the selection subcircuit includes: an eighth transistor, the control electrode of the eighth transistor is electrically connected to the second light-emitting control line, and the second electrode is electrically connected to the first electrode of one of the multiple light-emitting devices; the orthographic projection of the eighth transistor on the substrate and the orthographic projection of the driving transistor on the substrate are respectively located on opposite sides of the orthographic projection of the first light-emitting control line on the substrate.

[0036] In some embodiments, the display panel further includes: a first transfer electrode, a second transfer electrode, and a third transfer electrode; the first electrode of one of the multiple light-emitting devices connected to the pixel driving circuit is electrically connected to the first transfer electrode through a first via; the first transfer electrode is electrically connected to the second transfer electrode through a second via, the second transfer electrode is electrically connected to the third transfer electrode through a third via, and the third transfer electrode is electrically connected to the second electrode of the eighth transistor through a fourth via.

[0037] In some embodiments, the display panel includes a semiconductor layer, a first gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a transparent conductive layer, which are arranged in sequence along a direction away from the base substrate; the second electrode of the eighth transistor is located in the semiconductor layer, the first light-emitting control line and the second light-emitting control line are located in the first gate metal layer, the first transfer electrode is located in the transparent conductive layer, the second transfer electrode is located in the second source-drain metal layer, and the third transfer electrode is located in the first source-drain conductive layer.

[0038] In some embodiments, the plurality of light-emitting devices include a first light-emitting device and a second light-emitting device; the second electrode of the eighth transistor is electrically connected to the first light-emitting device; the gating subcircuit further includes: a sixth transistor and a ninth transistor;

[0039] The control electrode of the sixth transistor is electrically connected to the first light emitting control line, the first electrode is electrically connected to the second electrode of the driving transistor, and the second electrode is electrically connected to the first electrode of the eighth transistor;

[0040] The control electrode of the ninth transistor is electrically connected to the third light emitting control line, the first electrode is electrically connected to the second electrode of the sixth transistor, and the second electrode is electrically connected to the second light emitting device;

[0041] The first light emitting control line, the third light emitting control line and the second light emitting control line are provided in the same layer and are arranged in sequence in a direction away from the driving transistor.

[0042] In some embodiments, the display panel further includes: a fourth switching electrode, the fourth switching electrode being electrically connected to the first electrode of the eighth transistor through a fifth via hole, and being electrically connected to the second electrode of the sixth transistor through a sixth via hole.

[0043] In some embodiments, the display panel includes a semiconductor layer, a first gate metal layer, and a first source-drain metal layer arranged in sequence in a direction away from the base substrate; the first light-emitting control line and the second light-emitting control line are located in the first gate metal layer, the first electrode of the eighth transistor and the second electrode of the sixth transistor are located in the semiconductor layer, and the fourth transfer electrode is located in the first source-drain metal layer.

[0044] In some embodiments, the display panel further includes: a fifth switching electrode, a sixth switching electrode, and a seventh switching electrode; wherein,

[0045] The first electrode of the second light-emitting device is electrically connected to the fifth transfer electrode through the seventh via hole, the fifth transfer electrode is electrically connected to the sixth transfer electrode through the eighth via hole, the sixth transfer electrode is electrically connected to the seventh transfer electrode through the ninth via hole, and the seventh transfer electrode is electrically connected to the second electrode of the ninth transistor through the tenth via hole.

[0046] In some embodiments, the pixel driving circuit also includes a second reset sub-circuit, and the second reset sub-circuit includes: a seventh transistor, the control electrode of the seventh transistor is electrically connected to the second reset signal line, the first electrode is electrically connected to the second initialization voltage line, and the second electrode is electrically connected to the first electrode of the first light-emitting device.

[0047] In some embodiments, the display panel further includes an eighth switching electrode, the eighth switching electrode being electrically connected to the first electrode of the seventh transistor through an eleventh via hole, and being electrically connected to the second initialization voltage line through a twelfth via hole.

[0048] In some embodiments, the second initialization voltage line extends along a first direction;

[0049] The display panel further includes: a second initial voltage supply line extending along the second direction, the second initial voltage supply line being electrically connected to the eighth transfer electrode through a thirteenth via hole; the plurality of pixel driving circuits are arranged in a plurality of columns along the first direction and in a plurality of rows along the second direction; the display panel includes a plurality of second initial voltage supply lines arranged along the first direction;

[0050] The multiple eighth transfer electrodes connected to the multiple pixel driving circuits in the same row include multiple first-type transfer electrodes and multiple second-type transfer electrodes, wherein the first-type transfer electrodes are electrically connected to the second initial voltage supply line, and the orthographic projections of the two on the substrate overlap; the orthographic projections of the second-type transfer electrodes and the second initial voltage supply line on the substrate do not overlap; and at least one second-type transfer electrode is arranged between every two adjacent first-type transfer electrodes arranged along the first direction.

[0051] In some embodiments, the display panel includes: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, which are sequentially arranged in a direction away from the base substrate, wherein:

[0052] The first electrode of the seventh transistor is located in the semiconductor layer, the first light-emitting control line and the second light-emitting control line are located in the first gate metal layer, the second initialization voltage line is located in the second gate metal layer, the eighth transfer electrode is located in the first source-drain metal layer, and the second initial voltage supply line is located in the second source-drain metal layer.

[0053] In some embodiments, the second reset subcircuit further includes: a tenth transistor, wherein the control electrode of the tenth transistor is electrically connected to the second reset signal line, the first electrode is electrically connected to the second initialization voltage line, and the second electrode is electrically connected to the first electrode of the second light-emitting device.

[0054] In some embodiments, the display panel further includes: a seventh switching electrode, wherein the seventh switching electrode is electrically connected to the second electrode of the ninth transistor through a tenth via hole, and is electrically connected to the second electrode of the tenth transistor through a fourteenth via hole.

[0055] In some embodiments, the light emitting control subcircuit includes: a fifth transistor, a first electrode of the fifth transistor is electrically connected to the first light emitting control line, a first electrode is electrically connected to the first power line, and a second electrode is electrically connected to the first electrode of the driving transistor.

[0056] In some embodiments, the first power line includes: a first sub-power line and a second sub-power line, the first sub-power line is electrically connected to the first electrode of the fifth transistor through a fifteenth via hole, and the second sub-power line is connected to the first sub-power line through a sixteenth via hole;

[0057] The display panel includes a plurality of first sub-power lines and a plurality of second sub-power lines, and the plurality of first sub-power lines and the plurality of second sub-power lines are arranged to cross each other and are connected to form a grid structure.

[0058] In some embodiments, the pixel driving circuit further includes a first reset subcircuit, the first reset subcircuit including: a first transistor, a control electrode of the first transistor being electrically connected to a first reset signal line, a first electrode being electrically connected to a first initialization voltage line, and a second electrode being electrically connected to a control electrode of the driving transistor;

[0059] Wherein, the first transistor is located on a side of the driving transistor away from the eighth transistor;

[0060] The pixel driving circuit further includes a second reset subcircuit, the second reset subcircuit including: a seventh transistor, a control electrode of the seventh transistor being electrically connected to a second reset signal line;

[0061] The plurality of pixel driving circuits are arranged in a plurality of columns along the first direction and in a plurality of rows along the second direction; in two adjacent rows of pixel driving circuits, the second reset signal line connected to the seventh transistor in the upper row is integrated with the first reset signal line in the lower row.

[0062] In some embodiments, the active layer, the first electrode and the second electrode of the first transistor are connected into an L-shaped structure, and the L-shaped structure includes a first extension portion extending along a first direction and a second extension portion extending along a second direction, at least a portion of the first electrode of the first transistor is located on the first extension portion, and the second electrode of the first transistor is located on the second extension portion.

[0063] In some embodiments, the display panel further includes: a ninth switching electrode, the ninth switching electrode being electrically connected to the first electrode of the first transistor through an eighteenth via hole, and being electrically connected to the first initialization voltage line through a nineteenth via hole.

[0064] In some embodiments, the first initialization voltage line extends along a first direction.

[0065] The display panel further includes a first initial voltage supply line extending along a second direction, the second direction intersecting the first direction; the first initial voltage supply line is electrically connected to the ninth transfer electrode through a twentieth via hole.

[0066] In some embodiments, the plurality of pixel driving circuits are arranged in a plurality of columns along a first direction and in a plurality of rows along a second direction; the display panel includes a plurality of first initial voltage supply lines arranged along the first direction;

[0067] The multiple ninth switching electrodes connected to the multiple pixel driving circuits in the same row include multiple third-type switching electrodes and multiple fourth-type switching electrodes, wherein the third-type switching electrodes are electrically connected to the first initial voltage supply line, and the orthographic projections of the two on the substrate overlap; the orthographic projections of the fourth-type switching electrodes and the first initial voltage supply line on the substrate do not overlap; and at least one fourth-type switching electrode is arranged between every two adjacent third-type switching electrodes arranged along the first direction.

[0068] In some embodiments, the display panel includes: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, which are sequentially arranged in a direction away from the base substrate; wherein,

[0069] The control electrode of the first transistor is located in the first gate metal layer, the first electrode of the first transistor is located in the semiconductor layer, the first light-emitting control line and the second light-emitting control line are located in the first gate metal layer, the first initialization voltage line is located in the second gate metal layer, the ninth transfer electrode is located in the first source-drain metal layer, and the first initial voltage supply line is located in the second source-drain metal layer; the first reset signal line is located in the first source-drain metal layer and is electrically connected to the control electrode of the first transistor through a seventeenth via.

[0070] In some embodiments, the pixel driving circuit further includes a data writing subcircuit, and the data writing subcircuit includes: a fourth transistor and a second transistor;

[0071] The control electrode of the fourth transistor is electrically connected to the scan line, the first electrode is electrically connected to the data line, and the second electrode is electrically connected to the first electrode of the driving transistor;

[0072] The control electrode of the second transistor is electrically connected to the scan line, the first electrode is electrically connected to the second electrode of the driving transistor, and the second electrode is electrically connected to the control electrode of the driving transistor.

[0073] In some embodiments, the display panel includes: a first gate metal layer and a first source / drain metal layer, wherein the first source / drain metal layer is located on a side of the first gate metal layer away from the base substrate;

[0074] The control electrode of the second transistor and the control electrode of the fourth transistor are both located in the first gate metal layer; in two adjacent pixel driving circuits in the first direction, the control electrode of the second transistor of one pixel driving circuit is connected to the control electrode of the fourth transistor of the other pixel driving circuit to form an integrated structure;

[0075] The scan line is located in the first source-drain metal layer and is electrically connected to the control electrode of the fourth transistor through a thirty-second via hole.

[0076] In some embodiments, the pixel driving circuit further includes a storage capacitor, the storage capacitor including a first plate and a second plate oppositely disposed, the first plate being connected to the control electrode of the driving transistor as an integral structure; the first power line being electrically connected to the second plate through a thirty-fifth via hole;

[0077] The display panel further includes a sixteenth switching electrode, wherein the sixteenth switching electrode is electrically connected to the control electrode of the driving transistor through a thirty-third via hole, and is electrically connected to the second electrode of the second transistor through a thirty-fourth via hole.

[0078] In some embodiments, the second electrode plate has an avoidance gap so that the orthographic projection of the second electrode plate on the base substrate does not overlap with the orthographic projection of the thirty-third via hole on the base substrate.

[0079] In some embodiments, the plurality of pixel driving circuits are arranged in a plurality of columns along the first direction and in a plurality of rows along the second direction;

[0080] The display panel includes a plurality of data lines, a plurality of first initial voltage supply lines, a plurality of second initial voltage supply lines, a plurality of second power lines, and a plurality of second sub-power lines arranged in the same layer; the second electrode of the light-emitting device is electrically connected to the second power line; the data lines, the first initial voltage supply lines, the second initial voltage supply lines, the second power lines, and the second sub-power lines all extend along a second direction;

[0081] The multiple data lines include a first data line, a second data line and a third data line. Each column of the pixel driving circuit is electrically connected to one of the data lines. The first side of each of the data lines is adjacent to the second sub-power line, the second side of the first data line is adjacent to the first initial voltage supply line, the second side of the second data line is adjacent to the second initial voltage supply line, and the second side of the third data line is adjacent to the second power line.

[0082] In some embodiments, the display panel further comprises a pixel defining layer, the pixel defining layer being located on a side of the first electrode of the light-emitting device away from the base substrate; a pixel opening is defined in the pixel defining layer, the pixel opening exposing at least a portion of the first electrode, and the light-emitting functional layer of the light-emitting device is at least partially located in the pixel opening;

[0083] Part of the plurality of light-emitting devices connected to the pixel driving circuit corresponds to a plurality of pixel openings, and the remaining light-emitting devices correspond to one pixel opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0084] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0085] FIG1 is a schematic diagram of a pixel driving circuit provided in some embodiments of the present disclosure.

[0086] FIG2 is a schematic diagram of a pixel driving circuit provided in some embodiments of the present disclosure applied to a display panel.

[0087] FIG3 is another schematic diagram of a pixel driving circuit provided in some embodiments of the present disclosure applied to a display panel.

[0088] FIG4 is a schematic diagram of a specific structure of a pixel driving circuit provided in some embodiments of the present disclosure.

[0089] FIG. 5 is a timing diagram of the pixel driving circuit shown in FIG. 4 in the anti-peeping mode.

[0090] FIG6 is a timing diagram of the pixel driving circuit shown in FIG4 in a sharing mode.

[0091] FIG. 7 is a timing diagram of the pixel driving circuit shown in FIG. 4 in a bidirectional display mode.

[0092] FIG8 is another specific structural diagram of a pixel driving circuit provided in some embodiments of the present disclosure.

[0093] FIG9 is a timing diagram of the pixel driving circuit shown in FIG8 in the bidirectional display mode.

[0094] FIG10 is a schematic diagram of another specific structure of a pixel driving circuit provided in some embodiments of the present disclosure.

[0095] FIG11 is a timing diagram of the pixel driving circuit in FIG10 in the anti-peeping mode.

[0096] FIG12 is a timing diagram of the pixel driving circuit in FIG10 in the sharing mode.

[0097] FIG13 is a timing diagram of the pixel driving circuit in FIG10 in the bidirectional display mode.

[0098] FIG14 is a schematic plan view of a semiconductor layer of a display panel provided in some embodiments of the present disclosure.

[0099] FIG15 is a plan view of a first gate metal layer of a display panel provided in some embodiments of the present disclosure.

[0100] FIG16 is a plan view of a second gate metal layer of a display panel provided in some embodiments of the present disclosure.

[0101] FIG17 is a plan view of a first source / drain metal layer of a display panel provided in some embodiments of the present disclosure.

[0102] FIG18 is a plan view of a second source / drain metal layer of a display panel provided in some embodiments of the present disclosure.

[0103] 19 is a schematic diagram of the superposition of a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer of a display panel provided in some embodiments of the present disclosure.

[0104] FIG20 is a planar schematic diagram of a transparent conductive layer of a display panel provided in some embodiments of the present disclosure.

[0105] FIG21 is a planar schematic diagram of the first electrode layer of the display panel provided in some embodiments of the present disclosure.

[0106] FIG22 is a plan view of a pixel defining layer of a display panel provided in some embodiments of the present disclosure.

[0107] FIG23 is an overall plan view of the display panel provided in some embodiments of the present disclosure after the pixel driving circuit and the first electrode layer are connected

[0108] FIG. 24 is a cross-sectional view taken along line AA′ in FIG. 23 .

[0109] FIG25 is a plan view schematically showing a semiconductor layer of a display panel provided in some other embodiments of the present disclosure.

[0110] FIG26 is a plan view of a first gate metal layer of a display panel provided in some other embodiments of the present disclosure.

[0111] FIG27 is a plan view of a second gate metal layer of a display panel provided in some other embodiments of the present disclosure.

[0112] FIG28 is a plan view of a first source / drain metal layer of a display panel provided in some other embodiments of the present disclosure.

[0113] FIG29 is a plan view of a second source / drain metal layer of a display panel provided in some other embodiments of the present disclosure.

[0114] 30 is a schematic diagram of the superposition of the semiconductor layer, the first gate metal layer, the second gate metal layer, the first source-drain metal layer, and the second source-drain metal layer of the display panel provided in some other embodiments of the present disclosure.

[0115] FIG31 is a planar schematic diagram of a transparent conductive layer of a display panel provided in some other embodiments of the present disclosure.

[0116] FIG32 is a planar schematic diagram of the first electrode layer of a display panel provided in some other embodiments of the present disclosure.

[0117] FIG33 is a plan view of a pixel defining layer of a display panel provided in some other embodiments of the present disclosure.

[0118] FIG34 is an overall plan view of the pixel driving circuit and the first electrode layer of the display panel provided in some other embodiments of the present disclosure after being connected.

[0119] FIG35 is a cross-sectional view taken along line BB′ in FIG30 .

[0120] FIG36 is a planar schematic diagram of a semiconductor layer of a display panel provided in some further embodiments of the present disclosure.

[0121] FIG37 is a planar schematic diagram of the first gate metal layer of a display panel provided in some further embodiments of the present disclosure.

[0122] FIG38 is a planar schematic diagram of a second gate metal layer of a display panel provided in some further embodiments of the present disclosure.

[0123] FIG39 is a planar schematic diagram of the first source-drain metal layer of the display panel provided in some further embodiments of the present disclosure.

[0124] FIG40 is a planar schematic diagram of a second source-drain metal layer of a display panel provided in some further embodiments of the present disclosure.

[0125] 41 is a schematic diagram of the superposition of the semiconductor layer, the first gate metal layer, the second gate metal layer, the first source-drain metal layer, and the second source-drain metal layer of the display panel provided in some further embodiments of the present disclosure.

[0126] FIG42 is a planar schematic diagram of a transparent conductive layer of a display panel provided in some further embodiments of the present disclosure.

[0127] FIG43 is a planar schematic diagram of the first electrode layer of a display panel provided in some further embodiments of the present disclosure.

[0128] FIG44 is a planar schematic diagram of a pixel defining layer of a display panel provided in some further embodiments of the present disclosure.

[0129] Figure 45 is an overall plan view of the pixel driving circuit and the first electrode layer of the display panel provided in some other embodiments of the present disclosure after being connected.

[0130] FIG46 is a cross-sectional view taken along line CC' in FIG41. DETAILED DESCRIPTION

[0131] The following describes the specific embodiments of the present disclosure in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure and are not intended to limit the present disclosure.

[0132] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0133] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0134] It should be noted that the film layers in the embodiments of the present disclosure are schematically illustrated and do not represent the actual thickness of the film layers.

[0135] In addition, each transistor involved in the embodiments of the present disclosure can be independently selected from one of a polysilicon thin film transistor, an amorphous silicon thin film transistor, an oxide thin film transistor, and an organic thin film transistor. The "first electrode" involved in the present disclosure specifically refers to the source electrode of the transistor, and the corresponding "second electrode" specifically refers to the drain electrode of the transistor. Of course, those skilled in the art should know that the "first electrode" and the "second electrode" can be interchanged.

[0136] In addition, the working level state refers to a level state that can turn on the first and second poles of the transistor, and the non-working level state refers to a level state that can turn off the first and second poles of the transistor. Transistors can be divided into N-type transistors and P-type transistors. Each transistor in the present disclosure can be independently selected from an N-type transistor or a P-type transistor; for an N-type transistor, the working level state is a high level state, and the non-working level state is a low level state; for a P-type transistor, the working level state is a low level state, and the non-working level state is a high level state. In the following embodiments, all transistors in the pixel unit will be described as N-type transistors as an example. In this case, the transistors in the pixel driving circuit can be prepared simultaneously using the same preparation process.

[0137] In an OLED display, the pixel driving circuit in each pixel provides a driving current to the light emitting device 20 to drive the light emitting device 20 to emit light. In the related art, during a display cycle, each pixel driving circuit drives the corresponding light emitting device 20 to emit light, thereby jointly displaying an image.

[0138] Figure 1 is a schematic diagram of a pixel driving circuit provided in some embodiments of the present disclosure. As shown in Figure 1, the pixel driving circuit can drive multiple light-emitting devices 20. The pixel driving circuit includes: a driving transistor T3, a first reset sub-circuit 101, a second reset sub-circuit 102, a light-emitting control sub-circuit 105, a data writing sub-circuit 104, a selection sub-circuit 106 and an energy storage element 103; the energy storage element 103 is connected between the control electrode and the first electrode of the driving transistor T3.

[0139] The first reset sub-circuit 101 is configured to write a first initialization voltage signal into the control electrode of the driving transistor T3 in response to a first reset signal.

[0140] The second reset subcircuit 102 is configured to, in response to the second reset signal, write a second initialization voltage signal to the first electrode 201 of at least one of the plurality of light-emitting devices 20. In some embodiments, the light-emitting device 20 may be a current-driven light-emitting device 20, such as an LED (Light Emitting Diode) or an OLED (Organic Light Emitting Diode). In the embodiments disclosed herein, an OLED is used as an example. Optionally, the first electrode 201 of the light-emitting device 20 serves as an anode, and the second electrode serves as a cathode. The second electrode of the light-emitting device 20 may be connected to a second power line VSS, which may provide a low-level signal.

[0141] The data writing sub-circuit 104 is configured to write a data voltage signal and a threshold voltage signal of the driving transistor T3 into the energy storage element 103 in response to the scan signal.

[0142] The light emitting control subcircuit 105 is configured to connect the first power line VDD to the first electrode of the driving transistor T3 in response to one of the first light emitting control signal and the second light emitting control signal. The first power line VDD can provide a high level signal.

[0143] The gating sub-circuit 106 is configured to connect the second electrode of the driving transistor T3 to different light emitting devices 20 in response to different light emitting control signals.

[0144] The pixel driving circuit of the embodiment of the present disclosure may include multiple operating phases, each of which includes a reset sub-phase, a data write sub-phase, and a light emission sub-phase. In the reset sub-phase of each operating phase, the first reset sub-circuit 101 may be used to write a first initialization voltage signal to the control electrode (i.e., node N1) of the driving transistor T3, thereby resetting node N1. In each data write sub-phase, the second reset sub-circuit 102 may be used to write a second initialization voltage signal to the first electrode 201 of at least one of the multiple light-emitting devices 20, thereby resetting the first electrode 201 of at least one light-emitting device 20. Simultaneously, the data write sub-circuit 104 may be used to write a data voltage signal and a threshold voltage signal of the driving transistor T3 to the energy storage element 103. In each light emission sub-phase, the light emission control sub-circuit 105 may be used to connect the first power line VDD to the driving transistor T3. Furthermore, in the light emission sub-phases of different operating phases, the gating sub-circuit 106 may be used to connect the driving transistor T3 to different light-emitting devices 20, thereby causing different light-emitting devices 20 to emit light in different operating phases. Therefore, during different operating phases of the same display cycle, the light-emitting devices 20 driven by the same pixel driver circuit can exhibit different brightnesses. Therefore, in the display panel, by coordinating the configuration of the black matrix BM, different light-emitting devices 20 connected to the same pixel driver circuit can emit light at different angles, thereby allowing different images to be viewed at different viewing angles. For example, users in the driver's seat and the passenger seat can see different images on the same display panel.

[0145] FIG2 is a schematic diagram of a pixel driving circuit provided in some embodiments of the present disclosure applied to a display panel, and FIG3 is another schematic diagram of a pixel driving circuit provided in some embodiments of the present disclosure applied to a display panel. Both FIG2 and FIG3 illustrate an example of a pixel driving circuit connected to two light-emitting devices. As shown in FIG2 , an encapsulation layer 40 is provided on the side of the light-emitting device 20 away from the base substrate 30, and a double-layer black matrix BM is provided on the side of the encapsulation layer 40 away from the base substrate 30. The orthographic projections of the two layers of black matrix BM on the base substrate 30 can substantially overlap and are located in the space between the two light-emitting devices 20 connected to the pixel driving circuit 10. In this case, of the two light-emitting devices 20 connected to each pixel driving circuit 10, the light emitted by one light-emitting device 20 toward the L viewing angle is blocked by the black matrix BM; the light emitted by the other light-emitting device 20 toward the R viewing angle is blocked by the black matrix BM, thereby enabling different images to be viewed from the L viewing angle and the R viewing angle. In FIG2 , solid arrows represent light that can exit the display panel, and dashed arrows represent light that is blocked by the black matrix BM and cannot exit the display panel.

[0146] As shown in Figure 3, the black matrix BM defines a plurality of light outlets, and the orthographic projection of each light outlet on the base substrate 30 overlaps with the orthographic projection of a light-emitting device 20 on the base substrate 30. In this case, the display panel can realize display in anti-peeping mode and shared mode. Specifically, in anti-peeping mode, in the reset phase, the first reset subcircuit 101 resets the control electrode of the driving transistor T3; in the data writing phase, the data writing subcircuit 104 writes the data voltage signal and the threshold voltage signal of the driving transistor T3 to the energy storage element 103; in the light-emitting phase, by reasonably configuring the light-emitting control signal, the light-emitting control subcircuit 105 connects the first power line VDD to the first electrode of the driving transistor T3; at the same time, the selection subcircuit 106 connects the second electrode of the driving transistor T3 to one of the light-emitting devices 20, thereby providing a driving current for one of the light-emitting devices 20, realizing light emission with a small viewing angle, thereby realizing anti-peeping display. As for the light-emitting device 20 in the shared mode, by reasonably configuring the light-emitting control signal, the light-emitting control subcircuit 105 turns on the second electrode of the driving transistor T3 and the multiple light-emitting devices 20, thereby providing driving current for the multiple light-emitting devices 20, so that the multiple light-emitting devices 20 emit light at the same time, achieving light emission with a wide viewing angle.

[0147] In one example, as shown in FIG3 , of the two light-emitting devices 20 connected to the same pixel driving circuit 10, one light-emitting device 20 has a smaller light outlet area, while the other light-emitting device 20 has a larger light outlet area. In the privacy protection mode, the light-emitting device 20 corresponding to the smaller light outlet area can be controlled to emit light to improve the privacy protection effect.

[0148] FIG4 is a schematic diagram of the specific structure of a pixel driving circuit provided in some embodiments of the present disclosure. FIG4 is a specific implementation of FIG1. ​​As shown in FIG4, the light-emission control subcircuit 105 may include a fifth transistor T5, wherein the control electrode of the fifth transistor T5 is electrically connected to the first light-emission control line EM1, the first electrode is electrically connected to the first power line VDD, and the second electrode is electrically connected to the first electrode of the driving transistor T3. When the first light-emission control signal on the first light-emission control line EM1 is at an operating level, the first electrode and the second electrode of the fifth transistor T5 are conductive, thereby transmitting the signal on the first power line VDD to the first electrode of the driving transistor T3.

[0149] In some embodiments, the gating subcircuit 106 includes a sixth transistor T6, an eighth transistor T8, and a ninth transistor T9. The control electrode of the sixth transistor T6 is electrically connected to the first emission control line EM1, and the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the driving transistor T3. The control electrode of the eighth transistor T8 is electrically connected to the second emission control line EM2, the first electrode of the eighth transistor T8 is electrically connected to the second electrode of the sixth transistor T6, and the second electrode of the eighth transistor T8 is electrically connected to the first light-emitting device 21. The control electrode of the ninth transistor T9 is electrically connected to the third emission control line EM3, the first electrode of the ninth transistor T9 is electrically connected to the second electrode of the sixth transistor T6, and the second electrode of the ninth transistor T9 is electrically connected to the second light-emitting device 22.

[0150] When the first light emitting control signal on the first light emitting control line EM1 and the second light emitting control signal on the second light emitting control line EM2 are both at an operating level, the sixth transistor T6 conducts the second electrode of the driving transistor T3 to the N4 node, and the eighth transistor T8 conducts the N4 node to the first light emitting device 21, thereby providing a driving current to the first light emitting device 21. When the first light emitting control signal on the first light emitting control line EM1 and the third light emitting control signal on the third light emitting control line EM3 are both at an operating level, the sixth transistor T6 conducts the second electrode of the driving transistor T3 to the N4 node, and the ninth transistor T9 conducts the N4 node to the second light emitting device 22, thereby providing a driving current to the second light emitting device 22.

[0151] In some embodiments, as shown in FIG4 , the first reset sub-circuit 101 includes a first transistor T1, wherein a control electrode of the first transistor T1 is electrically connected to a first reset signal line Re1, a first electrode of the first transistor T1 is electrically connected to a first initialization voltage line Vinit1, and a second electrode of the first transistor T1 is electrically connected to a control electrode of a driving transistor T3. When a first reset signal on the first reset signal line Re1 is at an operating level, the first reset signal writes the voltage on the first initialization voltage line Vinit1 to a node N1, thereby resetting the node N1.

[0152] In some embodiments, as shown in FIG4 , the second reset sub-circuit 102 includes: the second reset sub-circuit 102 includes: a seventh transistor T7, wherein the control electrode of the seventh transistor T7 is electrically connected to the second reset signal line Re2, the first electrode is electrically connected to the second initialization voltage line Vinit2, and the second electrode is electrically connected to the first electrode 201 of the first light-emitting device 21. When the second reset signal on the second reset signal line Re2 is at an operating level, the seventh transistor T7 writes the voltage on the second initialization voltage line Vinit2 into the first electrode 201 of the first light-emitting device 21, thereby resetting the first electrode 201 of the first light-emitting device 21.

[0153] In some embodiments, multiple pixel driving circuits are arranged in an array, and in every two adjacent rows of pixel driving circuits, the second reset signal line Re2 connected to the upper row of pixel driving circuits and the first reset signal line Re1 connected to the lower row of pixel driving circuits can be shared.

[0154] In some embodiments, the data writing sub-circuit 104 includes a fourth transistor T4 and a second transistor T2. The fourth transistor T4 has a control electrode electrically connected to the scan line GT, a first electrode electrically connected to the data line DL, and a second electrode electrically connected to the first electrode of the driving transistor T3. The second transistor T2 has a control electrode electrically connected to the scan line GT, a first electrode electrically connected to the second electrode of the driving transistor T3, and a second electrode electrically connected to the control electrode of the driving transistor T3.

[0155] In some embodiments, the energy storage element 103 includes a storage capacitor Cst, which includes a first plate and a second plate. The first plate is electrically connected to the control electrode of the driving transistor T3, and the second plate is electrically connected to the first electrode of the driving transistor T3.

[0156] FIG5 is a timing diagram of the pixel driving circuit shown in FIG4 in the anti-peeping mode. As shown in FIG5 , the pixel driving circuit includes a reset sub-stage t1 , a data writing sub-stage t2 and a light emitting sub-stage t3 in each display cycle.

[0157] During the reset sub-phase t1, the first reset signal is at an operating level, and the first transistor T1 is turned on, thereby transmitting the voltage signal on the first initialization voltage line Vinit1 to the N1 node, thereby resetting the N1 node. Furthermore, the scan signal on the scan line GT, the second reset signal on the second reset signal line Re2, and the first light control signal on the first light control line EM1 are all at a non-operating level, thereby turning off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. The second light control signal on the second light control line EM2 and the third light control signal on the third light control line EM3 can both be at an operating level, and the eighth transistor T8 and the ninth transistor T9 are both turned on.

[0158] In the data writing sub-phase t2, the second reset signal on the second reset signal line Re2, the second light-emitting control signal on the second light-emitting control transistor, and the third light-emitting control signal on the third light-emitting control line EM3 are all in an operating level state, thereby turning on the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9. This allows the voltage signal on the second initialization voltage line Vinit2 to be transmitted to the first electrode 201 of the first light-emitting device 21 and the first electrode 201 of the second light-emitting device 22, thereby resetting the first electrodes 201 of the two light-emitting devices 20. Furthermore, the scan signal on the scan line GT is in an operating level state, thereby turning on the second transistor T2 and the fourth transistor T4. The data voltage signal on the data line DL is written to the first electrode of the driving transistor T3, and the control electrode and the second electrode of the driving transistor T3 are short-circuited to form a diode structure. At this time, the data voltage signal flows through the driving transistor T3 and the second transistor T2 to the control electrode of the driving transistor T3. The potential of the control electrode of the driving transistor T3 reaches Vdata+Vth, where Vth is the threshold voltage of the second transistor T2 and Vdata is the voltage of the data voltage signal.

[0159] In the light-emitting sub-stage t3, the first light-emitting control signal on the first light-emitting control line EM1 and the second light-emitting control signal on the second light-emitting control line EM2 are both in an operating level state, and the first reset signal on the first reset signal line Re1, the second reset signal on the second reset signal line Re2, the scan signal on the scan line GT, and the third light-emitting control signal on the third light-emitting control line EM3 are all in a non-operating level state. At this time, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the driving transistor T3 are all turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the ninth transistor T9 are all turned off. Under the voltage maintenance effect of the storage capacitor Cst, the potential of the control electrode of the driving transistor T3 is maintained at Vdata + Vth; the voltage on the first power line VDD generates a driving current through the fifth transistor T5 and the driving transistor T3, which flows into the first light-emitting device 21; the second light-emitting device 22 does not emit light. At this time, the driving current I OLED The following saturation current formula is satisfied: I OLED =K(Vgs-Vth) 2 =K(Vdata+Vth-ELVDD-Vth) 2 =K(Vdata-ELVDD) 2 (1)

[0160] Wherein, K is a coefficient related to the characteristics of the driving transistor T3 itself, Vgs is the gate-source voltage of the driving transistor T3, that is, the voltage between the control electrode and the first electrode of the driving transistor T3, and ELVDD is the voltage provided by the first power line VDD.

[0161] FIG6 is a timing diagram of the pixel driving circuit shown in FIG4 in the sharing mode. As shown in FIG6 , the pixel driving circuit includes a reset sub-phase t1 , a data writing sub-phase t2 and a light emitting sub-phase t3 in each display cycle.

[0162] Among them, in the reset sub-stage t1 and the data writing sub-stage t2 in the sharing mode, the timing of each signal is the same as the timing of the reset sub-stage t1 and the data writing sub-stage t2 in the anti-peep mode. The switching state of each transistor can be found in the above description and will not be repeated here.

[0163] In the light-emitting sub-stage t3 in the shared mode, the first reset signal on the first reset signal line Re1, the second reset signal on the second reset signal line Re2, and the scan signal on the scan line GT are all in a non-operating state. The first transistor T1, the seventh transistor T7, the second transistor T2, and the fourth transistor T4 are all turned off. The first light-emitting control signal on the first light-emitting control line EM1, the second light-emitting control signal on the second light-emitting control line EM2, and the third light-emitting control signal on the third light-emitting control line EM3 are all in an operating state, thereby turning on the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9. The voltage on the first power line VDD generates a drive current through the fifth transistor T5 and the drive transistor T3, which flows into the first light-emitting device 21 and the second light-emitting device 22, thereby causing the first light-emitting device 21 and the second light-emitting device 22 to emit light, thereby increasing the viewing angle. The drive current is shown in the above formula.

[0164] FIG7 is a timing diagram of the pixel driving circuit shown in FIG4 in the bidirectional display mode. As shown in FIG7 , the pixel driving circuit includes two working stages in each display cycle. Each working stage includes a reset sub-stage t1, a data writing sub-stage t2, and a light emitting sub-stage t3.

[0165] During the reset sub-phase t1 of the first operating phase, the first reset signal is at an operating level, and the first transistor T1 is turned on, thereby transmitting the voltage signal on the first initialization voltage line Vinit1 to the N1 node, resetting the N1 node. Furthermore, the scan signal on the scan line GT, the second reset signal on the second reset signal line Re2, and the first light control signal on the first light control line EM1 are all at a non-operating level, thereby turning off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. The second light control signal on the second light control line EM2 and the third light control signal on the third light control line EM3 can both be at an operating level, and the eighth transistor T8 and the ninth transistor T9 are both turned on.

[0166] During the data writing sub-phase t2 of the first working phase, the second reset signal on the second reset signal line Re2, the second light-emitting control signal on the second light-emitting control transistor, and the third light-emitting control signal on the third light-emitting control line EM3 are all at an operating level, thereby turning on the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9. This allows the voltage signal on the second initialization voltage line Vinit2 to be transmitted to the first electrode 201 of the first light-emitting device 21 and the first electrode 201 of the second light-emitting device 22, thereby resetting the first electrodes 201 of the two light-emitting devices 20. Furthermore, the scan signal on the scan line GT is at an operating level, thereby turning on the second transistor T2 and the fourth transistor T4. The data voltage signal on the data line DL is written to the first electrode of the driving transistor T3, and the control electrode and the second electrode of the driving transistor T3 are short-circuited to form a diode structure. At this point, the data voltage signal flows through the driving transistor T3 and the second transistor T2 to the control electrode of the driving transistor T3, and the potential of the control electrode of the driving transistor T3 reaches Vdata + Vth.

[0167] In the light-emitting sub-stage t3 of the first working stage, the first light-emitting control signal on the first light-emitting control line EM1 and the second light-emitting control signal on the second light-emitting control line EM2 are both in the working level state, and the third light-emitting control signal on the third light-emitting control line EM3, the scan signal on the scan line GT, the first reset signal on the first reset signal line Re1, and the second reset signal on the second reset signal line Re2 are all in the non-working level state. At this time, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the driving transistor T3 are all turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 are all turned off. Under the voltage maintenance effect of the storage capacitor Cst, the potential of the control electrode of the driving transistor T3 is maintained at Vdata + Vth; the voltage on the first power line VDD generates a driving current through the fifth transistor T5 and the driving transistor T3, and flows into the first light-emitting device 21. The magnitude of the driving current is shown in the above formula (1).

[0168] During the reset sub-phase t1 of the second operating phase, the first reset signal is at an operating level, and the first transistor T1 is turned on, thereby transmitting the voltage signal on the first initialization voltage line Vinit1 to the N1 node, resetting the N1 node. Furthermore, the scan signal on the scan line GT, the second reset signal on the second reset signal line Re2, the first light control signal on the first light control line EM1, and the third light control signal on the third light control line EM3 are all at non-operating levels, thereby turning off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9. The second light control signal on the second light control line EM2 can be at an operating level, and the eighth transistor T8 is turned on.

[0169] During the data writing sub-phase t2 of the second working phase, the second reset signal line Re2 and the third light-emitting control signal on the third light-emitting control transistor are both at an operating level, thereby turning on the seventh transistor T7 and the ninth transistor T9, and thus transmitting the voltage signal on the second initialization voltage line Vinit2 to the first electrode 201 of the second light-emitting device 22. In addition, the scan signal on the scan line GT is at an operating level, thereby turning on the second transistor T2 and the fourth transistor T4. Similar to the data writing sub-phase of the first working phase, the control electrode potential of the driving transistor T3 reaches Vdata+Vth.

[0170] During the light-emitting sub-stage t3 of the second operating phase, the first light-emitting control signal on the first light-emitting control line EM1 and the third light-emitting control signal on the third light-emitting control line EM3 are both at an operating level. The second light-emitting control signal on the second light-emitting control line EM2, the scan signal on the scan line GT, the first reset signal on the first reset signal line Re1, and the second reset signal on the second reset signal line Re2 are all at a non-operating level. At this time, the fifth transistor T5, the sixth transistor T6, the ninth transistor T9, and the driving transistor T3 are all turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are all turned off. Under the voltage maintenance effect of the storage capacitor Cst, the potential of the control electrode of the driving transistor T3 is maintained at Vdata + Vth. The voltage on the first power line VDD generates a driving current through the fifth transistor T5 and the driving transistor T3, which flows into the second light-emitting device 22. The magnitude of the driving current is shown in the above formula (1).

[0171] It can be seen that in each display cycle, the pixel driving circuit can time-share drive the two light-emitting devices 20 to emit light respectively, thereby realizing bidirectional display.

[0172] FIG8 is another schematic diagram of a specific structure of a pixel driving circuit provided in some embodiments of the present disclosure, and FIG8 is another specific implementation of FIG1. ​​Similar to FIG4, in FIG8, the first reset sub-circuit 101 includes a first transistor T1; the data write sub-circuit 104 includes a second transistor T2 and a fourth transistor T4; the light emission control sub-circuit 105 specifically includes a fifth transistor T5; the gating sub-circuit 106 includes a sixth transistor T6, an eighth transistor T8, and a ninth transistor T9; the connection relationship between the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, and the driving transistor T3 is the same as in FIG4 and will not be repeated here.

[0173] Unlike the pixel driving circuit shown in FIG4 , in FIG8 , the second reset sub-circuit 102 includes a seventh transistor T7 and a tenth transistor T10. The seventh transistor T7 has a control electrode connected to the second reset signal line Re2, a first electrode electrically connected to the second initialization voltage line Vinit2, and a second electrode electrically connected to the first electrode 201 of the first light-emitting device 21. The tenth transistor T10 has a control electrode electrically connected to the second reset signal line Re2, a first electrode electrically connected to the second initialization voltage line Vinit2, and a second electrode electrically connected to the first electrode 201 of the second light-emitting device 22.

[0174] Among them, in the anti-peep mode, the timing of each signal of the pixel driving circuit shown in Figure 8 is the same as that in Figure 5. In the reset sub-phase t1, the first transistor T1 is turned on, thereby transmitting the voltage signal on the first initialization voltage line Vinit1 to the N1 node, thereby resetting the N1 node. The second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 are all turned off. In the data writing sub-phase t2, the seventh transistor T7, the tenth transistor T10, the eighth transistor T8, and the ninth transistor T9 are all turned on, and the voltage signal on the second initialization voltage line Vinit2 is transmitted to the first electrode 201 of the first light-emitting device 21 through the seventh transistor T7, and is transmitted to the second electrode of the second light-emitting device 22 through the tenth transistor T10. At the same time, the second transistor T2 and the fourth transistor T4 are turned on, and the control electrode potential of the driving transistor T3 reaches Vdata+Vth. In the light-emitting sub-stage t3, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the driving transistor T3 are all turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 are all turned off. The driving transistor T3 provides a driving current to the first light-emitting device 21, and the second light-emitting device 22 does not emit light.

[0175] In shared mode, the timing sequences of the various signals in the pixel driving circuit shown in FIG8 are the same as those in FIG6 . In shared mode, the switching states of the first to ninth transistors T1 to T9 in each sub-phase are the same as the switching states of the transistors in the pixel circuit of FIG4 in shared mode in each sub-phase, and are not further described here. The operating state of the tenth transistor T10 in each sub-phase is the same as the switching state of the seventh transistor T7.

[0176] FIG9 is a timing diagram of the pixel driving circuit shown in FIG8 in the bidirectional display mode. As shown in FIG9 , the pixel driving circuit includes two working stages in each display cycle. Each working stage includes a reset sub-stage t1, a data writing sub-stage t2, and a light emitting sub-stage t3.

[0177] During the reset sub-phase t1 of the first operating phase, the first reset signal is at an operating level, while the second reset signal, scan signal, first light-emission control signal, second light-emission control signal, and third light-emission control signal are all at non-operating levels. The first transistor T1 is turned on, thereby transmitting the voltage signal on the first initialization voltage line Vinit1 to the control electrode of the driving transistor T3, thereby resetting the driving transistor. The remaining transistors are all turned off.

[0178] During the data writing sub-phase t2 of the first working phase, the scan signal and the second reset signal are at working levels, while the first reset signal, the first light-emitting control signal, the second light-emitting control signal, and the third light-emitting control signal are at non-working levels. At this time, the seventh transistor T7 and the tenth transistor T10 are turned on, thereby writing the second initialization voltage signal on the second initialization voltage line Vinit2 into the first electrode 201 of each light-emitting device 20. Simultaneously, the second transistor T2 and the fourth transistor T4 are turned on, allowing the data voltage signal to flow through the drive transistor T3 and the second transistor T2 to the control electrode of the drive transistor T3, causing the control electrode potential of the drive transistor T3 to reach Vdata + Vth.

[0179] During the light-emitting sub-stage t3 of the first operating stage, the first reset signal, the second reset signal, the scan signal, and the third light-emitting control signal are all in a non-operating state, while the first light-emitting control signal and the second light-emitting control signal are both in an operating state. At this time, the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 are all turned off; the fifth transistor T5, the sixth transistor T6, the driving transistor T3, and the eighth transistor T8 are turned on, and the potential of the control electrode of the driving transistor T3 is maintained at Vdata + Vth; the driving transistor T3 provides a driving current to the first light-emitting device 21. The magnitude of the driving current is shown in the above formula (1).

[0180] In the reset sub-phase t1 and data writing sub-phase t2 of the second working phase, the timing of each signal is the same as that of the reset sub-phase t1 and data writing sub-phase t2 of the first working phase. The switching state of each transistor refers to the description of the reset sub-phase t1 and data writing sub-phase t2 of the first working phase.

[0181] In the light-emitting sub-stage t3 of the second working stage, the first reset signal, the second reset signal, the scan signal, and the second light-emitting control signal are all in a non-working level state, and the first light-emitting control signal and the second light-emitting control signal are all in a working level state. At this time, the fifth transistor T5, the sixth transistor T6, the ninth transistor T9, and the driving transistor T3 are all turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10 are all turned off. The potential of the control electrode of the driving transistor T3 is maintained at Vdata + Vth; the driving transistor T3 provides a driving current to the second light-emitting device 22. The magnitude of the driving current is shown in the above formula (1).

[0182] FIG10 is another schematic diagram of a specific structure of a pixel driving circuit provided in some embodiments of the present disclosure, and FIG10 is another specific implementation scheme of FIG1. ​​Similar to FIG8, in FIG10, the first reset sub-circuit 101 includes a first transistor T1; the data write sub-circuit 104 includes a second transistor T2 and a fourth transistor T4; and the energy storage element 103 includes a storage capacitor Cst. The connection relationship between the first transistor T1, the second transistor T2, the fourth transistor T4, and the storage capacitor Cst is described in FIG8. The second reset sub-electrode includes a seventh transistor T7 and a tenth transistor T10, wherein the control electrodes of the seventh transistor T7 and the tenth transistor T10 are both electrically connected to the second reset signal line Re2, the first electrode of the seventh transistor T7 is electrically connected to the second initialization voltage line Vinit2, and the second electrode is electrically connected to the first electrode 201 of the first light-emitting device 21; the first electrode of the tenth transistor T10 is electrically connected to the second initialization voltage line Vinit2, and the second electrode is electrically connected to the first electrode 201 of the second light-emitting device 22.

[0183] Unlike FIG8 , in FIG10 , the light-emission control subcircuit 105 includes a fifth transistor T5 and a ninth transistor T9; the gating subcircuit 106 includes a sixth transistor T6 and an eighth transistor T8. The fifth transistor T5 has a control electrode electrically connected to the first light-emission control line EM1, a first electrode electrically connected to the first power line VDD, and a second electrode electrically connected to the first electrode of the driving transistor T3. The ninth transistor T9 has a control electrode electrically connected to the second light-emission control line EM2, a first electrode electrically connected to the first power line VDD, and a second electrode electrically connected to the first electrode of the driving transistor T3. The sixth transistor T6 has a control electrode electrically connected to the first light-emission control line EM1, a first electrode electrically connected to the second electrode of the driving transistor T3, and a second electrode electrically connected to the first light-emitting device 21. The eighth transistor T8 has a control electrode electrically connected to the second light-emission control line EM2, a first electrode electrically connected to the second electrode of the driving transistor T3, and a second electrode electrically connected to the second light-emitting device 22.

[0184] FIG11 is a timing diagram of the pixel driving circuit in FIG10 in the anti-peeping mode. As shown in FIG11 , the pixel driving circuit includes a reset sub-stage t1 , a data writing sub-stage t2 and a light emitting sub-stage t3 in each display cycle.

[0185] In the reset sub-phase t1, the first reset signal on the first reset signal line Re1 is at an operating level, and the first transistor T1 is turned on, thereby transmitting the voltage signal on the first initialization voltage line Vinit1 to the N1 node, thereby resetting the N1 node. In addition, the second reset signal on the second reset signal line Re2, the scan signal on the scan line GT, the first light control signal on the first light control line EM1, and the second light control signal on the second light control line EM2 are all at a non-operating level, and the second transistor T2 to the tenth transistor T10 are all turned off.

[0186] During the data writing sub-phase t2, the second reset signal is at an operating level, thereby turning on the seventh transistor T7 and the tenth transistor T10, and thereby transmitting the voltage signal on the second initialization voltage line Vinit2 to the first electrode 201 of the first light-emitting device 21 and the first electrode 201 of the second light-emitting device 22. Furthermore, the scan signals are all at an operating level, thereby turning on the second transistor T2 and the fourth transistor T4. The data voltage signal flows through the driving transistor T3 and the second transistor T2 to the control electrode of the driving transistor T3, and the potential of the control electrode of the driving transistor T3 reaches Vdata + Vth. Furthermore, during the data writing sub-phase t2, the first reset signal, the first light-emitting control signal, and the second light-emitting control signal are all at non-operating levels, and the first transistor T1, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 are all turned off.

[0187] In the light-emitting sub-stage t3, the first light-emitting control signal is in an active level state, thereby turning on the fifth transistor T5 and the sixth transistor T6. The voltage on the first power line VDD generates a driving current through the fifth transistor T5 and the driving transistor T3, and then flows into the first light-emitting device 21. In addition, the second light-emitting control signal, the first reset signal, the second reset signal, and the scan signal are all in a non-operating level state. Therefore, the ninth transistor T9, the eighth transistor T8, the first transistor T1, the second transistor T2, and the fourth transistor T4 are all turned off, and the second light-emitting device 22 does not emit light.

[0188] FIG12 is a timing diagram of the pixel driving circuit in FIG10 in the sharing mode. As shown in FIG12 , the pixel driving circuit includes a reset sub-stage t1 , a data writing sub-stage t2 and a light emitting sub-stage t3 in each display cycle.

[0189] In the reset sub-stage t1 and the data writing sub-stage t2 in the sharing mode, the timing of each signal is the same as that of the reset sub-stage t2 and the data writing sub-stage t2 in the anti-peep mode. The switching state of each transistor refers to the switching state of the reset sub-stage t2 and the data writing sub-stage t2 in the anti-peep mode, which will not be repeated here.

[0190] In the light-emitting sub-stage in the shared mode, the first light-emitting control signal and the second light-emitting control signal are both in an operating level state. At this time, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, and the driving transistor T3 are all turned on, thereby transmitting the driving current to the first light-emitting device 21 and the second light-emitting device 22, so that the first light-emitting device 21 and the second light-emitting device 22 emit light simultaneously. In addition, the first reset signal, the second reset signal, and the scan signal are all in a non-operating level state, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the tenth transistor T10 are all turned off.

[0191] FIG13 is a timing diagram of the pixel driving circuit in FIG10 in the bidirectional display mode. As shown in FIG13 , the pixel driving circuit includes two working stages in each display cycle. Each working stage includes a reset sub-stage t1, a data writing sub-stage t2, and a light-emitting sub-stage t3.

[0192] During the reset sub-phase t1 of the first operating phase, the first reset signal is at an operating level, and the first transistor T1 is turned on, thereby transmitting the voltage signal on the first initialization voltage line Vinit1 to the N1 node, resetting the N1 node. Furthermore, the second reset signal, the scan signal, the first light-emitting control signal, and the second light-emitting control signal are all at non-operating levels, thereby turning off the second transistor T2 and the fourth transistor T4 through the tenth transistor T10.

[0193] During the data writing sub-phase t2 of the first working phase, the second reset signal is at an operating level, thereby turning on the seventh transistor T7 and the tenth transistor T10, and thereby transmitting the voltage signal on the second initialization voltage line Vinit2 to the first electrode 201 of the first light-emitting device 21 and the first electrode 201 of the second light-emitting device 22. Furthermore, the scan signals are all at an operating level, thereby turning on the second transistor T2 and the fourth transistor T4. The data voltage signal flows through the driving transistor T3 and the second transistor T2 to the control electrode of the driving transistor T3, and the potential of the control electrode of the driving transistor T3 reaches Vdata + Vth. Furthermore, during the data writing sub-phase t2, the first reset signal, the first light-emitting control signal, and the second light-emitting control signal are all at non-operating levels, and the first transistor T1, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 are all turned off.

[0194] During the light-emitting sub-stage t3 of the first operating stage, the first light-emitting control signal is in an active level state, thereby turning on the fifth transistor T5 and the sixth transistor T6. The voltage on the first power line VDD generates a driving current through the fifth transistor T5 and the driving transistor T3, which flows into the first light-emitting device 21. In addition, the second light-emitting control signal, the first reset signal, the second reset signal, and the scan signal are all in a non-operating level state. Therefore, the ninth transistor T9, the eighth transistor T8, the first transistor T1, the second transistor T2, and the fourth transistor T4 are all turned off, and the second light-emitting device 22 does not emit light.

[0195] During the reset sub-phase t1 and the data writing sub-phase t2 of the second working phase, the timing of each signal is the same as that of the reset sub-phase t1 and the data writing sub-phase t2 of the first working phase, and the switching state of each transistor is the same as that of the reset sub-phase t1 and the data writing sub-phase t2 of the first working phase. Detailed description is omitted here.

[0196] During the light-emitting sub-phase t3 of the second operating phase, the second light-emitting control signal is in an operating level state, thereby turning on the ninth transistor T9 and the eighth transistor T8. The voltage on the first power line VDD generates a driving current through the fifth transistor T5 and the driving transistor T3, which flows into the second light-emitting device 22. In addition, the first light-emitting control signal, the first reset signal, the second reset signal, and the scan signal are all in a non-operating level state. Therefore, the fifth transistor T5, the sixth transistor T6, the first transistor T1, the seventh transistor T7, the eighth transistor T8, the fourth transistor T4, and the second transistor T2 are all turned off, and the first light-emitting device 21 does not emit light.

[0197] The present disclosure also provides a display panel comprising a plurality of pixel driving circuits, each of which is electrically connected to a plurality of light-emitting devices 20. The pixel driving circuit includes a driving transistor T3, a light-emitting control subcircuit 105, and a gating subcircuit 106. The light-emitting control subcircuit 105 is configured to, in response to a first light-emitting control signal on a first light-emitting control line EM1 or a second light-emitting control signal on a second light-emitting control line EM2, electrically connect a first power line VDD to a first electrode of the driving transistor T3; and the gating subcircuit 106 is configured to, in response to different light-emitting control signals, electrically connect a second electrode of the driving transistor T3 to different light-emitting devices 20.

[0198] In some embodiments, the pixel driving circuit adopts the structure shown in Figure 4. In this case, the layout of each film layer in the display panel is shown in Figures 14 to 23. In particular, the embodiment of the present disclosure is described by taking the pixel driving circuit as an array arrangement as an example, and multiple pixel driving circuits are arranged in multiple rows along the second direction and in multiple columns along the first direction.

[0199] FIG14 is a plan view of a semiconductor layer of a display panel provided in some embodiments of the present disclosure; FIG15 is a plan view of a first gate metal layer of a display panel provided in some embodiments of the present disclosure; FIG16 is a plan view of a second gate metal layer of a display panel provided in some embodiments of the present disclosure; FIG17 is a plan view of a first source / drain metal layer of a display panel provided in some embodiments of the present disclosure; FIG18 is a plan view of a second source / drain metal layer of a display panel provided in some embodiments of the present disclosure; FIG19 is a schematic diagram of the stacking of the semiconductor layer, the first gate metal layer, the second gate metal layer, the first source / drain metal layer, and the second source / drain metal layer of a display panel provided in some embodiments of the present disclosure; FIG20 is a plan view of a transparent conductive layer of a display panel provided in some embodiments of the present disclosure; FIG21 is a plan view of a first electrode layer of a display panel provided in some embodiments of the present disclosure; FIG22 is a plan view of a pixel defining layer of a display panel provided in some embodiments of the present disclosure; FIG23 is an overall plan view of the display panel provided in some embodiments of the present disclosure after the pixel driving circuit and the first electrode layer are connected; and FIG24 is a cross-sectional view taken along line AA' in FIG23.

[0200] As shown in Figures 14 to 19, the control electrode T8_g of the eighth transistor T8 is electrically connected to the second light-emitting control line EM2, and the second electrode T8_2 is electrically connected to the first electrode 201 of one of the multiple light-emitting devices 20; the orthographic projection of the eighth transistor T8 on the base substrate 30 and the orthographic projection of the driving transistor T3 on the base substrate 30 are respectively located on opposite sides of the orthographic projection of the first light-emitting control line EM1 on the base substrate 30.

[0201] In some embodiments, as shown in Figures 14 to 24, the display panel includes a semiconductor layer ACT, a first gate metal layer G1, a second gate metal layer G2, a first source and drain metal layer SD1, a second source and drain metal layer SD2, a transparent conductive layer TL, a first electrode layer AND1 and a pixel defining layer PDL, which are arranged in sequence along a direction away from the base substrate 30.

[0202] As shown in FIG14 , a semiconductor layer ACT is provided on a substrate 30 , wherein the semiconductor layer ACT can be formed by patterning a semiconductor material, and the semiconductor material can be a polycrystalline silicon material. The semiconductor layer ACT can include an active layer and a doping region pattern of each transistor in the pixel driving circuit. For the same transistor, doping region patterns are provided on both sides of the active layer of the transistor, and the doping region patterns on both sides of the active layer can serve as the first pole and the second pole of the transistor, respectively. FIG14 shows the active layers T1_a to T9_a of each transistor. It should be noted that in the embodiment of the present disclosure, the position of the active layer of each transistor represents the position of the corresponding transistor.

[0203] The second electrode T1_2 of the first transistor T1 and the second electrode T2_2 of the second transistor T2 form an integrated structure. The first electrode T2_1 of the second transistor T2, the second electrode T3_2 of the driving transistor T3, and the first electrode T6_1 of the sixth transistor T6 form an integrated structure. The second electrode T6_2 of the sixth transistor T6 and the first electrode T9_1 of the ninth transistor T9 form an integrated structure. The second electrode T4_2 of the fourth transistor T4, the first electrode T3_1 of the driving transistor T3, and the second electrode T5_2 of the fifth transistor T5 form an integrated structure. The second electrode T7_2 of the seventh transistor T7 and the second electrode T8_2 of the eighth transistor T8 form an integrated structure.

[0204] In an example, the active layer T1_a, the first electrode T1_1, and the second electrode T1_2 of the first transistor T1 are connected into an L-shaped structure, the L-shaped structure including a first extension portion extending along a first direction and a second extension portion extending along a second direction, at least a portion of the first electrode T1_1 of the first transistor T1 is located on the first extension portion, and the second electrode T1_2 of the first transistor T1 is located on the second extension portion.

[0205] In one example, in two adjacent pixel driving circuits in the same column, the active layer T7_a of the seventh transistor T7 in the previous pixel driving circuit and the active layer T1_a of the first transistor T1 in the next pixel driving circuit are arranged substantially along the first direction.

[0206] In an example, the first transistor T1 is located on a side of the driving transistor T3 away from the eighth transistor T8 .

[0207] In some embodiments, a first gate insulating layer GI1 is disposed between the semiconductor layer ACT and the first gate metal layer G1. The first gate insulating layer GI1 may include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The first gate insulating layer GI1 may be formed as a single layer or multiple layers.

[0208] In some embodiments, as shown in FIG15 , the first gate metal layer G1 includes control electrodes T1_g to T9_g of each transistor, and a first electrode plate C11 of a storage capacitor Cst, wherein the first electrode plate C11 of the storage capacitor Cst is shared with the control electrode T3_g of the driving transistor T3. The first transistor T1 and the second transistor T2 can both be dual-gate transistors. The control electrode T2_g of the second transistor T2 and the control electrode T4_g of the fourth transistor T4 in the same pixel driving circuit can be separated, and in two adjacent pixel driving circuits in the same row, the control electrode T2_g of the second transistor T2 of one pixel driving circuit can be connected to the control electrode T4_g of the fourth transistor T4 in the other pixel driving circuit to form an integrated structure. In two adjacent pixel driving circuits in the same column, the control electrode T7_g of the seventh transistor T7 in the previous pixel driving circuit can be connected to the control electrode T1_g of the first transistor T1 in the next pixel driving circuit to form an integrated structure.

[0209] In addition, the first gate metal layer G1 may further include: a first light-emitting control line EM1, a second light-emitting control line EM2, and a third light-emitting control line EM3. The first light-emitting control line EM1, the second light-emitting control line EM2, and the third light-emitting control line EM3 all extend along a first direction. The third light-emitting control line EM3 is located on a side of the first light-emitting control line EM1 away from the driving transistor T3, and the second light-emitting control line EM2 is located on a side of the third light-emitting control line EM3 away from the driving transistor T3. The control electrode T5_g of the fifth transistor T5 and the control electrode T6_g of the sixth transistor T6 are integrally formed with the first light-emitting control line EM1. The control electrode T8_g of the eighth transistor T8 is integrally formed with the second light-emitting control line EM2. The control electrode T9_g of the ninth transistor T9 is integrally formed with the third light-emitting control line EM3.

[0210] It should be noted that the signal line involved in the embodiments of the present disclosure "extending along the first direction" (or "extending along the second direction") does not necessarily mean that the signal line must be a straight line, and it may also have certain bends, as long as the signal line as a whole tends to extend along the first direction (or second direction).

[0211] In some embodiments, the first gate metal layer G1 may include, for example, a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. For example, the first gate metal layer GI1 may include gold (Au), a gold alloy, silver (Ag), a silver alloy, aluminum (Al), an aluminum alloy, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), a copper alloy, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), a molybdenum alloy, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc. The first gate metal layer GI1 may have a single layer or multiple layers.

[0212] In some embodiments, the second gate insulating layer GI2 is disposed on a side of the first gate metal layer G1 away from the base substrate 30. The second gate insulating layer GI2 may include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The second gate insulating layer GI2 may be formed as a single layer or multiple layers.

[0213] In some embodiments, as shown in FIG16 , a second gate metal layer G2 is disposed on a side of the second gate insulation layer GI2 away from the substrate 30. The second gate metal layer G2 may include: a first initialization voltage line Vinit1, a second initialization voltage line Vinit2, and a second electrode C12 of the storage capacitor Cst. The first initialization voltage line Vinit1 is located on a side of the second initialization voltage line Vinit2 away from the second electrode C12 and may have a wavy structure extending generally along a first direction. The second initialization signal line extends generally along the first direction and includes a signal line body and a connector connected to the signal line body. The signal line body extends along the first direction, one end of the connector is connected to the signal line body, and the other end is connected to the first electrode T7_1 of the seventh transistor T7.

[0214] In some embodiments, the interlayer dielectric layer ILD is arranged on the side of the second gate metal layer G2 away from the base substrate 30. The material of the interlayer dielectric layer ILD can be selected from the materials of the first gate insulation layer GI1 and the second gate insulation layer GI2 listed above. The interlayer dielectric layer ILD can be one layer or multiple layers.

[0215] In some embodiments, the first source-drain metal layer SD1 is arranged on a side of the interlayer dielectric layer ILD away from the base substrate 30. As shown in Figure 17, the first source-drain metal layer SD1 includes: a first reset signal line Re1, a scan line GT, a third transfer electrode E3, a fourth transfer electrode E4, a seventh transfer electrode E7, an eighth transfer electrode E8, a ninth transfer electrode E9, a fifteenth transfer electrode E15, a sixteenth transfer electrode E16, and a first sub-power line Vdd1.

[0216] The first reset signal line Re1 extends along a first direction, and the scan line GT has a zigzag structure extending entirely along the first direction. The first sub-power line Vdd1 may include a power line main portion Vdda and a power line connection portion Vddb. The power line main portion Vdda extends along the first direction, and the power line connection portion Vddb is integrally connected to the power line main portion Vdda. The power line connection portion Vddb is electrically connected to the first electrode T5_1 of the fifth transistor T5 via a fifteenth via V15.

[0217] Among them, the first reset signal line Re1, the scan line GT, and the first sub-power line Vdd1 connected to the same pixel driving circuit are arranged in sequence in the second direction, the ninth transfer electrode E9 is located on the side of the first reset signal line Re1 away from the scan line GT, the eighth transfer electrode E8 and the fifteenth transfer electrode E15 are located between the scan line GT and the first reset signal line Re1, the sixteenth transfer electrode E16 is located between the scan line GT and the first sub-power line Vdd1, and the third transfer electrode E3, the fourth transfer electrode E4 and the seventh transfer electrode E7 are located on the side of the first sub-power line Vdd1 away from the scan line GT.

[0218] As shown in FIG17 , the scan line GT can have a zigzag structure and extend generally along the first direction. The scan line GT is electrically connected to the control electrode T4_g of the fourth transistor T4 via the thirty-second via V32. In two adjacent pixel drive circuits in the same row, the control electrode T4_g of the fourth transistor T4 of one pixel drive circuit is integrally connected to the control electrode T2_g of the second transistor T2 of the other pixel drive circuit. Therefore, by electrically connecting the scan line GT to the control electrode T4_g of the fourth transistor T4, the control electrodes T4_g of the fourth transistors T4 and the control electrodes T2_g of the second transistors T2 of multiple pixel drive circuits in the same row can all be connected to the scan line GT.

[0219] 17 , the first reset signal line Re1 is electrically connected to the control electrode T1_g of the first transistor T1 through the seventeenth via V17 , and the first sub-power line Vdd1 is electrically connected to the second plate C12 of the storage capacitor Cst through the thirty-fifth via V35 .

[0220] As shown in FIG. 17 , the third switching electrode E3 is electrically connected to the second electrode of the eighth transistor T8 through the fourth via hole V4 . The third switching electrode E3 is used to connect to the first electrode 201 of one of the light-emitting devices 20 .

[0221] The fourth transfer electrode E4 is electrically connected to the first electrode T8_1 of the eighth transistor T8 through the fifth via V5, and is electrically connected to the second electrode T6_2 of the sixth transistor T6 through the sixth via V6, thereby achieving electrical connection between the second electrode T6_2 of the sixth transistor T6 and the first electrode T8_1 of the eighth transistor T8 via the fourth transfer electrode E4. Each pixel driving circuit corresponds to a fourth transfer electrode E4, and the fourth transfer electrodes E4 corresponding to multiple pixel driving circuits in the same row are arranged along the first direction.

[0222] One end of the seventh transfer electrode E7 is electrically connected to the second electrode T9_2 of the ninth transistor T9 through the tenth via V10, and the other end is electrically connected to the first electrode 201 of the second light-emitting device 22. In one example, the seventh transfer electrode E7 and the fourth transfer electrode E4 are arranged along the first direction, and the seventh transfer electrode E7 can be a strip structure extending along the second direction.

[0223] The eighth transfer electrode E8 is electrically connected to the first electrode T7_1 of the seventh transistor T7 through the eleventh via V11 and to the second initialization voltage line Vinit2 through the twelfth via V12, thereby transmitting the voltage signal on the second initialization voltage line Vinit2 to the first electrode T7_1 of the seventh transistor T7.

[0224] Among them, a portion of the multiple eighth transfer electrodes E8 connected to the multiple pixel driving circuits in the same row can be used to connect to the second initial voltage supply line V2a, thereby transmitting the voltage signal provided by the second initial voltage supply line V2a to the second initialization voltage line Vinit2. For example, the multiple eighth transfer electrodes E8 connected to the multiple pixel driving circuits in the same row include multiple first-type transfer electrodes E81 and multiple second-type transfer electrodes E82, and the first-type transfer electrodes E81 are used to electrically connect to the second initial voltage supply line V2a.

[0225] In some embodiments, as shown in Figure 17, the ninth transfer electrode E9 is electrically connected to the first electrode T1_1 of the first transistor T1 through the eighteenth via V18, and is electrically connected to the first initialization voltage line Vinit1 through the nineteenth via V19, thereby using the ninth transfer electrode E9 to electrically connect the first electrode of the first transistor T1 to the first initialization voltage line Vinit1.

[0226] In some embodiments, the plurality of ninth transfer electrodes E9 connected to the plurality of pixel drive circuits in the same row include a plurality of third-type transfer electrodes E91 and a plurality of fourth-type transfer electrodes E92. The third-type transfer electrodes E91 overlap with the orthographic projection of the first initialization voltage supply line V1a on the base substrate 30, and the third-type transfer electrodes E91 are electrically connected to the first initialization voltage line Vinit1 via a nineteenth via V19. The fourth-type transfer electrodes E92 overlap with the orthographic projection of the first initialization voltage line Vinit1 on the base substrate 30, but do not overlap with the orthographic projection of the first initialization voltage supply line V1a on the base substrate 30. At least one fourth-type transfer electrode E92 is disposed between every two adjacent third-type transfer electrodes E91 arranged along the first direction.

[0227] The third-type transfer electrode E91 can be used to be electrically connected to the first initial voltage supply line V1a, so as to transmit the voltage signal on the first initial voltage supply line V1a to the first initialization voltage line Vinit1.

[0228] The orthographic projection of the third-type switching electrode E91 on the base substrate 30 may overlap with the orthographic projection of the second light-emitting control line EM2 on the base substrate 30 .

[0229] In some embodiments, as shown in FIG. 17 , the fifteenth transfer electrode E15 is used to connect the data line DL and the first electrode T4_1 of the fourth transistor T4 , thereby transmitting the data signal to the fourth transistor T4 .

[0230] As shown in Figure 17, the sixteenth transfer electrode E16 is electrically connected to the control electrode T3_g of the driving transistor T3 through the thirty-third via V33, and is electrically connected to the second electrode T2_2 of the second transistor T2 through the thirty-fourth via V34, thereby realizing the electrical connection between the control electrode T3_g of the driving transistor T3 and the second electrode T2_2 of the second transistor T2.

[0231] As shown in Figures 16 and 17, the second plate C12 of the storage capacitor Cst has an avoidance gap H0, which is located in the middle or edge of the second plate, and the edge of the avoidance gap H0 is located around the thirty-third via V33, so that the orthographic projection of the second plate C12 on the base substrate 30 and the orthographic projection of the thirty-third via V33 on the base substrate 30 do not overlap, thereby preventing the second plate from short-circuiting with the control electrode T3_g (that is, the first plate C11) of the driving transistor T3.

[0232] In some embodiments, in two adjacent rows of pixel driving circuits, the second reset signal line Re2 connected to the pixel driving circuits in the previous row is shared with the first reset signal line Re1 connected to the pixel driving circuits in the next row.

[0233] In some embodiments, the orthographic projection of the first initialization voltage line Vinit1 is located on a side of the orthographic projection of the second initialization voltage line Vinit2 away from the orthographic projection of the first reset signal line Re1 . The orthographic projection of each signal line refers to the orthographic projection of the signal line on the substrate 30 .

[0234] In some embodiments, as shown in FIG24 , an insulating spacer layer 60 is located on the side of the first source / drain metal layer SD1 away from the base substrate 30. The insulating spacer layer 60 may include at least one of a passivation layer and a first planarization layer. For example, the insulating spacer layer 60 may include only a passivation layer, or only a first planarization layer, or a passivation layer and a first planarization layer, with the first planarization layer located on the side of the passivation layer away from the base substrate 30. The material of the passivation layer may be selected from the materials for the first gate insulating layer GI1 listed above, and will not be further described here. The material of the first planarization layer may include an organic insulating material, such as a resin material such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, or siloxane. The passivation layer may be a single layer or multiple layers.

[0235] In some embodiments, the second source-drain metal layer SD2 is located on the side of the insulating spacer layer 60 away from the base substrate 30. The material of the second source-drain metal layer SD2 can be selected from the materials of the first gate metal layer G1 listed above. Of course, in addition to the materials of the first gate metal layer G1 listed above, the second source-drain metal layer SD2 can also be made of molybdenum / titanium alloy or a stack, which can be, for example, a titanium / aluminum / titanium stack.

[0236] As shown in FIG18 , the second source / drain metal layer SD2 may include: a data line DL, a first initial voltage supply line V1a, a second initial voltage supply line V2a, a second sub-power line Vdd2, and a second power line VSS. Each signal line extends along the second direction. The first initial voltage supply line V1a is connected to the first initialization voltage line Vinit1 to provide a first initialization voltage signal to the first initialization voltage line Vinit1; the second initial voltage supply line V2a is connected to the second initialization voltage line Vinit2 to provide a second initialization voltage signal to the second initialization voltage line Vinit2. Multiple first initial voltage supply lines V1a and second initial voltage supply lines V2a can be provided. This allows each first initialization voltage line Vinit1 to be electrically connected to multiple first initial voltage supply lines V1a at multiple locations, and each second initialization voltage line Vinit2 to be electrically connected to multiple second initial voltage supply lines V2a at multiple locations, thereby achieving more uniform voltage distribution across the first initialization voltage line Vinit1 and the second initialization voltage line Vinit2.

[0237] As shown in Figures 17 and 18, the second initial voltage supply line V2a is electrically connected to the eighth transfer electrode E8 via the thirteenth via V13. Since the eighth transfer electrode E8 is electrically connected to the second initialization voltage line Vinit2 via the twelfth via V12, the voltage signal on the second initial voltage supply line V2a can be transmitted to the second initialization voltage line Vinit2 via the eighth transfer electrode E8. In one example, as shown in Figure 17, the plurality of eighth transfer electrodes E8 connected to the pixel driving circuits in the same row include a plurality of first-type transfer electrodes E81 and a plurality of second-type transfer electrodes E82. The orthographic projections of the second initial voltage supply line V2a and the first-type transfer electrodes E81 on the base substrate 30 overlap, thereby electrically connecting the second initial voltage supply line V2a to the first-type transfer electrode E81 through the thirteenth via V13. The orthographic projections of the second initial voltage supply line V2a and the second-type transfer electrodes E82 on the base substrate 30 may not overlap, and the two may not be directly connected.

[0238] As shown in FIG18 , the first initial voltage supply line V1a is electrically connected to the ninth transfer electrode E9 via the twentieth via V20. Since the ninth transfer electrode E9 is electrically connected to the first initialization voltage line Vinit1 via the nineteenth via V19, the ninth transfer electrode E9 can transmit the voltage signal on the first initial voltage supply line V1a to the first initialization voltage line Vinit1. In one example, as shown in FIG17 , the plurality of ninth transfer electrodes E9 connected to the same row of pixel drive circuits include a plurality of third-type transfer electrodes E91 and a plurality of fourth-type transfer electrodes E92. The orthographic projections of the first initial voltage supply line V1a and the third-type transfer electrodes E91 on the base substrate 30 overlap, allowing the first initial voltage supply line V1a to be electrically connected to the third-type transfer electrode E91 through the twentieth via V20. The orthographic projections of the first initial voltage supply line V1a and the fourth-type transfer electrode E92 on the base substrate 30 may not overlap, and the two may not be directly connected.

[0239] As shown in Figures 17 and 18, the first power line VDD includes multiple first sub-power lines Vdd1 and multiple second sub-power lines Vdd2. The multiple first sub-power lines Vdd1 and the multiple second sub-power lines Vdd2 are cross-connected to form a grid structure. This can reduce the voltage drop of the first power line VDD, which is beneficial to the uniformity of the display image.

[0240] In some embodiments, the second sub-power line Vdd2 is connected to the first sub-power line Vdd1 through a sixteenth via V16, and the first sub-power line Vdd1 is electrically connected to the first electrode of the fifth transistor T5 through a fifteenth via V15. For example, the second sub-power line Vdd2 is electrically connected to the power line body Vdda of the first sub-power line Vdd1 through the sixteenth via V16; and the power line connection portion Vddb of the first sub-power line Vdd1 is electrically connected to the first electrode T5_1 of the fifth transistor T5 through the fifteenth via V15.

[0241] In some embodiments, the orthographic projection of the second sub-power line Vdd2 on the base substrate 30 may overlap with the orthographic projection of the active layer of at least one transistor on the base substrate 30, thereby reducing leakage current generated by the transistor due to light exposure and improving the electrical characteristics of the transistor. For example, the orthographic projection of the second sub-power line Vdd2 on the base substrate 30 may overlap with the orthographic projections of the active layer T1_a of the first transistor T1 and the active layer T3_a of the driving transistor T3 on the base substrate 30.

[0242] The second power line VSS is used to electrically connect to the second electrode of each light emitting device 20. For example, the second electrode of the light emitting device 20 extends to the peripheral area, where the second electrode of the light emitting device 20 is connected to the second power line VSS through a via.

[0243] In some embodiments, the orthographic projection of the data line DL on the base substrate 30 overlaps with the orthographic projection of the fifteenth transfer electrode E15 on the base substrate 30, the data line DL is electrically connected to the fifteenth transfer electrode E15 through the thirtieth via V30, and the fifteenth transfer electrode E15 is electrically connected to the first electrode T4_1 of the fourth transistor T4 through the thirty-first via V31.

[0244] In some embodiments, as shown in FIG18 , the plurality of data lines DL include a first data line DL1, a second data line DL2, and a third data line DL3. Each column of pixel driving circuits is electrically connected to a data line DL. The first side of each data line DL is adjacent to the second sub-power line Vdd2. The second side of the first data line DL1 is adjacent to the first initial voltage supply line V1a. The second side of the second data line DL2 is adjacent to the second initial voltage supply line V2a. The second side of the third data line DL3 is adjacent to the second power line VSS. In this case, as shown in FIG17 , two second-type transfer electrodes E82 are disposed between every two adjacent first-type transfer electrodes E81 arranged along the first direction. Two fourth-type transfer electrodes E92 are disposed between every two adjacent third-type transfer electrodes E91 arranged along the first direction.

[0245] In some embodiments, as shown in Figure 18, the data line DL includes a transmission portion DLb and a protruding portion DLa, the protruding portion DLa is electrically connected to the fifteenth transfer electrode E15 through the thirtieth via V30, and the diameter of the protruding portion DLa is larger than the diameter of the transmission portion DLb; the first initial voltage power supply line V1a, the second initial voltage power supply line V2a, the second sub-power line Vdd2, and the second power line VSS are all formed with recessed portions at positions corresponding to the protruding portion DLa.

[0246] In addition, as shown in Figure 18, the second source-drain metal layer SD2 also includes: a second transfer electrode E2 and a sixth transfer electrode E6. The second transfer electrode E2 is electrically connected to the third transfer electrode E3 through a via; the sixth transfer electrode E6 is electrically connected to the seventh transfer electrode E7 through a via, and further electrically connected to the second electrode T9_2 of the ninth transistor T9 through the seventh transfer electrode E7.

[0247] The first sub-power line Vdd1 has a first concave portion Va and a second concave portion Vb on both side edges thereof. The second switching electrode E2 is disposed in the first concave portion Va, and the sixth switching electrode E6 is disposed in the second concave portion Vb.

[0248] In some embodiments, as shown in Figure 24, the second planarization layer PLN2 is arranged on the side of the second source and drain metal layer SD2 away from the base substrate 30. The material of the second planarization layer PLN2 may include an organic insulating material, which can be specifically selected from the materials of the first planarization layer listed above.

[0249] In some embodiments, the transparent conductive layer TL is located on a side of the second planarization layer PLN2 away from the base substrate 30. The transparent conductive layer TL can be made of a transparent material such as indium tin oxide (ITO) or indium zinc oxide (IZO). As shown in FIG20 , the transparent conductive layer TL can include a plurality of first transfer electrodes E1 and a plurality of fifth transfer electrodes E5. Of the two light-emitting devices 20 connected to each pixel driving circuit, the first electrode 201 of one light-emitting device 20 is electrically connected to the first transfer electrode E1, and the first electrode 201 of the other light-emitting device 20 is electrically connected to the fifth transfer electrode E5.

[0250] In some embodiments, as shown in FIG24 , the third planarization layer PLN3 is disposed on a side of the transparent conductive layer TL away from the base substrate 30 . The material of the third planarization layer PLN3 may include an organic insulating material, specifically selected from the materials of the first planarization layer listed above.

[0251] In some embodiments, as shown in Figures 21 and 24, the first electrode layer AND1 is arranged on the side of the third planarization layer PLN3 away from the base substrate 30. The first electrode layer AND1 can be made of transparent materials such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0252] As shown in FIG21 , the first electrode layer AND1 includes the first electrode 201 of each light-emitting device 20. In conjunction with FIG14 to FIG24 , among the two light-emitting devices 20 connected to each pixel driving circuit, the first electrode 201 of one of the light-emitting devices 20 is electrically connected to the first transfer electrode E1 through the first via V1, the first transfer electrode E1 is electrically connected to the second transfer electrode E2 through the second via V2, the second transfer electrode E2 is electrically connected to the third transfer electrode E3 through the third via V3, and the third transfer electrode E3 is electrically connected to the second electrode of the eighth transistor T8 through the fourth via V4. Thus, the first electrode 201 of one of the light-emitting devices 20 is electrically connected to the second electrode T8_2 of the eighth transistor T8 through the first transfer electrode E1, the second transfer electrode E2, and the third transfer electrode E3. For example, in FIG. 14 to FIG. 24 , the electrical connection between the first electrode 201 of the first light emitting device 21 and the second electrode T8_2 of the eighth transistor T8 is achieved through the first switching electrode E1 , the second switching electrode E2 and the third switching electrode E3 .

[0253] As shown in Figures 14 to 24, the first electrode 201 of the second light-emitting device 22 is electrically connected to the fifth transfer electrode E5 through the seventh via hole V7, the fifth transfer electrode E5 is electrically connected to the sixth transfer electrode E6 through the eighth via hole V8, the sixth transfer electrode E6 is electrically connected to the seventh transfer electrode E7 through the ninth via hole V9, and the seventh transfer electrode E7 is electrically connected to the second electrode of the ninth transistor T9 through the tenth via hole V10.

[0254] The display panel also includes a pixel-defining layer (PDL), which is located on the side of the first electrode 201 of the light-emitting device 20 away from the base substrate 30. A pixel opening Pv is defined in the pixel-defining layer PDL, exposing at least a portion of the first electrode 201. The light-emitting functional layer of the light-emitting device 20 is at least partially located within the pixel opening Pv. Among the multiple light-emitting devices 20 connected to the pixel driving circuit, some of the light-emitting devices 20 correspond to multiple pixel openings Pv, while the remaining light-emitting devices 20 correspond to one pixel opening Pv. For example, the first light-emitting device 21 corresponds to one pixel opening Pv, and the second light-emitting device 22 corresponds to two pixel openings Pv.

[0255] A black matrix may be provided on the side of the pixel defining layer PDL away from the base substrate 30, and at least a portion of the orthographic projection of the black matrix on the base substrate 30 does not overlap with the orthographic projection of the pixel openings Pv on the base substrate 30. By aligning some of the light-emitting devices 20 with the plurality of pixel openings Pv, the light emission angle of the light-emitting devices 20 is reduced, thereby improving the anti-peeping effect of the display panel in anti-peeping mode.

[0256] In one example, the multiple light-emitting devices 20 connected to the same pixel drive circuit emit the same color, for example, red, green, blue, or white. The multiple light-emitting devices 20 of the display panel are divided into multiple repeating units, each of which includes multiple light-emitting devices 20 connected to the pixel drive circuits. For example, each repeating unit includes three light-emitting devices 20 connected to the pixel drive circuits. The light-emitting devices 20 connected to the three pixel drive circuits emit red, green, and blue light, respectively.

[0257] In other embodiments, the pixel driving circuit adopts the structure shown in FIG8. In this case, the layout of each film layer in the display panel is shown in FIG25 to FIG34. In particular, the embodiments of the present disclosure are described using the pixel driving circuit arranged in an array as an example, with multiple pixel driving circuits arranged in multiple rows along the second direction and in multiple columns along the first direction.

[0258] FIG25 is a schematic plan view of a semiconductor layer of a display panel provided in other embodiments of the present disclosure; FIG26 is a schematic plan view of a first gate metal layer of a display panel provided in other embodiments of the present disclosure; FIG27 is a schematic plan view of a second gate metal layer of a display panel provided in other embodiments of the present disclosure; FIG28 is a schematic plan view of a first source / drain metal layer of a display panel provided in other embodiments of the present disclosure; FIG29 is a schematic plan view of a second source / drain metal layer of a display panel provided in other embodiments of the present disclosure; FIG30 is a schematic plan view of the semiconductor layer, first gate metal layer, second gate metal layer, first source / drain metal layer, and second source / drain metal layer of a display panel provided in other embodiments of the present disclosure; FIG31 is a schematic plan view of a transparent conductive layer of a display panel provided in other embodiments of the present disclosure; FIG32 is a schematic plan view of a first electrode layer of a display panel provided in other embodiments of the present disclosure; FIG33 is a schematic plan view of a pixel defining layer of a display panel provided in other embodiments of the present disclosure; FIG34 is a plan view of the entire display panel after connection between a pixel driving circuit and the first electrode layer provided in other embodiments of the present disclosure; and FIG35 is a cross-sectional view along line BB' in FIG30.

[0259] As shown in Figures 25 to 34, the control electrode T8_g of the eighth transistor T8 is electrically connected to the second light-emitting control line EM2, and the second electrode is electrically connected to the first electrode 201 of one of the multiple light-emitting devices 20; the orthographic projection of the eighth transistor T8 on the base substrate 30 and the orthographic projection of the driving transistor T3 on the base substrate 30 are respectively located on opposite sides of the orthographic projection of the first light-emitting control line EM1 on the base substrate 30.

[0260] In some embodiments, as shown in Figures 25 to 35, the display panel includes a semiconductor layer ACT, a first gate metal layer G1, a second gate metal layer G2, a first source and drain metal layer SD1, a second source and drain metal layer SD2, a transparent conductive layer TL, a first electrode layer AND1 and a pixel defining layer PDL, which are arranged in sequence along a direction away from the base substrate 30.

[0261] As shown in Figure 25 , a semiconductor layer ACT is disposed on a substrate 30. The semiconductor layer ACT in Figure 25 includes the active layer and doped region patterns of each transistor in the pixel driver circuit shown in Figure 8 . For a given transistor, doped region patterns are provided on both sides of the active layer, and the doped region patterns on both sides of the active layer serve as the transistor's first and second electrodes, respectively. Figure 25 identifies the active layers T1_a through T10_a of each transistor.

[0262] The semiconductor layer ACT shown in FIG25 has a pattern similar to that of the semiconductor layer ACT shown in FIG14 , except that the semiconductor layer ACT shown in FIG25 further includes an active layer T7_a, a first electrode T7_1, and a second electrode T7_2 of the seventh transistor T7. The active layer T7_a of the seventh transistor T7 and the active layer T10_a of the tenth transistor T10 are arranged along a first direction, with the active layer T10_a of the seventh transistor T7 located on a side of the active layer T10_a of the tenth transistor T10 away from the active layer T1_a of the first transistor T1. The first electrode T7_1 of the seventh transistor T7 and the first electrode T10_1 of the tenth transistor T10 are connected to form an integral structure.

[0263] The other structures of the semiconductor layer ACT in FIG25 can be found in the description of FIG14 and will not be repeated here.

[0264] In FIG. 25 to FIG. 35 , the first gate insulating layer GI1 is disposed between the semiconductor layer ACT and the first gate metal layer G1 . The material of the first gate insulating layer GI1 is as described in the above embodiment.

[0265] In Figures 25 to 35, the first gate metal layer G1 is disposed on a side of the first gate insulating layer GI1 away from the base substrate 30. As shown in Figure 26, the first gate metal layer G1 includes: a first light-emitting control line EM1, a second light-emitting control line EM2, and a third light-emitting control line EM3, as well as control electrodes T1_g to T10_g of each transistor. The specific graphical structure of the first gate metal layer G1 is similar to that in Figure 15, except that in Figure 26, the first gate metal layer G1 also includes the control electrode T10_g of the tenth transistor T10, and the control electrode T10_g of the tenth transistor T10 is connected to the control electrode T7_g of the seventh transistor T7 as an integrated structure. In addition, in two adjacent pixel driving circuits in the same column, the control electrode T7_g of the seventh transistor T7 and the control electrode T10_g of the tenth transistor T10 in the previous pixel driving circuit are connected to the control electrode T10_g of the tenth transistor T10 in the next pixel driving circuit as an integrated structure.

[0266] In FIG. 25 to FIG. 35 , the second gate insulating layer GI2 is disposed on a side of the first gate metal layer G1 away from the base substrate 30 . The material of the second gate insulating layer GI2 is as described in the above embodiment and will not be repeated here.

[0267] In Figures 25 to 35, the second gate metal layer G2 is disposed on a side of the second gate insulation layer GI2 away from the base substrate 30 and may include: a first initialization voltage line Vinit1, a second initialization voltage line Vinit2, and a second plate C12 of the storage capacitor Cst. The first initialization voltage line Vinit1 is located on a side of the second initialization voltage line Vinit2 away from the second plate C12 and may have a wavy structure extending overall along a first direction. The second initialization voltage line Vinit2 extends overall along the first direction and includes a signal line main portion Vinit21 and a connecting portion Vinit22 connected to the signal line main portion Vinit21. The signal line main portion Vinit21 extends along the first direction, and one end of the connecting portion Vinit22 is connected to the signal line main portion Vinit21.

[0268] As shown in FIG. 25 to FIG. 35 , the interlayer dielectric layer ILD is disposed on a side of the second gate metal layer G2 away from the base substrate 30 . The material of the interlayer dielectric layer ILD is as described in the above embodiment.

[0269] As shown in Figures 25 to 35, the first source-drain metal layer SD1 is arranged on the side of the interlayer dielectric layer ILD away from the base substrate 30, and includes: a first reset signal line Re1, a scan line GT, a third transfer electrode E3, a fourth transfer electrode E4, a seventh transfer electrode E7, an eighth transfer electrode E8, a ninth transfer electrode E9, a fifteenth transfer electrode E15, a sixteenth transfer electrode E16, and a first sub-power line Vdd1.

[0270] In FIG28 , the seventh transition electrode E7 extends substantially along the second direction, and the length of the seventh transition electrode E7 may be greater than that of the seventh transition electrode E7 in FIG17 . Furthermore, unlike the seventh transition electrode E7 in FIG17 , in FIG28 , the seventh transition electrode E7 is electrically connected to the second electrode T9_2 of the ninth transistor T9 and the first electrode 201 of the second light-emitting device 22, in addition to being electrically connected to the second electrode T10_2 of the tenth transistor T10. For example, the end of the seventh transition electrode E7 remote from the first sub-power line Vdd1 is electrically connected to the second electrode T10_2 of the tenth transistor T10 via a fourteenth via V14. The middle portion of the seventh transition electrode E7 is electrically connected to the second electrode T9_2 of the ninth transistor T9 via a tenth via V10. The seventh transition electrode E7, located near the first sub-power line Vdd1, is connected to the first electrode 201 of the second light-emitting device 22.

[0271] The connection relationship of the other structures in FIG28 except the seventh transfer electrode E7 can be found in the above description of FIG17 , which will not be repeated here.

[0272] As shown in FIG. 25 to FIG. 35 , the insulating spacer layer 60 is located on the side of the first source / drain metal layer SD1 away from the base substrate 30 . The specific material thereof is described in the above embodiment and will not be repeated here.

[0273] The second source-drain metal layer SD2 is arranged on the side of the insulating spacer layer 60 away from the base substrate 30. The material and structure of the second source-drain metal layer SD2 can be the same as the second source-drain metal layer SD2 in Figure 18, which will not be repeated here.

[0274] As shown in Figures 25 to 35 , the second planarization layer is disposed on the side of the second source / drain metal layer SD2 away from the base substrate 30. The transparent conductive layer TL is located on the side of the second planarization layer away from the base substrate 30. The third planarization layer is disposed on the side of the transparent conductive layer TL away from the base substrate 30. The first electrode layer AND1 is disposed on the side of the third planarization layer away from the base substrate 30. The first electrode layer AND1 includes the first electrode 201 of each light-emitting device 20. The pixel-defining layer PDL is located on the side of the first electrode 201 of the light-emitting device 20 away from the base substrate 30. The materials and structures of each layer in the second planarization layer, transparent conductive layer TL, third planarization layer, first electrode layer AND1, and pixel-defining layer can be found in the description of Figures 14 to 24 above and will not be repeated here.

[0275] In some further embodiments, the pixel driving circuit adopts the structure shown in FIG10. In this case, the layout of each film layer in the display panel is shown in FIG36 to FIG46. In particular, the embodiments of the present disclosure are described by taking the pixel driving circuits arranged in an array as an example, with multiple pixel driving circuits arranged in multiple rows along the second direction and in multiple columns along the first direction.

[0276] FIG36 is a plan view of a semiconductor layer of a display panel provided in further embodiments of the present disclosure; FIG37 is a plan view of a first gate metal layer of a display panel provided in further embodiments of the present disclosure; FIG38 is a plan view of a second gate metal layer of a display panel provided in further embodiments of the present disclosure; FIG39 is a plan view of a first source / drain metal layer of a display panel provided in further embodiments of the present disclosure; FIG40 is a plan view of a second source / drain metal layer of a display panel provided in further embodiments of the present disclosure; FIG41 is a schematic view of the semiconductor layer, first gate metal layer, second gate metal layer, first source / drain metal layer, and second source / drain metal layer of a display panel provided in further embodiments of the present disclosure; FIG42 is a plan view of a transparent conductive layer of a display panel provided in further embodiments of the present disclosure; FIG43 is a plan view of a first electrode layer of a display panel provided in further embodiments of the present disclosure; FIG44 is a plan view of a pixel defining layer of a display panel provided in further embodiments of the present disclosure; FIG45 is an overall plan view of a pixel driving circuit and a first electrode layer of a display panel provided in further embodiments of the present disclosure after connection; and FIG46 is a cross-sectional view along line CC' in FIG41.

[0277] As shown in Figures 36 to 46, the control electrode T8_g of the eighth transistor T8 is electrically connected to the second light-emitting control line EM2, and the second electrode is electrically connected to the first electrode 201 of one of the multiple light-emitting devices 20; the orthographic projection of the eighth transistor T8 on the base substrate 30 and the orthographic projection of the driving transistor T3 on the base substrate 30 are respectively located on opposite sides of the orthographic projection of the first light-emitting control line EM1 on the base substrate 30.

[0278] As shown in Figure 36 , a semiconductor layer ACT is provided on a base substrate 30 . The material and shape of the semiconductor layer ACT in Figure 36 are the same as those of the semiconductor layer ACT in Figure 14 . Specifically, the semiconductor layer ACT in Figure 36 includes active layers T1_a to T10_a of the transistors.

[0279] The second electrode T1_2 of the first transistor T1 and the second electrode T2_2 of the second transistor T2 form an integrated structure. The first electrode T2_1 of the second transistor T2, the second electrode T3_2 of the driving transistor T3, and the first electrode T6_1 of the sixth transistor T6 form an integrated structure. The second electrode T4_2 of the fourth transistor T4, the first electrode T3_1 of the driving transistor T3, and the second electrode T5_2 of the fifth transistor T5 form an integrated structure. The first electrode T5_1 of the fifth transistor T5 and the first electrode T9_1 of the ninth transistor T9 form an integrated structure. The second electrode T7_2 of the seventh transistor T7 and the second electrode T8_2 of the eighth transistor T8 form an integrated structure. The first electrode T7_1 of the seventh transistor T7 and the first electrode T10_1 of the tenth transistor T10 form an integrated structure. The active layer T7_a of the seventh transistor T7 and the active layer T10_a of the tenth transistor T10 are arranged along a first direction. The active layer T9_a of the ninth transistor T9 and the active layer T8_a of the eighth transistor T8 are arranged along the first direction.

[0280] As shown in Figure 36, in one example, the active layer T1_a, the first electrode T1_1 and the second electrode T1_2 of the first transistor T1 are connected into an L-shaped structure, and the L-shaped structure includes a first extension portion extending along a first direction and a second extension portion extending along a second direction. At least a portion of the first electrode T1_1 of the first transistor T1 is located on the first extension portion, and the second electrode T1_2 of the first transistor T1 is located on the second extension portion.

[0281] In an example, in two adjacent pixel driving circuits in the same column, the active layer T7_a of the seventh transistor T7 and the active layer T10_a of the tenth transistor T10 in the previous pixel driving circuit and the active layer T1_a of the first transistor T1 in the next pixel driving circuit are arranged roughly along the first direction.

[0282] In an example, the first transistor T1 is located on a side of the driving transistor T3 away from the eighth transistor T8 .

[0283] As shown in FIG46 , the first gate insulating layer GI1 is disposed on a side of the semiconductor layer ACT away from the base substrate 30 . The material of the first gate insulating layer GI1 is as described in the above embodiment and will not be repeated here.

[0284] As shown in FIG37 , the material of the first gate metal layer G1 can be the same as that of the gate metal layer G1 in FIG15 , and its shape is similar. The difference is that in FIG37 , in addition to the control electrodes T1_g to T9_g of the first to ninth transistors T1 to T9 and the first electrode plate C11 of the storage capacitor Cst, the first gate metal layer G1 also includes the control electrode T10_g of the tenth transistor T10. Furthermore, the first gate metal layer G1 includes the first and second emission control lines EM1 and EM2, but does not include the third emission control line EM3. As shown in FIG37 , the first emission control line EM1 is located between the second emission control line EM2 and the first electrode plate C11. Both the first transistor T1 and the second transistor T2 can be dual-gate transistors. In two adjacent rows of pixel driver circuits, the control electrode T7_g of the seventh transistor T7 and the control electrode T10_g of the tenth transistor T10 in the pixel driver circuit of the previous row can be connected to one of the control electrodes T1_g of the first transistor T1 in the pixel driver circuit of the next row, forming an integrated structure.

[0285] As shown in Figure 37, the control electrode T5_g of the fifth transistor T5, the control electrode T6_g of the sixth transistor T6 and the first light-emitting control line EM1 form an integrated structure; the control electrode T8_g of the eighth transistor T8 and the control electrode T9_g of the ninth transistor T9 form an integrated structure with the second light-emitting control line EM2.

[0286] As shown in FIG37 , the first plate C11 of the storage capacitor Cst shares a common control electrode T3_g of the driving transistor T3. The control electrode T2_g of the second transistor T2 and the control electrode T4_g of the fourth transistor T4 in the same pixel driving circuit can be separated. In two adjacent pixel driving circuits in the same row, the control electrode T2_g of the second transistor T2 in one pixel driving circuit can be connected to the control electrode T4_g of the fourth transistor T4 in the other pixel driving circuit to form an integrated structure.

[0287] As shown in FIG46 , the second gate insulating layer GI2 is disposed on a side of the first gate metal layer G1 away from the base substrate 30 . The material of the second gate insulating layer GI2 is as described in the above embodiment and will not be repeated here.

[0288] As shown in FIG46 , the second gate metal layer G2 is disposed on a side of the second gate insulation layer GI2 away from the substrate 30. As shown in FIG38 , the second gate metal layer G2 includes a first initialization voltage line Vinit1, a second initialization voltage line Vinit2, and a second electrode plate C12 of the storage capacitor Cst. The first initialization voltage line Vinit1 is located on a side of the second initialization voltage line Vinit2 away from the second electrode plate C12 and may have a wavy structure extending generally in a first direction. The second initialization signal line extends generally in the first direction and includes a signal line body and a connector connected to the signal line body. The signal line body extends in the first direction, one end of the connector is connected to the signal line body, and the other end is connected to the first electrode T7_1 of the seventh transistor T7.

[0289] As shown in FIG46 , the interlayer dielectric layer ILD is disposed on a side of the second gate metal layer G2 away from the base substrate 30 . The material thereof is described in the above embodiment and will not be repeated here.

[0290] As shown in FIG46 , the first source / drain metal layer SD1 is disposed on a side of the interlayer dielectric layer ILD away from the base substrate 30. As shown in FIG39 , the first source / drain metal layer SD1 includes: a first reset signal line Re1, a scan line GT, a first sub-power line Vdd1, a third transfer electrode E3, an eighth transfer electrode E8, a ninth transfer electrode E9, a tenth transfer electrode E10, an eleventh transfer electrode E11, a fourteenth transfer electrode E14, a fifteenth transfer electrode E15, and a sixteenth transfer electrode E16.

[0291] The first reset signal line Re1 extends along a first direction, and the scan line GT has a zigzag structure extending entirely along the first direction. The first sub-power line Vdd1 can include a power line main portion Vdda and a power line connection portion Vddb. The power line main portion Vdda extends along the first direction, and the power line connection portion Vddb extends along a second direction and is integrally connected to the power line main portion Vdda. The power line connection portion Vddb is electrically connected to the first electrode T5_1 of the fifth transistor T5 through a fifteenth via V15.

[0292] Among them, the first reset signal line Re1, the scan line GT, and the first sub-power line Vdd1 connected to the same pixel driving circuit are arranged in sequence in the second direction, the ninth transfer electrode E9 is located on the side of the first reset signal line Re1 away from the scan line GT, the eighth transfer electrode E8 and the fifteenth transfer electrode E15 are located between the scan line GT and the first reset signal line Re1, the sixteenth transfer electrode E16 is located between the scan line GT and the first sub-power line Vdd1, and the third transfer electrode E3 is located on the side of the first sub-power line Vdd1 away from the scan line GT.

[0293] As shown in FIG39 , the scan line GT can have a zigzag structure and generally extend along the first direction. The scan line GT is electrically connected to the control electrode T4_g of the fourth transistor T4 via the thirty-second via V32. In two adjacent pixel drive circuits in the same row, the control electrode T4_g of the fourth transistor T4 of one pixel drive circuit is integrally connected to the control electrode T2_g of the second transistor T2 of the other pixel drive circuit. Therefore, by electrically connecting the scan line GT to the control electrode T4_g of the fourth transistor T4, the control electrodes T4_g of the fourth transistors T4 and the control electrodes T2_g of the second transistors T2 of multiple pixel drive circuits in the same row can all be connected to the scan line GT.

[0294] 39 , the first reset signal line Re1 is electrically connected to the control electrode T1_g of the first transistor T1 through the seventeenth via V17, and the first sub-power line Vdd1 is electrically connected to the second plate C12 of the storage capacitor Cst through the thirty-fifth via V35.

[0295] As shown in FIG. 39 , the third switching electrode E3 is electrically connected to the second electrode of the eighth transistor T8 through the fourth via hole V4 . The third switching electrode E3 is used to connect to the first electrode 201 of one of the light-emitting devices 20 .

[0296] As shown in FIG39 , the arrangement positions and connection relationships of the eighth switching electrode E8 and the ninth switching electrode E9 are similar to those described in the above embodiment and are not described again here.

[0297] As shown in Figure 39, the tenth transfer electrode E10 is located on the side of the first sub-power line Vdd1 away from the scan line GT. The tenth transfer electrode E10 is electrically connected to the second electrode T5_2 of the fifth transistor T5 through the twenty-first via hole V21, and is electrically connected to the second electrode T9_2 of the ninth transistor T9 through the twenty-second via hole V22, thereby realizing the electrical connection between the second electrode T5_2 of the fifth transistor T5 and the second electrode T9_2 of the ninth transistor T9.

[0298] As shown in Figure 39, the eleventh conversion electrode E11 is located on the side of the first sub-power line Vdd1 away from the scan line GT. The eleventh conversion electrode E11 is electrically connected to the first electrode T8_1 of the eighth transistor T8 through the twenty-third via hole V23, and is electrically connected to the second electrode T3_2 of the driving transistor T3 through the twenty-fourth via hole V24, thereby realizing the electrical connection between the first electrode T8_1 of the eighth transistor T8 and the second electrode T3_2 of the driving transistor T3.

[0299] As shown in FIG39 , the fourteenth transfer electrode E14 is electrically connected to the second electrode T6_2 of the sixth transistor T6 through the twenty-eighth via hole V28 and is electrically connected to the second electrode T7_2 of the seventh transistor T7 through the twenty-ninth via hole V29, thereby achieving electrical connection between the second electrode T6_2 of the sixth transistor T6 and the second electrode T7_2 of the seventh transistor T7.

[0300] As shown in FIG. 39 , the fifteenth transfer electrode E15 is used to connect the data line DL and the first electrode T4_1 of the fourth transistor T4 , thereby transmitting the data signal to the fourth transistor T4 .

[0301] As shown in Figure 39, the sixteenth transfer electrode E16 is electrically connected to the control electrode T3_g of the driving transistor T3 through the thirty-third via V33, and is electrically connected to the second electrode T2_2 of the second transistor T2 through the thirty-fourth via V34, thereby realizing the electrical connection between the control electrode T3_g of the driving transistor T3 and the second electrode T2_2 of the second transistor T2.

[0302] As shown in FIG46 , the insulating spacer layer 60 is located on the side of the first source / drain metal layer SD1 away from the base substrate 30 . The material thereof is described in the above embodiment and will not be repeated here.

[0303] As shown in FIG46 , the second source-drain metal layer SD2 is located on the side of the insulating spacer layer 60 away from the base substrate 30 . The material thereof is described in the above embodiment and will not be repeated here.

[0304] 40 , the second source / drain metal layer SD2 may include: a data line DL, a first initial voltage supply line V1a, a second initial voltage supply line V2a, a second sub-power line Vdd2, and a second power line VSS. Each signal line extends along the second direction.

[0305] As shown in Figures 39 and 40, the second initial voltage supply line V2a is electrically connected to the eighth transfer electrode E8 via the thirteenth via V13. Since the eighth transfer electrode E8 is electrically connected to the second initialization voltage line Vinit2 via the twelfth via V12, the voltage signal on the second initial voltage supply line V2a can be transmitted to the second initialization voltage line Vinit2 via the eighth transfer electrode E8. In one example, as shown in Figure 39, the plurality of eighth transfer electrodes E8 connected to the pixel driving circuits in the same row include a plurality of first-type transfer electrodes E81 and a plurality of second-type transfer electrodes E82. The orthographic projections of the second initial voltage supply line V2a and the first-type transfer electrodes E81 on the base substrate 30 overlap, thereby electrically connecting the second initial voltage supply line V2a to the first-type transfer electrode E81 through the thirteenth via V13. The orthographic projections of the second initial voltage supply line V2a and the second-type transfer electrodes E82 on the base substrate 30 may not overlap, and the two may not be directly connected.

[0306] As shown in Figures 39 and 40, the first initial voltage supply line V1a is electrically connected to the ninth transfer electrode E9 via the twentieth via V20. Since the ninth transfer electrode E9 is electrically connected to the first initialization voltage line Vinit1 via the nineteenth via V19, the voltage signal on the first initial voltage supply line V1a can be transmitted to the first initialization voltage line Vinit1 via the ninth transfer electrode E9. In one example, as shown in Figure 39, the plurality of ninth transfer electrodes E9 connected to the same row of pixel driving circuits include a plurality of third-type transfer electrodes E91 and a plurality of fourth-type transfer electrodes E92. The orthographic projections of the first initial voltage supply line V1a and the third-type transfer electrodes E91 on the base substrate 30 overlap, allowing the first initial voltage supply line V1a to be electrically connected to the third-type transfer electrode E91 through the twentieth via V20. The orthographic projections of the first initial voltage supply line V1a and the fourth-type transfer electrode E92 on the base substrate 30 may not overlap, and the two may not be directly connected.

[0307] As shown in Figures 39 and 40, the first power line VDD includes multiple first sub-power lines Vdd1 and multiple second sub-power lines Vdd2. The multiple first sub-power lines Vdd1 and the multiple second sub-power lines Vdd2 are cross-connected to form a grid structure. This can reduce the voltage drop of the first power line VDD, which is beneficial to the uniformity of the display image.

[0308] In some embodiments, as shown in Figures 39 and 40, the second sub-power line Vdd2 is connected to the first sub-power line Vdd1 through a sixteenth via V16, and the first sub-power line Vdd1 is electrically connected to the first electrode of the fifth transistor T5 through a fifteenth via V15. For example, the second sub-power line Vdd2 is electrically connected to the power line main portion Vdda of the first sub-power line Vdd1 through the sixteenth via V16; and the power line connection portion Vddb of the first sub-power line Vdd1 is electrically connected to the first electrode T5_1 of the fifth transistor T5 through the fifteenth via V15.

[0309] In some embodiments, as shown in Figures 40 and 41 , the orthographic projection of the second sub-power line Vdd2 on the substrate 30 can overlap with the orthographic projection of the active layer of at least one transistor on the substrate 30, thereby reducing leakage current generated by the transistor due to light exposure and improving the electrical characteristics of the transistor. For example, the orthographic projection of the second sub-power line Vdd2 on the substrate 30 overlaps with the orthographic projections of the active layer T1_a of the first transistor T1 and the active layer T3_a of the driving transistor T3 on the substrate 30.

[0310] The second power line VSS is used to electrically connect to the second electrode of each light emitting device 20. For example, the second electrode of the light emitting device 20 extends to the peripheral area, where the second electrode of the light emitting device 20 is connected to the second power line VSS through a via.

[0311] In some embodiments, as shown in Figures 39 to 41, the orthographic projection of the data line DL on the base substrate 30 overlaps with the orthographic projection of the fifteenth transfer electrode E15 on the base substrate 30, the data line DL is electrically connected to the fifteenth transfer electrode E15 through the thirtieth via hole V30, and the fifteenth transfer electrode E15 is electrically connected to the first electrode T4_1 of the fourth transistor T4 through the thirty-first via hole V31.

[0312] In some embodiments, as shown in Figure 40, the multiple data lines DL include a first data line DL1, a second data line DL2 and a third data line DL3, each column of pixel driving circuit is electrically connected to a data line DL, the first side of each data line DL is adjacent to the second sub-power line Vdd2, the second side of the first data line DL1 is adjacent to the first initial voltage supply line V1a, the second side of the second data line DL2 is adjacent to the second initial voltage supply line V2a, and the second side of the third data line DL3 is adjacent to the second power line VSS.

[0313] In some embodiments, as shown in Figures 39 to 41, the orthographic projections of the first initial voltage supply line V1a, the second initial voltage supply line V2a, and the second power line VSS on the base substrate 30 all overlap with the orthographic projection of the tenth transfer electrode E10 on the base substrate 30.

[0314] In some embodiments, as shown in Figure 40, the data line DL includes a transmission portion DLb and a protruding portion DLa, the protruding portion DLa is electrically connected to the fifteenth transfer electrode E15 through the thirtieth via V30, and the diameter of the protruding portion DLa is larger than the diameter of the transmission portion DLb; the first initial voltage power supply line V1a, the second initial voltage power supply line V2a, the second sub-power line Vdd2, and the second power line VSS all form a curved structure at the position corresponding to the protruding portion DLa to avoid the protruding portion DLa.

[0315] As shown in FIG40 , the second source-drain metal layer SD2 further includes a second transfer electrode E2 and a thirteenth transfer electrode E13. The second transfer electrode E2 is electrically connected to the third transfer electrode E3 via a via. The thirteenth transfer electrode E13 is electrically connected to the fourteenth transfer electrode E14 via a twenty-seventh via V27. The fourteenth transfer electrode E14 is electrically connected to the second electrode T6_2 of the sixth transistor T6 via a twenty-eighth via V28. The thirteenth transfer electrode E13 is used to connect to the first electrode 201 of the first light-emitting device 21, thereby electrically connecting the first electrode 201 of the first light-emitting device 21 to the second electrode T6_2 of the sixth transistor T6.

[0316] As shown in FIG40 , both side edges of the first sub-power line Vdd1 have a first concave portion Va and a second concave portion Vb, respectively. The second switching electrode E2 is disposed in the first concave portion Va, and the thirteenth switching electrode E13 is disposed in the second concave portion Vb.

[0317] The second planarization layer is disposed on a side of the second source / drain metal layer SD2 away from the base substrate 30 . The material thereof is as described in the above embodiment and will not be described again here.

[0318] The transparent conductive layer TL is located on a side of the second planarization layer away from the base substrate 30 . The material of the transparent conductive layer TL is as described in the above embodiment and will not be described again here.

[0319] As shown in Figure 42, the transparent conductive layer TL includes multiple first transfer electrodes E1 and multiple twelfth transfer electrodes E12, wherein, among the two light-emitting devices 20 connected to each pixel driving circuit, the first electrode 201 of one light-emitting device 20 is electrically connected to the first transfer electrode E1, and the first electrode 201 of the other light-emitting device 20 is electrically connected to the fifth transfer electrode E5.

[0320] The third planarization layer is disposed on a side of the transparent conductive layer TL away from the base substrate 30 . The material of the third planarization layer is as described in the above embodiment and will not be described again here.

[0321] As shown in FIG43 , the first electrode layer AND1 is disposed on a side of the third planarization layer away from the base substrate 30 . The first electrode layer AND1 may be made of a transparent material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0322] The first electrode layer AND1 includes the first electrode 201 of each light-emitting device 20. As shown in Figures 36 to 46 , among the two light-emitting devices 20 connected to each pixel driving circuit, the first electrode 201 of one of the light-emitting devices 20 is electrically connected to the first transfer electrode E1 through a first via V1. The first transfer electrode E1 is electrically connected to the second transfer electrode E2 through a second via V2. The second transfer electrode E2 is electrically connected to the third transfer electrode E3 through a third via V3. The third transfer electrode E3 is electrically connected to the second electrode of the eighth transistor T8 through a fourth via V4. Thus, the first electrode 201 of one of the light-emitting devices 20 is electrically connected to the second electrode T8_2 of the eighth transistor T8 via the first transfer electrode E1, the second transfer electrode E2, and the third transfer electrode E3. For example, in Figures 36 to 46 , the first electrode 201 of the second light-emitting device 22 is electrically connected to the second electrode T8_2 of the eighth transistor T8 via the first transfer electrode E1, the second transfer electrode E2, and the third transfer electrode E3.

[0323] As shown in Figures 36 to 46, the first electrode 201 of the first light-emitting device is electrically connected to the twelfth transfer electrode E12 via the twenty-fifth via hole V25. The twelfth transfer electrode E12 is electrically connected to the thirteenth transfer electrode E13 via the twenty-sixth via hole V26. The thirteenth transfer electrode E13 is electrically connected to the fourteenth transfer electrode E14 via the twenty-seventh via hole V27. The fourteenth transfer electrode E14 is electrically connected to the second electrode T6_2 of the sixth transistor T6 via the twenty-eighth via hole V28. The electrical connection between the first light-emitting device 21 and the second electrode T6_2 of the sixth transistor T6 is achieved through the twelfth transfer point, the thirteenth transfer electrode E13, and the fourteenth transfer electrode E14.

[0324] The display panel also includes a pixel-defining layer (PDL), which is located on the side of the first electrode 201 of the light-emitting device 20 away from the base substrate 30. A pixel opening Pv is defined in the pixel-defining layer PDL, exposing at least a portion of the first electrode 201. The light-emitting functional layer of the light-emitting device 20 is at least partially located within the pixel opening Pv. Among the multiple light-emitting devices 20 connected to the pixel driving circuit, some of the light-emitting devices 20 correspond to multiple pixel openings Pv, while the remaining light-emitting devices 20 correspond to one pixel opening Pv. For example, the first light-emitting device 21 corresponds to one pixel opening Pv, and the second light-emitting device 22 corresponds to two pixel openings Pv.

[0325] The light-emitting functional layer may include a light-emitting layer, which may include a small molecule organic material or a polymer molecule organic material, and may be a fluorescent light-emitting material or a phosphorescent light-emitting material, and may emit red, green, blue, or white light. Furthermore, as needed, the light-emitting functional layer may also include a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer, and the like.

[0326] In one example, the multiple light-emitting devices 20 connected to the same pixel drive circuit emit the same color, for example, red, green, blue, or white. The multiple light-emitting devices 20 of the display panel are divided into multiple repeating units, each of which includes multiple light-emitting devices 20 connected to the pixel drive circuits. For example, each repeating unit includes three light-emitting devices 20 connected to the pixel drive circuits. The light-emitting devices 20 connected to the three pixel drive circuits emit red, green, and blue light, respectively.

[0327] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A pixel driving circuit, comprising: A driving transistor, a first reset subcircuit, a second reset subcircuit, a light emitting control subcircuit, a data writing subcircuit, a gating subcircuit and an energy storage element; The energy storage element is connected between the control electrode and the first electrode of the driving transistor; wherein, The first reset subcircuit is configured to write a first initialization voltage signal to the control electrode of the driving transistor in response to a first reset signal; The second reset subcircuit is configured to write a second initialization voltage signal to a first electrode of at least one of the plurality of light emitting devices in response to a second reset signal; The data writing subcircuit is configured to write a data voltage signal and a threshold voltage signal of the driving transistor into the energy storage element in response to a scan signal; The light emitting control subcircuit is configured to connect the first power line to the first electrode of the driving transistor in response to one of the first light emitting control signal and the second light emitting control signal; The gating subcircuit is configured to connect the second electrode of the driving transistor to different light emitting devices in response to different light emitting control signals.

2. The pixel driving circuit according to claim 1, wherein: The light emitting control subcircuit comprises: A fifth transistor, wherein a control electrode of the fifth transistor is electrically connected to the first light emitting control line, a first electrode is electrically connected to the first power supply line, and a second electrode is electrically connected to the first electrode of the driving transistor.

3. The pixel driving circuit according to claim 2, wherein: The gating subcircuit comprises: a sixth transistor, an eighth transistor and a ninth transistor, wherein: The control electrode of the sixth transistor is electrically connected to the first light emitting control line, and the first electrode of the sixth transistor is electrically connected to the second electrode of the driving transistor; The control electrode of the eighth transistor is electrically connected to the second light emitting control line, the first electrode of the eighth transistor is electrically connected to the second electrode of the sixth transistor, and the second electrode of the eighth transistor is electrically connected to the The first light emitting device is electrically connected; The control electrode of the ninth transistor is electrically connected to the third light emitting control line, the first electrode of the ninth transistor is electrically connected to the second electrode of the sixth transistor, and the second electrode of the ninth transistor is electrically connected to the second light emitting device.

4. The pixel driving circuit according to claim 1, wherein: The light emitting control subcircuit comprises: a fifth transistor and a ninth transistor, wherein: The control electrode of the fifth transistor is electrically connected to the first light emitting control line, the first electrode is electrically connected to the first power line, and the second electrode is electrically connected to the first electrode of the driving transistor; The control electrode of the ninth transistor is electrically connected to the second light emitting control line, the first electrode is electrically connected to the first power line, and the second electrode is electrically connected to the first electrode of the driving transistor.

5. The pixel driving circuit according to claim 4, wherein: The gating subcircuit comprises: a sixth transistor and an eighth transistor; wherein, The control electrode of the sixth transistor is electrically connected to the first light emitting control line, the first electrode is electrically connected to the second electrode of the driving transistor, and the second electrode is electrically connected to the first light emitting device; The control electrode of the eighth transistor is electrically connected to the second light emitting control line, the first electrode is electrically connected to the second electrode of the driving transistor, and the second electrode is electrically connected to the second light emitting device.

6. The pixel driving circuit according to any one of claims 1 to 5, wherein: The first reset subcircuit includes: a first transistor, a control electrode of the first transistor is electrically connected to a first reset signal line, a first electrode is electrically connected to a first initialization voltage line, and a second electrode is electrically connected to a control electrode of the driving transistor.

7. The pixel driving circuit according to any one of claims 1 to 5, wherein: The second reset subcircuit includes: a seventh transistor, a control electrode of the seventh transistor is electrically connected to the second reset signal line, a first electrode is electrically connected to the second initialization voltage line, and a second electrode is electrically connected to the first electrode of the first light emitting device.

8. The pixel driving circuit according to claim 7, wherein: The second reset subcircuit further includes: a tenth transistor, a control electrode of the tenth transistor is electrically connected to the second reset signal line, a first electrode is electrically connected to the second initialization voltage line, and a second electrode is electrically connected to the first electrode of the second light emitting device.

9. The pixel driving circuit according to any one of claims 1 to 5, wherein: The data writing sub-circuit comprises: a fourth transistor and a second transistor, The control electrode of the fourth transistor is electrically connected to the scan line, the first electrode is electrically connected to the data line, and the second electrode is electrically connected to the first electrode of the driving transistor; The control electrode of the second transistor is electrically connected to the scan line, the first electrode is electrically connected to the second electrode of the driving transistor, and the second electrode is electrically connected to the control electrode of the driving transistor.

10. The pixel driving circuit according to any one of claims 1 to 5, wherein: The energy storage element includes a storage capacitor, and the storage capacitor includes a first plate and a second plate. The first plate is electrically connected to the control electrode of the driving transistor, and the second plate is electrically connected to the first electrode of the driving transistor.

11. A driving method for a pixel driving circuit as claimed in any one of claims 1 to 10, comprising a plurality of working stages, wherein: In the reset sub-phase of each of the working phases, the first reset sub-circuit writes a first initialization voltage signal to the control electrode of the driving transistor in response to a first reset signal; In each data writing sub-phase of the working phase, the second reset sub-circuit writes a second initialization signal to the first electrode of at least one of the plurality of light emitting devices in response to the second reset signal. voltage signal; the data writing subcircuit writes the data voltage signal and the threshold voltage signal of the driving transistor into the energy storage element in response to the scan signal; In the light-emitting sub-stage of each of the working stages, the light-emitting control sub-circuit responds to at least one of the first light-emitting control signal and the second light-emitting control signal to connect the first power line to the first electrode of the driving transistor; and, in the light-emitting sub-stages of different working stages, the selection sub-circuit responds to different light-emitting control signals to connect the second electrode of the driving transistor to different light-emitting devices.

12. A display panel, comprising: A base substrate and a plurality of pixel driving circuits disposed on the base substrate, each of the plurality of pixel driving circuits being electrically connected to a plurality of light emitting devices; The pixel driving circuit includes: a driving transistor, a light emitting control subcircuit, and a gating subcircuit; wherein, The light emitting control subcircuit is configured to connect the first power line to the first electrode of the driving transistor in response to a first light emitting control signal on the first light emitting control line or a second light emitting control signal on the second light emitting control line; The gating subcircuit is configured to connect the second electrode of the driving transistor to different light emitting devices in response to different light emitting control signals; Wherein, the selection subcircuit includes: an eighth transistor, the control electrode of the eighth transistor is electrically connected to the second light-emitting control line, and the second electrode is electrically connected to the first electrode of one of the multiple light-emitting devices; the orthographic projection of the eighth transistor on the substrate and the orthographic projection of the driving transistor on the substrate are respectively located on opposite sides of the orthographic projection of the first light-emitting control line on the substrate.

13. The display panel according to claim 12, wherein: The display panel also includes: a first switching electrode, a second switching electrode and a third switching electrode; the first electrode of one of the multiple light-emitting devices connected to the pixel driving circuit is electrically connected to the first switching electrode through a first via hole; the first switching electrode is electrically connected to the second switching electrode through a second via hole, the second switching electrode is electrically connected to the third switching electrode through a third via hole, and the third switching electrode is electrically connected to the second electrode of the eighth transistor through a fourth via hole.

14. The display panel according to claim 13, wherein: The display panel includes a semiconductor layer, a first gate metal layer, a first source-drain metal layer, a second source-drain metal layer and a transparent conductive layer, which are arranged in sequence along a direction away from the base substrate; the second electrode of the eighth transistor is located in the semiconductor layer, the first light-emitting control line and the second light-emitting control line are located in the first gate metal layer, the first transfer electrode is located in the transparent conductive layer, the second transfer electrode is located in the second source-drain metal layer, and the third transfer electrode is located in the first source-drain conductive layer.

15. The display panel according to claim 12, wherein: The plurality of light emitting devices include a first light emitting device and a second light emitting device; the second electrode of the eighth transistor is electrically connected to the first light emitting device; the gating subcircuit further includes: a sixth transistor and a ninth transistor; The control electrode of the sixth transistor is electrically connected to the first light-emitting control line, the first electrode is electrically connected to the second electrode of the driving transistor, and the second electrode is electrically connected to the first electrode of the eighth transistor; The control electrode of the ninth transistor is electrically connected to the third light emitting control line, the first electrode is electrically connected to the second electrode of the sixth transistor, and the second electrode is electrically connected to the second light emitting device; The first light emitting control line, the third light emitting control line and the second light emitting control line are provided in the same layer and are arranged in sequence in a direction away from the driving transistor.

16. The display panel according to claim 15, wherein: The display panel further includes: a fourth switching electrode, wherein the fourth switching electrode is electrically connected to the first electrode of the eighth transistor through a fifth via hole, and is electrically connected to the second electrode of the sixth transistor through a sixth via hole.

17. The display panel according to claim 16, wherein: The display panel includes a semiconductor layer, a first gate metal layer and a first source-drain metal layer which are arranged in sequence along a direction away from the base substrate; the first light-emitting control line and the second light-emitting control line are located in the first gate metal layer, the first electrode of the eighth transistor and the second electrode of the sixth transistor are located in the semiconductor layer, and the fourth transfer electrode is located in the first source-drain metal layer.

18. The display panel according to claim 15, wherein: The display panel further includes: a fifth switching electrode, a sixth switching electrode and a seventh switching electrode; wherein, The first electrode of the second light-emitting device is electrically connected to the fifth switching electrode through the seventh via hole, the fifth switching electrode is electrically connected to the sixth switching electrode through the eighth via hole, the sixth switching electrode is electrically connected to the seventh switching electrode through the ninth via hole, and the seventh switching electrode is electrically connected to the second electrode of the ninth transistor through the tenth via hole.

19. The display panel according to claim 15, wherein: The pixel driving circuit also includes a second reset subcircuit, which includes: a seventh transistor, a control electrode of the seventh transistor is electrically connected to the second reset signal line, a first electrode is electrically connected to the second initialization voltage line, and a second electrode is electrically connected to the first electrode of the first light-emitting device.

20. The display panel according to claim 19, wherein: The display panel further includes an eighth switching electrode, wherein the eighth switching electrode is electrically connected to the first electrode of the seventh transistor through an eleventh via hole, and is electrically connected to the second initialization voltage line through a twelfth via hole.

21. The display panel according to claim 20, wherein: The second initialization voltage line extends along the first direction; the display panel further comprises: a second initialization voltage supply line extending along the second direction, the second initialization voltage supply line being electrically connected to the eighth transfer electrode through a thirteenth via hole; The plurality of pixel driving circuits are arranged in a plurality of columns along a first direction and in a plurality of rows along a second direction; the display panel comprises a plurality of the second initial voltage supply lines arranged along the first direction; The multiple eighth transfer electrodes connected to the multiple pixel driving circuits in the same row include multiple first-type transfer electrodes and multiple second-type transfer electrodes, wherein the first-type transfer electrodes are electrically connected to the second initial voltage supply line, and the orthographic projections of the two on the substrate overlap; the orthographic projections of the second-type transfer electrodes and the second initial voltage supply line on the substrate do not overlap; and at least one second-type transfer electrode is arranged between every two adjacent first-type transfer electrodes arranged along the first direction.

22. The display panel according to claim 21, wherein: The display panel comprises: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, which are sequentially arranged in a direction away from the base substrate, wherein: The first electrode of the seventh transistor is located in the semiconductor layer, the first light-emitting control line and the second light-emitting control line are located in the first gate metal layer, the second initialization voltage line is located in the second gate metal layer, the eighth transfer electrode is located in the first source-drain metal layer, and the second initial voltage supply line is located in the second source-drain metal layer.

23. The display panel according to claim 19, wherein: The second reset subcircuit further includes: a tenth transistor, a control electrode of the tenth transistor is electrically connected to the second reset signal line, a first electrode is electrically connected to the second initialization voltage line, and a second electrode is electrically connected to the first electrode of the second light emitting device.

24. The display panel according to claim 23, wherein: The display panel further includes: a seventh switching electrode, wherein the seventh switching electrode is electrically connected to the second electrode of the ninth transistor through a tenth via hole, and is electrically connected to the second electrode of the tenth transistor through a fourteenth via hole.

25. The display panel according to claim 15, wherein: The light emitting control subcircuit includes: a fifth transistor, a first electrode of the fifth transistor is electrically connected to the first light emitting control line, a first electrode is electrically connected to the first power line, and a second electrode is electrically connected to the first electrode of the driving transistor.

26. The display panel according to claim 25, wherein: The first power line includes: a first sub-power line and a second sub-power line, the first sub-power line is electrically connected to the first electrode of the fifth transistor through a fifteenth via hole, and the second sub-power line is connected to the first sub-power line through a sixteenth via hole; The display panel includes a plurality of the first sub-power lines and a plurality of the second sub-power lines, and the plurality of the first sub-power lines and the plurality of the second sub-power lines are cross-arranged and connected to form a grid structure.

27. The display panel according to any one of claims 12 to 26, wherein: The pixel driving circuit further includes a first reset subcircuit, the first reset subcircuit including: a first transistor, a control electrode of the first transistor being electrically connected to a first reset signal line, a first electrode being electrically connected to a first initialization voltage line, and a second electrode being electrically connected to a control electrode of the driving transistor; wherein the first transistor is located on a side of the driving transistor away from the eighth transistor; The pixel driving circuit further includes a second reset subcircuit, the second reset subcircuit including: a seventh transistor, a control electrode of the seventh transistor being electrically connected to a second reset signal line; The plurality of pixel driving circuits are arranged in a plurality of columns along a first direction and in a plurality of rows along a second direction; in two adjacent rows of pixel driving circuits, the second reset signal line connected to the seventh transistor in the upper row is integrated with the first reset signal line in the lower row.

28. The display panel according to claim 27, wherein: The active layer, the first pole and the second pole of the first transistor are connected to form an L-shaped structure, and the L-shaped structure includes a first extension portion extending along a first direction and a second extension portion extending along a second direction, at least a portion of the first pole of the first transistor is located on the first extension portion, and the second pole of the first transistor is located on the second extension portion.

29. The display panel according to claim 27, wherein: The display panel further includes a ninth switching electrode, wherein the ninth switching electrode is electrically connected to the first electrode of the first transistor through an eighteenth via hole, and is electrically connected to the first initialization voltage line through a nineteenth via hole.

30. The display panel according to claim 29, wherein: The first initialization voltage line extends along a first direction, The display panel further includes: a first initial voltage supply line extending along a second direction, the second direction intersecting the first direction; the first initial voltage supply line is electrically connected to the ninth transfer electrode through a twentieth via hole.

31. The display panel according to claim 30, wherein: The plurality of pixel driving circuits are arranged in a plurality of columns along a first direction and in a plurality of rows along a second direction; the display panel comprises a plurality of the first initial voltage supply lines arranged along the first direction; The multiple ninth switching electrodes connected to the multiple pixel driving circuits in the same row include multiple third-type switching electrodes and multiple fourth-type switching electrodes, wherein the third-type switching electrodes are electrically connected to the first initial voltage supply line, and the orthographic projections of the two on the substrate overlap; the orthographic projections of the fourth-type switching electrodes and the first initial voltage supply line on the substrate do not overlap; and at least one fourth-type switching electrode is arranged between every two adjacent third-type switching electrodes arranged along the first direction.

32. The display panel according to claim 30, wherein: The display panel comprises: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, which are sequentially arranged in a direction away from the base substrate; wherein: The control electrode of the first transistor is located in the first gate metal layer, the first electrode of the first transistor is located in the semiconductor layer, the first light-emitting control line and the second light-emitting control line are located in the first gate metal layer, the first initialization voltage line is located in the second gate metal layer, the ninth transfer electrode is located in the first source-drain metal layer, and the first initial voltage supply line is located in the second source-drain metal layer; the first reset signal line is located in the first source-drain metal layer, and is electrically connected to the control electrode of the first transistor through a seventeenth via.

33. The display panel according to any one of claims 12 to 26, wherein: The pixel driving circuit further includes a data writing subcircuit, and the data writing subcircuit includes: a fourth transistor and a second transistor; The control electrode of the fourth transistor is electrically connected to the scan line, the first electrode is electrically connected to the data line, and the second electrode is electrically connected to the first electrode of the driving transistor; The control electrode of the second transistor is electrically connected to the scan line, the first electrode is electrically connected to the second electrode of the driving transistor, and the second electrode is electrically connected to the control electrode of the driving transistor.

34. The display panel according to claim 33, wherein: The display panel comprises: a first gate metal layer and a first source-drain metal layer, wherein the first source-drain metal layer is located on a side of the first gate metal layer away from the base substrate; The control electrode of the second transistor and the control electrode of the fourth transistor are both located in the first gate metal layer; in two pixel driving circuits adjacent to each other in the first direction, the control electrode of the second transistor of one pixel driving circuit is connected to the control electrode of the fourth transistor of the other pixel driving circuit as an integrated structure; The scan line is located in the first source-drain metal layer and is electrically connected to the control electrode of the fourth transistor through a thirty-second via hole.

35. The display panel according to claim 33, wherein: The pixel driving circuit further includes a storage capacitor, the storage capacitor includes a first electrode plate and a second electrode plate which are arranged opposite to each other, and the first electrode plate is connected to the control electrode of the driving transistor to form an integrated structure; The first power line is electrically connected to the second electrode plate through a thirty-fifth via hole; The display panel further includes: a sixteenth switching electrode, wherein the sixteenth switching electrode is electrically connected to the control electrode of the driving transistor through a thirty-third via hole, and is electrically connected to the second electrode of the second transistor through a thirty-fourth via hole.

36. The display panel according to claim 35, wherein: The second electrode plate has an avoidance gap so that the orthographic projection of the second electrode plate on the base substrate does not overlap with the orthographic projection of the thirty-third via hole on the base substrate.

37. The display panel according to any one of claims 12 to 26, wherein: The plurality of pixel driving circuits are arranged in a plurality of columns along a first direction and in a plurality of rows along a second direction; The display panel includes a plurality of data lines, a plurality of first initial voltage supply lines, a plurality of second initial voltage supply lines, a plurality of second power lines and a plurality of second sub-power lines arranged in the same layer; the second electrode of the light-emitting device is electrically connected to the second power line; the data lines, the first initial voltage supply lines, the second initial voltage supply lines, the second power lines and the second sub-power lines all extend along the second direction; The multiple data lines include a first data line, a second data line and a third data line, each column of the pixel driving circuit is electrically connected to one of the data lines, the first side of each of the data lines is adjacent to the second sub-power line, the second side of the first data line is adjacent to the first initial voltage supply line, the second side of the second data line is adjacent to the second initial voltage supply line, and the second side of the third data line is adjacent to the second power line.

38. The display panel according to any one of claims 12 to 26, wherein: The display panel further comprises a pixel defining layer, the pixel defining layer being located on a side of the first electrode of the light emitting device away from the base substrate; a pixel opening is formed on the pixel defining layer, the pixel opening exposes at least a portion of the first electrode, and the light emitting functional layer of the light emitting device is at least partially located in the pixel opening; Part of the plurality of light-emitting devices connected to the pixel driving circuit corresponds to a plurality of pixel openings, and the remaining light-emitting devices correspond to one pixel opening.

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