Light-emitting drive circuit and display panel

Abstract

A light-emitting drive circuit (30) and a display panel (10), which relate to the field of display panels. The light-emitting drive circuit (30) comprises a multi-stage light-emitting drive unit and a timing controller (20), wherein each stage of the light-emitting drive unit comprises twelve transistors, three capacitors, one signal input end (IN), one signal output end (Enout), and two timing control ends (c1, c2); and the timing controller (20) comprises a first timing control signal line (CKE1) and a second timing control signal line (CKE2). By means of the provision of the novel light-emitting drive circuit (30), each node is independently controlled to avoid the nodes impacting each other, thereby improving the output stability of the light-emitting drive unit, reducing display abnormalities of the display panel (10), and prolonging the service life of the display panel (10); in addition, by means of reducing the usage of the timing control signal lines (CKE1 and CKE2), the border width of the display panel (10) is reduced.

Description

Light-emitting driving circuit and display panel Technical Field

[0001] The present invention relates to the field of display panels, and in particular to a light-emitting drive circuit and a display panel. Background Art

[0002] The display panel includes a pixel array and a scanning drive circuit and a light-emitting drive circuit that control the pixel array. The display panel adopts a row-by-row scanning display mode, in which the scanning drive circuit is used to generate a scanning signal to turn on each row of pixels in turn, and the light-emitting drive circuit is used to provide a data signal to it when a row of pixels is turned on to realize pixel display.

[0003] The light-emitting driving circuit includes multiple cascaded light-emitting driving units, wherein each level of the light-emitting driving unit is usually mainly composed of several transistors and capacitors. By inputting a clock signal and a start pulse signal into the light-emitting driving unit, a level signal is output at the output end.

[0004] Chinese patent CN105741749A provides a light-emitting driver circuit, as shown in Figures 1 and 2. Figure 1 shows a circuit diagram of a light-emitting driver unit in the prior art; Figure 2 shows a waveform diagram of the light-emitting driver unit shown in Figure 1 during operation; and Figure 3 shows a schematic diagram of the conduction state of the light-emitting driver unit during Step 5 in Figure 2. "H" represents a high-level signal, and "L" represents a low-level signal. Referring to Figures 2 and 3, when the circuit enters Step 6 from Step 5, the ideal circuit operation is that the second node N2, due to the low potential of the second timing control signal c2, turns on the eighth transistor M8, writing a low potential to the signal input terminal in, thereby turning on the third transistor M3. A high potential of the first power supply VDD is written to the first node N1, turning off the seventh transistor M7. However, when this circuit is used for a long time or due to manufacturing process errors, the aspect ratio of the transistor changes, resulting in a shift in the threshold voltage device Vth of the transistor, or when the impedance of the timing control signal is too large, it may cause the potential written to the second node N2 to be too high when the circuit enters Step 6, the third transistor M3 cannot be effectively turned on, the potential of the first node N1 cannot be pulled to the high potential of the first power supply VDD, the seventh transistor M7 cannot be turned off and remains on, the second node N2 is written to the high potential of the first power supply VDD due to the turning on of the seventh transistor M7, the potential of the second node N2 is even higher, and finally the signal output terminal out outputs an undesired low potential, thereby causing the panel to display an abnormal image.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to ordinary technicians in this field.

[0006] Summary of the Invention

[0007] In view of this, the present invention provides a light-emitting driving circuit and a display panel, which improve the output stability of the light-emitting driving unit, reduce display abnormalities of the display panel, and increase the service life of the display panel.

[0008] One aspect of the present invention provides a light-emitting driving circuit, comprising a multi-stage light-emitting driving unit, wherein the light-emitting driving unit comprises a control module, a reset module, and an output setting module;

[0009] The control module includes:

[0010] a fourth transistor, wherein a second electrode of the fourth transistor is connected to the first node;

[0011] a fifth transistor, wherein a first electrode of the fifth transistor is connected to the third node, a second electrode is connected to the first timing control terminal, and a gate is connected to the signal input terminal;

[0012] a sixth transistor, wherein a first electrode of the sixth transistor is connected to the third node, a second electrode of the sixth transistor is connected to the second power supply, and a gate of the sixth transistor is connected to the first timing control terminal;

[0013] The reset module includes:

[0014] a third transistor, wherein a first electrode of the third transistor is connected to the first power supply, a second electrode of the third transistor is connected to the first node, and a gate of the third transistor is connected to the second node;

[0015] a seventh transistor, wherein a second electrode of the seventh transistor is connected to the second node;

[0016] a twelfth transistor, wherein a first electrode of the twelfth transistor is connected to the first power supply, and a second electrode of the twelfth transistor is connected to the first electrode of the seventh transistor;

[0017] The output setting module includes:

[0018] a first transistor, wherein a first electrode of the first transistor is connected to the first power supply, a second electrode of the first transistor is connected to the signal output terminal, and a gate of the first transistor is connected to the first node;

[0019] a second transistor, wherein a first electrode of the second transistor is connected to the signal output terminal, a second electrode of the second transistor is connected to the second power supply, and a gate of the second transistor is connected to a fourth node;

[0020] an eighth transistor, wherein a first electrode of the eighth transistor is connected to the signal input terminal, a second electrode of the eighth transistor is connected to the second node, and a gate of the eighth transistor is connected to the second timing control terminal;

[0021] a ninth transistor, wherein a second electrode of the ninth transistor is connected to the fourth node, and a gate of the ninth transistor is connected to the second power supply;

[0022] an eleventh transistor, wherein a first electrode of the eleventh transistor is connected to the second power supply, a second electrode is connected to the first electrode of the fourth transistor, and a gate is connected to the second timing control end.

[0023] In some embodiments, the output setting module further includes:

[0024] A tenth transistor, wherein a first electrode of the tenth transistor is connected to the second node, a second electrode is connected to the first electrode of the ninth transistor, and a gate is connected to the second power supply.

[0025] In some embodiments, the gate of the fourth transistor is connected to the third node;

[0026] The gate of the seventh transistor is connected to the first node;

[0027] The gate of the twelfth transistor is connected to the first timing control terminal.

[0028] In some embodiments, the control module further comprises:

[0029] A tenth transistor, wherein a first electrode of the tenth transistor is connected to the gate of the fourth transistor, a second electrode of the tenth transistor is connected to the third node, and a gate of the tenth transistor is connected to the second power supply.

[0030] In some embodiments, the gate of the seventh transistor is connected to the third node;

[0031] The first electrode of the ninth transistor is connected to the second node;

[0032] The gate of the twelfth transistor is connected to the second timing control.

[0033] In some embodiments, the light-emitting driving unit further includes:

[0034] a first capacitor, wherein a first electrode of the first capacitor is connected to the first timing control terminal, and a second electrode of the first capacitor is connected to the fourth node;

[0035] a second capacitor, wherein a first electrode of the second capacitor is connected to the first electrode of the fourth transistor, and a second electrode of the second capacitor is connected to the gate of the fourth transistor;

[0036] A third capacitor, wherein a first electrode of the third capacitor is connected to the first power supply, and a second electrode of the third capacitor is connected to the first node.

[0037] In some embodiments, a timing controller is further included, and the timing controller includes a first timing control signal line and a second timing control signal line.

[0038] In some embodiments, the first timing control signal line is used to output a first timing control signal; and the second timing control signal line is used to output a second timing control signal.

[0039] In some embodiments, the first timing control signal and the second timing control signal are square wave signals with the same output frequency and a phase difference of 180°.

[0040] In some embodiments, the light-emitting driving unit at the previous stage outputs a light-emitting driving signal to the light-emitting driving unit at the next stage, and the light-emitting driving unit at the last stage outputs a light-emitting driving signal.

[0041] In some embodiments, in the odd-numbered light-emitting driving units, the first timing control terminal is connected to the first timing control signal line, and the second timing control terminal is connected to the second timing control signal line.

[0042] In some embodiments, in the even-numbered light-emitting driving units, the first timing control terminal is connected to the second timing control signal line, and the second timing control terminal is connected to the first timing control signal line.

[0043] In some embodiments, the first to eleventh transistors are all P-type MOS transistors.

[0044] Another aspect of the present invention further provides a display panel, comprising any one of the above-mentioned light-emitting driving circuits.

[0045] The beneficial effects of the present invention compared with the prior art include at least:

[0046] The light-emitting drive circuit and display panel of the present invention provide a new light-emitting drive circuit, which enables independent control of the first node, the second node, and the third node, thereby avoiding mutual influence among the three nodes, thereby improving the output stability of the light-emitting drive unit, reducing display anomalies of the display panel, and increasing the service life of the display panel; in addition, the present invention reduces the number of components of the light-emitting drive circuit by reducing the use of timing control signal lines, thereby reducing the border width of the display panel and adapting to the trend of narrow borders of display panels.

[0047] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings are incorporated into and constitute a part of this specification, illustrate embodiments consistent with the present invention, and together with the description, serve to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and it is clear that those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0049] FIG1 shows a circuit diagram of a light-emitting driving unit in the prior art;

[0050] FIG2 shows a waveform diagram of the light-emitting driving unit shown in FIG1 when it is working;

[0051] FIG3 is a schematic diagram showing the conduction state of the light-emitting driving unit in Step 5 of FIG2 ;

[0052] FIG4 is a schematic diagram showing a display panel of the present invention;

[0053] FIG5 shows a schematic diagram of the cascade connection of the light-emitting drive circuit of the present invention;

[0054] FIG6 shows a circuit diagram of a light-emitting driving unit according to a first embodiment of the present invention;

[0055] FIG7 shows a waveform diagram of the light-emitting driving unit shown in FIG6 when it is working;

[0056] FIG8 is a schematic diagram showing the conduction state of the light-emitting driving unit in Step 11 of FIG7 ;

[0057] FIG9 is a schematic diagram showing the conduction state of the light-emitting driving unit in Step 12 of FIG7 ;

[0058] FIG10 is a schematic diagram showing the conduction state of the light-emitting driving unit in Step 13 of FIG7 ;

[0059] FIG11 is a schematic diagram showing the conduction state of the light-emitting driving unit in Step 14 of FIG7 ;

[0060] FIG12 is a schematic diagram showing the conduction state of the light-emitting driving unit in Step 15 of FIG7 ;

[0061] FIG13 is a schematic diagram showing the conduction state of the light-emitting driving unit in Step 16 of FIG7 ;

[0062] FIG14 is a schematic diagram showing the conduction state of the light-emitting driving unit in Step 17 of FIG7 ;

[0063] FIG15 shows a circuit diagram of a light-emitting driving unit according to a second embodiment of the present invention;

[0064] FIG16 shows a waveform diagram of the light-emitting driving unit shown in FIG15 when it is working;

[0065] FIG17 is a schematic diagram showing the conduction state of the light-emitting driving unit in Step 21 of FIG16 ;

[0066] FIG18 is a schematic diagram showing the conduction state of the light-emitting driving unit in Step 22 of FIG16 ;

[0067] FIG19 is a schematic diagram showing the conduction state of the light-emitting driving unit in Step 23 of FIG16 ;

[0068] FIG20 is a schematic diagram showing the conduction state of the light-emitting driving unit in Step 24 of FIG16 ;

[0069] FIG21 is a schematic diagram showing the conduction state of the light-emitting driving unit in Step 25 of FIG16 ;

[0070] FIG22 is a schematic diagram showing the conduction state of the light-emitting driving unit in Step 26 of FIG16 ;

[0071] FIG. 23 is a schematic diagram showing the conduction state of the light-emitting driving unit in Step 27 in FIG. 16 .

[0072] Reference Signs: 10 display panel 11 display area 20 timing controller 30 light emitting driving circuit CKE1 first timing control signal line CKE2 second timing control signal line c1 first timing control terminal c2 second timing control terminal IN signal input terminal Enout signal output terminal M1 first transistor M2 second transistor M3 third transistor M4 fourth transistor M5 fifth transistor M6 sixth transistor M7 seventh transistor M8 eighth transistor M9 ninth transistor M10 tenth transistor M11 eleventh transistor M12 twelfth transistor C1 first capacitor C2 second capacitor C3 third capacitor VDD first power supply VEE second power supply N1 first node N2 second node N3 third node N4 fourth node DETAILED DESCRIPTION

[0073] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Identical reference numerals in the figures represent identical or similar structures, and thus a repeated description thereof will be omitted.

[0074] The terms "first," "second," and similar terms used in the specific description do not denote any order, quantity, or importance, but are simply used to distinguish different components. Furthermore, in the description of the present invention, the terms "upper," "lower," and similar terms indicating orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings. These terms are used solely for ease of description and do not indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0075] It should be noted that, in the absence of conflict, the embodiments of the present invention and features in different embodiments may be combined with each other.

[0076] Through careful and in-depth research, the inventors of this case have provided a solution to the problems existing in the prior art. Figure 4 shows a schematic diagram of the display panel of the present invention; Figure 5 shows a cascade schematic diagram of the light-emitting drive circuit of the present invention; Figure 6 shows a circuit diagram of the light-emitting drive unit of the first embodiment of the present invention; Figure 15 shows a circuit diagram of the light-emitting drive unit of the second embodiment of the present invention. As shown in Figures 4, 5, 6 and 15, the present invention discloses a light-emitting drive circuit 30 and a display panel 10, wherein the light-emitting drive circuit 30 includes a multi-stage light-emitting drive unit and a timing controller 20. Each stage of the light-emitting drive unit includes a control module, a reset module and an output setting module, specifically including 12 transistors, 3 capacitors, a signal input terminal, a signal output terminal and two timing control terminals. The timing controller 20 includes two timing control signal lines. In addition, the light-emitting drive unit includes three nodes. The light-emitting drive circuit and display panel of the present invention provide a new light-emitting drive circuit, which enables independent control of the first node N1, the second node N2, and the third node N3, thereby preventing the three from restraining each other and influencing each other, thereby improving the output stability of the light-emitting drive unit, reducing display anomalies of the display panel, and increasing the service life of the display panel. In addition, the present invention reduces the number of components of the light-emitting drive circuit by reducing the use of timing control signal lines, thereby reducing the border width of the display panel and adapting to the trend of narrow borders of display panels.

[0077] The specific embodiments of the present invention are further described in detail below with reference to the accompanying drawings.

[0078] As shown in FIG4 , the present invention provides a display panel 10 comprising a display area 11 and a non-display area. A light-emitting driver circuit 30, a data driver, and a scan driver circuit are located in the non-display area of ​​the display panel 10. The display area 11 includes an array of light-emitting pixels and pixel circuits. The light-emitting pixels emit light under the combined action of the light-emitting driver circuit 30, the data driver, the scan driver circuit, and the pixel circuit.

[0079] As shown in FIG. 4 and FIG. 5 , the present invention further provides a light-emitting driving circuit 30 , which includes a multi-stage light-emitting driving unit and a timing controller 20 .

[0080] In some embodiments, the light-emitting driver unit includes 12 transistors, 3 capacitors, a signal input terminal IN, a signal output terminal Enout, a first timing control terminal c1, and a second timing control terminal c2. Each level of the light-emitting driver unit outputs a light-emitting drive signal, which is input to a row of pixel circuits in the display area 11 of the display panel 10 to drive the pixels in that row to emit light. The light-emitting driver unit at the previous level simultaneously outputs the light-emitting drive signal to the signal input terminal IN of the light-emitting driver unit at the next level as a start signal. Because the last level of the light-emitting driver unit does not exist at the next level, the light-emitting drive signal it outputs is only input to the pixel circuits in that row.

[0081] Specifically, FIG5 takes five cascaded light-emitting driver units as an example. A start pulse signal STE is input to a signal input terminal IN1 of a first-stage light-emitting driver unit E1. A signal output terminal E1out of the first-stage light-emitting driver unit E1 outputs a light-emitting driver signal as an input signal to a second-stage light-emitting driver unit E2. The signal output terminal E1out of the first-stage light-emitting driver unit E1 is connected to a signal input terminal IN2 of the second-stage light-emitting driver unit E2. A signal output terminal E2out of the second-stage light-emitting driver unit E2 outputs a light-emitting driver signal as an input signal to a third-stage light-emitting driver unit E3. The signal output terminal E2out of the second-stage light-emitting driver unit E2 is connected to a signal input terminal IN3 of the third-stage light-emitting driver unit E3. A signal output terminal E3out of the third-stage light-emitting driver unit E3 outputs a light-emitting driver signal as an input signal to a fourth-stage light-emitting driver unit E4. The signal output terminal E3out of the third-stage light-emitting driver unit E3 is connected to a signal input terminal IN4 of the fourth-stage light-emitting driver unit E4. The signal output terminal E4out of the fourth-stage light-emitting driving unit E4 outputs a light-emitting driving signal as an input signal of the fifth-stage light-emitting driving unit E5. The signal output terminal E4out of the fourth-stage light-emitting driving unit E4 is connected to the signal input terminal IN5 of the fifth-stage light-emitting driving unit E5. The subsequent-stage light-emitting driving units repeat this process to form a light-emitting driving circuit 30.

[0082] Figure 7 shows a waveform diagram of the light-emitting drive unit shown in Figure 6 when in operation; Figure 16 shows a waveform diagram of the light-emitting drive unit shown in Figure 15 when in operation. In some embodiments, as shown in Figures 5, 7, and 15, the timing controller 20 includes a first timing control signal line CKE1 and a second timing control signal line CKE2. The first timing control signal line CKE1 is used to output a first timing control signal. The second timing control signal line CKE2 is used to output a second timing control signal. The first timing control signal and the second timing control signal are square wave signals with the same output frequency and a phase difference of 180°.

[0083] In some embodiments, as shown in Figure 5, in the first-level light-emitting driving unit, the first timing control terminal c1 is connected to the first timing control signal line CKE1 for receiving the first timing control signal. The second timing control terminal c2 is connected to the second timing control signal line CKE2 for receiving the second timing control signal. In the second-level light-emitting driving unit, the first timing control terminal c1 is connected to the second timing control signal line CKE2 for receiving the second timing control signal. The second timing control terminal c2 is connected to the first timing control signal line CKE1 for receiving the first timing control signal. In the third-level light-emitting driving unit, the first timing control terminal c1 is connected to the first timing control signal line CKE1 for receiving the first timing control signal. The second timing control terminal c2 is connected to the second timing control signal line CKE2 for receiving the second timing control signal. In the fourth-level light-emitting driving unit, the first timing control terminal c1 is connected to the second timing control signal line CKE2 for receiving the second timing control signal. The second timing control terminal c2 is connected to the first timing control signal line CKE1 for receiving the first timing control signal. In the fifth-level light-emitting driving unit, the first timing control terminal c1 is connected to the first timing control signal line CKE1 for receiving the first timing control signal. The second timing control terminal c2 is connected to the second timing control signal line CKE2 for receiving the second timing control signal... and so on, it is obtained that: in the odd-level light-emitting driving unit, the first timing control terminal c1 is connected to the first timing control signal line CKE1 for receiving the first timing control signal, and the second timing control terminal c2 is connected to the second timing control signal line CKE2 for receiving the second timing control signal. In the even-level light-emitting driving unit, the first timing control terminal c1 is connected to the second timing control signal line CKE2 for receiving the second timing control signal, and the second timing control terminal c2 is connected to the first timing control signal line CKE1 for receiving the first timing control signal.

[0084] In the first embodiment of the present invention, referring to Figures 4 to 14, Figure 8 shows a schematic diagram of the conduction state of the light-emitting driving unit in Step 11 of Figure 7; Figure 9 shows a schematic diagram of the conduction state of the light-emitting driving unit in Step 12 of Figure 7; Figure 10 shows a schematic diagram of the conduction state of the light-emitting driving unit in Step 13 of Figure 7; Figure 11 shows a schematic diagram of the conduction state of the light-emitting driving unit in Step 14 of Figure 7; Figure 12 shows a schematic diagram of the conduction state of the light-emitting driving unit in Step 15 of Figure 7; Figure 13 shows a schematic diagram of the conduction state of the light-emitting driving unit in Step 16 of Figure 7; and Figure 14 shows a schematic diagram of the conduction state of the light-emitting driving unit in Step 17 of Figure 7.

[0085] In this embodiment, as shown in FIG6 , each level of the light-emitting driving unit includes a control module, a reset module, and an output setting module. Specifically, the light-emitting driving unit includes 12 transistors, 3 capacitors, a signal input terminal IN, a signal output terminal Enout, a first timing control terminal c1, and a second timing control terminal c2.

[0086] In this embodiment, as shown in FIG6 , the control module includes a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. The second electrode of the fourth transistor M4 is connected to the first node N1. The first electrode of the fifth transistor M5 is connected to the third node N3, the second electrode is connected to the first timing control terminal c1, and the gate is connected to the signal input terminal IN. The first electrode of the sixth transistor M6 is connected to the third node N3, the second electrode is connected to the second power supply VEE, and the gate is connected to the first timing control terminal c1.

[0087] In this embodiment, as shown in FIG6 , the reset module includes a third transistor M3, a seventh transistor M7, and a twelfth transistor M12. The third transistor M3 has a first electrode connected to the first power supply VDD, a second electrode connected to the first node N1, and a gate connected to the second node N2. The seventh transistor M7 has a second electrode connected to the second node N2. The twelfth transistor M12 has a first electrode connected to the first power supply VDD, and a second electrode connected to the first electrode of the seventh transistor M7.

[0088] In this embodiment, as shown in FIG6 , the output set module includes: a first transistor M1, a second transistor M2, an eighth transistor M8, a ninth transistor M9, and an eleventh transistor M11. The first transistor M1 has a first electrode connected to the first power supply VDD, a second electrode connected to the signal output terminal Enout, and a gate connected to the first node N1. The second transistor M2 has a first electrode connected to the signal output terminal Enout, a second electrode connected to the second power supply VEE, and a gate connected to the fourth node N4. The eighth transistor M8 has a first electrode connected to the signal input terminal IN, a second electrode connected to the second node N2, and a gate connected to the second timing control terminal c2. The ninth transistor M9 has a second electrode connected to the fourth node N4, and a gate connected to the second power supply VEE. The eleventh transistor M11 has a first electrode connected to the second power supply VEE, a second electrode connected to the first electrode of the fourth transistor M4, and a gate connected to the second timing control terminal c2.

[0089] In this embodiment, as shown in FIG6 , the above features are also present in other embodiments of the present invention. Specifically, the output set module of the first embodiment further includes a tenth transistor M10. The first electrode of the tenth transistor M10 is connected to the second node N2, the second electrode is connected to the first electrode of the ninth transistor M9, and the gate is connected to the second power supply VEE. Furthermore, the gate of the fourth transistor M4 is connected to the third node N3. The gate of the seventh transistor M7 is connected to the first node N1. The gate of the twelfth transistor M12 is connected to the first timing control terminal c1.

[0090] In this embodiment, as shown in FIG6 , the light driving unit further includes: a first capacitor C1, a second capacitor C2, and a third capacitor C3. A first electrode of the first capacitor C1 is connected to the first timing control terminal C1, and a second electrode is connected to the fourth node N4. A first electrode of the second capacitor C2 is connected to the first electrode of the fourth transistor M4, and a second electrode is connected to the gate of the fourth transistor M4. A first electrode of the third capacitor C3 is connected to the first power supply VDD, and a second electrode is connected to the first node N1.

[0091] In this embodiment, the first transistor M1 to the twelfth transistor M12 are all P-type MOS transistors. The control terminal of the PMOS transistor is the gate, the first terminal is the source, and the second terminal is the drain, or the first terminal is the drain and the second terminal is the source. The on-level of the PMOS transistor is a low level, and the off-level is a high level. In other embodiments, those skilled in the art will readily appreciate that the light-emitting drive unit provided by the present invention can be easily modified to include all N-type MOS transistors. Furthermore, the light-emitting drive unit provided by the present invention can also be easily modified to include CMOS transistors, etc.

[0092] In this embodiment, referring to FIG7 , the waveform diagram shown in FIG7 includes 7 specific processes: Step 11 to Step 17, and subsequent processes not shown. In these processes, the output signal of the signal output terminal Enout of the above-mentioned light-emitting drive unit completes a process from setting to resetting. It should be noted that, for ease of understanding, the high-level signal is represented by "H" and the low-level signal is represented by "L" in the accompanying drawings. The relationship between the input and output of the light-emitting drive unit in the above-mentioned 7 processes is analyzed below in combination with the waveform diagram of FIG7 and the circuit diagram of FIG6 :

[0093] In this embodiment, referring to Figures 7 and 8, during Step 11, a high level is input to the signal input terminal IN, a low level is input to the first timing control signal line CKE1, and a high level is input to the second timing control signal line CKE2. At this time, the second transistor M2, the third transistor M3, the fourth transistor M4, the sixth transistor M6, the ninth transistor M9, the tenth transistor M10, and the twelfth transistor M12 are turned on, while the first transistor M1, the fifth transistor M5, the seventh transistor M7, the eighth transistor M8, and the eleventh transistor M11 are turned off. Specifically, a low level is input to the first timing control signal line CKE1, the sixth transistor M6 and the twelfth transistor M12 are turned on, the low potential of the second power supply VEE is written to the third node N3, and the fourth transistor M4 is turned on. At the same time, the second timing control signal line CKE2 inputs a high level, turning off the eighth transistor M8 and the eleventh transistor M11. The second node N2 maintains its previous low potential, while the second transistor M2 and the third transistor M3 turn on. Due to the turning on of the third transistor M3, the high potential of the first power supply VDD is written to the first node N1, turning off the first transistor M1 and the seventh transistor M7. Consequently, the first transistor M1 turns off, and the second transistor M2 turns on. Ultimately, the signal output terminal Enout outputs the low potential of the second power supply VEE.

[0094] In this embodiment, referring to Figures 7 and 9, during Step 12, a high level is input to the signal input terminal IN, a high level is input to the first timing control signal line CKE1, and a low level is input to the second timing control signal line CKE2. At this time, the first transistor M1, the fourth transistor M4, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are turned on, and the second transistor M2, the third transistor M3, the fifth transistor M5, the sixth transistor M6, and the twelfth transistor M12 are turned off. Specifically, a high level is input to the first timing control signal line CKE1, the sixth transistor M6 and the twelfth transistor M12 are turned off, the third node N3 maintains the low potential at the previous moment, and the fourth transistor M4 is turned on. At the same time, the second timing control signal line CKE2 inputs a low level, turning on the eighth transistor M8 and the eleventh transistor M11. Due to the eighth transistor M8 being turned on, the second node N2 is written with a high potential at the signal input terminal IN. The second transistor M2 and the third transistor M3 are turned off. Due to the fourth transistor M4 and the eleventh transistor M11 being turned on, the first node N1 is written with a low potential at the second power supply VEE, turning on the first transistor M1. Consequently, the first transistor M1 is turned on, and the second transistor M2 is turned off. Ultimately, the signal output terminal Enout outputs a high potential at the first power supply VDD.

[0095] In this embodiment, referring to Figures 7 and 10, during Step 13, a high level is input to the signal input terminal IN, a low level is input to the first timing control signal line CKE1, and a high level is input to the second timing control signal line CKE2. At this time, the first transistor M1, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, the ninth transistor M9, the tenth transistor M10, and the twelfth transistor M12 are turned on, while the second transistor M2, the third transistor M3, the fifth transistor M5, the eighth transistor M8, and the eleventh transistor M11 are turned off. Specifically, a low level is input to the first timing control signal line CKE1, the sixth transistor M6 and the twelfth transistor M12 are turned on, the low potential of the second power supply VEE is written to the third node N3, and the fourth transistor M4 is turned on. At the same time, the second timing control signal line CKE2 inputs a high level, turning off the eighth transistor M8 and the eleventh transistor M11. The first node N1 maintains its previous low potential, while the first transistor M1 and the seventh transistor M7 turn on. Due to the seventh transistor M7 and the twelfth transistor M12 turning on, the second node N2 is written to a high potential of the first power supply VDD. The second transistor M2 and the third transistor M3 turn off. As a result, the first transistor M1 turns on and the second transistor M2 turns off. Ultimately, the signal output terminal Enout outputs a high potential of the first power supply VDD.

[0096] In this embodiment, referring to Figures 7 and 11, during Step 14, a high level is input to the signal input terminal IN, a high level is input to the first timing control signal line CKE1, and a low level is input to the second timing control signal line CKE2. At this time, the first transistor M1, the fourth transistor M4, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are turned on, and the second transistor M2, the third transistor M3, the fifth transistor M5, the sixth transistor M6, and the twelfth transistor M12 are turned off. Specifically, a high level is input to the first timing control signal line CKE1, the sixth transistor M6 and the twelfth transistor M12 are turned off, the third node N3 maintains the low potential at the previous moment, and the fourth transistor M4 is turned on. At the same time, the second timing control signal line CKE2 inputs a low level, turning on the eighth transistor M8 and the eleventh transistor M11. Due to the eighth transistor M8 being turned on, the second node N2 is written with a high potential at the signal input terminal IN. The second transistor M2 and the third transistor M3 are turned off. Due to the fourth transistor M4 and the eleventh transistor M11 being turned on, the first node N1 is written with a low potential at the second power supply VEE, turning on the first transistor M1. Consequently, the first transistor M1 is turned on, and the second transistor M2 is turned off. Ultimately, the signal output terminal Enout outputs a high potential at the first power supply VDD.

[0097] In this embodiment, referring to Figures 7 and 12, during Step 15, a low level is input to the signal input terminal IN, a low level is input to the first timing control signal line CKE1, and a high level is input to the second timing control signal line CKE2. At this time, the first transistor M1, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the ninth transistor M9, the tenth transistor M10, and the twelfth transistor M12 are turned on, and the second transistor M2, the third transistor M3, the eighth transistor M8, and the eleventh transistor M11 are turned off. Specifically, a low level is input to the signal input terminal IN and the first timing control signal line CKE1, the fifth transistor M5, the sixth transistor M6, and the twelfth transistor M12 are turned on, and the third node N3 is simultaneously written with the low potential of the first timing control signal line CKE1 and the second power supply VEE due to the turning on of the fifth transistor M5 and the sixth transistor M6, and the fourth transistor M4 is turned on. At the same time, the second timing control signal line CKE2 inputs a high level, turning off the eighth transistor M8 and the eleventh transistor M11. The first node N1 maintains its previous low potential, while the first transistor M1 and the seventh transistor M7 turn on. Due to the seventh transistor M7 and the twelfth transistor M12 turning on, the second node N2 is written to a high potential of the first power supply VDD. The second transistor M2 and the third transistor M3 turn off. As a result, the first transistor M1 turns on and the second transistor M2 turns off. Ultimately, the signal output terminal Enout outputs a high potential of the first power supply VDD.

[0098] In this embodiment, referring to Figures 7 and 13, during Step 16, the signal input terminal IN inputs a low level, the first timing control signal line CKE1 inputs a high level, and the second timing control signal line CKE2 inputs a low level. At this time, the second transistor M2, the third transistor M3, the fifth transistor M5, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are turned on, and the first transistor M1, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, and the twelfth transistor M12 are turned off. Specifically, the first timing control signal line CKE1 inputs a high level, the sixth transistor M6 and the twelfth transistor M12 are turned off, the third node N3 signal input terminal IN inputs a low potential, causing the fifth transistor M5 to turn on and write the high potential of the first timing control signal line CKE1, and the fourth transistor M4 is turned off. At the same time, the second timing control signal line CKE2 receives a low level input, turning on the eighth transistor M8 and the eleventh transistor M11. Due to the eighth transistor M8 being turned on, the second node N2 is written with the low potential of the signal input terminal IN. The second transistor M2 and the third transistor M3 are turned on, and due to the third transistor M3 being turned on, the first node N1 is written with the high potential of the first power supply VDD. The first transistor M1 is turned off. Consequently, the first transistor M1 is turned off, and the second transistor M2 is turned on. Ultimately, the signal output terminal Enout outputs the low potential of the second power supply VEE.

[0099] In this embodiment, referring to Figures 7 and 14, during Step 17, a low level is input to the signal input terminal IN, a low level is input to the first timing control signal line CKE1, and a high level is input to the second timing control signal line CKE2. At this time, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the ninth transistor M9, the tenth transistor M10, and the twelfth transistor M12 are turned on, and the first transistor M1, the seventh transistor M7, the eighth transistor M8, and the eleventh transistor M11 are turned off. Specifically, a low level is input to the signal input terminal IN and the first timing control signal line CKE1, the fifth transistor M5, the sixth transistor M6, and the twelfth transistor M12 are turned on, and the third node N3 is simultaneously written with the low potential of the first timing control signal line CKE1 and the second power supply VEE due to the turning on of the fifth transistor M5 and the sixth transistor M6, and the fourth transistor M4 is turned on. At the same time, the second timing control signal line CKE2 inputs a high level, turning off the eighth transistor M8 and the eleventh transistor M11. The second node N2 maintains its previous low potential, while the second transistor M2 and the third transistor M3 turn on. Due to the turning on of the third transistor M3, the high potential of the first power supply VDD is written to the first node N1, turning off the first transistor M1. Consequently, the first transistor M1 turns off, and the second transistor M2 turns on. Ultimately, the signal output terminal Enout outputs the low potential of the second power supply VEE.

[0100] In this embodiment, the light driving unit repeats the process from Step 16 to Step 17 after Step 17 until the next frame begins to be displayed, and the start pulse signal STE or the signal input terminal IN inputs a high potential, and then re-enters the next round of Step 11 process.

[0101] In this embodiment, the relationship between the input and output of the light-emitting driving unit is as follows: when the start pulse signal STE or the signal input terminal IN inputs a high-level signal at the start of a process, the signal output terminal Enout outputs a high-level signal when the next process starts; when the start pulse signal STE or the signal input terminal IN inputs a low-level signal at a certain moment, the signal output terminal Enout outputs a low-level signal when the second process starts after that moment. At other times, the signal output from the signal output terminal Enout and the signal input from the start pulse signal STE or the signal input terminal IN are both low-level signals.

[0102] In the second embodiment of the present invention, referring to Figures 4 to 5 and 15 to 23, Figure 17 shows a schematic diagram of the conduction state of the light-emitting driving unit in Step 21 of Figure 16; Figure 18 shows a schematic diagram of the conduction state of the light-emitting driving unit in Step 22 of Figure 16; Figure 19 shows a schematic diagram of the conduction state of the light-emitting driving unit in Step 23 of Figure 16; Figure 20 shows a schematic diagram of the conduction state of the light-emitting driving unit in Step 24 of Figure 16; Figure 21 shows a schematic diagram of the conduction state of the light-emitting driving unit in Step 25 of Figure 16; Figure 22 shows a schematic diagram of the conduction state of the light-emitting driving unit in Step 26 of Figure 16; and Figure 23 shows a schematic diagram of the conduction state of the light-emitting driving unit in Step 27 of Figure 16.

[0103] In this embodiment, as shown in FIG15 , each level of the light-emitting driving unit includes a control module, a reset module, and an output setting module. Specifically, the light-emitting driving unit includes 12 transistors, 3 capacitors, a signal input terminal IN, a signal output terminal Enout, a first timing control terminal c1, and a second timing control terminal c2.

[0104] In this embodiment, as shown in FIG15 , in addition to the same technical features as the first embodiment of the present invention, the second embodiment differs from the first embodiment in that the control module further includes a tenth transistor M10. The tenth transistor M10 has a first electrode connected to the gate of the fourth transistor M4, a second electrode connected to the third node N3, and a gate connected to the second power supply VEE. The gate of the seventh transistor M7 is connected to the third node N3. The first electrode of the ninth transistor M9 is connected to the second node N2. The gate of the twelfth transistor M12 is connected to the second timing control. The similarities between the second embodiment and the first embodiment of the present invention are not repeated here.

[0105] In this embodiment, the light driving unit further includes: a first capacitor C1, a second capacitor C2, and a third capacitor C3, the connection method of which is the same as that of the first embodiment and will not be repeated here.

[0106] In this embodiment, the specific selection of the first transistor M1 to the twelfth transistor M12 is the same as that in the first embodiment, and will not be repeated here.

[0107] In this embodiment, referring to FIG16 , the waveform diagram shown in FIG16 includes 7 processes: Step 21 to Step 27, and subsequent processes not shown. In these processes, the output signal of the signal output terminal Enout of the above-mentioned light-emitting drive unit completes a process from set to reset. It should be noted that, for ease of understanding, the high-level signal is represented by "H" and the low-level signal is represented by "L" in the accompanying drawings. The relationship between the input and output of the light-emitting drive unit in the above 7 processes is analyzed below in combination with the waveform diagram of FIG16 and the circuit diagram of FIG15 :

[0108] In this embodiment, referring to Figures 16 and 17, during Step 21, a high level is input to the signal input terminal IN, a low level is input to the first timing control signal line CKE1, and a high level is input to the second timing control signal line CKE2. At this time, the second transistor M2, the third transistor M3, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, the ninth transistor M9, and the tenth transistor M10 are turned on, while the first transistor M1, the fifth transistor M5, the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12 are turned off. Specifically, a low level is input to the first timing control signal line CKE1, the sixth transistor M6 is turned on, the low potential of the second power supply VEE is written to the third node N3, and the fourth transistor M4 and the seventh transistor M7 are turned on. At the same time, the second timing control signal line CKE2 inputs a high level, turning off the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12. The second node N2 maintains its previous low potential, while the second transistor M2 and the third transistor M3 turn on. Due to the turning on of the third transistor M3, the first node N1 is written to the high potential of the first power supply VDD, turning off the first transistor M1. Consequently, the first transistor M1 is turned off, and the second transistor M2 is turned on. Ultimately, the signal output terminal Enout outputs the low potential of the second power supply VEE.

[0109] In this embodiment, referring to Figures 16 and 18, during Step 22, a high level is input to the signal input terminal IN, a high level is input to the first timing control signal line CKE1, and a low level is input to the second timing control signal line CKE2. At this time, the first transistor M1, the fourth transistor M4, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are turned on, and the second transistor M2, the third transistor M3, the fifth transistor M5, and the sixth transistor M6 are turned off. Specifically, a high level is input to the first timing control signal line CKE1, the sixth transistor M6 is turned off, the third node N3 maintains the low potential at the previous moment, and the fourth transistor M4 and the seventh transistor M7 are turned on. At the same time, the second timing control signal line CKE2 inputs a low level, turning on the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12. Due to the turning on of the seventh transistor M7, the eighth transistor M8, and the twelfth transistor M12, the second node N2 is simultaneously written with the high potential of the signal input terminal IN and the first power supply VDD. The second transistor M2 and the third transistor M3 are turned off. Due to the turning on of the fourth transistor M4 and the eleventh transistor M11, the low potential of the second power supply VEE is written to the first node N1, turning on the first transistor M1. As a result, the first transistor M1 is turned on, and the second transistor M2 is turned off. Ultimately, the signal output terminal Enout outputs the high potential of the first power supply VDD.

[0110] In this embodiment, referring to Figures 16 and 19, during Step 23, a high level is input to the signal input terminal IN, a low level is input to the first timing control signal line CKE1, and a high level is input to the second timing control signal line CKE2. At this point, the first transistor M1, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, the ninth transistor M9, and the tenth transistor M10 are turned on, while the second transistor M2, the third transistor M3, the fifth transistor M5, the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12 are turned off. Specifically, a low level is input to the first timing control signal line CKE1, the sixth transistor M6 is turned on, the low level of the second power supply VEE is written to the third node N3, and the fourth transistor M4 and the seventh transistor M7 are turned on. Simultaneously, a high level is input to the second timing control signal line CKE2, the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12 are turned off, the first node N1 maintains the low level at the previous moment, and the first transistor M1 is turned on. The second node N2 maintains the high level at the previous moment, and the second transistor M2 and the third transistor M3 are turned off. Thus, the first transistor M1 is turned on and the second transistor M2 is turned off. Finally, the signal output terminal Enout outputs the high potential of the first power supply VDD.

[0111] In this embodiment, referring to Figures 16 and 20, during Step 24, a high level is input to the signal input terminal IN, a high level is input to the first timing control signal line CKE1, and a low level is input to the second timing control signal line CKE2. At this time, the first transistor M1, the fourth transistor M4, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are turned on, and the second transistor M2, the third transistor M3, the fifth transistor M5, and the sixth transistor M6 are turned off. Specifically, a high level is input to the first timing control signal line CKE1, the sixth transistor M6 is turned off, the third node N3 maintains the low potential at the previous moment, and the fourth transistor M4 and the seventh transistor M7 are turned on. At the same time, the second timing control signal line CKE2 inputs a low level, turning on the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12. Due to the turning on of the seventh transistor M7, the eighth transistor M8, and the twelfth transistor M12, the second node N2 is simultaneously written with the high potential of the signal input terminal IN and the first power supply VDD. The second transistor M2 and the third transistor M3 are turned off. Due to the turning on of the fourth transistor M4 and the eleventh transistor M11, the low potential of the second power supply VEE is written to the first node N1, turning on the first transistor M1. As a result, the first transistor M1 is turned on, and the second transistor M2 is turned off. Ultimately, the signal output terminal Enout outputs the high potential of the first power supply VDD.

[0112] In this embodiment, referring to Figures 16 and 21, during Step 25, a low level is input to the signal input terminal IN, a low level is input to the first timing control signal line CKE1, and a high level is input to the second timing control signal line CKE2. At this time, the first transistor M1, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the ninth transistor M9, and the tenth transistor M10 are turned on, and the second transistor M2, the third transistor M3, the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12 are turned off. Specifically, a low level is input to the signal input terminal IN and the first timing control signal line CKE1, the fifth transistor M5 and the sixth transistor M6 are turned on, and the third node N3 is simultaneously written with the low potential of the first timing control signal line CKE1 and the second power supply VEE due to the turning on of the fifth transistor M5 and the sixth transistor M6, and the fourth transistor M4 and the seventh transistor M7 are turned on. At the same time, the second timing control signal line CKE2 inputs a high level, turning off the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12. The first node N1 maintains the low potential at the previous moment, the first transistor M1 turns on, the second node N2 maintains the high potential at the previous moment, and the second transistor M2 and the third transistor M3 turn off. As a result, the first transistor M1 turns on and the second transistor M2 turns off. Ultimately, the signal output terminal Enout outputs a high potential of the first power supply VDD.

[0113] In this embodiment, referring to Figures 16 and 22, during Step 26, the signal input terminal IN inputs a low level, the first timing control signal line CKE1 inputs a high level, and the second timing control signal line CKE2 inputs a low level. At this time, the second transistor M2, the third transistor M3, the fifth transistor M5, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are turned on, and the first transistor M1, the fourth transistor M4, the sixth transistor M6, and the seventh transistor M7 are turned off. Specifically, the first timing control signal line CKE1 inputs a high level, the sixth transistor M6 is turned off, and the third node N3 is written with the high level of the first timing control signal line CKE1 due to the low level of the signal input terminal IN causing the fifth transistor M5 to turn on. The fourth transistor M4 and the seventh transistor M7 are turned off. At the same time, the second timing control signal line CKE2 inputs a low level, turning on the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12. Due to the turning on of the eighth transistor M8, the low potential of the signal input terminal IN is written to the second node N2. The second transistor M2 and the third transistor M3 are turned on. Due to the turning on of the third transistor M3, the high potential of the first power supply VDD is written to the first node N1, and the first transistor M1 is turned off. As a result, the first transistor M1 is turned off and the second transistor M2 is turned on. Ultimately, the signal output terminal Enout outputs the low potential of the second power supply VEE.

[0114] In this embodiment, referring to Figures 16 and 23, during Step 27, a low level is input to the signal input terminal IN, a low level is input to the first timing control signal line CKE1, and a high level is input to the second timing control signal line CKE2. At this time, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the ninth transistor M9, and the tenth transistor M10 are turned on, and the first transistor M1, the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12 are turned off. Specifically, a low level is input to the signal input terminal IN and the first timing control signal line CKE1, the fifth transistor M5 and the sixth transistor M6 are turned on, and the third node N3 is simultaneously written with the low potential of the first timing control signal line CKE1 and the second power supply VEE due to the turning on of the fifth transistor M5 and the sixth transistor M6, and the fourth transistor M4 and the seventh transistor M7 are turned on. At the same time, the second timing control signal line CKE2 inputs a high level, turning off the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12. The second node N2 maintains its previous low potential, while the second transistor M2 and the third transistor M3 turn on. Due to the turning on of the third transistor M3, the high potential of the first power supply VDD is written to the first node N1, turning off the first transistor M1. Consequently, the first transistor M1 turns off, and the second transistor M2 turns on. Ultimately, the signal output terminal Enout outputs the low potential of the second power supply VEE.

[0115] In this embodiment, the light driving unit repeats the process from Step 26 to Step 27 after Step 27 until the next frame begins to be displayed, and the start pulse signal STE or the signal input terminal IN inputs a high potential, and then re-enters the next round of Step 21 process.

[0116] In this embodiment, the relationship between the input and output of the light-emitting driving unit is as follows: when the start pulse signal STE or the signal input terminal IN inputs a high-level signal at the start of a process, the signal output terminal Enout outputs a high-level signal when the next process starts; when the start pulse signal STE or the signal input terminal IN inputs a low-level signal at a certain moment, the signal output terminal Enout outputs a low-level signal when the second process starts after that moment. At other times, the signal output from the signal output terminal Enout and the signal input from the start pulse signal STE or the signal input terminal IN are both low-level signals.

[0117] Based on the same inventive concept, embodiments of the present invention further provide a display device comprising the display panel 10 described above. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. The implementation of the display device can be referenced to the embodiments of the display panel 10 described above, and any repetitive details will not be repeated here.

[0118] In summary, the light-emitting driving circuit and display panel of the present invention provide a new light-emitting driving circuit, so that the first node N1, the second node N2 and the third node N3 are independently controlled, thereby avoiding the mutual restraint and influence of the three, thereby improving the output stability of the light-emitting driving unit, reducing the display abnormalities of the display panel, and increasing the service life of the display panel; in addition, the present invention reduces the number of components of the light-emitting driving circuit by reducing the use of timing control signal lines, thereby reducing the border width of the display panel and adapting to the trend of narrow borders of display panels.

[0119] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A light-emitting driving circuit, characterized in that: It includes a multi-stage light-emitting driving unit, and the light-emitting driving unit includes a control module, a reset module and an output setting module; The control module comprises: a fourth transistor, wherein a second electrode of the fourth transistor is connected to the first node; a fifth transistor, wherein a first electrode of the fifth transistor is connected to the third node, a second electrode of the fifth transistor is connected to the first timing control terminal, and a gate of the fifth transistor is connected to the signal input terminal; a sixth transistor, wherein a first electrode of the sixth transistor is connected to the third node, a second electrode of the sixth transistor is connected to the second power supply, and a gate of the sixth transistor is connected to the first timing control terminal; The reset module comprises: a third transistor, wherein a first electrode of the third transistor is connected to the first power supply, a second electrode of the third transistor is connected to the first node, and a gate of the third transistor is connected to the second node; a seventh transistor, a second electrode of the seventh transistor being connected to the second node; a twelfth transistor, wherein a first electrode of the twelfth transistor is connected to the first power source, and a second electrode of the twelfth transistor is connected to the first electrode of the seventh transistor; The output setting module comprises: a first transistor, wherein a first electrode of the first transistor is connected to the first power supply, a second electrode of the first transistor is connected to the signal output terminal, and a gate of the first transistor is connected to the first node; a second transistor, wherein a first electrode of the second transistor is connected to the signal output terminal, a second electrode of the second transistor is connected to the second power supply, and a gate of the second transistor is connected to a fourth node; an eighth transistor, wherein a first electrode of the eighth transistor is connected to the signal input terminal, a second electrode of the eighth transistor is connected to the second node, and a gate of the eighth transistor is connected to the second timing control terminal; a ninth transistor, wherein a second electrode of the ninth transistor is connected to the fourth node, and a gate of the ninth transistor is connected to the second power supply; An eleventh transistor, wherein a first electrode of the eleventh transistor is connected to the second power supply, a second electrode is connected to the first electrode of the fourth transistor, and a gate is connected to the second timing control terminal.

2. The light-emitting driving circuit according to claim 1, characterized in that: The output setting module also includes: A tenth transistor, a first electrode of the tenth transistor is connected to the second node, a second electrode The first electrode is connected to the ninth transistor, and the gate is connected to the second power supply.

3. The light-emitting driving circuit according to claim 2, characterized in that: The gate of the fourth transistor is connected to the third node; The gate of the seventh transistor is connected to the first node; The gate of the twelfth transistor is connected to the first timing control terminal.

4. The light-emitting driving circuit according to claim 1, characterized in that: The control module also includes: A tenth transistor, wherein a first electrode of the tenth transistor is connected to the gate of the fourth transistor, a second electrode of the tenth transistor is connected to the third node, and a gate of the tenth transistor is connected to the second power supply.

5. The light-emitting driving circuit according to claim 4, characterized in that: The gate of the seventh transistor is connected to the third node; The first electrode of the ninth transistor is connected to the second node; The gate of the twelfth transistor is connected to the second timing control.

6. The light-emitting driving circuit according to claim 3 or 5, characterized in that: The light-emitting driving unit further includes: A first capacitor, wherein a first electrode of the first capacitor is connected to the first timing control terminal, and a second electrode of the first capacitor is connected to the fourth node; a second capacitor, wherein a first electrode of the second capacitor is connected to the first electrode of the fourth transistor, and a second electrode of the second capacitor is connected to the gate of the fourth transistor; A third capacitor, wherein a first electrode of the third capacitor is connected to the first power supply, and a second electrode of the third capacitor is connected to the first node.

7. The light-emitting driving circuit according to claim 6, characterized in that: The invention also includes a timing controller, wherein the timing controller includes a first timing control signal line and a second timing control signal line.

8. The light-emitting driving circuit according to claim 7, characterized in that: The first timing control signal line is used to output a first timing control signal; the second timing control signal line is used to output a second timing control signal.

9. The light-emitting driving circuit according to claim 8, characterized in that: The first timing control signal and the second timing control signal are square wave signals with the same output frequency and a phase difference of 180°.

10. The light-emitting driving circuit according to claim 7, characterized in that: The light-emitting driving unit of the previous stage outputs a light-emitting driving signal to the light-emitting driving unit of the next stage, and the light-emitting driving unit of the last stage outputs a light-emitting driving signal.

11. The light-emitting driving circuit according to claim 10, characterized in that: In the odd-numbered light-emitting driving units, the first timing control terminal is connected to the first timing control signal line, and the second timing control terminal is connected to the second timing control signal line.

12. The light-emitting driving circuit according to claim 11, characterized in that: In the even-numbered light-emitting driving units, the first timing control terminal is connected to the second timing control signal line, and the second timing control terminal is connected to the first timing control signal line.

13. The light-emitting driving circuit according to claim 4, characterized in that: The first transistor to the eleventh transistor are all P-type MOS transistors.

14. A display panel, characterized in that: The invention comprises a light emitting driving circuit according to any one of claims 1 to 13.

Images