Shift register unit, gate driving circuit, and display apparatus

Abstract

Provided in the present invention are a shift register unit, a gate driving circuit and a display apparatus. The shift register unit comprises an input module, a first control module, a second control module, a third control module, a first output module, a second output module, a first capacitor, a second capacitor and a third capacitor; the input module controls the potential of a first node; the first control module controls the potential of a second node; the third control module controls the potentials of a third node and a fourth node; the third control module controls the potential of the fourth node; the first capacitor is connected between the first node and a first clock signal lead; the second capacitor is connected between the second node and the third node; the third capacitor is connected between the fourth node and a second voltage signal lead. The potentials of the nodes in the shift register unit provided by the present invention are updated mutually independently of each other, thereby ensuring correct and effective output signal waveforms of the shift register unit and the normal display of a display apparatus.

Description

Shift register unit, gate drive circuit and display device Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a shift register unit, a gate drive circuit and a display device. Background Art

[0002] A display device generally includes a display panel with a pixel array, as well as a gate driver circuit (also called a row driver circuit) and a source driver circuit (also called a column driver circuit) that control the display of the display panel. During operation, the display panel adopts a row-by-row scanning display mode, in which the gate driver circuit is used to generate a scanning signal to turn on each row of pixels in sequence, and the source driver circuit is used to provide a data signal to each row of pixels when it is turned on to realize the pixel display.

[0003] The gate drive circuit includes a shift register, which includes multiple cascaded shift register units, where each level of the shift register unit is usually mainly composed of several transistors. By inputting the clock signal CKV and the input signal STV / in (that is, the start pulse signal) into the circuit, a level signal (that is, the Gout signal) is output at the output end.

[0004] A shift register unit includes multiple transistors. When the threshold voltage (Vth) of the device shifts during manufacturing processes, such as burn-in testing, it can cause an abnormal output signal from the shift register unit, leading to an abnormal display on the display panel. For example, Chinese patent application CN105989797A discloses a shift register unit. Figure 1 shows a schematic circuit diagram of the shift register unit disclosed in CN105989797A. As shown in Figure 1, when the sixth node N6' is at a low potential, the third transistor M3 is turned on, and the high-level signal VDD' is transmitted to the first node N1' through the third transistor M3. When the first node N1' is at a high potential, the seventh transistor M7 is turned off. When the seventh transistor M7 needs to be turned on, the potential of the first node N1' needs to be updated to a low level. However, when the threshold voltage Vth of the third transistor M3 shifts, the third transistor M3 cannot be turned off in time, and the high-level signal VDD' is still transmitted to the first node N1' through the third transistor M3, so that the potential of the first node N1' cannot be updated in time. This will cause the seventh transistor M7 to be unable to turn on in time, resulting in an abnormal output signal of the shift register unit. It is necessary to solve the problem that the node potential cannot be updated in time due to the interference between the third transistor M3 and the seventh transistor M7 in the shift register unit, thereby causing the abnormal output signal of the shift register unit.

[0005] Summary of the Invention

[0006] In response to the problems in the prior art, the purpose of the present invention is to provide a shift register unit, a gate drive circuit and a display device. The potential update of each node in the shift register unit provided by the present invention is not affected by the potential of other nodes, which can ensure that the output signal waveform of the shift register unit is correct and effective, thereby enabling normal display of the display device.

[0007] An embodiment of the present invention provides a shift register unit, comprising:

[0008] An input module, configured to transmit an input signal at an input terminal of the shift register unit to the first node in response to a second clock signal; and to transmit a second voltage signal to the first node in response to the first clock signal and a signal at a fourth node;

[0009] a first control module, configured to transmit a first voltage signal to a second node in response to a first clock signal; and to transmit the first clock signal to the second node in response to the input signal;

[0010] a second control module, configured to transmit the second clock signal to a third node in response to a signal from the second node; and to transmit the second clock signal to the third node and the fourth node in response to the second clock signal;

[0011] a third control module, configured to transmit a second voltage signal to the fourth node in response to the signal of the first node;

[0012] a first output module, configured to transmit the second voltage signal to an output end of the shift register unit in response to a signal at the fourth node;

[0013] a second output module, configured to transmit a first voltage signal to the output terminal in response to the potential of the first node;

[0014] a first capacitor connected between the first node and a first clock signal lead;

[0015] a second capacitor connected between the second node and the third node;

[0016] The third capacitor is connected between the fourth node and the second voltage signal lead.

[0017] In some embodiments, the input module includes a first transistor, a control terminal of the first transistor is electrically connected to the second clock signal lead, a first terminal of the first transistor is electrically connected to the input terminal, and a second terminal of the first transistor is electrically connected to the first node.

[0018] In some embodiments, the input module further includes a second transistor and a third transistor, wherein the control terminal of the second transistor is electrically connected to the first clock signal lead, the first terminal of the second transistor is electrically connected to the second voltage signal lead, and the second terminal of the second transistor is electrically connected to the first terminal of the third transistor;

[0019] The control terminal of the third transistor is electrically connected to the fourth node, and the second terminal of the third transistor is electrically connected to the first node.

[0020] In some embodiments, the first control module includes a fourth transistor, a control end of the fourth transistor is electrically connected to the first clock signal lead, a first end of the fourth transistor is connected to the first voltage signal lead, and a second end of the fourth transistor is electrically connected to the second node.

[0021] In some embodiments, the first control module further includes a fifth transistor, a control end of the fifth transistor electrically connected to the input end, a first end of the fifth transistor electrically connected to the first clock signal lead, and a second end of the fifth transistor electrically connected to the second node.

[0022] In some embodiments, the first control module further includes a sixth transistor, a control end of the sixth transistor electrically connected to the second node, a first end of the sixth transistor electrically connected to the second clock signal lead, and a second end of the sixth transistor electrically connected to the third node.

[0023] In some embodiments, the second control module includes a seventh transistor, a control terminal of the seventh transistor is electrically connected to the second clock signal lead, a first terminal of the seventh transistor is electrically connected to the third node, and a second terminal of the seventh transistor is electrically connected to the fourth node.

[0024] In some embodiments, the third control module includes an eighth transistor, the control end of the eighth transistor is electrically connected to the first node, the first end of the eighth transistor is electrically connected to the second voltage signal lead, and the second end of the eighth transistor is electrically connected to the fourth node.

[0025] In some embodiments, the input module also includes a ninth transistor, the control end of the ninth transistor is electrically connected to the first voltage signal lead, the first end of the ninth transistor is electrically connected to the second end of the first transistor and the second end of the third transistor, and the second end of the ninth transistor is electrically connected to the first node.

[0026] In some embodiments, the first output module includes a tenth transistor, a control terminal of the tenth transistor is electrically connected to the fourth node, a first terminal of the tenth transistor is electrically connected to the second voltage signal lead, and a second terminal of the tenth transistor is electrically connected to the output terminal;

[0027] The second output module includes an eleventh transistor, a control terminal of the eleventh transistor is electrically connected to the first node, a first terminal of the eleventh transistor is electrically connected to the first voltage signal lead, and a second terminal of the eleventh transistor is electrically connected to the output terminal.

[0028] An embodiment of the present invention further provides a gate driving circuit, comprising the shift register unit described above.

[0029] In some embodiments, multiple shift register units are electrically connected in a cascade manner, wherein the input signal of the first-stage shift register unit is connected to the start pulse signal, and except for the last-stage shift register, the output signal end of each of the remaining shift register units is connected to the input end of the next-stage shift register unit.

[0030] An embodiment of the present invention further provides a display device, comprising the gate driving circuit as described above.

[0031] The shift register unit, gate drive circuit, and display device provided by the present invention have the following advantages:

[0032] The shift register unit includes an input module, a first control module, a second control module, a third control module, a first output module, a second output module, a first capacitor, a second capacitor, and a third capacitor. The input module controls the potential of the first node, the first control module controls the potential of the second node, the third control module controls the potentials of the third and fourth nodes, and the third control module controls the potential of the fourth node. The first capacitor is connected between the first node and a first clock signal lead; the second capacitor is connected between the second node and the third node; and the third capacitor is connected between the fourth node and a second voltage signal lead. The potential updates of the nodes in the shift register unit provided by the present invention are not mutually constrained, ensuring that the output signal waveform of the shift register unit is correct and effective, thereby ensuring normal display of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0034] FIG1 is an equivalent schematic diagram of a shift register unit disclosed in the prior art;

[0035] FIG2 is a schematic diagram of an equivalent circuit of a shift register unit according to an embodiment of the present invention;

[0036] 3 is a driving timing diagram of a shift register unit according to an embodiment of the present invention;

[0037] 4 to 10 are schematic diagrams showing the on-off state of the shift register unit in a circuit in a time period t1 to t7 according to an embodiment of the present invention;

[0038] FIG. 11 is a schematic diagram of a gate driving circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0039] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. In the figures, identical reference numerals denote identical or similar structures, and thus repetitive descriptions thereof will be omitted. The use of "or" and "either" in this specification may mean "and" or "or."

[0040] To solve the problems of the prior art, an embodiment of the present invention provides a shift register unit, as shown in FIG2 , wherein the shift register unit includes:

[0041] an input module for transmitting an input signal STE at an input end of the shift register unit to a first node N1 in response to a second clock signal CKE2; and for transmitting a second voltage signal VDD to the first node N1 in response to the first clock signal CKE1 and a signal at a fourth node N4;

[0042] a first control module for transmitting the first voltage signal VEE to the second node N2 in response to the first clock signal CKE1; and for transmitting the first clock signal CKE1 to the second node N2 in response to the input signal STE;

[0043] a second control module, configured to transmit the second clock signal CKE2 to a third node N3 in response to a signal at the second node N2; and to transmit the second clock signal CKE2 to the third node N3 and the fourth node N4 in response to the second clock signal CKE2;

[0044] a third control module, configured to transmit a second voltage signal VDD to the fourth node N4 in response to a signal at the first node N1;

[0045] a first output module, configured to transmit the second voltage signal VDD to an output end of the shift register unit in response to a signal at the fourth node N4;

[0046] a second output module, configured to transmit the first voltage signal VEE to the output terminal in response to the potential of the first node N1;

[0047] A first capacitor C1 is connected between the first node N1 and a first clock signal lead;

[0048] A second capacitor C2 is connected between the second node N2 and the third node N3;

[0049] The third capacitor C3 is connected between the fourth node N4 and the second voltage signal lead.

[0050] The first clock signal CKE1 and the second clock signal CKE2 are pulse signals with the same frequency and opposite phases.

[0051] The input module controls the potential of the first node, the first control module controls the potential of the second node, the second control module controls the potentials of the third node and the fourth node, and the third control module controls the potential of the fourth node. The potential updates of the nodes in the shift register unit are not mutually restrained, which can ensure that the output signal waveform of the shift register unit is correct and effective, thereby enabling normal display of the display device.

[0052] 2 , the input module includes a first transistor T1 , a control end of the first transistor T1 is electrically connected to the second clock signal lead, a first end of the first transistor T1 is electrically connected to the input end, and a second end of the first transistor T1 is electrically connected to the first node N1 .

[0053] The input module also includes a second transistor T2 and a third transistor T3, the control end of the second transistor T2 is electrically connected to the first clock signal lead, the first end of the second transistor T2 is electrically connected to the second voltage signal lead, and the second end of the second transistor T2 is electrically connected to the first end of the third transistor T3; the control end of the third transistor T3 is electrically connected to the fourth node N4, and the second end of the third transistor T3 is electrically connected to the first node N1.

[0054] The first control module includes a fourth transistor T4, a control end of the fourth transistor T4 is electrically connected to the first clock signal lead, a first end of the fourth transistor T4 is connected to the first voltage signal lead, and a second end of the fourth transistor T4 is electrically connected to the second node N2.

[0055] The first control module further includes a fifth transistor T5, a control end of the fifth transistor T5 is electrically connected to the input end, a first end of the fifth transistor T5 is electrically connected to the first clock signal lead, and a second end of the fifth transistor T5 is electrically connected to the second node N2.

[0056] The first control module further includes a sixth transistor T6, a control end of the sixth transistor T6 is electrically connected to the second node N2, a first end of the sixth transistor T6 is electrically connected to the second clock signal lead, and a second end of the sixth transistor T6 is electrically connected to the third node N3.

[0057] The second control module includes a seventh transistor T7, a control end of the seventh transistor T7 is electrically connected to the second clock signal lead, a first end of the seventh transistor T7 is electrically connected to the third node N3, and a second end of the seventh transistor T7 is electrically connected to the fourth node N4.

[0058] The third control module includes an eighth transistor T8, a control end of the eighth transistor T8 is electrically connected to the first node N1, a first end of the eighth transistor T8 is electrically connected to the second voltage signal lead, and a second end of the eighth transistor T8 is electrically connected to the fourth node N4.

[0059] The input module further includes a ninth transistor T9, a control terminal of the ninth transistor T9 being electrically connected to the first voltage signal lead, a first terminal of the ninth transistor T9 being electrically connected to the second terminal of the first transistor T1 and the second terminal of the third transistor T3, and a second terminal of the ninth transistor T9 being electrically connected to the first node N1. In this embodiment, the ninth transistor T9 is a dual-gate transistor.

[0060] The first output module includes a tenth transistor T10, a control terminal of the tenth transistor T10 is electrically connected to the fourth node N4, a first terminal of the tenth transistor T10 is electrically connected to the second voltage signal lead, and a second terminal of the tenth transistor T10 is electrically connected to the output terminal.

[0061] The second output module includes an eleventh transistor T11, a control end of the eleventh transistor T11 is electrically connected to the first node N1, a first end of the eleventh transistor T11 is electrically connected to the first voltage signal lead, and a second end of the eleventh transistor T11 is electrically connected to the output end.

[0062] In this embodiment, the first voltage signal VEE is at a low level, the second voltage signal VDD is at a high level, and the input signal STE is a high-level start pulse signal.

[0063] In this embodiment, the first transistor T1 to the tenth transistor T10 are all PMOS transistors, wherein the control terminal of the PMOS transistor is the gate, the first terminal is the source, and the second terminal is the drain; the on-level of the PMOS transistor is a low level, and the off-level is a high level. In other embodiments, those skilled in the art will readily appreciate that the shift register unit provided by the present invention can be easily modified to include all N-type transistors. Alternatively, the shift register unit provided by the present invention can be easily modified to include all CMOS transistors, etc.

[0064] Figure 3 shows a timing diagram of the shift register unit provided by an embodiment of the present invention, and the working principle of the shift register unit provided by an embodiment of the present invention is described in conjunction with Figure 3. It should be noted that, for ease of understanding, high-level signals are represented by "H" and low-level signals are represented by "L".

[0065] FIG3 shows the driving timing of the shift register unit in the first time period t1 in an embodiment of the present disclosure; FIG4 shows a schematic diagram of the circuit on-off of the shift register unit in the first time period t1. Combining FIG3 and FIG4, it can be seen that in the first time period t1, the input signal STE is high, the first clock signal CKE1 is low, and the second clock signal CKE2 is high. Then, the first transistor T1, the fifth transistor T5, and the seventh transistor T7 are turned off, and the second transistor T2 and the fourth transistor T4 are turned on. The control terminal of the ninth transistor T9 is connected to the first voltage signal VEE. The first voltage signal VEE is a continuously low signal, so the ninth transistor T9 is continuously turned on. The reason for the conduction of the ninth transistor T9 will not be explained below. The first voltage signal VEE is transmitted to the second node N2 through the fourth transistor T4. The signal at the second node N2 is low, and the sixth transistor T6 is turned on. The second clock signal CKE2 is transmitted to the third node N3 through the sixth transistor T6. The signal at the third node N3 is high, and the second capacitor C2 is charged. Under the influence of the input signal STE, the first clock signal CKE1, and the second clock signal CKE2 at the previous moment, the first node N1 is at a low level, and the eighth transistor T8 and the eleventh transistor T11 are turned on. The second voltage signal VDD is transmitted to the fourth node N4 through the eighth transistor T8. At this time, the signal at the fourth node N4 is at a high level, and the tenth transistor T10 is turned off. The first voltage signal VEE is transmitted to the output terminal through the eleventh transistor T11, and the output signal Eout of the shift register unit in the first time period t1 is a low level signal.

[0066] FIG3 shows the driving timing of the shift register unit during the second time period t2; FIG5 shows a schematic diagram of the circuit on-off of the shift register unit during the second time period t2. As shown in FIG3 and FIG5 , during the second time period t2, the input signal STE is high, the first clock signal CKE1 is high, and the second clock signal CKE2 is low. The second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off, and the first transistor T1 and the seventh transistor T7 are turned on. The input signal STE is transmitted to the first node N1 via the first transistor T1 and the ninth transistor T9. At this time, the signal at the first node N1 is high, and the eighth transistor T8 and the eleventh transistor T11 are turned off. Under the action of the second capacitor C2, the signal at the second node N2 is low, and the sixth transistor T6 is turned on. The second clock signal CKE2 is transmitted to the third node N3 via the sixth transistor T6. At this time, the signal at the third node N3 is low, and the low-level signal at the third node N3 is transmitted to the fourth node N4 via the seventh transistor T7. When the signal at the fourth node N4 is low, the third transistor T3 and the tenth transistor T10 are turned on, and the third capacitor C3 is charged. The second voltage signal VDD is transmitted to the output terminal through the tenth transistor T10. During time period t2, the output terminal outputs the second voltage signal VDD at a high level.

[0067] FIG3 shows the driving timing of the shift register unit in the third time period t3; FIG6 shows a schematic diagram of the circuit on-off in the shift register unit in the third time period t3. As shown in FIG3 and FIG6, in the third time period t3, the input signal STE is at a high level, the first clock signal CKE1 is at a low level, and the second clock signal CKE2 is at a high level, then the first transistor T1, the fifth transistor T5, and the seventh transistor T7 are turned off, and the second transistor T2 and the fourth transistor T4 are turned on. Under the action of the second capacitor C2, the signal at the second node N2 is at a low level, the sixth transistor T6 is turned on, and the second clock signal CKE2 is transmitted to the third node N3 through the sixth transistor T6. At this time, the signal at the third node N3 is at a high level, and the second capacitor C2 is charged. Under the action of the third capacitor C3, the signal at the fourth node N4 is at a low level, the third transistor T3 and the tenth transistor T10 are turned on, and the second voltage signal VDD is transmitted to the first node N1 through the second transistor T2, the third transistor T3, and the ninth transistor T9. When the signal at the first node N1 is at a high level, the eleventh transistor T11 is turned off, and the first capacitor C1 is charged. The second voltage signal VDD is transmitted to the output terminal through the tenth transistor T10. During the third time period t3, the output terminal outputs the second voltage signal VDD at a high level.

[0068] FIG3 shows the driving timing of the shift register unit in the fourth time period t4; FIG7 shows a schematic diagram of the circuit on-off in the shift register unit in the fourth time period t4. As shown in FIG3 and FIG7, in the fourth time period t4, the input signal STE is high, the first clock signal CKE1 is high, and the second clock signal CKE2 is low, then the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off, and the first transistor T1 and the seventh transistor T7 are turned on. The input signal STE is transmitted to the first node N1 through the first transistor T1 and the ninth transistor T9. At this time, the signal at the first node N1 is high. Under the action of the high signal at the first node N1, the eighth transistor T8 and the eleventh transistor T11 are turned off, and the signals at both ends of the first capacitor C1 are both high signals. Under the action of the second capacitor C2, the signal at the second node N2 is at a low level. The second clock signal CKE2 is transmitted to the third node N3 via the sixth transistor T6. At this time, the signal at the third node N3 is also at a low level. The signal at the third node N3 is then transmitted to the fourth node N4 via the seventh transistor T7. The signal at the fourth node N4 is also at a low level, and the third capacitor C3 is charged. With the signal at the fourth node N4 at a low level, the third transistor T3 and the tenth transistor T10 are turned on, and the second voltage signal VDD is transmitted to the output terminal via the tenth transistor T10. During the fourth time period t4, the output terminal outputs the second voltage signal VDD at a high level.

[0069] Figure 3 shows the driving timing of the shift register unit during the fifth time period t5; Figure 8 shows a schematic diagram of the circuit switching within the shift register unit during the fifth time period t5. As shown in Figures 3 and 8 , during the fifth time period t5, the input signal STE is low, the first clock signal CKE1 is low, and the second clock signal CKE2 is high. Consequently, the first transistor T1 and the seventh transistor T7 are turned off, while the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned on. The first clock signal CKE1 is transmitted to the second node N2 via the fifth transistor T5, and the first voltage signal VEE is transmitted to the second node N2 via the fourth transistor T4. The signal at the second node N2 is low. Due to the low signal at the second node N2, the sixth transistor T6 is turned on. The second clock signal CKE2 is transmitted to the third node N3 via the sixth transistor T6. The signal at the third node N3 is high, and the second capacitor C2 is charged. Due to the action of the third capacitor C3, the fourth node N4 is low, turning on the third transistor T3 and the tenth transistor T10. The second voltage signal VDD is transmitted to the first node N1 through the second transistor T2 and the third transistor T3. When the signal at the first node N1 is high, the eleventh transistor T11 is turned off, and the first capacitor C1 is charged. During the fifth time period t5, the second voltage signal VDD is transmitted to the output terminal through the tenth transistor T10, and the output terminal outputs the high-level second voltage signal VDD.

[0070] Figure 3 shows the driving timing of the shift register unit during the sixth time period t6; Figure 9 shows a schematic diagram of the circuit switching within the shift register unit during the sixth time period t6. As shown in Figure 9, during the sixth time period t6, the input signal STE is low, the first clock signal CKE1 is high, and the second clock signal CKE2 is low. Consequently, the first transistor T1, the fifth transistor T5, and the seventh transistor T7 are turned on, while the second transistor T2 and the fourth transistor T4 are turned off. The first clock signal CKE1 is transmitted to the second node N2 via the fifth transistor T5. When the signal at the second node N2 is high, the sixth transistor T6 is turned off. Under the action of the second capacitor C2, the signal at the third node N3 is high. This signal is transmitted to the fourth node N4 via the seventh transistor T7, and the signal at the fourth node N4 is high. Under the action of the fourth node N4, the third transistor T3 and the tenth transistor T10 are turned off. The input signal STE is transmitted to the first node N1 via the first transistor T1 and the ninth transistor T9. When the signal at the first node N1 is low, the eighth transistor T8 and the eleventh transistor T11 are turned on. The second voltage signal transmits a high level signal to the fourth node N4 through the eighth transistor T8. The first voltage signal VEE is transmitted to the output terminal through the eleventh transistor T11. In the seventh time period t7, the output terminal outputs the low level first voltage signal VEE.

[0071] Figure 3 shows the driving timing of the shift register unit during the seventh time period t7; Figure 10 shows a schematic diagram of the on-off circuit within the shift register unit during the seventh time period t7. As shown in Figure 10, during the seventh time period t7, the input signal STE is low, the first clock signal CKE1 is low, and the second clock signal CKE2 is high. The second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned on, while the first transistor T1 and the seventh transistor T7 are turned off. The first clock signal CKE1 is transmitted to the second node via the fifth transistor T5, and the first voltage signal is transmitted to the second node N2 via the fourth transistor T4. The signal at the second node N2 is low, turning on the sixth transistor T6. The second clock signal CKE2 is transmitted to the third node N3 via the sixth transistor T6. The signal at the third node N3 is high, and the second capacitor C2 is charged. Under the action of the first capacitor C1, the signal at the first node N1 is at a low level, the eighth transistor T8 and the eleventh transistor T11 are turned on, and the second voltage signal VDD is transmitted to the fourth node N4 via the eighth transistor T8. The signal at the fourth node N4 is at a high level, and the third transistor T3 and the tenth transistor T10 are turned off. The first voltage signal VEE is transmitted to the output terminal via the eleventh transistor T11. During the seventh time period t7, the output terminal outputs the low-level first voltage signal VEE.

[0072] The shift register unit repeats the sixth time period t6 and the seventh time period t7 in subsequent working steps, which will not be repeated here, until the high level STE signal appears next time and the first time period t1 to the fifth time period t5 working steps are started again.

[0073] An embodiment of the present invention further provides a gate drive circuit comprising the shift register unit described above. A plurality of the shift register units are electrically connected in cascade, wherein the input signal of the first stage of the shift register unit is connected to a revelation pulse signal, and, except for the last stage of the shift register, the output signal terminals of each of the remaining stages of the shift register unit are connected to the input terminals of the next stage of the shift register unit.

[0074] Specifically, FIG11 takes four cascaded shift register units as an example. Specifically, FIG11 takes four cascaded shift register units as an example. The input signal STE of the input terminal in of the first-stage shift register unit SR1 is a start pulse signal; the output signal Eout1 of the output terminal out of the first-stage shift register unit SR1 serves as the input signal of the second-stage shift register unit SR2, and the output terminal out of the first-stage shift register unit SR1 is connected to the input terminal in of the second-stage shift register unit SR2; the output signal Eout2 of the second-stage shift register unit SR2 serves as the input signal of the third-stage shift register unit SR3, and the output terminal out of the second-stage shift register unit SR2 is connected to the input terminal in of the third-stage shift register unit SR3; the output signal Eout3 of the third-stage shift register unit SR3 serves as the input signal of the fourth-stage shift register unit SR4, and the output terminal out of the third-stage shift register unit SR3 is connected to the input terminal in of the fourth-stage shift register unit SR4… and this is repeated to form a gate drive circuit.

[0075] As shown in FIG11 , the gate drive circuit further includes a clock signal generating unit (not shown in the figure), which is used to generate a first clock signal CKE1 and a second clock signal CKE2. Specifically, the first clock signal CKE1 and the second clock signal CKE2 in the first-stage shift register unit SR1 are respectively the first clock signal CKE1 and the second clock signal CKE2 generated by the clock signal generating unit; the first clock signal CKE1 and the second clock signal CKE2 in the second-stage shift register unit SR2 are respectively the second clock signal CKE2 and the first clock signal CKE1 generated by the clock signal generating unit; the first clock signal CKE1 and the second clock signal CKE2 in the third-stage shift register unit SR3 are respectively the first clock signal CKE1 and the second clock signal CKE2 generated by the clock signal generating unit; and the fourth-stage shift register unit SR4 is respectively the first clock signal CKE1 and the second clock signal CKE2 generated by the clock signal generating unit. The first clock signal CKE1 and the second clock signal CKE2 in the shift register unit SR4 are respectively the second clock signal CKE1 and the first clock signal CKE2 generated by the clock signal unit; by analogy, the first clock signal CKE1 and the second clock signal CKE2 in the n-th stage shift register unit SRn are respectively the first clock signal CKE1 and the second clock signal CKE2 generated by the clock signal unit; the first clock signal CKE1 and the second clock signal CKE2 in the (n+1)-th stage shift register unit SRn+1 are respectively the second clock signal CKE2 and the first clock signal CKE1 generated by the clock signal generating unit.

[0076] An embodiment of the present invention further provides a display device comprising the gate drive circuit described above. The gate scan lines in the display device are activated row by row using the signals output from the shift register units. Specifically, the signals output from the output signal terminals of the shift register units serve as gate scan line signals for each row of pixel units. Furthermore, the display device further comprises a source drive circuit for providing data voltages to the corresponding pixel units when the gate scan lines are activated. The display device, comprising the gate drive circuit described above, can achieve the technical advantages of the aforementioned embodiments.

[0077] The shift register unit, gate drive circuit, and display device provided by the present invention have the following advantages:

[0078] The potential updates of the nodes in the shift register unit provided by the present invention are not mutually restrained, which can ensure that the shift register unit outputs a correct and effective signal waveform, thereby enabling normal display of the display device.

[0079] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A shift register unit, characterized in that: include: An input module, configured to transmit an input signal at an input end of the shift register unit to a first node in response to a second clock signal; and for transmitting a second voltage signal to the first node in response to the first clock signal and a signal of a fourth node; A first control module, configured to transmit a first voltage signal to a second node in response to a first clock signal; and for transmitting the first clock signal to the second node in response to the input signal; A second control module, configured to transmit the second clock signal to a third node in response to a signal from the second node; and for transmitting the second clock signal to the third node and the fourth node in response to the second clock signal; a third control module, configured to transmit a second voltage signal to the fourth node in response to the signal of the first node; a first output module, configured to transmit the second voltage signal to an output end of the shift register unit in response to a signal at the fourth node; a second output module, configured to transmit a first voltage signal to the output terminal in response to the potential of the first node; A first capacitor connected between the first node and a first clock signal lead; A second capacitor connected between the second node and the third node; A third capacitor is connected between the fourth node and the second voltage signal lead.

2. The shift register unit according to claim 1, characterized in that: The input module includes a first transistor, a control terminal of the first transistor is electrically connected to the second clock signal lead, a first terminal of the first transistor is electrically connected to the input terminal, and a second terminal of the first transistor is electrically connected to the first node.

3. The shift register unit according to claim 2, characterized in that: The input module further includes a second transistor and a third transistor, wherein the control end of the second transistor is electrically connected to the first clock signal lead, the first end of the second transistor is electrically connected to the second voltage signal lead, and the second end of the second transistor is electrically connected to the first end of the third transistor; The control terminal of the third transistor is electrically connected to the fourth node, and the second terminal of the third transistor is electrically connected to the first node.

4. The shift register unit according to claim 3, characterized in that: The first control module includes a fourth transistor, a control end of the fourth transistor is electrically connected to the first clock signal lead, a first end of the fourth transistor is connected to the first voltage signal lead, and a second end of the fourth transistor is electrically connected to the second node.

5. The shift register unit according to claim 4, characterized in that: The first control module also includes a fifth transistor, a control end of the fifth transistor is electrically connected to the input end, a first end of the fifth transistor is electrically connected to the first clock signal lead, and a second end of the fifth transistor is electrically connected to the second node.

6. The shift register unit according to claim 5, characterized in that: The first control module also includes a sixth transistor, a control end of the sixth transistor is electrically connected to the second node, a first end of the sixth transistor is electrically connected to the second clock signal lead, and a second end of the sixth transistor is electrically connected to the third node.

7. The shift register unit according to claim 6, characterized in that: The second control module includes a seventh transistor, a control end of the seventh transistor is electrically connected to the second clock signal lead, a first end of the seventh transistor is electrically connected to the third node, and a second end of the seventh transistor is electrically connected to the fourth node.

8. The shift register unit according to claim 7, characterized in that: The third control module includes an eighth transistor, a control end of the eighth transistor is electrically connected to the first node, a first end of the eighth transistor is electrically connected to the second voltage signal lead, and a second end of the eighth transistor is electrically connected to the fourth node.

9. The shift register unit according to claim 3, characterized in that: The input module also includes a ninth transistor, a control end of the ninth transistor is electrically connected to the first voltage signal lead, a first end of the ninth transistor is electrically connected to the second end of the first transistor and the second end of the third transistor, and a second end of the ninth transistor is electrically connected to the first node.

10. The shift register unit according to claim 1, characterized in that: The first output module includes a tenth transistor, a control terminal of the tenth transistor is electrically connected to the fourth node, a first terminal of the tenth transistor is electrically connected to the second voltage signal lead, and a second terminal of the tenth transistor is electrically connected to the output terminal; The second output module includes an eleventh transistor, a control end of the eleventh transistor is electrically connected to the first node, a first end of the eleventh transistor is electrically connected to the first voltage signal lead, and a second end of the eleventh transistor is electrically connected to the output end.

11. A gate drive circuit, characterized in that: The invention comprises a shift register unit as claimed in any one of claims 1 to 10.

12. The gate driving circuit according to claim 11, characterized in that: The multiple shift register units are electrically connected in a cascade manner, wherein the input signal of the first-stage shift register unit is connected to the start pulse signal, and except for the last-stage shift register, the output signal end of each stage of the shift register unit is connected to the input end of the next-stage shift register unit.

13. A display device, characterized in that: Comprising the gate drive circuit as described in any one of claims 11 or 12.

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