Display panel and terminal device

Abstract

Disclosed in the embodiments of the present application are a display panel and a terminal device. The display panel comprises scanning lines and pixel units, a pixel unit P(n) being electrically connected to a scanning line G(n+1), and at least one of scanning lines G(n-1) and G(n) being arranged to overlap a pixel electrode of P(n). By means of cross-row charging, at least one of G(n-1) and G(n) forms a compensation capacitance with the pixel electrode of P(n), so as to reduce the coupling voltage Vft(n+1), thus reducing dark lines.

Description

Display panels, terminal equipment Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a terminal device. Background Art

[0002] Please refer to Figure 1. In the existing display panel, the pixel unit P(n) is electrically connected to the scan line G(n), and a shielding electrode is provided between adjacent pixel electrodes of the existing display panel. The shielding electrode is used to shield the influence of the signal between the scan line and the pixel electrode. There is a certain gap between the shielding electrode and the pixel electrodes on both sides, resulting in a large spacing between adjacent pixel electrodes, low transmittance of the pixel unit, and dark stripes on the display.

[0003] Therefore, existing display panels have technical problems of dark lines and low transmittance. SUMMARY OF THE INVENTION

[0004] The embodiments of the present application provide a display panel and a terminal device, which can alleviate the technical problems of dark lines and low transmittance in existing display panels.

[0005] An embodiment of the present application provides a display panel, comprising scan lines and pixel units, wherein a pixel unit is arranged between adjacent scan lines, the pixel unit comprising a pixel electrode, one scan line is connected to a corresponding pixel unit, the pixel units comprising P(1)...P(n), P(n+1), the scan lines comprising G(0)...G(n-1), G(n), G(n+1), wherein the pixel unit P(n) is electrically connected to the scan line G(n+1), at least one of G(n-1), G(n-1), and G(n) is arranged to overlap with the pixel electrode of the pixel unit P(n), and n is a positive integer greater than or equal to 2.

[0006] Optionally, in some embodiments of the present application, the pixel unit further includes a TFT device, the pixel unit P(n) includes the nth TFT device and the nth pixel electrode, and the pixel unit P(n+1) includes the (n+1)th TFT device and the (n+1)th pixel electrode.

[0007] Optionally, in some embodiments of the present application, the nth pixel electrode is connected to the (n+1)th TFT device.

[0008] Optionally, in some embodiments of the present application, when the scan line G(n+1) provides a scan signal to the pixel unit (n), a compensation capacitor Cco is formed between G(n-1), the G(n) and the pixel electrode of the pixel unit P(n).

[0009] Optionally, in some embodiments of the present application, the display panel is a liquid crystal display panel, and the TFT device includes a gate, a source, and a drain.

[0010] Optionally, in some embodiments of the present application, the voltage change of the gate is Vgh-Vgl, the capacitance of the drain and gate is Cgs, the liquid crystal capacitor is Clc, and the storage capacitor is Cst, wherein the coupling voltage Vft(n+1)=(Vgh-Vgl)×Cgs / (Cst+Cgs+Clc+Cco).

[0011] Optionally, in some embodiments of the present application, the nth pixel electrode is connected to the source electrode of the (n+1)th TFT device through a via hole.

[0012] Optionally, in some embodiments of the present application, when the G(n-1) is turned off, the G(n-1) generates a first coupling deviation Vft(n-1) to the G(n+1).

[0013] Optionally, in some embodiments of the present application, when the G(n) is turned off, the G(n) generates a second coupling deviation Vft(n) to the G(n+1).

[0014] Optionally, in some embodiments of the present application, the Vft(n) is smaller than the Vft(n-1).

[0015] Optionally, in some embodiments of the present application, the voltage value of the scan line G(n+1) after being turned on is V, and V>Vft(n+1)>Vft(n-1)>Vft(n).

[0016] Optionally, in some embodiments of the present application, the intervals between adjacent scan lines being turned on are equal, and the scan lines are scanned periodically.

[0017] Optionally, in some embodiments of the present application, when the G(n-1) is turned off, the G(n+1) is turned on, and the scanning time of adjacent scan lines is twice the interval time of turning on adjacent scan lines.

[0018] Optionally, in some embodiments of the present application, the interval time between adjacent scan lines being turned on is less than or equal to 2.5 microseconds.

[0019] Optionally, in some embodiments of the present application, the scanning time of the scanning line is 5 microseconds, and the interval time between adjacent scanning lines being turned on is 2.5 microseconds.

[0020] Optionally, in some embodiments of the present application, the spacing between adjacent pixel electrodes ranges from 4 microns to 5 microns.

[0021] Optionally, in some embodiments of the present application, there is no need to provide a shielding electrode for shielding signal interference between adjacent pixel electrodes.

[0022] Optionally, in some embodiments of the present application, compensation capacitance is formed between the G(n-1) and the G(n) and the pixel electrode of the pixel unit P(n).

[0023] Optionally, in some embodiments of the present application, a compensation capacitor is formed between any one of the G(n-1) and the G(n) and the pixel electrode of the pixel unit P(n).

[0024] An embodiment of the present application provides a terminal device, which includes the display panel described in any of the above embodiments. Beneficial effects

[0025] Cross-row charging is achieved by electrically connecting the pixel unit P(n) to the scan line G(n+1), thereby eliminating the need for a shielding electrode between adjacent pixel electrodes, reducing the spacing between adjacent pixel electrodes, and increasing the transmittance of the pixel unit. At the same time, the pixel electrodes of G(n-1), G(n) and the pixel unit P(n) are arranged to overlap on different surfaces. When the scan line G(n+1) scans and drives the pixel unit P(n), a compensation capacitor is formed between at least one of G(n-1) and G(n) and the pixel electrode of the pixel unit P(n), thereby reducing the coupling voltage, reducing dark lines, improving the display quality, and alleviating the technical problems of dark lines and low transmittance in existing display panels. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0027] FIG1 is a cross-sectional schematic diagram of a display panel provided by the prior art;

[0028] FIG2 is a timing diagram of a display panel provided by the prior art;

[0029] FIG3 is a schematic cross-sectional view of a display panel provided in the present application;

[0030] FIG4 is a timing diagram of a display panel provided by the present application;

[0031] FIG. 5 is a schematic diagram of the distance d in the specific area 2 of the display panel provided in FIG. 3 of the present application.

[0032] Description of reference numerals:

[0033] Modes for Carrying Out the Invention

[0034] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0035] Please refer to Figure 3. The display panel 1 provided in the present application includes scan lines and pixel units. A pixel unit is arranged between adjacent scan lines. The pixel unit includes a pixel electrode. One scan line is connected to a corresponding pixel unit. The pixel units include P(1)...P(n), P(n+1). The scan lines include G(0)...G(n-1), G(n), G(n+1). The pixel unit P(n) 10 is electrically connected to the scan line G(n+1) 50. At least one of G(n-1) and G(n) is arranged to overlap with the pixel electrode of the pixel unit P(n) 10 on different planes. n is a positive integer greater than or equal to 2.

[0036] In this embodiment, cross-row charging is achieved by electrically connecting the pixel unit P(n) 10 to the scan line G(n+1) 50, thereby eliminating the need to provide a shielding electrode 60 between adjacent pixel electrodes, reducing the spacing d between adjacent pixel electrodes and increasing the transmittance of the pixel unit. At the same time, the G(n-1), the G(n) and the pixel electrode of the pixel unit P(n) 10 are overlapped. When the scan line G(n+1) 50 scans and drives the pixel unit P(n) 10, a compensation capacitor is formed between at least one of the G(n-1) and the G(n) and the pixel electrode of the pixel unit P(n) 10, thereby reducing the coupling voltage, reducing dark lines, improving the display quality, and alleviating the technical problem of dark lines and low transmittance in the existing display panel 1.

[0037] The technical solution of this application is now described in conjunction with specific embodiments.

[0038] The embodiment of the present application only takes the example of the pixel unit P(n) 10 being electrically connected to the scan line G(n+1) 50 to achieve cross-row charging. Other implementation methods that meet the requirements of cross-row charging between pixel units and scan lines also fall within the scope of protection of the present application.

[0039] The present application enables the pixel unit and the scan line to be charged across rows, thereby eliminating the need to set a shielding electrode 60 between adjacent pixel electrodes, thereby increasing the area of ​​the pixel electrode and thus increasing the transmittance; at the same time, due to the increase in the pixel electrode area of ​​the pixel unit P(n)10, a compensation capacitor is formed between the pixel unit P(n)40 and the scan lines G(n)40 and G(n-1), and the compensation capacitor can reduce the coupling voltage of G(n+1), thereby increasing the pixel unit's ability to resist process fluctuations and improving the display quality.

[0040] In one embodiment, compensation capacitance is formed between the G(n-1) and the G(n) and the pixel electrode of the pixel unit P(n) 10 .

[0041] In this embodiment, by forming compensation capacitance between G(n-1) and G(n) and the pixel electrode of the pixel unit P(n) 10, the compensation capacitance is increased, the coupling voltage of G(n+1) is further reduced, the ability of the pixel unit to resist process fluctuations is increased, and the display quality is improved.

[0042] In one embodiment, referring to FIG3 , the pixel unit further includes a TFT device, the pixel unit P(n) 10 includes an n-th TFT device 102 and an n-th pixel electrode 101, and the pixel unit P(n+1) 20 includes an (n+1)-th TFT device 202 and an (n+1)-th pixel electrode 201, wherein the n-th pixel electrode 101 is connected to the (n+1)-th TFT device 202.

[0043] It can be understood that the pixel unit P(n)10 is electrically connected to the scan line G(n+1)50 by connecting the nth pixel electrode 101 of the pixel unit P(n)10 to the (n+1)th TFT device 202 of the pixel unit P(n+1)20, and the (n+1)th TFT device 202 is connected to the scan line G(n+1)50.

[0044] In one embodiment, the intervals between adjacent scanning lines being turned on are equal, and the scanning lines are scanned periodically.

[0045] In one embodiment, when G(n-1) is turned off and G(n+1) is turned on, the scanning time between adjacent scan lines is twice the interval time between the adjacent scan lines being turned on.

[0046] In one embodiment, referring to FIG. 3 , when the scan line G(n+1) 50 provides a scan signal to the pixel unit (n), a compensation capacitor Cco is formed between G(n-1), G(n) and the pixel electrode of the pixel unit P(n) 10.

[0047] It can be understood that since the scanning line G(n-1) 30 and the scanning line G(n) 40 have an overlapping area with the pixel electrode of the pixel unit P(n) 10 in the film thickness direction, in the overlapping area, the scanning line G(n-1) 30, the scanning line G(n) 40 and the pixel electrode of the pixel unit P(n) 10 will form a compensation capacitor, and the compensation capacitor can increase the size of the storage capacitor.

[0048] It can be understood that for the cross-row charging structure of the present application, the coupling voltage Vft(n+1) is inversely proportional to Cst, that is, when the storage capacitor Cst increases, the coupling voltage Vft(n+1) can be reduced, thereby improving the quality; therefore, the present application forms a compensation capacitor through the scan line G(n-1) 30, the scan line G(n) 40 and the pixel electrode of the pixel unit P(n) 10, thereby increasing the storage capacitor Cst and reducing the coupling voltage Vft(n+1).

[0049] In this embodiment, by forming a compensation capacitor Cco between G(n-1), G(n) and the pixel electrode of the pixel unit P(n) 10, the storage capacitor Cst can be increased, thereby reducing the coupling voltage Vft(n+1) and improving the display quality.

[0050] In one embodiment, referring to FIG3 , the display panel 1 is a liquid crystal display panel 1 , the TFT device includes a gate 70 , a source 80 , and a drain. The voltage variation of the gate 70 is Vgh-Vgl. The capacitance between the drain and the gate 70 is Cgs, the liquid crystal capacitance is Clc, and the storage capacitance is Cst. The coupling voltage Vft(n+1)=(Vgh-Vgl)×Cgs / (Cst+Cgs+Clc+Cco).

[0051] The formula of the coupling voltage Vft(n+1) further illustrates that the coupling voltage Vft(n+1) can be reduced by forming the compensation capacitor, thereby increasing the ability of the pixel unit to resist process fluctuations and improving the quality.

[0052] It is understandable that the coupling voltage Vft(n+1) can also be reduced by increasing the liquid crystal capacitance Clc or increasing Cgs.

[0053] It is understandable that the coupling voltage Vft(n+1) can be reduced by increasing the voltage change (Vgh−Vgl) of the gate 70 .

[0054] In this embodiment, by adjusting at least one of Clc, Cgs, Cst, (Vgh-Vgl), and Cco, the coupling voltage Vft(n+1) can be reduced, thereby improving the pixel unit's ability to resist process fluctuations and enhancing quality.

[0055] In one embodiment, the nth pixel electrode 101 is connected to the source electrode 80 of the (n+1)th TFT device 202 through a via hole.

[0056] In one embodiment, referring to FIG3 and FIG4 , when the G(n-1) is turned off, the G(n-1) generates a first coupling deviation Vft(n-1) to the G(n+1); when the G(n) is turned off, the G(n) generates a second coupling deviation Vft(n) to the G(n+1), wherein the Vft(n) is smaller than the Vft(n-1).

[0057] It can be understood that, referring to FIG3 , in the present application, due to cross-row charging, the scan line G(n+1) 50 scans and drives the pixel unit P(n) 10, and the scan line G(n-1) 30 and the scan line G(n) 40 both produce a coupling effect on the scan line G(n+1) 50 when they are turned off, resulting in two coupling deviations. In the prior art, however, since it is the scan line G(n) 40 that scans and drives the pixel unit P(n) 10, referring to FIG2 , only the scan line G(n-1) 30 produces a coupling deviation Vft'(n-1) on the scan line G(n) 40 when it is turned off. That is, the prior art has only one coupling deviation. When the scan line G(n) 40 is turned off, the generated coupling voltage Vft'(n) = (Vgh-Vgl)×Cgs / (Cst+Cgs+Clc). Obviously, Vft'(n) is greater than Vft(n+1), that is, the coupling voltage of the present application is smaller, thereby increasing the ability of the pixel unit to resist process fluctuations, and the quality will be better.

[0058] It should be noted that although the scanning line G(n+1) 50 in this application will have two coupling deviations due to cross-row charging, when the scanning line G(n+1) 50 is turned off, the size of the coupling voltage Vft(n+1) can be obtained as shown in the above formula Vft(n+1)=(Vgh-Vgl)×Cgs / (Cst+Cgs+Clc+Cco). Since the present application has a compensation capacitor Cco, and there is no overlap between the pixel electrode and the scanning line in the prior art, the coupling voltage Vft(n+1) of the present application is smaller, thereby improving the display quality.

[0059] In one embodiment, referring to FIG. 4 , when G(n−1) is turned off, G(n+1) is turned on, the scanning time of the scan line is 5 microseconds, and the interval time between adjacent scan lines being turned on is 2.5 microseconds.

[0060] Here, only the scanning time of the scanning line is 5 microseconds and the scanning interval is 2.5 microseconds as an example for explanation. Other scanning times and scanning intervals should also fall within the protection scope of this application.

[0061] It can be understood that the interval time between the adjacent scanning lines is 2.5 microseconds, so that the scanning interval time is equal, and multiple scanning lines are scanned periodically, which improves stability.

[0062] It is understandable that when the scan line G(n-1) 30 is turned off, it produces a coupling effect on the scan line G(n+1) 50, resulting in a voltage drop of Vft(n-1). Similarly, when the scan line G(n) 40 is turned off, it produces a coupling effect on the scan line G(n+1) 50, resulting in a voltage drop of Vft(n). Because the voltage drops of Vft(n-1) and Vft(n) only last for 2.5us, they are not visible to the human eye and therefore do not affect the display effect. By limiting the scanning time and interval time, the display quality can be improved, and the coupling deviation Vft(n-1) and Vft(n) voltage drops cannot be seen by the human eye, thereby preventing the human eye from seeing them and affecting the display effect.

[0063] In one embodiment, referring to FIG. 4 , the voltage value of the scan line G(n+1) 50 after it is turned on is V, wherein V>Vft(n+1)>Vft(n-1)>Vft(n).

[0064] In one embodiment, referring to FIG. 5 , the distance d between adjacent pixel electrodes ranges from 4 microns to 5 microns.

[0065] It can be understood that, please refer to Figure 5, which is an enlarged schematic diagram of the specific area 2 in Figure 3. Figure 5 is used to illustrate the spacing d between adjacent pixels. The present application does not require the additional setting of a shielding electrode 60 through cross-row charging; please refer to Figure 1. In the existing design, the width of the shielding electrode 60 is usually about 11 microns. The shielding electrode 60 is usually set between adjacent pixel electrodes, and the distance between the shielding electrode 60 and the pixel electrodes on both sides ranges from 4 microns to 5 microns. Therefore, in the prior art, the spacing d between adjacent pixel electrodes = the width of the shielding electrode 60 + the distance between the shielding electrode 60 and the pixel electrode on one side + the distance between the shielding electrode 60 and the pixel electrode on the other side. Taking the above value range as an example, the spacing d between adjacent pixel electrodes in the prior art is usually 19 to 21 microns, while the present application does not require the setting of the shielding electrode 60, reducing the width of the shielding electrode 60 itself and the width between the shielding electrode 60 and the pixel electrode on one side. The present application only needs to reserve a certain width between adjacent pixel units to prevent short circuits caused by process errors. This width can be 4 to 5 microns.

[0066] It should be noted that this embodiment is only illustrated by taking a spacing of 4 to 5 microns and a width of the shielding electrode 60 of 11 microns as an example. Under the premise of meeting the process conditions and display requirements, other spacing ranges should also fall within the protection scope of this application.

[0067] The present application realizes cross-row charging by electrically connecting the pixel unit P(n) to the scan line G(n+1). Cross-row charging does not require setting a shielding electrode between adjacent pixel electrodes, thereby reducing the distance between adjacent pixel electrodes and improving the transmittance.

[0068] In addition, since the distance between adjacent pixel electrodes is reduced, the pixel electrodes and the scan lines can be arranged in an overlapping manner. Specifically, the G(n-1) and the G(n) are arranged in an overlapping manner with the pixel electrodes of the pixel unit P(n); when the scan line G(n+1) scans and drives the pixel unit P(n), a compensation capacitor is formed between at least one of the scan line G(n-1) and the scan line G(n) and the pixel electrode of the pixel unit P(n), thereby reducing the coupling voltage, reducing dark lines, and improving the display quality.

[0069] The present application also proposes a display module and a terminal device, both of which include the above-mentioned display panel, which will not be described in detail here.

[0070] The display panel provided by the embodiment of the present application includes a scan line and a pixel unit, wherein a pixel unit is arranged between adjacent scan lines, the pixel unit includes a pixel electrode, one scan line is connected to a corresponding pixel unit, the pixel unit includes P(1)...P(n), P(n+1), the scan line includes G(0)...G(n-1), G(n), G(n+1), wherein the pixel unit P(n) is electrically connected to the scan line G(n+1), the G(n-1), the G(n) and the pixel electrode of the pixel unit P(n) are overlapped, and n is a positive integer greater than or equal to 2; by ) is electrically connected to the scanning line G(n+1) to realize cross-row charging, so that there is no need to set a shielding electrode between adjacent pixel electrodes, so that the spacing between adjacent pixel electrodes becomes smaller, thereby increasing the transmittance of the pixel unit. At the same time, the pixel electrodes of G(n-1), G(n) and the pixel unit P(n) are arranged to overlap on different sides. When the scanning line G(n+1) scans and drives the pixel unit P(n), compensation capacitance is formed between the pixel electrodes of G(n-1), G(n) and the pixel unit P(n), thereby reducing the coupling voltage, reducing dark lines, improving the display quality, and alleviating the technical problems of dark lines and low transmittance of existing display panels.

[0071] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0072] The above is a detailed introduction to the display panel provided in the embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, comprising scan lines and pixel units, wherein a pixel unit is arranged between adjacent scan lines, the pixel unit comprises a pixel electrode, a scan line is connected to a corresponding pixel unit, the pixel unit comprises P(1) ... P(n), P(n+1), the scan lines comprise G(0) ... G(n-1), G(n), G(n+1), wherein: The pixel unit P(n) is electrically connected to the scan line G(n+1), and at least one of G(n-1) and G(n) is arranged to overlap with the pixel electrode of the pixel unit P(n) in different planes, and n is a positive integer greater than or equal to 2.

2. The display panel according to claim 1, wherein: The pixel unit further includes a TFT device, the pixel unit P(n) includes an nth TFT device and an nth pixel electrode, and the pixel unit P(n+1) includes an (n+1)th TFT device and an (n+1)th pixel electrode.

3. The display panel according to claim 2, wherein: The nth pixel electrode is connected to the (n+1)th TFT device.

4. The display panel according to claim 3, wherein: When the scanning line G(n+1) provides a scanning signal to the pixel unit (n), a compensation capacitor Cco is formed between G(n-1), G(n) and the pixel electrode of the pixel unit P(n).

5. The display panel according to claim 4, wherein: The display panel is a liquid crystal display panel, and the TFT device includes a gate, a source, and a drain.

6. The display panel according to claim 5, wherein: The voltage change of the gate is Vgh-Vgl, the capacitance of the drain and the gate is Cgs, the liquid crystal capacitance is Clc, and the storage capacitance is Cst, wherein the coupling voltage Vft(n+1)=(Vgh-Vgl)×Cgs / (Cst+Cgs+Clc+Cco).

7. The display panel according to claim 6, wherein: The nth pixel electrode is connected to the source electrode of the (n+1)th TFT device through a via hole.

8. The display panel according to claim 6, wherein: When the G(n-1) is turned off, the G(n-1) generates a first coupling deviation Vft(n-1) to the G(n+1).

9. The display panel according to claim 8, wherein: When the G(n) is turned off, the G(n) generates a second coupling deviation Vft(n) to the G(n+1).

10. The display panel according to claim 9, wherein: The Vft(n) is smaller than the Vft(n-1).

11. The display panel according to claim 10, wherein: The voltage value of the scanning line G(n+1) after being turned on is V, wherein V>Vft(n+1)>Vft(n-1)>Vft(n).

12. The display panel according to claim 6, wherein: The interval time between adjacent scanning lines being turned on is equal, and the scanning lines are scanned periodically.

13. The display panel according to claim 12, wherein: When the G(n-1) is turned off, the G(n+1) is turned on, and the scanning time between adjacent scanning lines is twice the interval time between the adjacent scanning lines being turned on.

14. The display panel according to claim 13, wherein: The interval time between adjacent scanning lines being turned on is less than or equal to 2.5 microseconds.

15. The display panel according to claim 14, wherein: The scanning time of the scanning line is 5 microseconds, and the interval time between adjacent scanning lines being turned on is 2.5 microseconds.

16. The display panel according to claim 1, wherein: The distance between adjacent pixel electrodes ranges from 4 microns to 5 microns.

17. The display panel according to claim 16, wherein: There is no need to arrange shielding electrodes for shielding signal interference between adjacent pixel electrodes.

18. The display panel according to claim 1, wherein: A compensation capacitor is formed between the G(n-1) and the G(n) and the pixel electrode of the pixel unit P(n).

19. The display panel according to claim 1, wherein: A compensation capacitor is formed between any one of the G(n-1) and the G(n) and the pixel electrode of the pixel unit P(n).

20. A terminal device comprising the display panel according to any one of claims 1 to 19.

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