Solar cell and preparation method therefor, and photovoltaic module

Abstract

A solar cell and a preparation method therefor, and a photovoltaic module. The solar cell comprises the following structure: a substrate; a first passivation layer, an N-type doped zinc sulfide layer and a first transparent conductive oxide layer which are sequentially stacked on a first surface of the substrate; and a second passivation layer, a P-type doped layer and a second transparent conductive oxide layer which are sequentially stacked on a second surface of the substrate; wherein the first passivation layer comprises a silicon dioxide layer.

Description

Solar cell and preparation method thereof and photovoltaic module

[0001] Related applications

[0002] This application claims priority to the Chinese patent application filed on September 7, 2023, with application number 202311156208.8, and invention name “Solar cells, preparation methods thereof, and photovoltaic modules”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of photovoltaics, and in particular to a solar cell and a preparation method thereof, and a photovoltaic module. Background Art

[0004] Crystalline silicon (c-Si) solar cells currently dominate the photovoltaic (PV) industry, holding approximately 95% of the market share. Heterojunction cells, based on a core structure of "single-crystal silicon / hydrogenated intrinsic amorphous silicon / hydrogenated doped microcrystalline silicon," have attracted significant attention from researchers due to their excellent charge-selective transport and interface passivation properties, high efficiency, low temperature coefficient, and high bifaciality. However, traditional heterojunction solar cells also suffer from shortcomings such as poor spectral response in the short wavelength range, low utilization of long wavelengths after they penetrate the silicon wafer, and ultraviolet attenuation (UVID).

[0005] Summary of the Invention

[0006] According to various embodiments of the present application, a solar cell is provided, including the following structure:

[0007] a substrate having opposing first and second surfaces;

[0008] A first passivation layer, an N-type doped zinc sulfide layer, and a first transparent conductive oxide layer are sequentially stacked on the first surface of the substrate, and a second passivation layer, a P-type doped layer, and a second transparent conductive oxide layer are sequentially stacked on the second surface of the substrate; wherein the first passivation layer includes a silicon dioxide layer.

[0009] In one embodiment, the first surface is a velvet surface, and the second surface is a polished surface.

[0010] In one embodiment, the material of the second passivation layer includes silicon dioxide or hydrogenated intrinsic amorphous silicon.

[0011] In one embodiment, the thickness of the second passivation layer is 1 nm-15 nm.

[0012] In one embodiment, the material of the P-type doped layer includes P-type hydrogenated doped microcrystalline silicon or P-type doped nickel oxide.

[0013] In one embodiment, the thickness of the P-type doped layer is 5 nm-50 nm.

[0014] In one embodiment, the materials of the first transparent conductive oxide layer and the second transparent conductive oxide layer independently include one or more of indium tin oxide, tungsten-doped indium oxide, cerium-doped indium oxide, aluminum-doped zinc oxide, indium-doped cadmium oxide, and antimony-doped tin oxide.

[0015] In one embodiment, the thickness of the first transparent conductive oxide layer and / or the second transparent conductive oxide layer is 40 nm-80 nm.

[0016] In one embodiment, the thickness of the N-type doped zinc sulfide layer is 5 nm-25 nm.

[0017] In one embodiment, the thickness of the first passivation layer is 1 nm-5 nm.

[0018] Furthermore, the present application also provides a method for preparing the solar cell as described above, comprising the following steps:

[0019] providing the substrate;

[0020] The first passivation layer, the N-type doped zinc sulfide layer, and the first transparent conductive oxide layer are sequentially prepared on the first surface of the substrate, and the second passivation layer, the P-type doped layer, and the second transparent conductive oxide layer are sequentially prepared on the second surface of the substrate.

[0021] Furthermore, the present application provides a photovoltaic assembly, comprising the solar cell as described above.

[0022] In this application, by selecting silicon dioxide as the first passivation layer between the substrate and the N-type doped layer, and using zinc sulfide as the N-type doped layer, the surface reflection can be effectively reduced, the surface recombination rate can be further reduced, the light trapping effect can be enhanced, and the carrier lifetime can be increased to improve the electrical performance of the substrate. Solar cells with this structure achieve high external quantum efficiency, spectral response in the short wavelength range (ultraviolet region), low transmittance of long wavelength (near infrared region) photons, and almost no attenuation caused by ultraviolet rays. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the accompanying drawings should not be considered to limit the scope of the disclosed inventions, the presently described embodiments and / or examples, and any of the best modes currently understood for these inventions.

[0024] FIG1 is a solar cell structure according to a specific example of the present application.

[0025] FIG2 is a graph showing the reflectivity, absorptivity, and external quantum response test results of the solar cell structure of Example 1.

[0026] FIG3 is an IV curve of the solar cell structure of Example 1.

[0027] Explanation of the reference numerals: 10: solar cell; 100: substrate; 110: first passivation layer; 120: N-type doped zinc sulfide layer; 130: first transparent conductive oxide layer; 140: second passivation layer; 150: P-type doped layer; 160: second transparent conductive oxide layer; 170: first electrode; 180: second electrode. DETAILED DESCRIPTION

[0028] The present invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided for the purpose of providing a more thorough and comprehensive understanding of the disclosure of the present invention. Of course, they are merely illustrative and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and / or letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or arrangements discussed.

[0029] When describing positional relationships, unless otherwise specified, when an element, such as a layer, film, or substrate, is referred to as being "on" another layer, it can be directly on the other layer or intervening layers may also be present. Furthermore, when a layer is referred to as being "under" another layer, it can be directly under or one or more intervening layers may also be present. It will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.

[0030] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part without departing from the teachings of the present invention.

[0031] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0032] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the elements in the drawings are drawn only as examples to facilitate understanding of the present invention, but are not necessarily drawn to true scale. The scales in the drawings do not constitute a limitation of the present invention. It should be noted that when a component is referred to as being "on another component," "connected to another component," "coupled to another component," or "contacting another component," it can be directly on, connected to, coupled to, or in contact with the other component, or there can be intervening components. In contrast, when a component is referred to as being "directly on another component," "directly connected to," "directly coupled to," or "directly in contact with" another component, there are no intervening components. Similarly, when a first component is referred to as being "electrically in contact" or "electrically coupled to" a second component, there is an electrical path between the first and second components that allows current to flow. This electrical path can include capacitors, coupled inductors, and / or other components that allow current to flow, even when there is no direct contact between the conductive components.

[0033] As shown in FIG1 , the present application provides a solar cell 10 including the following structure:

[0034] A substrate 100 having a first surface and a second surface opposite to each other;

[0035] A first passivation layer 110, an N-type doped zinc sulfide layer 120, and a first transparent conductive oxide layer 130 are sequentially stacked on a first surface of the substrate 100, and a second passivation layer 140, a P-type doped layer 150, and a second transparent conductive oxide layer 160 are sequentially stacked on a second surface of the substrate 100; wherein the first passivation layer 110 includes a silicon dioxide layer.

[0036] In this application, by selecting silicon dioxide as the first passivation layer 110 between the substrate 100 and the N-type doped zinc sulfide layer 120, and using zinc sulfide as the N-type doping layer, surface reflection can be effectively reduced, the surface recombination rate can be further reduced, the light trapping effect can be enhanced, and the carrier lifetime can be increased, thereby improving the electrical performance of the substrate 100. The solar cell 10 with this structure achieves high external quantum efficiency, spectral response in the short wavelength range (ultraviolet region), low transmittance of long wavelength (near infrared region) photons, and almost no attenuation caused by ultraviolet rays.

[0037] Traditional silicon-based heterojunction solar cells are susceptible to ultraviolet radiation due to the presence of hydrogen atoms at the interface between the hydrogenated intrinsic amorphous silicon layer and the crystalline silicon layer. When exposed to sunlight, the hydrogen atoms can be excited and diffuse into the bulk of the silicon substrate, leading to the formation of defects such as dangling bonds and hydrogenated vacancies. These defects can recombine charge carriers, reducing minority carrier lifetime and lowering cell efficiency.

[0038] Solar cells based on zinc sulfide do not suffer from this problem because they do not contain hydrogen atoms in their structure. Zinc sulfide (ZnS) is a semiconductor material with a wide bandgap (3.6-3.7 eV) that has been widely studied for its potential use in solar cells. ZnS is a highly transparent material in the visible range of the electromagnetic spectrum, a property that makes it an ideal candidate for use as a window layer in solar cells. ZnS has high electron mobility, meaning that electrons can easily move through the material, which is important for efficient charge transport in solar cells. ZnS is chemically stable, which enables it to reduce degradation when exposed to the environment and maintain the long-term stability of solar cells. In addition, ZnS has a wider bandgap and higher electron affinity than hydrogen-doped microcrystalline silicon, which helps to reduce the recombination of photogenerated carriers and improve cell efficiency. ZnS is also a relatively low-cost material, making it very attractive for the commercial production of solar cells.

[0039] Furthermore, the substrate 100 is an n-type single crystal silicon wafer (c-Si silicon wafer). Preferably, the resistivity of the substrate 100 is 0.3Ω·cm to 7Ω·cm, and the thickness is 50μm to 150μm. <100> Crystal orientation, area > 100cm 2 .

[0040] In a specific example, the thickness of the first passivation layer 110 is 1 nm to 5 nm. Specifically, the thickness of the first passivation layer 110 can be, but is not limited to, 1 nm, 2 nm, 3 nm, 4 nm, or 5 nm.

[0041] In a specific example, the thickness of the N-type doped zinc sulfide layer 120 is 5 nm to 25 nm. Specifically, the thickness of the N-type doped zinc sulfide layer 120 can be, but is not limited to, 5 nm, 10 nm, 15 nm, 20 nm, or 25 nm.

[0042] In a specific example, the first surface is a suede surface, and the second surface is a polished surface.

[0043] It can be understood that the first surface is textured to enhance light trapping and absorption in the solar cell 10 , while the second surface is polished to enhance reflection of internal long-wavelength photons to reduce their transmission.

[0044] In a specific example, the material of the second passivation layer 140 includes silicon dioxide or hydrogenated intrinsic amorphous silicon.

[0045] Preferably, the material of the second passivation layer 140 is silicon dioxide. It can be understood that silicon dioxide can improve the electrical properties of the substrate 100 by reducing the surface recombination rate and increasing the carrier lifetime. It can also reduce surface reflection and enhance the light trapping effect, thereby increasing light absorption and improving device performance.

[0046] In a specific example, the thickness of the second passivation layer 140 is 1 nm to 15 nm. Further, the thickness of the second passivation layer 140 can be, but is not limited to, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 11 nm, 12 nm, 13 nm, 14 nm, or 15 nm.

[0047] It can be understood that the thickness of the first passivation layer 110 is less than or equal to the thickness of the second passivation layer 140 .

[0048] In a specific example, the material of the P-type doping layer 150 includes P-type hydrogenated doped microcrystalline silicon or P-type doped nickel oxide.

[0049] Preferably, the material of the P-type doped layer 150 is P-type doped nickel oxide. Since nickel oxide has a very high work function (5.0 eV), compared with materials such as single crystal / polycrystalline silicon, copper indium gallium selenide, cadmium telluride, and poly (3-hexylthiophene), nickel oxide has a relatively high work function, which is conducive to achieving efficient hole extraction. In addition, it can form selective contact with carriers that is conducive to hole transport but blocks electron transport, thereby strengthening the separation of photogenerated electron-hole pairs, helping to reduce recombination losses, and making the battery more efficient.

[0050] Furthermore, nickel oxide (NiOx) has good hierarchical arrangement, conductivity, solution processability, stability, and cost-effectiveness. Specifically, nickel oxide has a suitable energy level arrangement that enables efficient hole extraction and electron blocking in solar cell structures, helping to reduce recombination losses and improve charge collection. Nickel oxide has relatively high conductivity and can achieve efficient charge transport in the p-type layer, which also helps improve device performance. Nickel oxide has good solution processability and can be deposited using solution technology, so large-area, cost-effective manufacturing processes can be adopted. In contrast, single crystal / polycrystalline silicon, copper indium gallium selenide, and cadmium telluride generally require more complex manufacturing methods. Nickel oxide has good chemical and thermal stability compared to certain more easily degradable organic materials such as poly(3-hexylthiophene), which can ensure its long-term performance in solar cell devices. Nickel oxide is based on nickel, an abundant and relatively low-cost element. This helps to improve the cost-effectiveness of nickel oxide-based devices compared to materials such as molybdenum oxide and vanadium oxide, which have limited reserves and higher material costs.

[0051] In a specific example, the thickness of the P-type doping layer 150 is 5 nm to 50 nm. Specifically, the thickness of the P-type doping layer 150 can be, but is not limited to, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm.

[0052] In one specific example, the materials of the first transparent conductive oxide layer 130 and the second transparent conductive oxide layer 160 independently include, but are not limited to, one or more of indium tin oxide, tungsten-doped indium oxide, cerium-doped indium oxide, aluminum-doped zinc oxide, indium-doped cadmium oxide, and antimony-doped tin oxide. It will be appreciated that the first transparent conductive oxide layer 130 and the second transparent conductive oxide layer 160, acting as conductive electrodes, not only help reduce light reflection from the cell surface but also allow light to pass through while enabling rapid carrier extraction.

[0053] In a specific example, the thickness of the first transparent conductive oxide layer 130 and the second transparent conductive oxide layer 160 are independently 40 nm to 80 nm.

[0054] Furthermore, the thickness of the first transparent conductive oxide layer 130 is 40 nm to 80 nm, and the thickness of the second transparent conductive oxide layer 160 is 40 nm to 70 nm.

[0055] Specifically, the thickness of the first transparent conductive oxide layer 130 may be, but is not limited to, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, or 80 nm. The thickness of the second transparent conductive oxide layer 160 may be, but is not limited to, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, or 70 nm.

[0056] In a specific example, the first electrode 170 is disposed on the first transparent conductive oxide layer 130 and the second electrode 180 is disposed on the second transparent conductive oxide layer 160 .

[0057] It can be understood that the first electrode 170 includes a first main gate and a first sub-gate. Specifically, the first fine gate includes 40 to 80 metal gate lines with a width of 30μm-60μm and a height of 5μm-15μm. The first main gate includes 12 to 36 metal gate lines with a width of 50μm-100μm and a height of 5μm-15μm. The cross-sectional shape of the first fine gate and the first main gate is square.

[0058] Furthermore, the material of the first electrode 170 includes one or more metals such as silver, copper, aluminum, zinc, nickel and tin. Specifically, the first electrode 170 is one or more of silver, copper, aluminum, silver-copper, silver-aluminum, silver-zinc, silver-nickel, silver-tin, silver-clad copper, silver-clad aluminum, silver-clad zinc, silver-clad nickel and silver-clad tin, with a resistivity of 10 -5 Ω·cm-10 -7 Ω·cm.

[0059] Furthermore, the second electrode 180 includes a second main gate and a second sub-gate. Specifically, the second fine gate includes 100-150 metal grid lines with a width of 30μm-60μm and a height of 5μm-15μm. The second main gate includes 12-36 metal grid lines with a width of 50μm-100μm and a height of 5μm-15μm. The cross-sectional shape of the second fine gate and the second main gate is square.

[0060] In a specific example, the material of the second electrode 180 includes one or more metals such as silver, copper, aluminum, zinc, nickel and tin. Specifically, the second electrode 180 is one or more of silver, copper, aluminum, silver-copper, silver-aluminum, silver-zinc, silver-nickel, silver-tin, silver-clad copper, silver-clad aluminum, silver-clad zinc, silver-clad nickel and silver-clad tin, and the resistivity is 10 -5 Ω·cm-10 -7 Ω·cm.

[0061] Furthermore, the present application also provides a method for preparing the solar cell 10 as described above, comprising the following steps:

[0062] providing a substrate 100;

[0063] A first passivation layer 110 , an N-type doped zinc sulfide layer 120 , and a first transparent conductive oxide layer 130 are sequentially formed on the first surface of the substrate 100 , and a second passivation layer 140 , a P-type doped layer 150 , and a second transparent conductive oxide layer 160 are sequentially formed on the second surface of the substrate 100 .

[0064] It is understood that, before forming the first passivation layer 110 on the first surface of the substrate 100, the substrate 100 is further prepared to have a textured first surface, including texturing the substrate 100 using an anisotropic wet etching method in a dilute alkaline solution. The substrate 100 is then cleaned using the RCA standard cleaning method, specifically using deionized water, RCA1, deionized water, and RCA2 and deionized water to clean the silicon wafer in sequence.

[0065] Furthermore, RCA standard cleaning is a two-step process using a mixture of chemicals including deionized water, hydrogen peroxide (H2O2), ammonia monohydrate (NH3·H2O), and hydrochloric acid (HCl) in varying proportions. The two main solutions used for RCA cleaning are commonly referred to as RCA1 (Solution 1) and RCA2 (Solution 2).

[0066] Furthermore, when texturing is performed, the surface of the silicon wafer that does not need to be texturized must be protected from the influence of the etching solution to prevent unnecessary damage to the polished surface. The single-sided texturing step is usually completed by using a mask or a protective layer, which covers the silicon wafer surface during the etching process. The mask or protective layer can be made of various materials, such as photoresist, paraffin or high molecular polymer. In addition to using a mask or a protective layer to shield the surface that does not need to be texturized, there is another method for single-sided etching process, that is, immersing the surface of the side of the silicon wafer that needs to be texturized in the etching solution, while the surface of the side that does not need to be texturized is covered with a water film. The depth of the etching solution is very shallow and will not affect the coverage of the water film on the surface of the side that does not need to be texturized, but at the same time can provide a good etching effect on the surface that needs to be texturized.

[0067] It is understood that before forming the second passivation layer 140 on the second surface of the substrate 100, the surface of the substrate 100 to be polished is also polished. Specifically, the polishing method includes one or both of mechanical polishing and chemical polishing. Mechanical polishing achieves higher flatness; chemical polishing is often performed using a mixed etching solution of nitric acid and hydrofluoric acid, but it has poorer flatness. Chemical-mechanical polishing (CMP) uses a polishing solution to simultaneously chemically etch and mechanically grind the silicon wafer surface, combining the advantages of both chemical and mechanical polishing methods. The polishing solution used is generally a colloidal solution composed of polishing powder and sodium hydroxide solution, and the polishing powder is usually SiO2.

[0068] In a specific example, the method of preparing the first passivation layer 110 and the second passivation layer 140 may be, but is not limited to, atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), thermal oxidation or sol-gel deposition.

[0069] In a specific example, the method of preparing the N-type doped zinc sulfide layer 120 may be, but is not limited to, chemical bath deposition (CBD), atomic layer deposition (ALD), pulsed laser deposition (PLD), or spray pyrolysis (SP).

[0070] In a specific example, the method of preparing the P-type doping layer 150 may be, but is not limited to, chemical vapor deposition (CVD), magnetron sputtering physical vapor deposition (PVD), or reactive physical vapor deposition (RPD).

[0071] In a specific example, the first transparent conductive oxide layer 130 and the second transparent conductive oxide layer 160 are each independently selected from, but not limited to, magnetron sputtering (PVD), evaporation, or chemical vapor deposition (CVD).

[0072] Furthermore, the methods of forming the first electrode 170 and the second electrode 180 are independently selected from, but not limited to, screen printing, electroplating, laser transfer, mask sputtering, or mask evaporation.

[0073] Furthermore, the present application provides a photovoltaic assembly, comprising the solar cell as described above.

[0074] The following provides specific examples and comparative examples to further illustrate the solar cell 10 of the present application. Unless otherwise specified, the raw materials involved in the following specific embodiments can all be obtained from commercial sources.

[0075] Example 1

[0076] This embodiment provides a solar cell structure, including a substrate, which is an n-type c-Si silicon wafer grown by the modified Siemens method (Czochralski) on the market. The first surface of the substrate is textured, and a silicon dioxide layer with a thickness of 1 nm is prepared on the textured surface as a first passivation layer, an N-type doped zinc sulfide layer with a thickness of 8 nm, and an indium tin oxide (ITO) with a thickness of 50 nm are prepared as a first transparent conductive oxide layer. The second surface of the substrate is polished, and a silicon dioxide layer with a thickness of 1 nm is prepared on the polished surface as a second passivation layer, a P-type doped nickel oxide layer with a thickness of 30 nm is prepared as a P-type doped layer, and an indium tin oxide (ITO) with a thickness of 40 nm is prepared as a second transparent conductive oxide layer. The first electrode is silver / copper / aluminum / silver-copper / silver-aluminum / silver-zinc / silver-nickel / silver-tin / silver-copper / silver-coated aluminum / silver-coated zinc / silver-coated nickel / silver-coated tin, etc., with a resistivity of 10 -5 Ω·cm-10 -7 Ω·cm, the first electrode includes a first main grid and a first sub-grid. Specifically, the first fine grid includes 40 to 80 metal grid lines with a width of 30μm-60μm and a height of 5μm-15μm, and the first main grid includes 12 to 36 metal grid lines with a width of 50μm-100μm and a height of 5μm-15μm. The second electrode is made of silver / copper / aluminum / silver-copper / silver-aluminum / silver-zinc / silver-nickel / silver-tin / silver-copper / silver-coated aluminum / silver-coated zinc / silver-coated nickel / silver-coated tin, etc., with a resistivity of 10 -5 Ω·cm-10 -7 The second electrode includes a second main grid and a second sub-grid. Specifically, the second fine grid includes 100-150 metal grid lines with a width of 30 μm-60 μm and a height of 5 μm-15 μm. The second main grid includes 12-36 metal grid lines with a width of 50 μm-100 μm and a height of 5 μm-15 μm.

[0077] The solar cell provided in this embodiment was tested, and the test results are shown in Figures 2 and 3. The reflectivity and external quantum response research results in Figure 2 show that higher external quantum efficiency EQE and absorption in the short wavelength range will lead to higher short-circuit current density, thereby improving the efficiency of the solar cell. The figure also shows that there is a higher reflection from 900nm to 1200nm, which means that the transmittance is low in this range. Currently, silicon solar cells are developing in the direction of thinning, and the utilization rate of the long wavelength band is also declining. This structure alleviates this problem very well. Figure 2 (b) shows the IV curve of the battery with this structure, and Jsc exceeds 40.25mA / cm 2 , that is, it has a higher short-circuit current density, indicating that there is less recombination of electrons and holes and the charge separation efficiency of the battery is better.

[0078] Example 2

[0079] This embodiment provides a solar cell structure, including a substrate, which is an n-type c-Si silicon wafer grown by the modified Siemens method (Czochralski) on the market. The first surface of the substrate is textured, and a silicon dioxide layer with a thickness of 1 nm is prepared on the textured surface as a first passivation layer, a N-type doped zinc sulfide layer with a thickness of 25 nm, and an indium tin oxide (ITO) layer with a thickness of 70 nm are prepared as a first transparent conductive oxide layer. The second surface of the substrate is polished, and a hydrogenated intrinsic amorphous silicon layer with a thickness of 5 nm is prepared on the polished surface as a second passivation layer, a P-type hydrogenated doped microcrystalline silicon layer with a thickness of 20 nm is prepared as a P-type doped layer, and an indium tin oxide (ITO) layer with a thickness of 50 nm is prepared as a second transparent conductive oxide layer. The first electrode is silver / copper / aluminum / silver-copper / silver-aluminum / silver-zinc / silver-nickel / silver-tin / silver-copper / silver-coated aluminum / silver-coated zinc / silver-coated nickel / silver-coated tin, etc., with a resistivity of 10 -5 Ω·cm-10 -7 Ω·cm, the first electrode includes a first main grid and a first sub-grid. Specifically, the first fine grid includes 40-80 metal grid lines with a width of 30μm-60μm and a height of 5μm-15μm, and the first main grid includes 12-36 metal grid lines with a width of 50μm-100μm and a height of 5μm-15μm. The second electrode is made of silver / copper / aluminum / silver-copper / silver-aluminum / silver-zinc / silver-nickel / silver-tin / silver-copper / silver-coated aluminum / silver-coated zinc / silver-coated nickel / silver-coated tin, etc., with a resistivity of 10 -5 Ω·cm-10 -7 The second electrode includes a second main grid and a second sub-grid. Specifically, the second fine grid includes 100-150 metal grid lines with a width of 30 μm-60 μm and a height of 5 μm-15 μm. The second main grid includes 12-36 metal grid lines with a width of 50 μm-100 μm and a height of 5 μm-15 μm.

[0080] Example 3

[0081] This embodiment provides a solar cell structure, including a substrate, which is an n-type c-Si silicon wafer grown by the modified Siemens method (Czochralski) on the market. The first surface of the substrate is textured, and a 2nm thick silicon dioxide layer is sequentially prepared on the textured surface as a first passivation layer, a 25nm thick N-type doped zinc sulfide layer, and a 80nm thick tungsten-doped indium oxide (IWO) layer are sequentially prepared as a first transparent conductive oxide layer. The second surface of the substrate is polished, and an 8nm thick hydrogenated intrinsic amorphous silicon layer is sequentially prepared on the polished surface as a second passivation layer, a 25nm thick P-type doped nickel oxide layer is sequentially prepared as a P-type doped layer, and a 55nm thick indium tin oxide (ITO) layer is sequentially prepared as a second transparent conductive oxide layer. The first electrode is silver / copper / aluminum / silver-copper / silver-aluminum / silver-zinc / silver-nickel / silver-tin / silver-copper / silver-coated aluminum / silver-coated zinc / silver-coated nickel / silver-coated tin, etc., with a resistivity of 10 -5 Ω·cm-10 -7 Ω·cm, the first electrode includes a first main grid and a first sub-grid. Specifically, the first fine grid includes 40-80 metal grid lines with a width of 30μm-60μm and a height of 5μm-15μm, and the first main grid includes 12-36 metal grid lines with a width of 50μm-100μm and a height of 5μm-15μm. The second electrode is made of silver / copper / aluminum / silver-copper / silver-aluminum / silver-zinc / silver-nickel / silver-tin / silver-clad copper / silver-clad aluminum / silver-clad zinc / silver-clad nickel / silver-clad tin, etc., with a resistivity of 10 -5 Ω·cm-10 -7 The second electrode includes a second main grid and a second sub-grid. Specifically, the second fine grid includes 100-150 metal grid lines with a width of 30 μm-60 μm and a height of 5 μm-15 μm. The second main grid includes 12-36 metal grid lines with a width of 50 μm-100 μm and a height of 5 μm-15 μm.

[0082] Example 4

[0083] This embodiment provides a solar cell structure, including a substrate, which is an n-type c-Si silicon wafer grown by the modified Siemens method (Czochralski) on the market. The first surface of the substrate is textured, and a 2nm thick silicon dioxide layer is sequentially prepared on the textured surface as a first passivation layer, a 15nm thick N-type doped zinc sulfide layer, and a 50nm thick cerium-doped indium oxide (ICO) as a first transparent conductive oxide layer. The second surface of the substrate is polished, and a 2nm thick silicon dioxide layer is sequentially prepared on the polished surface as a second passivation layer, a 25nm thick P-type hydrogenated doped microcrystalline silicon layer is used as a P-type doping layer, and a 70nm thick indium tin oxide (ITO) as a second transparent conductive oxide layer. The first electrode is silver / copper / aluminum / silver-copper / silver-aluminum / silver-zinc / silver-nickel / silver-tin / silver-copper / silver-coated aluminum / silver-coated zinc / silver-coated nickel / silver-coated tin, etc., with a resistivity of 10 -5 Ω·cm-10 -7 Ω·cm, the first electrode includes a first main grid and a first sub-grid. Specifically, the first fine grid includes 40-80 metal grid lines with a width of 30μm-60μm and a height of 5μm-15μm, and the first main grid includes 12-36 metal grid lines with a width of 50μm-100μm and a height of 5μm-15μm. The second electrode is made of silver / copper / aluminum / silver-copper / silver-aluminum / silver-zinc / silver-nickel / silver-tin / silver-clad copper / silver-clad aluminum / silver-clad zinc / silver-clad nickel / silver-clad tin, etc., with a resistivity of 10 -5 Ω·cm-10 -7 The second electrode includes a second main grid and a second sub-grid. Specifically, the second fine grid includes 100 to 150 metal grid lines with a width of 30 μm to 60 μm and a height of 5 μm to 15 μm. The second main grid includes 12 to 36 metal grid lines with a width of 50 μm to 100 μm and a height of 5 μm to 15 μm.

[0084] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0085] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0086] The embodiments described above only express several implementation methods of the present invention, which are convenient for understanding the technical solutions of the present invention in a specific and detailed manner, but they cannot be understood as limiting the scope of protection of the patent application. It should be pointed out that for ordinary technicians in this field, without departing from the concept of the present invention, several variations and improvements can be made, which all fall within the scope of protection of the present invention. It should be understood that the technical solutions obtained by those skilled in the art through logical analysis, reasoning or limited experiments on the basis of the technical solutions provided by the present invention are all within the scope of protection of the claims attached to the present invention. Therefore, the scope of protection of the patent of the present invention shall be based on the content of the attached claims, and the description can be used to interpret the content of the claims.

Claims

1. A solar cell, characterized in that: Includes the following structures: a substrate having opposing first and second surfaces; as well as A first passivation layer, an N-type doped zinc sulfide layer and a first transparent conductive oxide layer are sequentially stacked on the first surface of the substrate, and a second passivation layer, a P-type doped layer and a second transparent conductive oxide layer are sequentially stacked on the second surface of the substrate; wherein the first passivation layer includes a silicon dioxide layer.

2. The solar cell according to claim 1, wherein: The first surface is a suede surface, and the second surface is a polished surface.

3. The solar cell according to claim 1, wherein: The material of the second passivation layer includes silicon dioxide or hydrogenated intrinsic amorphous silicon.

4. The solar cell according to claim 3, wherein: The thickness of the second passivation layer is 1 nm-15 nm.

5. The solar cell according to claim 1, wherein: The material of the P-type doping layer includes P-type hydrogenated doped microcrystalline silicon or P-type doped nickel oxide.

6. The solar cell according to claim 5, wherein: The thickness of the P-type doping layer is 5nm-50nm.

7. The solar cell according to claim 1, wherein: The materials of the first transparent conductive oxide layer and the second transparent conductive oxide layer independently include one or more of indium tin oxide, tungsten-doped indium oxide, cerium-doped indium oxide, aluminum-doped zinc oxide, indium-doped cadmium oxide and antimony-doped tin oxide.

8. The solar cell according to claim 7, wherein: The thickness of the first transparent conductive oxide layer and / or the second transparent conductive oxide layer is 40 nm-80 nm.

9. The solar cell according to any one of claims 1 to 8, wherein: The thickness of the N-type doped zinc sulfide layer is 5nm-25nm.

10. The solar cell according to any one of claims 1 to 8, wherein: The thickness of the first passivation layer is 1 nm to 5 nm.

11. A method for preparing a solar cell according to any one of claims 1 to 10, characterized in that: The following steps are involved: providing the substrate; The first passivation layer, the N-type doped zinc sulfide layer and the first transparent conductive oxide layer are sequentially prepared on the first surface of the substrate, and the second passivation layer, the P-type doped layer and the second transparent conductive oxide layer are sequentially prepared on the second surface of the substrate.

12. A photovoltaic module, characterized in that: Comprising the solar cell according to any one of claims 1 to 10.

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