Input and output driver structure, input and output control method, and communication system

Abstract

The present application relates to the technical field of input and output drivers, and discloses an input and output driver structure, an input and output control method, and a communication system. In the input and output driver structure, a first single-ended output module is used for outputting a first single-ended signal to a first terminal, a first single-ended input module is used for sending a second single-ended signal to a first target device, a first differential input module is used for carrying out differential decoding on a first differential signal and a second differential signal, a first differential output module is used for carrying out differential encoding on a fourth differential signal, a second single-ended output module is used for outputting a third single-ended signal to a second terminal, a second single-ended input module is used for sending a fourth single-ended signal to the first target device, and a second differential input module is used for carrying out differential decoding on a seventh differential signal and an eighth differential signal. The present application avoids the problem that input and output driver hardware needs to be replaced under the condition of scene changes, and reduces user input costs.

Description

Input / output driver structure, input / output control method, and communication system

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on September 6, 2023, with application number 202311146414.0 and invention name “Input and output driver structure, input and output control method and communication system”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of input / output driver technology, and in particular to an input / output driver structure, an input / output control method, and a communication system. Background Art

[0004] Field Programmable Gate Array (FPGA) needs to communicate with external devices through input and output drivers (IO BUF). The input and output drivers are used to convert signals inside the field programmable gate array into signals that can be recognized by external devices, and to convert signals emitted by external devices into signals that can be recognized by the field programmable gate array. When designing input and output drivers, relevant technicians often need to consider factors such as voltage level, signal speed, and power consumption. To reduce the design difficulty, the relevant technology provides a variety of input and output driver architectures, but each input and output driver architecture is often only applicable to specific scenarios. When the scenario changes, another input and output driver architecture must be used. The problem caused by this is that when the external device is replaced or the communication parameters of the external device are updated, the input and output driver architecture must also be replaced. This situation not only leads to increased user investment costs, but also prolongs project delivery time. Therefore, the conventional input and output driver architecture has the problem of limited usage scenarios, and it is urgent to improve or optimize the conventional input and output driver architecture.

[0005] Summary of the Invention

[0006] In view of this, the present application provides an input / output driver structure, an input / output control method, and a communication system to solve the problem that conventional input / output driver architectures have limited usage scenarios.

[0007] In a first aspect, the present application provides an input / output driver structure, comprising:

[0008] a first single-ended output module connected to the first terminal, the first single-ended output module being used to output a first single-ended signal emitted by the first target device to the first terminal, the first terminal being used to be connected to the second target device;

[0009] a first single-ended input module connected to the first terminal, the first single-ended input module being configured to send a second single-ended signal input from the first terminal to the first target device, the second single-ended signal being sent by the second target device;

[0010] a first differential input module connected to the first terminal and the second terminal, respectively, the first differential input module being used to differentially decode a first differential signal input from the first terminal and a second differential signal input from the second terminal, and to send a third differential signal obtained by the differential decoding to the first target device, the first differential signal and the second differential signal both being sent by the second target device, and the second terminal being used to connect to the second target device;

[0011] a first differential output module, connected to the first terminal and the second terminal respectively, and configured to perform differential encoding on the fourth differential signal to obtain a fifth differential signal output through the first terminal and a sixth differential signal output through the second terminal;

[0012] a second single-ended output module connected to the second terminal, the second single-ended output module being used to output the third single-ended signal emitted by the first target device to the second terminal, the second terminal being used to be connected to the second target device;

[0013] a second single-ended input module connected to the second terminal, the second single-ended input module being configured to transmit a fourth single-ended signal input from the second terminal to the first target device, the fourth single-ended signal being transmitted by the second target device;

[0014] A second differential input module is connected to the first terminal and the second terminal respectively. The second differential input module is used to differentially decode the seventh differential signal input from the first terminal and the eighth differential signal input from the second terminal, and to send the ninth differential signal obtained by the differential decoding to the first target device. The seventh differential signal and the eighth differential signal are both sent by the second target device.

[0015] Compared with the problem that the input and output driver architecture in conventional technology can only be applied to specific scenarios, the present application provides a new input and output driver structure, which can support a single-ended output working mode provided by a first single-ended output module and / or a second single-ended output module, a single-ended input working mode provided by a first single-ended input module and / or a second single-ended input module, a differential input working mode provided by a first differential input module and / or a second differential input module, and a differential output working mode provided by a first differential output module. Therefore, the present application can use corresponding working modules in different usage scenarios. When the scenario changes, there is no need to replace the input and output driver structure, which avoids the problem of the related technology that the input and output driver hardware must be replaced when the scenario changes, thereby significantly reducing the user's investment cost and shortening the delivery time of input and output driver related projects.

[0016] In an optional embodiment, the first single-ended output module has a first input end and a first output end, the first input end is used to receive the first single-ended signal, the first output end is used to output the first single-ended signal processed by the first single-ended output module, and the first output end is connected to the first terminal;

[0017] The first single-ended input module has a second input end and a second output end, the second input end is used to receive the second single-ended signal, the second input end is connected to the first terminal, and the second output end is used to send the second single-ended signal processed by the first single-ended input module;

[0018] The first differential input module has a third input terminal, a fourth input terminal and a third output terminal. The third input terminal is connected to the first terminal, the fourth input terminal is connected to the second terminal, the third input terminal is used to receive the first differential signal, the fourth input terminal is used to receive the second differential signal, and the third output terminal is used to send the third differential signal to the first target device.

[0019] The present application uses the first terminal to directly connect the first single-ended output module and the first single-ended input module, and uses the first terminal and the second terminal to directly connect the first differential input module. It can be seen that the present application realizes single-ended output function, single-ended input function and differential input function while using a smaller number of terminals.

[0020] In an optional embodiment, the first differential output module has a fifth input terminal, a fourth output terminal and a fifth output terminal, the fifth input terminal is used to receive a fourth differential signal, the fourth output terminal is connected to the first terminal, the fifth output terminal is connected to the second terminal, the fourth output terminal is used to output the fifth differential signal to the first terminal, and the fifth output terminal is used to output the sixth differential signal to the second terminal.

[0021] The present application uses the first terminal and the second terminal to directly connect the first differential output module. It can be seen that the present application can also realize single-ended output function, single-ended input function, differential input function and differential output function while using a smaller number of terminals.

[0022] In an optional embodiment, the second single-ended output module has a sixth input end and a sixth output end, the sixth input end is used to receive the third single-ended signal, the sixth output end is used to output the third single-ended signal processed by the second single-ended output module, and the sixth output end is connected to the second terminal;

[0023] The second single-ended input module has a seventh input terminal and a seventh output terminal, the seventh input terminal is used to receive the fourth single-ended signal, the seventh input terminal is connected to the second terminal, and the seventh output terminal is used to send the fourth single-ended signal processed by the second single-ended input module;

[0024] The second differential input module has an eighth input terminal, a ninth input terminal and an eighth output terminal, the eighth input terminal is connected to the first terminal, the ninth input terminal is connected to the second terminal, the eighth input terminal is used to receive the seventh differential signal, the ninth input terminal is used to receive the eighth differential signal, and the eighth output terminal is used to send the ninth differential signal to the first target device.

[0025] The present application uses the second terminal to directly connect the second single-ended output module and the second single-ended input module, and uses the second terminal and the first terminal to directly connect the second differential input module. It can be seen that the present application can also be based on the specific connection method and overall architectural design of the above-mentioned first terminal and second terminal with the first single-ended output module, the first single-ended input module, the first differential input module, the first differential output module, the second single-ended output module, the second single-ended input module, and the second differential input module respectively. While taking into account the single-ended output mode, the single-ended input mode, the differential output mode and the differential input mode, the present application still only uses two terminals to connect to external devices, that is, only the first terminal and the second terminal are used as the physical connection terminals between the first target device and the second target device. It can be seen that compared with the simple superposition of multiple conventional designs, the present application has fewer terminals for external connection and a more reasonable overall architectural design.

[0026] In an optional embodiment, the input-output driver structure further includes:

[0027] The second differential output module has a tenth input terminal, a ninth output terminal, and a tenth output terminal. The tenth input terminal is used to receive the tenth differential signal. The second differential output module is used to differentially encode the tenth differential signal to obtain an eleventh differential signal and a twelfth differential signal. The ninth output terminal is connected to the first terminal, the tenth output terminal is connected to the second terminal, the ninth output terminal is used to output the eleventh differential signal to the first terminal, and the tenth output terminal is used to output the twelfth differential signal to the second terminal.

[0028] The present application can also additionally add a second differential output module. This method not only enables the first differential output module and the second differential output module to work alternately, but also serves the purpose of redundancy when the first differential output module fails, thereby ensuring differential output performance and improving the reliability of the product of the present application.

[0029] In an optional embodiment, the first single-ended output module further has a first enable terminal, the first enable terminal is used to receive a first enable signal sent by the first target device, and the first enable signal is used to control whether the first single-ended output module outputs the first single-ended signal processed by the first single-ended output module;

[0030] The second single-ended output module also has a second enable terminal, which is used to receive a second enable signal sent by the second target device. The second enable signal is used to control whether the second single-ended output module outputs a third single-ended signal processed by the second single-ended output module.

[0031] The present application can also control the enable state of the first single-ended output module by sending a first enable signal to the first enable terminal or control the enable state of the second single-ended output module by sending a second enable signal to the second enable terminal, thereby achieving effective control of the single-ended output function.

[0032] In an optional implementation, the first differential output module is an LVDS output driver.

[0033] By using an LVDS (Low-Voltage Differential Signaling) output driver as the first differential output module, the present application can increase the data transmission rate in the differential output mode, improve the anti-interference ability, reduce the transmission power consumption, and realize long-distance transmission function.

[0034] In an optional embodiment, the input-output driver structure further includes:

[0035] A first bus holding module is connected to the first terminal, and is used to maintain the level state of the first terminal in a non-driving state;

[0036] The second bus holding module is connected to the second terminal and is used for holding the level state of the second terminal in a non-driving state.

[0037] The present application can maintain a valid level state on the first terminal when the first terminal is not connected or an invalid voltage is input through the first bus holding module, and can maintain a valid level state on the second terminal when the second terminal is not connected or an invalid voltage is input through the second bus holding module, thereby improving the reliability of the operation of the present application.

[0038] In an optional embodiment, the input-output driver structure further includes:

[0039] The first hot-swap module has a first connection end, a second connection end, and a third connection end, wherein the first connection end is connected to the first single-ended output module, the second connection end is connected to the first terminal, and the third connection end is connected to the second terminal; the first hot-swap module is used to offset or absorb an external input signal during a hot-swap operation, wherein the external input signal comes from the first terminal and / or the second terminal;

[0040] The second hot-swap module has a fourth connection end, a fifth connection end and a sixth connection end, the fourth connection end is connected to the second single-ended output module, the fifth connection end is connected to the second terminal, and the sixth connection end is connected to the first terminal; the second hot-swap module is used to offset or absorb external input signals during hot-swap operations, and the external input signals come from the first terminal and / or the second terminal.

[0041] The present application can protect the first single-ended output module, the first terminal and the second terminal through the first hot-swappable module, and protect the second single-ended output module, the first terminal and the second terminal through the second hot-swappable module, thereby effectively protecting the relevant electronic components inside the input and output driver structure of the present application.

[0042] In an optional embodiment, the input and output driver structure is manufactured based on a FinFET process.

[0043] The input-output driver structure provided in the present application can be adapted to the FinFET process, which has the characteristic of lower transistor operating voltage, so that the input-output driver structure can take into account the characteristics of small size, low power consumption, high frequency, high speed and wide voltage while being suitable for a variety of usage scenarios.

[0044] In an optional embodiment, the input and output driver structure is integrated on a field programmable gate array.

[0045] Compared to the prior art, the present application can provide an FPGA including an IO BUF with a single-ended output working mode, a single-ended input working mode, a differential input working mode, and a differential output working mode.

[0046] In an optional embodiment, the first terminal and the second terminal are both welding pads.

[0047] The present application realizes the communication connection between the first single-ended output module, the first single-ended input module, the first differential input module, the first differential output module, the second single-ended output module, the second single-ended input module, the second differential input module and the second target device through the welding pad, thereby improving the reliability of the connection between different devices.

[0048] In an optional embodiment, the first target device is an IP core on a field programmable gate array;

[0049] The second target device is an external device.

[0050] The present application realizes communication between an IP core on a field programmable gate array and an external device, and specifically can realize communication between the IP core and the external device through at least one of a single-ended output working mode, a single-ended input working mode, a differential input working mode and a differential output working mode.

[0051] In a second aspect, the present application provides an input / output control method, which is applied to the input / output driver structure of the first aspect or any corresponding embodiment thereof, and includes:

[0052] In the single-ended output working mode, outputting a first single-ended signal to the second target device through the first single-ended output module, and / or outputting a third single-ended signal to the second target device through the second single-ended output module;

[0053] In the single-ended input working mode, a second single-ended signal is input to the first target device through the first single-ended input module, and / or a fourth single-ended signal is input to the first target device through the second single-ended input module.

[0054] In the differential input working mode, a third differential signal obtained by differentially decoding the first differential signal and the second differential signal is input to the first target device through the first differential input module, and / or a ninth differential signal obtained by differentially decoding the seventh differential signal and the eighth differential signal is input to the first target device through the second differential input module;

[0055] In the differential output working mode, the fifth differential signal and the sixth differential signal obtained by differentially encoding the fourth differential signal are output to the second target device through the first differential output module.

[0056] Compared with the existing input and output control methods, the input and output control method of the present application can support single-ended output working mode, single-ended input working mode, differential input working mode and differential output working mode, so that the present application can use the corresponding working mode in different usage scenarios. When the scene changes, there is no need to replace the input and output driver structure, only the function needs to be switched based on the present application, thereby significantly reducing the user's investment cost and shortening the delivery time of input and output driver related projects.

[0057] In a third aspect, the present application provides a communication system, comprising an input / output driver manufactured based on the input / output driver structure of the first aspect or any corresponding embodiment thereof; the communication system further comprising a first target device and a second target device:

[0058] The first target device communicates with the second target device via an input / output driver;

[0059] The second target device communicates with the second target device via the input / output driver.

[0060] The communication system in the present application can provide a switchable single-ended output working mode, a single-ended input working mode, a differential input working mode and a differential output working mode for the communication process between the first target device and the second target device, so that the communication system of the present application can be applied to more scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0062] FIG1 is a schematic diagram of an input / output driver structure according to an embodiment of the present application;

[0063] FIG2 is a schematic diagram of another input-output driver structure according to an embodiment of the present application;

[0064] FIG3 is a schematic diagram of a communication system according to an embodiment of the present application;

[0065] FIG4 is a schematic diagram of another communication system according to an embodiment of the present application;

[0066] FIG5 is a schematic diagram of yet another communication system according to an embodiment of the present application. DETAILED DESCRIPTION

[0067] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of this application.

[0068] As shown in Figure 1, one or more embodiments of the present application provide an input-output driver structure, which may include but is not limited to a first single-ended output module 101, a first single-ended input (single-end in) module 102, a first differential input (diff in) module 103, a first differential output module 104, a second single-ended output module 105, a second single-ended input module 106, a second differential input module 107, a first terminal 201 and a second terminal 202, as described in detail below.

[0069] The first single-ended output module 101 is connected to the first terminal 201 . The first single-ended output module 101 is used to output the first single-ended signal sent by the first target device 501 to the first terminal 201 . The first terminal 201 is used to connect to the second target device 502 .

[0070] Among them, the first single-ended output module 101 processes the first single-ended signal, which may include but is not limited to level conversion processing (level raising), noise reduction processing, etc. The noise reduction processing may include filtering processing and de-jitter processing, etc., thereby realizing the shaping and processing of the output signal to ensure the accuracy and reliability of the output signal.

[0071] The first single-ended input module 102 is connected to the first terminal 201 . The first single-ended input module 102 is used to send the second single-ended signal input from the first terminal 201 to the first target device 501 . The second single-ended signal is sent by the second target device 502 .

[0072] Among them, the first single-ended input module 102 processes the second single-ended signal, which may include but is not limited to level conversion processing (level reduction), noise reduction processing, etc. The noise reduction processing may include filtering processing and de-jitter processing, etc., thereby realizing the shaping and processing of the input signal to ensure the accuracy and reliability of the input signal.

[0073] The first differential input module 103 is connected to the first terminal 201 and the second terminal 202 respectively. The first differential input module 103 is used to differentially decode the first differential signal input from the first terminal 201 and the second differential signal input from the second terminal 202, and to send the third differential signal obtained by differential decoding to the first target device 501. The first differential signal and the second differential signal are both sent by the second target device 502. The second terminal 202 is used to connect to the second target device 502.

[0074] Among them, the first differential signal and the third differential signal are in phase, and the second differential signal and the third differential signal are in anti-phase. By differentially decoding the first differential signal and the second differential signal, common mode noise can be better suppressed, thereby improving the integrity and reliability of the input signal.

[0075] In some optional implementations, the number of the second target devices 502 may be two. In this case, the first terminal 201 is connected to one of the second target devices 502 , and the second terminal 202 is connected to the other second target device 502 .

[0076] In some optional implementations, the number of the second target device 502 may be one. In this case, the first terminal 201 and the second terminal 202 are both connected to one second target device 502 .

[0077] The first differential output module 104 is connected to the first terminal 201 and the second terminal 202 respectively. The first differential output module 104 is used to differentially encode the fourth differential signal to obtain a fifth differential signal output through the first terminal 201 and a sixth differential signal output through the second terminal 202 .

[0078] Among them, the first differential output module 104 differentially encodes the fourth differential signal, and makes the fifth differential signal in phase with the fourth differential signal, and the sixth differential signal in anti-phase with the fourth differential signal. The differential encoding method can improve the signal anti-interference ability and is more suitable for long-distance signal transmission.

[0079] The second single-ended output module 105 is connected to the second terminal 202 . The second single-ended output module 105 is used to output the third single-ended signal sent by the first target device 501 to the second terminal 202 . The second terminal 202 is used to connect to the second target device 502 .

[0080] Among them, the second single-ended output module 105 processes the third single-ended signal, which may include but is not limited to level conversion processing (level raising), noise reduction processing, etc. The noise reduction processing may include filtering processing and de-jitter processing, etc., thereby realizing the shaping and processing of the output signal to ensure the accuracy and reliability of the output signal.

[0081] The second single-ended input module 106 is connected to the second terminal 202 . The second single-ended input module 106 is configured to send the fourth single-ended signal input from the second terminal 202 to the first target device 501 . The fourth single-ended signal is sent by the second target device 502 .

[0082] Among them, the second single-ended input module 106 processes the fourth single-ended signal, which may include but is not limited to level conversion processing (level reduction), noise reduction processing, etc. The noise reduction processing may include filtering processing and de-jitter processing, etc., thereby realizing the shaping and processing of the input signal to ensure the accuracy and reliability of the input signal.

[0083] The second differential input module 107 is connected to the first terminal 201 and the second terminal 202 respectively. The second differential input module 107 is used to differentially decode the seventh differential signal input from the first terminal 201 and the eighth differential signal input from the second terminal 202, and to send the ninth differential signal obtained by the differential decoding to the first target device 501. The seventh differential signal and the eighth differential signal are both sent by the second target device 502.

[0084] Among them, the seventh differential signal and the ninth differential signal are in phase, and the eighth differential signal and the ninth differential signal are in anti-phase. By differentially decoding the seventh differential signal and the eighth differential signal, common mode noise can be better suppressed, thereby improving the integrity and reliability of the input signal.

[0085] The present application provides a multi-mode IO BUF that can flexibly adapt to different input / output requirements without using more different buffers or logic circuits. It can be seen that the present application simplifies circuit design and reduces BOM (Bill of Material) costs, and improves system integration and flexibility.

[0086] Compared with the problem that the input and output driver architecture in conventional technology can only be applied to specific scenarios, the present application provides a new input and output driver structure that can support a single-ended output working mode provided by the first single-ended output module 101 and / or the second single-ended output module 105, a single-ended input working mode provided by the first single-ended input module 102 and / or the second single-ended input module 106, a differential input working mode provided by the first differential input module 103 and / or the second differential input module 107, and a differential output working mode provided by the first differential output module 104. Therefore, the present application can use corresponding working modules in different usage scenarios. When the scenario changes, there is no need to replace the input and output driver structure, but the new scenario can be adapted by mode switching, that is, the problem of the related technology that the input and output driver hardware must be replaced when the scenario changes is avoided, thereby significantly reducing the user's investment cost and shortening the related project delivery time of the input and output driver.

[0087] In some optional embodiments, the first single-ended output module 101 has a first input end and a first output end, the first input end is used to receive the first single-ended signal, the first output end is used to output the first single-ended signal processed by the first single-ended output module 101, and the first output end is connected to the first terminal 201.

[0088] In the embodiment of the present application, the power supply of the first single-ended output module 101 is, for example, a first auxiliary power supply (mvccaux), and the first auxiliary power supply is an external power supply.

[0089] The first single-ended input module 102 has a second input end and a second output end. The second input end is used to receive the second single-ended signal and is connected to the first terminal 201 . The second output end is used to send the second single-ended signal processed by the first single-ended input module 102 .

[0090] In the embodiment of the present application, the power supply of the first single-ended input module 102 is, for example, a second auxiliary power supply, and the second auxiliary power supply may be the same as the first auxiliary power supply.

[0091] The first differential input module 103 has a third input terminal, a fourth input terminal and a third output terminal. The third input terminal is connected to the first terminal 201, and the fourth input terminal is connected to the second terminal 202. The third input terminal is used to receive the first differential signal, the fourth input terminal is used to receive the second differential signal, and the third output terminal is used to send the third differential signal to the first target device 501.

[0092] In the embodiment of the present application, the power supply of the first differential input module 103 is, for example, a third auxiliary power supply, and the third auxiliary power supply may be the same as the first auxiliary power supply.

[0093] In an IO BUF architecture that implements multiple operating modes, the embodiment of the present application specifically uses the first terminal 201 to directly connect the first single-ended output module 101 and the first single-ended input module 102, and uses the first terminal 201 and the second terminal 202 to directly connect the first differential input module 103. The entire IO BUF architecture only uses two terminals when connected externally. It can be seen that the present application implements single-ended output function, single-ended input function and differential input function while using a relatively small number of terminals.

[0094] In some optional embodiments, the first differential output module 104 has a fifth input terminal, a fourth output terminal and a fifth output terminal, the fifth input terminal is used to receive the fourth differential signal, the fourth output terminal is connected to the first terminal 201, the fifth output terminal is connected to the second terminal 202, the fourth output terminal is used to output the fifth differential signal to the first terminal 201, and the fifth output terminal is used to output the sixth differential signal to the second terminal 202.

[0095] In the embodiment of the present application, the power supply of the first differential input module 103 is, for example, a first input-output power supply (mvccio).

[0096] In an IO BUF architecture that implements multiple operating modes, the embodiment of the present application specifically uses the first terminal 201 and the second terminal 202 to directly connect to the first differential output module 104. The entire IO BUF architecture only uses two terminals when connected externally. It can be seen that the present application can also implement single-ended output function, single-ended input function, differential input function and differential output function while using a smaller number of terminals.

[0097] In some optional embodiments, the second single-ended output module 105 has a sixth input terminal and a sixth output terminal, the sixth input terminal is used to receive the third single-ended signal, the sixth output terminal is used to output the third single-ended signal processed by the second single-ended output module 105, and the sixth output terminal is connected to the second terminal 202.

[0098] In the embodiment of the present application, the power supply of the second single-ended output module 105 is, for example, a fourth auxiliary power supply, and the fourth auxiliary power supply may be the same as the first auxiliary power supply.

[0099] The second single-ended input module 106 has a seventh input terminal and a seventh output terminal. The seventh input terminal is used to receive the fourth single-ended signal and is connected to the second terminal 202 . The seventh output terminal is used to send the fourth single-ended signal processed by the second single-ended input module 106 .

[0100] In the embodiment of the present application, the power supply of the second single-ended input module 106 is, for example, a fifth auxiliary power supply, and the fifth auxiliary power supply may be the same as the first auxiliary power supply.

[0101] The second differential input module 107 has an eighth input terminal, a ninth input terminal and an eighth output terminal. The eighth input terminal is connected to the first terminal 201, and the ninth input terminal is connected to the second terminal 202. The eighth input terminal is used to receive the seventh differential signal, the ninth input terminal is used to receive the eighth differential signal, and the eighth output terminal is used to send the ninth differential signal to the first target device 501.

[0102] In the embodiment of the present application, the power supply of the second differential input module 107 is, for example, a sixth auxiliary power supply, and the sixth auxiliary power supply may be the same as the first auxiliary power supply.

[0103] In an IO BUF architecture that implements multiple operating modes, the embodiment of the present application specifically uses the second terminal 202 to directly connect the second single-ended output module 105 and the second single-ended input module 106, and uses the second terminal 202 and the first terminal 201 to directly connect the second differential input module 107. This shows that the present application can also be based on the specific connection method and overall architecture design of the first terminal 201 and the second terminal 202 respectively connected to the first single-ended output module 101, the first single-ended input module 102, the first differential input module 103, the first differential output module 104, the second single-ended output module 105, the second single-ended input module 106, and the second differential input module 107. While taking into account the single-ended output mode, the single-ended input mode, the differential output mode, and the differential input mode, the present application still only uses two terminals to connect to external devices, that is, only the first terminal 201 and the second terminal 202 serve as the physical connection terminals between the first target device and the second target device. This shows that compared with the simple superposition of various conventional designs, the present application has fewer terminals for external connections and a more reasonable overall architecture design.

[0104] As shown in FIG2 , and in combination with FIG1 , the input / output driver structure in one or more embodiments of the present application may further include:

[0105] The second differential output module 108 has a tenth input terminal, a ninth output terminal, and a tenth output terminal. The tenth input terminal is used to receive the tenth differential signal. The second differential output module 108 is used to differentially encode the tenth differential signal to obtain an eleventh differential signal and a twelfth differential signal. The ninth output terminal is connected to the first terminal 201, and the tenth output terminal is connected to the second terminal 202. The ninth output terminal is used to output the eleventh differential signal to the first terminal 201, and the tenth output terminal is used to output the twelfth differential signal to the second terminal 202.

[0106] Among them, the second differential output module 108 differentially encodes the tenth differential signal, and makes the eleventh differential signal and the tenth differential signal in phase, and the twelfth differential signal and the tenth differential signal in anti-phase. The differential encoding method can improve the signal anti-interference ability and is more suitable for long-distance signal transmission.

[0107] In the embodiment of the present application, the power supply of the second differential output module 108 is, for example, a second input-output power supply, and the second input-output power supply may be the same as the first input-output power supply.

[0108] The present application can also additionally add a second differential output module 108. This method not only enables the first differential output module 104 and the second differential output module 108 to work alternately, but also serves as redundancy when the first differential output module 104 fails, thereby ensuring differential output performance and improving the reliability of the product of the present application.

[0109] As shown in Figures 1 and 2, in some optional embodiments, the first single-ended output module 101 further has a first enable terminal, which is used to receive a first enable signal issued by the first target device 501, and the first enable signal is used to control whether the first single-ended output module 101 outputs the first single-ended signal processed by the first single-ended output module 101; wherein, the first enable terminal of this embodiment is an OE (Output Enable) terminal, and its function is to control the output state of the first single-ended output module 101 according to the first enable signal, and the output state may include outputting the processed first single-ended signal and not outputting. For example, when OE is high, the first single-ended output module 101 is in an enabled state and can output the internal signal to the corresponding pin. In other words, when OE is valid, the first single-ended output module 101 will output the corresponding signal to the IO pin according to the state of the input signal. In this embodiment, the IO pin is the first terminal; when OE is low, the first single-ended output module 101 is in a disabled state, and the internal signal will not be output to the pin. This situation is usually used when it is necessary to control the output of the signal. For example, at a specific time or under certain conditions, it is necessary to disable the output signal of a certain pin, which can be achieved by controlling the OE signal.

[0110] The second single-ended output module 105 further includes a second enable terminal for receiving a second enable signal transmitted by the second target device 502. The second enable signal is used to control whether the second single-ended output module 105 outputs the third single-ended signal processed by the second single-ended output module 105. The second enable terminal is also known as the OE (Output Enable) terminal, and its function is to control the output state of the second single-ended output module 105 based on the second enable signal. The output state can include outputting the processed third single-ended signal or not outputting the signal. The specific operating details are similar to those of the first enable terminal.

[0111] The present application can also control the enable state of the first single-ended output module 101 by sending a first enable signal to the first enable terminal or control the enable state of the second single-ended output module 105 by sending a second enable signal to the second enable terminal, thereby achieving effective control of the single-ended output function.

[0112] In some optional implementations, the first differential output module 104 is an LVDS output driver.

[0113] By using an LVDS (Low-Voltage Differential Signaling) output driver as the first differential output module 104, the present application can increase the data transmission rate in the differential output mode, improve the anti-interference ability, reduce the transmission power consumption, and realize the long-distance transmission function.

[0114] As shown in FIG. 1 to FIG. 5 , in some optional implementations, the input / output driver structure further includes a first hot-swap module 301 and a second hot-swap module 302 .

[0115] The first hot-swap module 301 has a first connection end, a second connection end, and a third connection end. The first connection end is connected to the first single-ended output module 101, the second connection end is connected to the first terminal 201, and the third connection end is connected to the second terminal 202. The first hot-swap module 301 is used to offset or absorb external input signals during hot-swap operations, and the external input signals come from the first terminal 201 and / or the second terminal 202. The first hot-swap module 301 of this embodiment is a hot-swap device used to protect integrated circuits and related devices from the influence of voltage peaks and current peaks that may be generated during hot-swap operations. Specifically, the hot-swap device includes electronic components for offsetting or absorbing voltage peaks and current peaks to effectively reduce impact and damage to the device. The hot-swap device can effectively extend the life of the device and improve the reliability of the entire device.

[0116] The second hot-swap module 302 has a fourth connection terminal, a fifth connection terminal, and a sixth connection terminal. The fourth connection terminal is connected to the second single-ended output module 105, the fifth connection terminal is connected to the second terminal 202, and the sixth connection terminal is connected to the first terminal 201. The second hot-swap module 302 is used to offset or absorb external input signals during hot-swap operations. The external input signals come from the first terminal 201 and / or the second terminal 202. The second hot-swap module 302 of this embodiment has similar functions and implementations to the first hot-swap module 301 and will not be further described here.

[0117] Among them, the power supply of the first hot-swappable module 301 is, for example, the fifth input-output power supply, which can be the same as the first input-output power supply; the power supply of the second hot-swappable module 302 is, for example, the sixth input-output power supply, which can be the same as the first input-output power supply.

[0118] The present application can protect the first single-ended output module 101, the first terminal 201 and the second terminal 202 through the first hot-swappable module 301, and protect the second single-ended output module 105, the first terminal 201 and the second terminal 202 through the second hot-swappable module 302, thereby effectively protecting the relevant electronic components inside the input and output driver structure of the present application.

[0119] As shown in FIG. 1 to FIG. 5 , in some optional implementations, the input / output driver structure further includes a first bus holding module 401 and a second bus holding module 402 .

[0120] Among them, the power supply of the first bus holding module 401 is, for example, the third input and output power supply, and the second input and output power supply can be the same as the first input and output power supply. The power supply of the second bus holding module 402 is, for example, the fourth input and output power supply, and the fourth input and output power supply can be the same as the first input and output power supply.

[0121] The first bus holding module 401 is connected to the first terminal 201 and is used to maintain the level state of the first terminal 201 in a non-driven state. The first bus holding module 401 of this embodiment is a bus holding device. The bus holding device can be used to implement a pull-up function and / or a pull-down function. For example, it may include but is not limited to a pull-up resistor and a power supply, or a pull-down resistor and a ground. When an IO pin (such as the first terminal 201) is not connected or has an invalid voltage, it avoids the generation of an uncertain signal. Specifically, when a signal is driven to the IO pin, the bus holding device is used to maintain the level until a new valid signal is updated. When the IO pin is not connected, level drift usually occurs. The bus holding device is used to prevent the impact of level drift on the internal circuit. The bus holding device can be used to make the IO pin have a higher anti-interference ability to avoid the impact of interference signals on input or output signals, thereby improving communication reliability. The bus holding device can also reduce power consumption in the invalid state, reducing useless power consumption of the device.

[0122] The second bus holding module 402 is connected to the second terminal 202 , and is configured to hold the level of the second terminal 202 in a non-driving state.

[0123] The present application can maintain a valid level state on the first terminal 201 when the first terminal 201 is not connected or an invalid voltage is input through the first bus holding module 401, and can maintain a valid level state on the second terminal 202 when the second terminal 202 is not connected or an invalid voltage is input through the second bus holding module 402, thereby improving the reliability of the operation of the present application.

[0124] In some optional implementations, the input / output driver structure is manufactured based on a FinFET process.

[0125] Among them, the Fin Field Effect Transistor (FinFET) process is a three-dimensional transistor structure and an advanced integrated circuit device manufacturing technology. Compared with traditional processes, it has better electrical performance and low power consumption.

[0126] For example, FinFET uses a thin-film transistor structure in a vertical direction. Compared with the traditional planar structure, FinFET has more control gate electrode surface area, thus providing better current control capability; because the control gate in FinFET surrounds the thin-film transistor (Fin) structure, electrons are better controlled when moving in the channel, which can reduce current leakage and improve the quality and efficiency of electron flow; FinFET has better current control capability, so it can achieve lower leakage current, thereby reducing static power consumption. In addition, FinFET can also achieve the same performance at a lower voltage, thereby reducing the dynamic power consumption of the device; FinFET process can achieve higher switching frequency, better high-frequency characteristics and shorter delay, which makes FinFET have advantages in applications requiring high performance and high-speed operation, such as communications, computers and mobile devices.

[0127] Under the FinFET process, high-speed IO BUFs (with a maximum speed of 2400Mbps) in related technologies only support an IO voltage range of 1.8V to 1.0V, while high-voltage IO BUFs (with a voltage range of 3.3V to 1.2V) often only achieve a transmission rate of 300Mbps. This results in related technologies being unable to address both the high speed and wide voltage requirements of IO BUFs under FinFET process nodes, resulting in compatibility issues between high speed and wide voltage for existing IO BUFs manufactured based on FinFET processes. The input / output driver structure manufactured based on the present application under the FinFET process, due to its overall input / output driver architecture design, implements a multi-mode IO BUF design, making it possible to design an IO BUF with both high speed and wide voltage characteristics. In multiple test results, the IO BUF manufactured based on the present application can achieve a maximum speed of 4200Mbps while operating within a voltage range of 3.3V to 1.0V, achieving an IO BUF design that balances high speed and wide voltage.

[0128] In particular, because transistors using the FinFET process need to operate at lower voltages, thereby achieving lower power consumption, the input / output driver structure provided in this application can be used to convert high-voltage input signals into low-voltage input signals, and convert low-voltage output signals into high-voltage output signals. Therefore, the input / output driver structure manufactured based on the FinFET process is applicable to a wide range of voltages. In specific experiments, the IO BUF provided in this application can operate at a high transmission rate within an IO voltage range of 3.3V to 1.0V.

[0129] The input-output driver structure provided in the present application can be adapted to the FinFET process, which has the characteristic of lower transistor operating voltage, so that the input-output driver structure can take into account the characteristics of small size, low power consumption, high frequency, high speed and wide voltage while being suitable for a variety of usage scenarios.

[0130] As shown in FIG4 , the input and output driver structure is integrated on a Field Programmable Gate Array (FPGA).

[0131] In this embodiment, the input / output driver manufactured based on the input / output driver structure can be used as an IP module and integrated on the FPGA.

[0132] Compared to the prior art, the present application can provide an FPGA including an IO BUF with a single-ended output working mode, a single-ended input working mode, a differential input working mode, and a differential output working mode.

[0133] As shown in FIG. 5 , the input and output driver structure in some embodiments of the present application is an independent module, that is, an independently set IO BUF.

[0134] In some optional implementations, the first terminal 201 and the second terminal 202 are both pads (PADs).

[0135] For example, the first terminal 201 is PAD A, and the second terminal 202 is PAD B.

[0136] The present application realizes the communication connection between the first single-ended output module 101, the first single-ended input module 102, the first differential input module 103, the first differential output module 104, the second single-ended output module 105, the second single-ended input module 106, the second differential input module 107 and the second target device 502 through the welding pad, thereby improving the reliability of the connection between different devices.

[0137] In some optional implementations, the first target device 501 is an IP core on a field programmable gate array; and the second target device 502 is an external device.

[0138] The IP core (Intellectual Property Core) of this embodiment specifically refers to a functional module or subsystem that has been designed and verified and can be implemented on an FPGA. The core on the FPGA is written in a hardware description language (such as Verilog or VHDL) and integrated into the logic unit of the FPGA to implement a specific function. External devices can be, for example, related devices in the fields of communications or industrial control, specifically sensors, displays, memory devices, motors, external interface devices, switches, buttons, servos, etc. Memory devices can include but are not limited to DDR3 (Double Data Rate 3, double data rate third generation memory), DDR4 (Double Data Rate 4, double data rate fourth generation memory), etc.

[0139] This application implements communication between an IP core on a field programmable gate array and external devices. Specifically, the IP core can communicate with the external device through at least one of a single-ended output mode, a single-ended input mode, a differential input mode, and a differential output mode. Furthermore, the IP core is a verified and tested functional module that can be reused across different projects and applications, saving development time and design resources and improving development efficiency. The IP core can be parameterized and configured to adapt to different requirements and specifications, and can be customized based on application requirements to achieve specific functions and performance. The programmability and flexibility of the IP core enable highly optimized circuit design, thereby providing better power consumption performance. The IP core can accelerate specific tasks through parallel processing and specialized hardware logic. Compared to solutions implemented using software, the IP core on the FPGA can provide higher computing efficiency and data throughput.

[0140] In the second aspect, the present application provides an input-output control method, which is applied to the input-output driver structure of the above-mentioned first aspect or any corresponding embodiment thereof, wherein the input-output driver structure has been described in detail in the aforementioned embodiments and will not be repeated here.

[0141] 1 to 5 , the input-output control method includes one or more of the following steps:

[0142] In the single-ended output working mode, the first single-ended signal is output to the second target device 502 through the first single-ended output module 101, and / or, the third single-ended signal is output to the second target device 502 through the second single-ended output module 105; in the single-ended input working mode, the second single-ended signal is input to the first target device 501 through the first single-ended input module 102, and / or, the fourth single-ended signal is input to the first target device 501 through the second single-ended input module 106; in the differential input working mode, the third differential signal obtained by differentially decoding the first differential signal and the second differential signal is input to the first target device 501 through the first differential input module 103, and / or, the ninth differential signal obtained by differentially decoding the seventh differential signal and the eighth differential signal is input to the first target device 501 through the second differential input module 107; in the differential output working mode, the fifth differential signal and the sixth differential signal obtained by differentially encoding the fourth differential signal are output to the second target device 502 through the first differential output module 104.

[0143] When the input-output driver structure includes the second differential output module 108, in the differential output working mode, the second differential output module 108 can also output the eleventh differential signal and the twelfth differential signal obtained by differentially encoding the tenth differential signal to the second target device 502.

[0144] Compared with the existing input and output control methods, the input and output control method of the present application can support single-ended output working mode, single-ended input working mode, differential input working mode and differential output working mode, so that the present application can use the corresponding working mode in different usage scenarios. When the scene changes, there is no need to replace the input and output driver structure, only the function needs to be switched based on the present application, thereby significantly reducing the user's investment cost and shortening the delivery time of input and output driver related projects.

[0145] As shown in Figure 3, Figure 4 or Figure 5, the present application provides a communication system, which includes an input-output driver manufactured based on the input-output driver structure of the above-mentioned first aspect or any corresponding embodiment; the communication system also includes but is not limited to a first target device 501 and a second target device 502.

[0146] The input and output driver structures have been described in detail in the aforementioned embodiments and will not be described again here.

[0147] In this embodiment, the first target device 501 communicates with the second target device 502 via an input / output driver, and the second target device 502 communicates with the second target device 502 via an input / output driver.

[0148] Specifically, the first terminal 201 on the input / output driver can be connected to the third terminal on the second target device 502 via a transmission line, and the second terminal 202 on the input / output driver can be connected to the fourth terminal on the second target device 502 via another transmission line.

[0149] The communication system in the present application can provide a switchable single-ended output working mode, a single-ended input working mode, a differential input working mode and a differential output working mode for the communication process between the first target device 501 and the second target device 502, so that the communication system of the present application can be applied to more scenarios.

[0150] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0151] In this application, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two elements or interaction between two elements, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0152] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement the hardware: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0153] In the description of this specification, the description with reference to the terms "this embodiment", "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are mutually inconsistent.

[0154] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0155] Although the embodiments of the present application have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations shall fall within the scope defined by the appended claims.

Claims

1. An input-output driver structure, characterized in that: include: A first single-ended output module, connected to the first terminal, the first single-ended output module is used to output a first single-ended signal sent by the first target device to the first terminal, and the first terminal is used to connect to the second target device; a first single-ended input module connected to the first terminal, the first single-ended input module being used to send a second single-ended signal input from the first terminal to the first target device, the second single-ended signal being sent by the second target device; a first differential input module, connected to the first terminal and the second terminal respectively, the first differential input module is used to differentially decode a first differential signal input from the first terminal and a second differential signal input from the second terminal, and to send a third differential signal obtained by differential decoding to the first target device, the first differential signal and the second differential signal are both sent by the second target device, and the second terminal is used to be connected to the second target device; a first differential output module, connected to the first terminal and the second terminal respectively, and configured to perform differential encoding on the fourth differential signal to obtain a fifth differential signal output through the first terminal and a sixth differential signal output through the second terminal; a second single-ended output module connected to the second terminal, the second single-ended output module being used to output a third single-ended signal emitted by the first target device to the second terminal, the second terminal being used to be connected to the second target device; a second single-ended input module connected to the second terminal, the second single-ended input module being used to send a fourth single-ended signal input from the second terminal to the first target device, the fourth single-ended signal being sent by the second target device; A second differential input module is connected to the first terminal and the second terminal respectively, and the second differential input module is used to differentially decode the seventh differential signal input from the first terminal and the eighth differential signal input from the second terminal, and to send the ninth differential signal obtained by the differential decoding to the first target device, and the seventh differential signal and the eighth differential signal are both sent by the second target device.

2. The input-output driver structure according to claim 1, characterized in that: The first single-ended output module has a first input end and a first output end, the first input end is used to receive the first single-ended signal, the first output end is used to output the first single-ended signal processed by the first single-ended output module, and the first output end is connected to the first terminal; The first single-ended input module has a second input end and a second output end, the second input end is used to receive the second single-ended signal, the second input end is connected to the first terminal, and the second output end is used to send out the second single-ended signal processed by the first single-ended input module; The first differential input module has a third input terminal, a fourth input terminal and a third output terminal, the third input terminal is connected to the first terminal, the fourth input terminal is connected to the second terminal, the third input terminal is used to receive the first differential signal, the fourth input terminal is used to receive the second differential signal, and the third output terminal is used to send the third differential signal to the first target device.

3. The input-output driver structure according to claim 2, characterized in that: The first differential output module has a fifth input terminal, a fourth output terminal and a fifth output terminal, the fifth input terminal is used to receive the fourth differential signal, the fourth output terminal is connected to the first terminal, the fifth output terminal is connected to the second terminal, the fourth output terminal is used to output the fifth differential signal to the first terminal, and the fifth output terminal is used to output the sixth differential signal to the second terminal.

4. The input-output driver structure according to claim 3, characterized in that: The second single-ended output module has a sixth input terminal and a sixth output terminal, and the sixth input terminal is used to receive the third single-ended signal. The sixth output terminal is used to output the third single-ended signal processed by the second single-ended output module, and the sixth output terminal is connected to the second terminal; The second single-ended input module has a seventh input end and a seventh output end, the seventh input end is used to receive the fourth single-ended signal, the seventh input end is connected to the second terminal, and the seventh output end is used to send out the fourth single-ended signal processed by the second single-ended input module; The second differential input module has an eighth input terminal, a ninth input terminal and an eighth output terminal, the eighth input terminal is connected to the first terminal, the ninth input terminal is connected to the second terminal, the eighth input terminal is used to receive the seventh differential signal, the ninth input terminal is used to receive the eighth differential signal, and the eighth output terminal is used to send the ninth differential signal to the first target device.

5. The input-output driver structure according to claim 4, characterized in that: Also includes: The second differential output module has a tenth input terminal, a ninth output terminal and a tenth output terminal, the tenth input terminal is used to receive the tenth differential signal, the second differential output module is used to differentially encode the tenth differential signal to obtain an eleventh differential signal and a twelfth differential signal, the ninth output terminal is connected to the first terminal, the tenth output terminal is connected to the second terminal, the ninth output terminal is used to output the eleventh differential signal to the first terminal, and the tenth output terminal is used to output the twelfth differential signal to the second terminal.

6. The input-output driver structure according to claim 4, characterized in that: The first single-ended output module further has a first enable terminal, the first enable terminal is used to receive a first enable signal sent by the first target device, and the first enable signal is used to control whether the first single-ended output module outputs the first single-ended signal processed by the first single-ended output module; The second single-ended output module also has a second enable terminal, which is used to receive a second enable signal sent by the second target device, and the second enable signal is used to control whether the second single-ended output module outputs the third single-ended signal processed by the second single-ended output module.

7. The input-output driver structure according to claim 1, characterized in that: The first differential output module is a LVDS output driver.

8. The input-output driver structure according to claim 1, characterized in that: Also includes: A first bus holding module, connected to the first terminal, and configured to hold a level state of the first terminal in a non-driving state; The second bus holding module is connected to the second terminal, and is used for holding the level state of the second terminal in a non-driving state.

9. The input-output driver structure according to any one of claims 1 to 8, characterized in that: Also includes: A first hot-swap module, comprising a first connection end, a second connection end and a third connection end, wherein the first connection end is connected to the first single-ended output module, the second connection end is connected to the first terminal, and the third connection end is connected to the second terminal; the first hot-swap module is used to offset or absorb an external input signal during a hot-swap operation, wherein the external input signal comes from the first terminal and / or the second terminal; The second hot-swap module has a fourth connection end, a fifth connection end and a sixth connection end, the fourth connection end is connected to the second single-ended output module, the fifth connection end is connected to the second terminal, and the sixth connection end is connected to the first terminal; the second hot-swap module is used to offset or absorb external input signals during hot-swap operations, and the external input signals come from the first terminal and / or the second terminal.

10. The input-output driver structure according to claim 1, characterized in that: The input-output driver structure is manufactured based on the FinFET process.

11. The input-output driver structure according to claim 1 or 10, characterized in that: The input-output driver structure is integrated on a field programmable gate array.

12. The input-output driver structure according to claim 1, characterized in that: The first terminal and the second terminal are both welding pads.

13. The input-output driver structure according to claim 1, characterized in that: The first target device is an IP core on a field programmable gate array; The second target device is an external device.

14. An input-output control method, characterized in that: The method is applied to the input-output driver structure according to any one of claims 1 to 13, and the method comprises: In the single-ended output working mode, outputting a first single-ended signal to a second target device through a first single-ended output module, and / or outputting a third single-ended signal to the second target device through a second single-ended output module; In the single-ended input working mode, a second single-ended signal is input to the first target device through the first single-ended input module, and / or a fourth single-ended signal is input to the first target device through the second single-ended input module, In the differential input working mode, a third differential signal obtained by differentially decoding the first differential signal and the second differential signal is input to the first target device through the first differential input module, and / or a ninth differential signal obtained by differentially decoding the seventh differential signal and the eighth differential signal is input to the first target device through the second differential input module; In the differential output working mode, the fifth differential signal and the sixth differential signal obtained by differentially encoding the fourth differential signal are output to the second target device through the first differential output module.

15. A communication system, characterized in that: The communication system comprises an input-output driver manufactured based on the input-output driver structure according to any one of claims 1 to 13; the communication system further comprises a first target device and a second target device: The first target device communicates with the second target device via the input-output driver; The second target device communicates with the second target device through the input / output driver.

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