Solar cell and preparation method therefor

Abstract

A solar cell and a preparation method therefor. The preparation method comprises the following steps: preparing a first doped crystalline silicon layer and a second doped crystalline silicon layer on a front surface and a back surface of a silicon substrate, respectively; preparing a first transparent conductive layer on the first doped crystalline silicon layer, the first transparent conductive layer comprising an AZO material and an FTO material; and sequentially preparing a second transparent conductive layer and a third transparent conductive layer on the second doped crystalline silicon layer, the second transparent conductive layer comprising a VTTO material, and the third transparent conductive layer comprising an IWO material.

Description

Solar cell and preparation method thereof

[0001] Related applications

[0002] This application claims priority to Chinese patent application number 2023111645485, filed on September 8, 2023, entitled “Solar Cell and Method for Making Same,” the entire text of which is hereby incorporated by reference. Technical Field

[0003] The present application relates to the field of photovoltaic technology, and in particular to a solar cell and a method for preparing the same. Background Art

[0004] With the development of photovoltaic technology, solar cells, characterized by their simple structure and ability to be deposited over large areas, have gradually gained popularity. The doped crystalline silicon layers on both the front and back sides of the solar cell require the deposition of corresponding coatings to enhance the photovoltaic performance of the solar cell. However, the manufacturing process for these coatings is difficult to match that of the doped crystalline silicon layer, resulting in reduced absorption, electrical properties, and stability of the doped crystalline silicon layer.

[0005] Summary of the Invention

[0006] In a first aspect, the present application provides a method for preparing a solar cell, the method comprising the following steps: preparing a first doped crystalline silicon layer and a second doped crystalline silicon layer on the front and back sides of a silicon substrate, respectively; preparing a first transparent conductive layer on the first doped crystalline silicon layer, the first transparent conductive layer comprising an AZO material and an FTO material; and sequentially preparing a second transparent conductive layer and a third transparent conductive layer on the second doped crystalline silicon layer, the second transparent conductive layer comprising a VTTO material, and the third transparent conductive layer comprising an IWO material.

[0007] In one embodiment, the step of forming a first transparent conductive layer on the first doped crystalline silicon layer includes:

[0008] A first sublayer, a second sublayer and a third sublayer are sequentially prepared on the first doped crystalline silicon layer, wherein the first sublayer comprises AZO material, the second sublayer comprises AZO material and FTO material, and the third sublayer comprises FTO material.

[0009] In one embodiment, the second sub-layer is prepared by simultaneously magnetron sputtering an AZO target and a FTO target.

[0010] In one embodiment, the thickness of the second sub-layer is 3 nm to 7 nm.

[0011] In one embodiment, the third transparent conductive layer further comprises an ITO material, and the steps of sequentially preparing the second transparent conductive layer and the third transparent conductive layer on the second doped crystalline silicon layer include:

[0012] A second transparent conductive layer, a fourth sublayer and a fifth sublayer are sequentially prepared on the second doped crystalline silicon layer, wherein the fourth sublayer comprises an IWO material, and the fifth sublayer comprises an ITO material.

[0013] In one embodiment, the thickness of the fourth sublayer is 2 nm to 3 nm.

[0014] In one embodiment, the preparation method comprises the following steps:

[0015] S1, forming the first doped crystalline silicon layer and the second doped crystalline silicon layer on the front side and the back side of the silicon substrate respectively;

[0016] S2. forming the second transparent conductive layer on the second doped crystalline silicon layer;

[0017] S3, forming a first transparent conductive layer on the first doped crystalline silicon layer;

[0018] S4. Prepare the third transparent conductive layer on the second transparent conductive layer.

[0019] In one embodiment, the preparation method further includes: preparing a fourth transparent conductive layer on the first transparent conductive layer, wherein the fourth transparent conductive layer includes a VTTO material.

[0020] In one embodiment, the preparation method further comprises: before preparing the first doped crystalline silicon layer and the second doped crystalline silicon layer, texturing the silicon substrate;

[0021] A first intrinsic layer is prepared on the front side of the silicon substrate after texturing, and a second intrinsic layer is prepared on the back side of the silicon substrate, wherein the first intrinsic layer is located between the silicon substrate and the first doped crystalline silicon layer, and the second intrinsic layer is located between the silicon substrate and the second doped crystalline silicon layer.

[0022] In one embodiment, the preparation method further includes: after the steps of sequentially preparing a second transparent conductive layer and a third transparent conductive layer on the second doped crystalline silicon layer, post-processing to produce an electrode so that the electrode forms an ohmic contact with the third transparent conductive layer.

[0023] In a second aspect, the present application further provides a solar cell, which is prepared by the preparation method described in the first aspect.

[0024] In one embodiment, the solar cell comprises:

[0025] Silicon substrate;

[0026] A first doped crystalline silicon layer and a first transparent conductive layer are sequentially stacked on the front surface of the silicon substrate;

[0027] A second doped crystalline silicon layer, a second transparent conductive layer and a third transparent conductive layer are sequentially stacked on the back side of the silicon substrate.

[0028] In one embodiment, the solar cell further includes a fourth transparent conductive layer stacked on the first transparent conductive layer.

[0029] In one embodiment, the solar cell further includes a first intrinsic layer and a second intrinsic layer, wherein the first intrinsic layer is stacked between the silicon substrate and the first doped crystalline silicon layer, and the second intrinsic layer is stacked between the silicon substrate and the second doped crystalline silicon layer;

[0030] and an electrode, wherein the electrode is in ohmic contact with the third transparent conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the disclosed drawings without any creative work.

[0032] FIG1 is a flow chart of a method for preparing a solar cell provided in some embodiments of the present application.

[0033] FIG2 is a schematic diagram of the structure of a solar cell provided in some embodiments of the present application.

[0034] Explanation of the accompanying reference numerals: 100, solar cell; 101, silicon substrate; 102, first intrinsic layer; 103, first doped crystalline silicon layer; 104, first transparent conductive layer; 1041, first sublayer; 1042, second sublayer; 1043, third sublayer; 105, fourth transparent conductive layer; 106, second intrinsic layer; 107, second doped crystalline silicon layer; 108, second transparent conductive layer; 109, third transparent conductive layer; 1091, fourth sublayer; 1092, fifth sublayer; 110, electrode. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0036] The technical solution of the present invention will be described in detail below with reference to the embodiments:

[0037] In a first aspect, the present application provides a method for fabricating a solar cell. In some embodiments, the method includes the following steps: forming a first doped crystalline silicon layer and a second doped crystalline silicon layer on the front and back sides of a silicon substrate, respectively; forming a first transparent conductive layer on the first doped crystalline silicon layer, the first transparent conductive layer comprising an AZO material and an FTO material; and sequentially forming a second transparent conductive layer and a third transparent conductive layer on the second doped crystalline silicon layer, the second transparent conductive layer comprising a VTTO material and the third transparent conductive layer comprising an IWO material. The fabrication method of this embodiment makes each transparent conductive layer compatible with the doped crystalline silicon layer, thereby improving the matching between the transparent conductive layer and the doped crystalline silicon layer, thereby further matching the preparation process of the transparent conductive layer with the doped crystalline silicon layer, thereby improving the light absorption performance, electrical properties, and stability of the doped crystalline silicon layer.

[0038] The AZO material used in the embodiments of this application refers to aluminum-doped zinc oxide (ZnO:Al). The FTO material refers to fluorine-doped tin dioxide (SnO2:F). The VTTO material refers to tin-doped indium oxide (In2O3:Sn), where the mass ratio of indium oxide to tin is greater than or equal to 99:1. The IWO material refers to tungsten-doped indium oxide (In2O3:W). The ITO material refers to tin-doped indium oxide (In2O3:Sn), where the mass ratio of indium oxide to tin is 97:3.

[0039] In this embodiment, the front side refers to the light incident side, and the back side refers to the backlight side. The silicon substrate can be an N-type silicon wafer or a P-type silicon wafer. The doped crystalline silicon layer can be an N-type amorphous silicon layer, an N-type microcrystalline silicon layer, a P-type amorphous silicon layer, a P-type microcrystalline silicon layer, or the like. For example, when the silicon substrate is an N-type silicon wafer, the doped crystalline silicon layer can be an N-type microcrystalline silicon layer. Alternatively, the doped crystalline silicon layer can be an N-type amorphous silicon layer.

[0040] The first and second doped crystalline silicon layers are both doped microcrystalline silicon layers. Compared to doped amorphous silicon layers, which only absorb low-wavelength visible light, doped microcrystalline silicon has an optical bandgap closer to that of single-crystalline silicon, extending its spectral response into the infrared and absorbing long-wavelength sunlight. Furthermore, the doped microcrystalline silicon layer can be stacked with an intrinsic amorphous silicon layer as the absorption layer of a solar cell, further enhancing the solar cell's light absorption performance.

[0041] This embodiment does not limit the preparation method of each film layer, and the film layers may be prepared by chemical vapor deposition, spray pyrolysis, sol-gel method, magnetron sputtering method, etc.

[0042] This embodiment also does not limit the specific preparation order of the first transparent conductive layer, the second transparent conductive layer, and the third transparent conductive layer. For example, in some embodiments, the preparation order is: first, the first transparent conductive layer is prepared on the first doped crystalline silicon layer, then the second transparent conductive layer is prepared on the second doped crystalline silicon layer, and then the third transparent conductive layer is prepared on the second transparent conductive layer. In other embodiments, the preparation order is: first, the second transparent conductive layer is prepared on the second doped crystalline silicon layer, then the third transparent conductive layer is prepared on the second transparent conductive layer, and then the first transparent conductive layer is prepared on the first doped crystalline silicon layer. In still other embodiments, the preparation order is: first, the second transparent conductive layer is prepared on the second doped crystalline silicon layer, then the first transparent conductive layer is prepared on the first doped crystalline silicon layer, and then the third transparent conductive layer is prepared on the second transparent conductive layer. First, the second transparent conductive layer is prepared on the second doped crystalline silicon layer, then the first transparent conductive layer is prepared on the first doped crystalline silicon layer, and then the third transparent conductive layer is prepared on the second transparent conductive layer. In order to increase the light absorption on the front side of the solar cell, the gate line is set on the back side of the solar cell to increase the front side illumination area. After the grid lines are installed on the back side, the interaction factor between the grid lines and the back side film layer is greater than the interaction factor between the front side film layers. Therefore, the preparation of the back side film layer will have a greater impact on the solar cell. In order to reduce the impact of film preparation on solar cell performance, the preparation of the transparent conductive layer on the back side of the solar cell is first considered.

[0043] Furthermore, the incident light intensity on the back of the solar cell is not as high as that on the front. In order to maximize the light absorption on the back within the limited illumination, a material with high carrier mobility is selected to prepare the transparent conductive layer so that the limited photogenerated carriers on the back can be converted into electrical energy as much as possible. The IWO material has high carrier mobility and high long-wave transmittance, which can achieve a higher open-circuit voltage. However, the introduction of the IWO transparent conductive layer will cause the back film layer and the doped crystalline silicon layer, and the back film layer and the gate line to become extremely sensitive, which is not conducive to the stability of the back film layer structure. Therefore, it is necessary to set a neutralizing film layer between the IWO transparent conductive layer and the doped crystalline silicon layer to take into account the high carrier mobility and other characteristics of the IWO transparent conductive layer, while reducing the impact of the IWO transparent conductive layer on the doped crystalline silicon layer and the back gate line, thereby improving the stability of the back film layer structure.

[0044] The VTTO transparent conductive layer has a high indium content, good crystal structure stability, excellent film quality, and better matching with the doped crystalline silicon layer and the intrinsic layer. At the same time, the VTTO transparent conductive layer can make the film layer in contact with it have a stronger quantum mechanical effect, allowing more photogenerated carriers to tunnel and achieve better electrical energy diversion and conversion. The VTTO transparent conductive layer is compatible with the doped crystalline silicon layer and the IWO transparent conductive layer. While ensuring the stability of the back film structure, it can effectively improve the carrier mobility, thereby improving the electrical performance of the back of the solar cell. Therefore, the preparation method of the embodiment of the present application first prepares a second transparent conductive layer including VTTO material on the second doped crystalline silicon layer on the back of the silicon substrate.

[0045] After the second transparent conductive layer is prepared, it is not suitable to directly prepare the IWO transparent conductive layer. This is because the VTTO material in the first transparent conductive layer that has just been prepared has highly active indium, which is easy to mix and dope with the IWO material, affecting both the matching of the first transparent conductive layer and the doped crystalline silicon layer and the preparation of the IWO transparent conductive layer.

[0046] When preparing film layers for solar cells, stability is a priority. Preparing a film layer with excellent stability first is conducive to better exerting the performance of subsequent film layers and maximizing the performance of the solar cell. Therefore, it is necessary to prepare a relatively stable film layer on the front side of the solar cell as early as possible. The first transparent conductive layer prepared by AZO material and FTO material has good chemical stability and thermodynamic stability, and the film layer quality is high, which is suitable for priority preparation as a basic film layer to further improve the efficiency of the solar cell. In addition, the first transparent conductive layer prepared by AZO material and FTO material has high transmittance and low resistivity, and can effectively absorb more incident light on the basis of increasing the incident area of ​​​​the front light. It should be noted that during the growth process of the VTTO transparent conductive layer, AZO material and FTO material are easy to penetrate and mix with the VTTO material, resulting in overlap or intersection between the film layers on the front and back, affecting the overall performance and stability of the solar cell. Therefore, in order to prevent the presence of AZO material and FTO material from interfering with the VTTO transparent conductive layer, it is necessary to prepare AZO and FTO transparent conductive layers after the preparation of the VTTO transparent conductive layer is completed. Therefore, based on the consideration of the above multiple factors, taking into account the influence between the front and back film layer structures and improving the photoelectric performance of the front and back surfaces at the same time, the preparation method of this embodiment is to prepare a first transparent conductive layer including AZO material and FTO material on the first doped crystalline silicon layer on the front side of the silicon substrate.

[0047] In some embodiments, the step of forming a first transparent conductive layer on the first doped crystalline silicon layer includes: sequentially forming a first sublayer, a second sublayer, and a third sublayer on the first doped crystalline silicon layer, wherein the first sublayer comprises an AZO material, the second sublayer comprises an AZO material and an FTO material, and the third sublayer comprises an FTO material. The second sublayer is provided as a sandwich layer, which can serve as a buffer layer between the first sublayer and the third sublayer, reducing the difference between the AZO material and the FTO material, further improving the light absorption performance of the first transparent conductive layer, and reducing the resistivity.

[0048] In some embodiments, by simultaneously magnetron sputtering an AZO target and an FTO target to prepare the second sublayer, atomic penetration of the AZO material and the FTO material can be achieved during the thin film preparation process, thereby better achieving compatibility and complementarity in the performance of the AZO material and the FTO material.

[0049] In some embodiments, the thickness of the second sublayer is 3nm to 7nm. Simultaneous magnetron sputtering of AZO and FTO targets is used to prepare the second sublayer as an ultra-thin layer, resulting in an ultra-thin film. This further improves the contact between the first and third sublayers, shortens the carrier migration path, and improves carrier migration efficiency. For example, the thickness of the second sublayer can be any value within the above range, such as 3nm, 3.5nm, 4nm, 4.5nm, 5nm, 5.5nm, 6nm, 6.5nm, 7nm, etc.

[0050] Furthermore, after the first transparent conductive layer is prepared, the VTTO material in the second transparent conductive layer on the back becomes stable after a period of deposition, and the activity of the indium element is maintained at a relatively stable level. At this time, a third transparent conductive layer including IWO material can be prepared on the second transparent conductive layer.

[0051] In some embodiments, the third transparent conductive layer further comprises an ITO material, and the third transparent conductive layer comprises a fourth sublayer and a fifth sublayer, wherein the fourth sublayer comprises an IWO material and the fifth sublayer comprises an ITO material. The fifth sublayer can establish an ohmic contact with the gate line. Providing the fifth sublayer can enhance the contact ductility with the gate line and match the seed layer technology and patterning technology.

[0052] In some embodiments, the thickness of the fourth sublayer is 2nm to 3nm. Exemplarily, the thickness of the fourth sublayer may be any value within the above range, for example, 2nm, 2.1nm, 2.2nm, 2.3nm, 2.4nm, 2.5nm, 2.6nm, 2.7nm, 2.8nm, 2.9nm, 3nm, etc. Since the IWO material has high transmittance to long waves, setting the thickness of the first transparent conductive layer to 2nm to 3nm can capture more long waves and provide a shorter migration channel to further assist carrier migration. As a sandwich layer between the VTTO layer and the ITO layer, the IWO layer can not only provide ultra-high carrier mobility, but also will not affect the tension coefficient and stability between the ITO layer and the back gate line. The thickness of the fifth sublayer is 20nm to 30nm. Thinning the fifth sublayer can reduce the use of indium elements. Illustratively, the thickness of the fifth sublayer may be any value within the above range, for example, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, etc.

[0053] However, setting the IWO layer as an ultra-thin film makes it easy for it to interact with other film layers. In order to reduce the influence of the high long-wave transmittance of the IWO layer on the transmittance of the entire film layer, the IWO layer and the ITO layer are prepared simultaneously without affecting the VTTO layer. The ITO layer has a lower long-wave transmittance. Slight atomic penetration occurs at the edge of the inner thin surface of the IWO layer and the ITO layer, which can reduce the influence of the long-wavelength transmittance of the IWO layer.

[0054] After the first transparent conductive layer is prepared, the AZO and FTO materials have high activity after high-temperature sputtering, and FTO is easier to etch. The newly prepared second transparent conductive layer is prone to interaction with other film layers. Therefore, it is not suitable to immediately prepare other front film layers on the first transparent conductive layer after the second transparent conductive layer is prepared. After the third transparent conductive layer is prepared, the activity of the AZO and FTO materials in the first transparent conductive layer tends to stabilize. At this time, a fourth transparent conductive layer including VTTO material can be prepared on the first transparent conductive layer. The fourth transparent conductive layer can be prepared using an ultra-thin process.

[0055] Furthermore, in some embodiments, the preparation method of the present application also includes the following steps: texturing the silicon substrate before preparing the first doped crystalline silicon layer and the second doped crystalline silicon layer; and preparing the first intrinsic layer on the front of the silicon substrate after texturing, and preparing the second intrinsic layer on the back of the silicon substrate. Texturing the surface of the silicon substrate to form a pyramid-shaped velvet structure can improve light absorption. The first intrinsic layer and the second intrinsic layer refer to intrinsic amorphous silicon layers, which can better match the VTTO layer and improve the passivation effect of the solar cell. At the same time, the first intrinsic layer and the second intrinsic layer can be doped with oxygen to reduce light absorption, increase the open circuit voltage and carrier mobility.

[0056] Therefore, the preparation method of the present application includes the following steps: texturing a silicon substrate, preparing a first intrinsic layer on the front side of the texturized silicon substrate, preparing a second intrinsic layer on the back side of the silicon substrate, preparing a first doped crystalline silicon layer on the first intrinsic layer, and preparing a second doped crystalline silicon layer on the second intrinsic layer. Referring to FIG1 , first, a second transparent conductive layer (VTTO layer) is prepared on the second doped crystalline silicon layer, then a first transparent conductive layer (AZO, FTO mixed layer) is prepared on the first doped crystalline silicon layer, then a third transparent conductive layer (IWO layer and ITO layer) is prepared on the second transparent conductive layer, then a fourth transparent conductive layer (VTTO layer) is prepared on the first transparent conductive layer, and then post-processing is performed to prepare electrodes so that the electrodes form ohmic contact with the third transparent conductive layer (ITO layer), thereby completing the preparation of the solar cell.

[0057] The preparation sequence of this embodiment has the following advantages: it not only reduces the mutual influence between the front and back film layers, but also fully utilizes the advantages of each film layer. It reduces the influence of the front AZO and FTO layers on the doped crystalline silicon layer and the back VTTO layer, and reduces the influence of the back IWO layer on the doped crystalline silicon layer and the back VTTO layer, and fully preserves the matching of the doped crystalline silicon layer and the VTTO layer. Therefore, the preparation sequence of this embodiment can fully match the preparation process of the transparent conductive layer with the preparation process of the doped amorphous silicon layer, and can ensure that the transparent conductive layers on the front and back of the solar cell do not interfere with each other when preparing them, and can complement each other's advantages, greatly improving the photoelectric conversion efficiency of the solar cell.

[0058] In a second aspect, an embodiment of the present application further provides a solar cell, which is prepared by the preparation method of the first aspect. This embodiment does not limit the specific type of solar cell. For example, the solar cell may be a heterojunction solar cell, a back contact solar cell, etc.

[0059] In some embodiments, the solar cell includes a silicon substrate; a first intrinsic layer, a first doped crystalline silicon layer, a first transparent conductive layer, and a fourth transparent conductive layer sequentially stacked on the front surface of the silicon substrate; and a second intrinsic layer, a second doped crystalline silicon layer, a second transparent conductive layer, and a third transparent conductive layer sequentially stacked on the back surface of the silicon substrate, wherein the third transparent conductive layer is in ohmic contact with the electrode. This structure has been described in detail in the solar cell fabrication method described in the first aspect and will not be repeated here.

[0060] The technical solution of this application will be further introduced below with reference to specific embodiments and comparative examples:

[0061] Example 1

[0062] 2 , this embodiment provides a heterojunction solar cell 100, which includes: a silicon substrate 101; and a first intrinsic layer 102, a first doped crystalline silicon layer 103, a first transparent conductive layer 104, and a fourth transparent conductive layer 105 stacked sequentially on the front surface of the silicon substrate 101, wherein the first transparent conductive layer 104 includes a first sublayer 1041, a second sublayer 1042, and a third sublayer 1043 stacked sequentially; and a second intrinsic layer 106, a second doped crystalline silicon layer 107, a second transparent conductive layer 108, and a third transparent conductive layer 109 stacked sequentially on the back surface of the silicon substrate 101, wherein the third transparent conductive layer 109 includes a fourth sublayer 1091 and a fifth sublayer 1092, and the fifth sublayer 1092 is in ohmic contact with the electrode 110.

[0063] Among them, the silicon substrate 101 is an N-type silicon wafer; the first intrinsic layer 102 and the second intrinsic layer 106 are intrinsic amorphous silicon layers; the first doped crystalline silicon layer 103 and the second doped crystalline silicon layer 107 are N-type doped microcrystalline silicon layers; the first sublayer 1041 of the first transparent conductive layer 104 is an AZO layer, the second sublayer 1042 is an AZO and FTO mixed layer, the thickness of the second sublayer 1042 is 5 nm, and the third sublayer 1043 is an FTO layer; the fourth transparent conductive layer 105 is a VTTO layer; the second transparent conductive layer 108 is a VTTO layer; the fourth sublayer 1091 of the third transparent conductive layer 109 is an IWO layer, the thickness of the fourth sublayer 1091 is 2.5 nm, and the fifth sublayer 1092 is an ITO layer; the electrode 110 is a copper electrode.

[0064] This embodiment also provides a method for preparing a solar cell, which comprises the following steps:

[0065] S1, texturing the N-type silicon wafer;

[0066] S2, depositing an intrinsic amorphous silicon layer on the light incident surface and the backlight surface of the N-type silicon wafer after texturing;

[0067] S3, depositing a first doped crystalline silicon layer on the intrinsic amorphous silicon layer on the light incident side, and depositing a second doped crystalline silicon layer on the intrinsic amorphous silicon layer on the backlight side, wherein the first doped crystalline silicon layer and the second doped crystalline silicon layer are doped microcrystalline silicon layers;

[0068] S4, depositing a second transparent conductive layer on the second doped crystalline silicon layer, where the second transparent conductive layer is a VTTO layer;

[0069] S5, preparing a first transparent conductive layer on the first doped crystalline silicon layer, sequentially performing the following steps: depositing a first sublayer, simultaneously magnetron sputtering an AZO target and an FTO target to deposit a second sublayer and a third sublayer, and depositing the third sublayer; the first sublayer is an AZO layer, the second sublayer is a mixed layer of AZO and FTO, and the third sublayer is an FTO layer;

[0070] S6, depositing a third transparent conductive layer on the second transparent conductive layer, sequentially depositing the fourth sublayer and the fifth sublayer, wherein the fourth sublayer is an IWO layer and the fifth sublayer is an ITO layer;

[0071] S7, forming a fourth transparent conductive layer on the first transparent conductive layer, wherein the fourth transparent conductive layer is a VTTO layer;

[0072] S8. Fabricate a copper electrode on the fifth sub-layer.

[0073] Example 2

[0074] Example 2 provides a heterojunction solar cell and a preparation method thereof. Compared with Example 1, Example 2 places S4 between S5 and S6, and the rest of the method remains the same as Example 1.

[0075] Example 3

[0076] Example 3 provides a heterojunction solar cell and a preparation method thereof. Compared with Example 1, Example 3 places S6 between S4 and S5, and the rest remains the same as Example 1.

[0077] Example 4

[0078] The fourth embodiment provides a heterojunction solar cell and a preparation method thereof. Compared with the first embodiment, the fourth embodiment places S7 between S5 and S6, and the rest of the embodiment remains the same as the first embodiment.

[0079] Example 5

[0080] Example 5 provides a heterojunction solar cell and a preparation method thereof. Compared with Example 1, the order of S4 to S7 in Example 5 is S4, S6, S5, S7, and the rest remains the same as Example 1.

[0081] Example 6

[0082] Example 6 provides a heterojunction solar cell and a preparation method thereof. Compared with Example 1, the order of S4 to S7 in Example 6 is S5, S7, S4, S6, and the rest remains consistent with Example 1.

[0083] Example 7

[0084] Example 7 provides a heterojunction solar cell and a preparation method thereof. Compared with Example 1, Example 7 does not provide a second sublayer including AZO material and FTO material, and the rest is consistent with Example 1.

[0085] Example 8

[0086] The eighth embodiment provides a heterojunction solar cell and a preparation method thereof. Compared with the first embodiment, the first doped crystalline silicon layer and the second doped crystalline silicon layer in the eighth embodiment are doped amorphous silicon layers.

[0087] Example 9

[0088] Example 9 provides a heterojunction solar cell and a preparation method thereof. Example 10 is compared with Example 1. The thickness of the fourth sublayer of Example 9 is 5 nm.

[0089] Comparative Example 1

[0090] Comparative Example 1 provides a heterojunction solar cell and a preparation method thereof. Compared with Example 1, the second transparent conductive layer of Comparative Example 1 does not include VTTO material, and the rest is consistent with Example 1.

[0091] Comparative Example 2

[0092] Comparative Example 2 provides a heterojunction solar cell and a preparation method thereof. Compared with Example 1, the first transparent conductive layer of Comparative Example 2 does not include AZO material and FTO material, and the rest is consistent with Example 1.

[0093] Comparative Example 3

[0094] Comparative Example 3 provides a heterojunction solar cell and a preparation method thereof. Compared with Example 1, the third transparent conductive layer of Comparative Example 3 does not include IWO material, and the rest is consistent with Example 1.

[0095] Performance Testing

[0096] The solar cells provided in the Examples and Comparative Examples of this application were subjected to Auger recombination testing and performance testing of open-circuit voltage, short-circuit current, and fill factor using a Halm test and sorting device. The Halm machine is a device that simulates sunlight and is equipped with an electronic load, data acquisition, and computing equipment to test the electrical properties of photovoltaic devices (including solar cells), such as Eta, Voc, A, and FF, which are used to reflect the performance of solar cells. The silicon wafers used for the control tests were 182-inch in size and the calibrated light intensity was 1000±50W / m2. The experimental test results are as follows, where Eta represents Auger recombination, Voc represents open-circuit voltage, A represents short-circuit current, and FF represents fill factor.

[0097] Table 1. Performance test results of solar cells

[0098] Performance Analysis:

[0099] Compared with Example 1, the front preparation of Example 2 will affect the performance of the back VTTO film layer and have a greater impact on the fill factor.

[0100] Compared with Example 1, in Example 3, the preparation sequence of the back side affects the performance of the front VTTO film layer and has a greater impact on the short-circuit current.

[0101] Compared with Example 1, in Example 4, since the VTTO film layer is prepared on the front side first, the preparation of the IWO film layer on the back side may affect the preparation of the VTTO film layer on the front side, thereby causing the current to be lower, but the impact is relatively small.

[0102] Compared with Example 1, Example 5 adopts the preparation order of preparing all the film layers on the back first and then preparing all the film layers on the front. The efficiency of the front and back of the solar cell are affected, and the short-circuit current, open-circuit voltage and fill factor are all lower.

[0103] Compared with Example 1, Example 6 adopts the preparation order of preparing all the film layers on the front side first and then preparing all the film layers on the back side, and the short-circuit current, open-circuit voltage and fill factor are all lower.

[0104] Compared with the first embodiment, the second sub-layer including the FTO material and the AZO material is not provided in the seventh embodiment, and the effect of improving the filling factor is not as good as that of the first embodiment.

[0105] Compared with the first embodiment, the first embodiment adopts a doped microcrystalline silicon layer, while the eighth embodiment adopts a doped amorphous silicon layer. The doped microcrystalline silicon layer has better matching performance with the transparent conductive layer, and the performance of the solar cell is better.

[0106] Compared with the first embodiment, the thickness of the IWO layer in the ninth embodiment is thicker, which causes the long-wave light transmittance to change, and the efficiency is lower than that of the first embodiment.

[0107] Compared with Example 1, the second transparent conductive layer of Comparative Example 1 does not include VTTO material, so the IWO film layer directly contacts the microcrystalline layer, and the ITO film thickness is insufficient, which greatly affects the efficiency.

[0108] Compared with Example 1, the first transparent conductive layer of Comparative Example 2 does not include AZO material and FTO material, and the chemical stability and thermodynamic stability of the solar cell are reduced, the film quality is reduced, and the efficiency is reduced.

[0109] Compared with Example 1, the third transparent conductive layer of Comparative Example 3 does not include the IWO material, which reduces the light transmittance of the solar cell and reduces the efficiency.

[0110] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0111] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for preparing a solar cell, characterized in that: The preparation method comprises the following steps: A first doped crystalline silicon layer and a second doped crystalline silicon layer are respectively prepared on the front side and the back side of the silicon substrate; Preparing a first transparent conductive layer on the first doped crystalline silicon layer, wherein the first transparent conductive layer comprises AZO material and FTO material; A second transparent conductive layer and a third transparent conductive layer are sequentially prepared on the second doped crystalline silicon layer, wherein the second transparent conductive layer comprises a VTTO material, and the third transparent conductive layer comprises an IWO material.

2. The preparation method according to claim 1, characterized in that: The step of preparing a first transparent conductive layer on the first doped crystalline silicon layer comprises: A first sublayer, a second sublayer and a third sublayer are sequentially prepared on the first doped crystalline silicon layer, wherein the first sublayer comprises an AZO material, the second sublayer comprises an AZO material and an FTO material, and the third sublayer comprises an FTO material.

3. The preparation method according to claim 2, characterized in that: The second sub-layer is prepared by simultaneously magnetron sputtering an AZO target and a FTO target.

4. The preparation method according to claim 2, characterized in that: The thickness of the second sublayer is 3 nm to 7 nm.

5. The preparation method according to claim 3, characterized in that: The thickness of the second sublayer is 3 nm to 7 nm.

6. The preparation method according to any one of claims 1 to 5, characterized in that: The third transparent conductive layer further comprises an ITO material, and the steps of sequentially preparing the second transparent conductive layer and the third transparent conductive layer on the second doped crystalline silicon layer comprise: A second transparent conductive layer, a fourth sublayer and a fifth sublayer are sequentially prepared on the second doped crystalline silicon layer, wherein the fourth sublayer comprises an IWO material, and the fifth sublayer comprises an ITO material.

7. The preparation method according to claim 6, characterized in that: The thickness of the fourth sublayer is 2nm-3nm.

8. The preparation method according to any one of claims 1 to 7, characterized in that: The preparation method comprises the following steps: S1, preparing the first doped crystalline silicon layer and the second doped crystalline silicon layer on the front side and the back side of the silicon substrate respectively; S2, preparing the second transparent conductive layer on the second doped crystalline silicon layer; S3, preparing a first transparent conductive layer on the first doped crystalline silicon layer; S4. Prepare the third transparent conductive layer on the second transparent conductive layer.

9. The preparation method according to any one of claims 1 to 8, characterized in that: The preparation method further includes: preparing a fourth transparent conductive layer on the first transparent conductive layer, wherein the fourth transparent conductive layer includes a VTTO material.

10. The preparation method according to any one of claims 1 to 9, characterized in that: The preparation method further comprises: before preparing the first doped crystalline silicon layer and the second doped crystalline silicon layer, texturing the silicon substrate; A first intrinsic layer is prepared on the front side of the silicon substrate after texturing, and a second intrinsic layer is prepared on the back side of the silicon substrate, wherein the first intrinsic layer is located between the silicon substrate and the first doped crystalline silicon layer, and the second intrinsic layer is located between the silicon substrate and the second doped crystalline silicon layer.

11. The preparation method according to any one of claims 1 to 10, characterized in that: The preparation method further includes: after the step of sequentially preparing a second transparent conductive layer and a third transparent conductive layer on the second doped crystalline silicon layer, post-processing to manufacture an electrode so that the electrode forms an ohmic contact with the third transparent conductive layer.

12. A solar cell, characterized in that: The solar cell is prepared by the preparation method according to any one of claims 1 to 11.

13. The solar cell according to claim 12, characterized in that: The solar cell at least comprises: Silicon substrate; A first doped crystalline silicon layer and a first transparent conductive layer sequentially stacked on the front side of the silicon substrate; A second doped crystalline silicon layer, a second transparent conductive layer and a third transparent conductive layer are sequentially stacked on the back side of the silicon substrate.

14. The solar cell according to claim 13, characterized in that: The solar cell further includes a fourth transparent conductive layer stacked on the first transparent conductive layer.

15. The solar cell according to claim 13, characterized in that: The solar cell further comprises a first intrinsic layer and a second intrinsic layer, wherein the first intrinsic layer is stacked between the silicon substrate and the first doped crystalline silicon layer, and the second intrinsic layer is stacked between the silicon substrate and the second doped crystalline silicon layer; and an electrode, wherein the electrode is in ohmic contact with the third transparent conductive layer.

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