Semiconduactor structure and forming method

Abstract

A substrate (100) comprises a first area (I); a plurality of first shallow isolation trenches (101) are provided in the first area (I), and the substrate (100) between adjacent first shallow isolation trenches (101) forms an active area (AA); an isolation structure (113) is provided in the substrate (100) having the first area (I), the isolation structure (113) comprising a first portion (111), and the first portion (111) being lower than the bottom of the first shallow isolation trenches (101) and located at the bottom of the active area (AA). Integrating the isolation structure (113) in the bulk silicon process can integrate a power amplifier module (PA), a switch module (Switch) and a low noise amplifier (LNA) on the same chip, so that the size of radio frequency modules is greatly reduced, thus improving the performance of radio frequency front-end chips.

Description

Semiconductor structure and formation method

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on September 6, 2023, with application number 202311146091.5 and invention name “Semiconductor Structure and Formation Method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method. Background Art

[0003] The RF front-end architecture includes components such as a controller, a switch module, a filter module, a power amplifier module (PA), and a low-noise amplifier (LNA). The controller is connected to the switch module and the power amplifier module, and the switch module is connected to the power amplifier module through the filter module. The switch module is mainly manufactured based on the SOI (Silicon-On-Insulator) process or the GaAs pH EMT process; the controller is mainly manufactured based on the CMOS (Complementary Metal Oxide Semiconductor) process or the SOI process; the power amplifier module PA is mainly manufactured based on the SiGe, HEMT, or GaN process. The low-noise amplifier usually uses Bulk CMOS or SiGe process to reduce low noise.

[0004] However, due to different process technologies, the power amplifier module (PA), switch module (Switch) and low noise amplifier (LNA) cannot be integrated on the same chip, resulting in long-distance transmission between signals, affecting the increase of RF frequency and the reduction of power consumption.

[0005] Therefore, how to integrate the power amplifier module (PA), switch module (Switch) and low noise amplifier (LNA) into the same chip is a technical problem that needs to be solved urgently.

[0006] Summary of the Invention

[0007] The technical problem solved by the present invention is to provide a semiconductor structure and a formation method. Based on the Bulk CMOS or SiGe process, a local SOI process is realized to integrate the power amplifier module (PA), switch module (Switch) and low noise amplifier (LNA) into the same chip, thereby significantly reducing the size of the RF module and increasing the module operating frequency.

[0008] To solve the above problems, the present invention provides a semiconductor structure, comprising: providing a substrate, the substrate including a first region; a plurality of first shallow isolation trenches located in the first region, the substrate between adjacent first shallow isolation trenches constituting an active region; an isolation structure located in the substrate in the first region, the isolation structure including a first portion, the first portion being lower than the bottom of the first shallow isolation trench and located at the bottom of the active region.

[0009] Optionally, the isolation structure further includes a second portion located on the first portion, the second portion is located in the first shallow isolation trench, and a gap trench is provided between a sidewall of the second portion and a sidewall of the active region.

[0010] Optionally, the method further includes: a first gate device located on the active region, the first gate device spanning the active region.

[0011] Optionally, the first gate device includes a first gate layer, and a material of the first gate layer includes polysilicon.

[0012] Optionally, the substrate further includes a second region, the first region is adjacent to the second region, a plurality of second shallow isolation trenches are provided in the second region, and a second shallow isolation structure is provided in the second shallow isolation trenches.

[0013] Optionally, it further includes: a second gate device located on the second region, the second gate device is located on the substrate between adjacent second shallow isolation structures, the second gate device includes a second gate layer, and the material of the second gate layer includes polysilicon.

[0014] Optionally, the second portion extends along a first direction, the first gate device spans the active region along a second direction, and the first direction is perpendicular to the second direction.

[0015] Optionally, the depth of the first shallow isolation trench is 100 nm to 500 nm.

[0016] Optionally, a thickness of the first portion in the second direction is 50 nm to 500 nm.

[0017] Correspondingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region; etching the first region to form a plurality of first shallow isolation trenches in the substrate, wherein the substrate between adjacent first shallow isolation trenches constitutes an active region; forming an isolation structure in the substrate of the first region, the isolation structure including a first portion, the first portion being lower than the bottom of the first shallow isolation trench and located at the bottom of the active region.

[0018] Optionally, the substrate further includes a second region, the first region is adjacent to the second region, a plurality of second shallow isolation trenches are formed in the second region, and a second shallow isolation structure is formed in the second shallow isolation trenches.

[0019] Optionally, the step of forming the first shallow isolation trench and the second shallow isolation trench includes: etching the substrate to form a plurality of first shallow isolation trenches in the first region and forming a plurality of second shallow isolation trenches in the second region.

[0020] Optionally, before forming the isolation structure and after forming the first shallow isolation trench and the second shallow isolation trench, the method further includes: forming a barrier layer on the surface of the substrate; forming a buffer layer on the sidewalls and bottom of the first shallow isolation trench, the sidewalls and bottom of the second shallow isolation trench, and the surface of the barrier layer; and forming a protective layer on the surface of the buffer layer.

[0021] Optionally, the step of forming the isolation structure includes: forming a mask layer on the surface of the protective layer in the second region; using the mask layer as a mask, continuing to etch the substrate along the first shallow isolation groove to form a deep isolation groove at the bottom of the first shallow isolation groove in the first region, while exposing the buffer layer in the first region.

[0022] Optionally, the depth of the deep isolation trench is 200 nm to 5000 nm.

[0023] Optionally, the isolation structure further includes a second portion formed on the first portion, the second portion is formed in the first shallow isolation trench, and a gap trench is provided between a sidewall of the second portion and a sidewall of the active region.

[0024] Optionally, the step of forming the isolation structure includes oxidizing the substrate at the bottom and sidewalls of the deep isolation trench and the substrate at the bottom of the active area using a wet oxidation process to form a first isolation layer.

[0025] Optionally, after forming the first isolation layer, the method further includes: removing the protective layer on the second region to expose the surface of the buffer layer; forming an initial second isolation layer in the deep isolation trench, the first shallow isolation trench and the second shallow isolation trench; flattening the initial second isolation layer to expose the surface of the barrier layer to form a second isolation layer, the second isolation layer in the deep isolation trench and the first isolation layer constitute a first part, the second isolation layer in the first shallow isolation trench constitutes a second part, the first part and the second part constitute an isolation structure, and a second isolation structure is formed in the second shallow isolation trench.

[0026] Optionally, after forming the isolation structure, the method further includes removing the buffer layer and the barrier layer on the sidewall of the active area to form a gap groove between the second portion and the sidewall of the active area.

[0027] Optionally, after forming the gap groove, the method further includes forming a first gate device on the active area, the first gate device spanning the active area; and forming a second gate device on the second area, located on the substrate between adjacent second shallow isolation structures.

[0028] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0029] In the technical solution of the structure of the present invention, the substrate includes a first area; a plurality of first shallow isolation trenches are provided in the first area, and the substrate between adjacent first shallow isolation trenches constitutes an active area; an isolation structure is provided in the substrate of the first area, and the isolation structure includes a first part, wherein the first part is lower than the bottom of the shallow isolation trench and is located at the bottom of the active area. This isolation structure integrated in the bulk silicon process can realize the integration of the power amplifier module (PA), the switch module (Switch) and the low noise amplifier (LNA, Low Noise Amplifier) ​​into the same chip, greatly reducing the size of the RF module, thereby improving the performance of the RF front-end chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] 1 to 15 are schematic structural diagrams of various steps of a method for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0031] As mentioned in the background technology, the power amplifier module (PA), switch module (Switch) and low noise amplifier (LNA) cannot be integrated on the same chip due to different process technologies, resulting in long-distance transmission between signals, affecting the increase of RF frequency and the reduction of power consumption.

[0032] On this basis, the present invention provides a semiconductor structure and a formation method, wherein the substrate includes a first region; a plurality of first shallow isolation trenches are provided in the first region, and the substrate between adjacent first shallow isolation trenches constitutes an active region; an isolation structure is provided in the substrate of the first region, and the isolation structure includes a first part, wherein the first part is lower than the bottom of the shallow isolation trench and is located at the bottom of the active region. This isolation structure is integrated in the bulk silicon process, which enables the power amplifier module (PA), switch module (Switch) and low noise amplifier (LNA, Low Noise Amplifier) ​​to be integrated into the same chip, greatly reducing the size of the RF module, thereby improving the performance of the RF front-end chip.

[0033] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0034] 1 to 15 are schematic structural diagrams of various steps of a method for forming a semiconductor structure in one embodiment of the present invention.

[0035] 1 , a substrate 100 is provided. The substrate 100 includes a first region I and a second region II. The first region I and the second region II are adjacent to each other.

[0036] In this embodiment, the first region I is a local SOI region, and the second region II is a normal CMOS region.

[0037] In this embodiment, the material of the substrate 100 is silicon; in other embodiments, the material of the substrate 100 may also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0038] 2 , the substrate 100 is etched to form a plurality of first shallow isolation trenches 101 in the first region I and a plurality of second shallow isolation trenches 102 in the second region II. The substrate 100 between adjacent first shallow isolation trenches 101 constitutes an active area AA.

[0039] In this embodiment, the depth range of the first shallow isolation trench 101 and the second shallow isolation trench 102 is 100nm to 500nm. When the depth of the first shallow isolation trench 101 and the second shallow isolation trench 102 is less than 100nm, the thickness of the active area AA of the first region I will be consumed in the subsequent oxidation process; when the depth of the first shallow isolation trench 101 and the second shallow isolation trench 102 is greater than 500nm, the thickness of the active area AA of the first region I is too thick and does not meet the requirements of the radio frequency device.

[0040] In this embodiment, the substrate 100 in the active area AA is distributed in a stripe shape, and the width (d) of the stripe of the substrate 100 in the active area AA is between 90 nm and 1000 nm.

[0041] Continuing to refer to FIG. 2 , a barrier layer 103 is formed on the surface of the substrate 100 .

[0042] In this embodiment, the material of the barrier layer 103 is silicon nitride.

[0043] In other embodiments, the material of the barrier layer 103 may also be silicon carbide, silicon oxycarbide, silicon carbonitride, etc.

[0044] In this embodiment, the barrier layer 103 is formed by a chemical vapor deposition process.

[0045] In other embodiments, the process for forming the barrier layer 103 may also be a physical vapor deposition process or an atomic layer deposition process, etc.

[0046] 3 , a buffer layer 104 is formed on the sidewalls and bottom of the first shallow isolation trench 101 , the sidewalls and bottom of the second shallow isolation trench 102 , and the surface of the barrier layer 103 .

[0047] In this embodiment, the buffer layer 104 is made of silicon oxide.

[0048] In this embodiment, an oxidation process is used to form the buffer layer 104 on the sidewalls and bottom of the first shallow isolation trench 101 , the sidewalls and bottom of the second shallow isolation trench 102 , and the surface of the barrier layer 103 .

[0049] In other embodiments, a deposition process may be used to form the buffer layer 104 on the sidewall and bottom of the first shallow isolation trench 101 , the sidewall and bottom of the second shallow isolation trench 102 , and the surface of the barrier layer 103 .

[0050] In this embodiment, the thickness of the buffer layer 104 is 6 nm to 20 nm. When the thickness of the buffer layer 104 is less than 6 nm, it will be insufficient to serve as an etching barrier for the subsequent protective layer 105. When the thickness of the buffer layer 104 is greater than 20 nm, the spacing of the first shallow isolation trench in the first region I will be compressed.

[0051] In this embodiment, the buffer layer 104 can serve as an etching barrier layer so as not to etch the barrier layer 103 during the subsequent etching of the protective layer 105 .

[0052] Referring to FIG. 4 , a protection layer 105 is formed on the surface of the buffer layer 104 .

[0053] In this embodiment, the material of the protection layer 105 is silicon nitride.

[0054] In other embodiments, the material of the protection layer 105 may also be silicon carbide, silicon oxycarbide, silicon oxynitride, etc.

[0055] In this embodiment, the thickness of the protective layer 105 is 50nm to 200nm. When the thickness of the protective layer 105 is less than 50nm, the second shallow isolation trench in the second region II is insufficiently isolated and easily oxidized during the subsequent formation of the first isolation layer 108; when the thickness of the protective layer 105 is greater than 200nm, the spacing of the first shallow isolation trenches in the first region I will be compressed.

[0056] Please refer to Figure 5. A mask layer 106 is formed on the surface of the protective layer 105 in the second region II. Using the mask layer 106 as a mask, the substrate 100 is continuously etched along the first shallow isolation trench 101 to form a deep isolation trench 107 at the bottom of the first shallow isolation trench 101 in the first region I, while exposing the buffer layer 104 of the first region I.

[0057] In this embodiment, the material of the mask layer 106 is photoresist.

[0058] In this embodiment, since the thickness of the protection layer 105 at the bottom of the first shallow isolation trench 101 is relatively thinner than the thickness of the protection layer 105 on the surface of the active area AA (please refer to FIG. 4 ), the deep isolation trench 107 can be etched along the first shallow isolation trench 101 .

[0059] In this embodiment, the protection layer 105 on the surface of the buffer layer 104 in the first region I is removed simultaneously during the process of forming the deep isolation trench 107 .

[0060] In this embodiment, the depth of the deep isolation trench 107 ranges from 200 nm to 5000 nm. When the depth of the deep isolation trench 107 is less than 200 nm, the thickness of the first isolation layer 108 and the subsequent isolation structure 113 will not meet the requirements of the radio frequency device; when the depth of the deep isolation trench 107 is greater than 5000 nm, the local stress caused by the first isolation layer 108 and the subsequent isolation structure 113 will lift the active area AA of the substrate 100 in the first region I too high, affecting the subsequent process.

[0061] Referring to FIG. 6 , the mask layer 106 is removed.

[0062] In this embodiment, an ashing process is used to remove the mask layer 106 .

[0063] 7 , the substrate 100 at the bottom and sidewalls of the deep isolation trench 107 and the substrate 100 at the bottom of the active area AA are oxidized by a wet oxidation process to form a first isolation layer 108 .

[0064] In this embodiment, after the deep isolation trench 107 is formed, the buffer layer 104 and the protection layer 105 remain on the sidewalls of the first shallow isolation trench 101. Therefore, during the oxidation process, the sidewalls of the first shallow isolation trench 101 and the substrate 100 therebetween (ie, the active area AA) will not be oxidized.

[0065] In this embodiment, the thickness ( L1 ) of the first isolation layer 108 is in a range of 50 nm to 500 nm, within which the substrate 100 at the bottom of the active area AA is completely oxidized to form the first isolation layer 108 .

[0066] 8 , after the first isolation layer 108 is formed, a photoresist layer 109 is formed on the surface of the buffer layer 104 in the first region I, in the first shallow isolation trench 101 , and in the deep isolation trench 107 .

[0067] 9 , the protection layer 105 on the second region II is removed until the surface of the buffer layer 104 is exposed.

[0068] In this embodiment, after the protection layer 105 is removed, the photoresist layer 109 is removed.

[0069] In this embodiment, a wet etching process is used to remove the protection layer 105 .

[0070] 10 , an initial second isolation layer is formed in the deep isolation trench 107 , the first shallow isolation trench 101 , and the second shallow isolation trench 102 .

[0071] In this embodiment, the initial second isolation layer fills the first shallow isolation trench 101 and the second shallow isolation trench 102 .

[0072] In this embodiment, the material of the initial second isolation layer is silicon oxide.

[0073] Please continue to refer to Figure 10. The initial second isolation layer is flattened until the surface of the barrier layer 103 is exposed to form a second isolation layer 110. The second isolation layer 110 in the deep isolation trench 107 and the first isolation layer 108 constitute a first part 111. The second isolation layer 110 in the first shallow isolation trench 101 constitutes a second part 112. The first part 111 and the second part 112 constitute an isolation structure 113. A second shallow isolation structure 114 is formed in the second shallow isolation trench 102.

[0074] In this embodiment, the first portion 111 is lower than the bottom of the first shallow isolation trench 101 and is located at the bottom of the active area AA.

[0075] In this embodiment, the isolation structure 113 integrated in the bulk silicon process can integrate the power amplifier module (PA), switch module (Switch) and low noise amplifier (LNA, Low Noise Amplifier) ​​into the same chip, greatly reducing the size of the RF module, thereby improving the performance of the RF front-end chip.

[0076] 11 , the buffer layer 104 and the barrier layer 103 on the sidewalls of the active area AA are removed, and a gap 115 is formed between the second portion 112 and the sidewalls of the active area AA.

[0077] In this embodiment, due to the presence of the gap groove 115 , after the gate layer is subsequently formed, the gate layer spans the active area AA and completely fills the gap groove 115 .

[0078] 11 , the barrier layer 103 on the surface of the substrate 100 in the second region II is removed at the same time until the surface of the substrate 100 in the second region II is exposed.

[0079] In this embodiment, during the process of removing the barrier layer 103 , the buffer layer 104 on the sidewall of the first shallow isolation trench 101 is removed simultaneously, so that the active area AA is fin-shaped.

[0080] Referring to FIG. 12 , an initial gate layer 116 is formed on the surface of the substrate 100 , and the initial gate layer 116 completely fills the gap trench 115 .

[0081] In this embodiment, the material of the initial gate layer 116 is polysilicon.

[0082] 13 , the initial gate layer 116 is patterned to expose a portion of the surface of the substrate 100 , and a first gate device 117 is formed on the active area AA, the first gate device 117 spanning the active area AA; a second gate device 118 is formed on the second area II, located on the substrate 100 between adjacent second shallow isolation structures 114 .

[0083] Please refer to Figures 14 and 15. A dielectric layer 119 is formed on the surfaces of the substrate 100 and the first gate device 117 and the second gate device 118. A first contact hole (not marked in the figure), a second contact hole (not marked in the figure) and a third contact hole (not marked in the figure) are formed in the dielectric layer 119. The bottom of the first contact hole exposes a portion of the surface of the first gate device 117, the bottom of the second contact hole exposes a portion of the surface of the second gate device 118, and the bottom of the third contact hole exposes a portion of the surface of the substrate 100 in the second region II. Conductive layers are filled in the first contact hole, the second contact hole and the third contact hole, respectively, to form a first conductive plug 120, a second conductive plug 121 and a third conductive plug 122.

[0084] FIG. 15 shows an arrangement relationship between the first gate device 117 on the first region I and the fin substrate 100 on the active region AA.

[0085] Correspondingly, the present invention also provides a semiconductor structure, please refer to Figure 14, providing a substrate 100, the substrate 100 includes a first region I; a plurality of first shallow isolation trenches 101 located in the first region I, and the substrate 100 between adjacent first shallow isolation trenches 101 constitutes an active area AA; an isolation structure 113 located in the substrate 100 of the first region I, the isolation structure 113 includes a first portion 111, the first portion 111 is lower than the bottom of the first shallow isolation trench and is located at the bottom of the active area AA.

[0086] In this embodiment, the isolation structure 113 integrated in the bulk silicon process can integrate the power amplifier module (PA), switch module (Switch) and low noise amplifier (LNA, Low Noise Amplifier) ​​into the same chip, greatly reducing the size of the RF module, thereby improving the performance of the RF front-end chip.

[0087] In this embodiment, the isolation structure 113 further includes a second portion 112 located on the first portion 111 . The second portion 112 is located in the first shallow isolation trench 101 . A gap 115 is defined between a sidewall of the second portion 112 and a sidewall of the active area AA.

[0088] In this embodiment, the device further includes: a first gate device 117 located on the active area AA, and the first gate device 117 spans the active area AA.

[0089] In this embodiment, the first gate device 117 includes a first gate layer, and the material of the first gate layer includes polysilicon.

[0090] In this embodiment, the substrate 100 further includes a second region II. The first region I is adjacent to the second region II. The second region II has a plurality of second shallow isolation trenches 102 . The second shallow isolation trenches 102 have second shallow isolation structures 114 .

[0091] In this embodiment, it also includes: a second gate device 118 located on the second region II, the second gate device 118 is located on the substrate 100 between adjacent second shallow isolation structures 114, the second gate device 118 includes a second gate layer, and the material of the second gate layer includes polysilicon.

[0092] In this embodiment, the second portion 112 extends along a first direction (Y), and the first gate device 117 spans the active area AA along a second direction (X), where the first direction (Y) is perpendicular to the second direction (X).

[0093] In this embodiment, the depth of the first shallow isolation trench 101 is 100 nm to 500 nm.

[0094] In this embodiment, the thickness of the first portion 111 in the second direction (X) is 50 nm to 500 nm.

[0095] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

[0096] The protection scope of this invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a first region; A plurality of first shallow isolation trenches are located in the first region, and the substrate between adjacent first shallow isolation trenches constitutes an active region; An isolation structure is located in the substrate in the first region, wherein the isolation structure includes a first portion, the first portion is lower than a bottom of the first shallow isolation trench and is located at the bottom of the active region.

2. The semiconductor structure according to claim 1, wherein: The isolation structure further includes a second portion located on the first portion, the second portion is located in the first shallow isolation trench, and a gap trench is provided between a sidewall of the second portion and a sidewall of the active region.

3. The semiconductor structure according to claim 2, wherein: Also includes: A first gate device is located on the active region, and the first gate device spans the active region.

4. The semiconductor structure according to claim 3, characterized in that The first gate device includes a first gate layer, and a material of the first gate layer includes polysilicon.

5. The semiconductor structure according to claim 1, wherein: The substrate further includes a second region, the first region is adjacent to the second region, a plurality of second shallow isolation trenches are provided in the second region, and a second shallow isolation structure is provided in the second shallow isolation trenches.

6. The semiconductor structure according to claim 5, characterized in that Also includes: A second gate device is located on the second region, the second gate device is located on the substrate between adjacent second shallow isolation structures, the second gate device comprises a second gate layer, and a material of the second gate layer comprises polysilicon.

7. The semiconductor structure according to claim 3, wherein: The second portion extends along a first direction, and the first gate device crosses the active region along a second direction, the first direction being perpendicular to the second direction.

8. The semiconductor structure according to claim 1, wherein: The depth of the first shallow isolation trench is 100 nm to 500 nm.

9. The semiconductor structure according to claim 1, wherein: The thickness of the first portion in the second direction is 50 nm to 500 nm.

10. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a first region; Etching the first region to form a plurality of first shallow isolation grooves in the substrate, wherein the substrate between adjacent first shallow isolation grooves constitutes an active region; An isolation structure is formed in the substrate of the first region, wherein the isolation structure includes a first portion, wherein the first portion is lower than a bottom of the first shallow isolation trench and is located at a bottom of the active region.

11. The method for forming a semiconductor structure according to claim 10, wherein: The substrate further includes a second region, the first region is adjacent to the second region, a plurality of second shallow isolation trenches are formed in the second region, and a second shallow isolation structure is formed in the second shallow isolation trenches.

12. The method for forming a semiconductor structure according to claim 11, wherein: The steps of forming the first shallow isolation trench and the second shallow isolation trench include: etching the substrate, forming a plurality of the first shallow isolation trenches in the first region, and forming a plurality of the second shallow isolation trenches in the second region.

13. The method for forming a semiconductor structure according to claim 12, wherein: Before forming the isolation structure and after forming the first shallow isolation trench and the second shallow isolation trench, the method further includes: forming a barrier layer on the surface of the substrate; forming a buffer layer on the sidewall and bottom of the first shallow isolation trench, the sidewall and bottom of the second shallow isolation trench, and the surface of the barrier layer respectively; A protective layer is formed on the surface of the buffer layer.

14. The method for forming a semiconductor structure according to claim 13, wherein: The steps of forming the isolation structure include: forming a mask layer on a surface of the protective layer in the second region; Using the mask layer as a mask, the substrate is continuously etched along the first shallow isolation trench to form a deep isolation trench located at the bottom of the first shallow isolation trench in the first region, while exposing the buffer layer in the first region.

15. The method for forming a semiconductor structure according to claim 14, wherein: The depth of the deep isolation trench is 200 nm to 5000 nm.

16. The method for forming a semiconductor structure according to claim 15, wherein: The isolation structure further includes a second portion formed on the first portion, the second portion is formed in the first shallow isolation trench, and a gap trench is provided between a sidewall of the second portion and a sidewall of the active region.

17. The method for forming a semiconductor structure according to claim 16, wherein: The step of forming the isolation structure includes oxidizing the substrate at the bottom and sidewalls of the deep isolation trench and the substrate at the bottom of the active area by a wet oxidation process to form a first isolation layer.

18. The method for forming a semiconductor structure according to claim 17, wherein: After forming the first isolation layer, the method further includes: removing the protective layer on the second region until the surface of the buffer layer is exposed; forming an initial second isolation layer in the deep isolation trench, the first shallow isolation trench, and the second shallow isolation trench; The initial second isolation layer is planarized until the surface of the barrier layer is exposed to form a second isolation layer, the second isolation layer in the deep isolation trench and the first isolation layer constitute the first part, the second isolation layer in the first shallow isolation trench constitutes the second part, and the first part and the second part constitute the isolation structure.

19. The method for forming a semiconductor structure according to claim 18, wherein: After forming the isolation structure, the method further includes removing the buffer layer and the barrier layer on the sidewall of the active region, and forming a gap groove between the second portion and the sidewall of the active region.

20. The method for forming a semiconductor structure according to claim 18, wherein: After forming the gap groove, the method further includes forming a first gate device on the active area, wherein the first gate device spans the active area; and forming a second gate device on the second area, which is located on the substrate between adjacent second shallow isolation structures.

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