Gate tube material, phase change storage chip, storage device, and electronic device

Abstract

Disclosed are a gate tube material, a phase change storage chip, a storage device, and an electronic device, which belong to the technical field of storage. The chemical general formula of the gate tube material is (A xTe 1-x) 1-yB y; the element A is selected from Zn or Ca; the element B is selected from at least one of Ge, B, C, N, O, Si, P, Al, Sn, Se, and S, wherein x and y are both atomic percentages, 0.3≤x＜0.6, and 0＜y≤0.15. By synergizing each element of the gate tube material and limiting the atomic percentage of each element within the corresponding range as stated above, it is not only conducive to enhancing the synergy between each element, thereby improving the gating performance thereof, but also conducive to improving the thermal stability and cycle life of the gate tube material, which enables the gate tube material to have the advantages of strong thermal stability, long cycle life, and excellent gating performance, etc.

Description

Gate tube materials, phase change memory chips, storage devices and electronic devices

[0001] This application claims priority to Chinese patent application No. 202311149498.3 filed on September 6, 2023, entitled “Gate tube material, phase change memory chip, storage device and electronic device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of storage technology, and in particular to gate tube materials, phase change memory chips, storage devices, and electronic devices. Background Art

[0003] Phase Change Memory (PCM) includes multiple phase change memory cells. To prevent leakage current from read, erase, or write operations on a target phase change memory cell from affecting adjacent phase change memory cells, a gate transistor unit that acts as a switch is configured for each phase change memory cell.

[0004] The gate tube unit includes a gate layer made of a gate tube material. The gate layer has a great influence on the performance of the gate tube unit. It is expected that the gate layer has low leakage current, strong thermal stability and long cycle life. In related technologies, the materials used for the gate layer include GeTe6, GeAsSiTe, ZnTe, MgTe, etc. However, these gate tube materials cannot have the advantages of low leakage current, strong thermal stability and long cycle life.

[0005] Public content

[0006] In view of this, the present disclosure provides a gate tube material, a phase change memory chip, a storage device and an electronic device, which can solve the technical problems in the related art.

[0007] Specifically, the following technical solutions are included:

[0008] On the one hand, the embodiment of the present disclosure provides a gate tube material, the chemical formula of the gate tube material is (A x Te 1-x ) 1-y B y ;

[0009] The element A is selected from Zn or Ca; the element B is selected from at least one of Ge, B, C, N, O, Si, P, Al, Sn, Se, and S;

[0010] Wherein, x and y are both atomic percentages, 0.3≤x<0.6, 0<y≤0.15.

[0011] In the gate tube material provided by the embodiment of the present disclosure, element A is selected from Zn element or Ca element, and Zn element or Ca element and element Te can exist in the form of ZnTe or CaTe, and ZnTe or CaTe is in a polycrystalline form, which has a stable structure and strong temperature resistance, which is beneficial to improving the thermal stability of the gate tube material. Element B is selected from at least one of Ge, B, C, N, O, Si, P, Al, Sn, Se, and S. Element B can be a single element or multiple elements. Such B elements cooperate with ZnTe or CaTe to make the gate tube material have good gate characteristics. In particular, by limiting the atomic percentage of each element component in the gate tube material to the corresponding range shown above, it is not only beneficial to enhance the synergistic effect between the elements, thereby improving its gate performance, but also beneficial to improve the thermal stability and cycle life of the gate tube material, which makes the gate tube material have the advantages of strong thermal stability, long cycle life, and excellent gate performance.

[0012] In some possible implementations, the element B is a single element, and the element B is selected from one of Ge, B, C, N, O, Si, and P.

[0013] For the gate tube material of the ternary system, the element B is selected from one of Ge, B, C, N, O, Si, and P. When this type of element B is doped into the ZnTe polycrystalline system or the CaTe polycrystalline system, this type of element B can gather at the grain boundaries and inhibit grain growth, thereby refining the large grains in the ZnTe or CaTe polycrystalline system, ensuring that larger grains exist in the middle of the gate tube material to destroy its structure, making the structure of the gate tube material more stable.

[0014] For the ternary system of the gate tube material, when the element B is selected from one of Ge, B, C, N, O, Si, and P, and the Te element, Zn / Ca element, and B element are combined in the atomic percentages shown above, the thermal stability of the obtained ternary system of the gate tube material is stronger. Even if the gate tube material undergoes a high-temperature annealing process, it can ensure that the material itself will not experience element volatilization, element separation, precipitation, etc. When the gating layer based on the gate tube material is used for the gate tube device, the gate tube device has both good gating performance and thermal stability, so that the gate tube device can withstand higher operating currents and operating temperatures, thereby improving its operating reliability and stability. In addition, the gate tube material also has a long cycle life, and its electrical properties remain stable after multiple cycles.

[0015] In some possible implementations, the element B includes element B1 and element B2, and the chemical formula of the gate tube material is (A x Te 1- x ) 1-y1-y2 B1y1 B2 y2 ;

[0016] Element B1 is selected from one of Ge, B, C, N, O, Si, and P;

[0017] Element B2 is different from element B1, and element B2 is selected from one of Ge, Si, Al, Sn, Se, and S;

[0018] x, y1 and y2 are all atomic percentages, 0.45≤x≤0.55, 0.01≤y1≤0.1, 0<y2≤0.05.

[0019] For the quaternary system of the gate tube material, the element B1 is selected from one of Ge, B, C, N, O, Si, and P. When the element B1 is doped into the ZnTe polycrystalline system or the CaTe polycrystalline system, the large grains in the polycrystalline system can be refined, making the structure of the gate tube material more stable. By further doping with the element B2, the element B2 is selected from one of Ge, Si, Al, Sn, Se, and S. Binary element doping effectively inhibits the generation of homogeneous bonds, which is beneficial to reducing the Vth drift of the gate tube device, further improving the operating reliability and stability of the gate tube device, and its electrical performance remains stable after multiple cycles. In addition, the presence of element B2 can also inhibit the aggregation of B1 elements such as C and B during the cycling process of the gate tube device to form clusters and cause performance degradation, thereby improving the fatigue characteristics and cycle life of the gate tube device. In addition, the gate tube material also has a lower leakage current.

[0020] In particular, when Te, Zn / Ca, B1, and B2 are combined in the atomic percentages shown above, the quaternary gate material has at least the following advantages: On the one hand, it can further enhance the thermal stability of the gate material. Even after undergoing a high-temperature annealing process, the quaternary gate material can ensure that the material itself will not experience element volatilization, element separation, precipitation, etc. On the other hand, it can also enable the gate material to have lower leakage current and longer cycle life (cycle life can be as high as 10 10 times), and after multiple cycles, its electrical properties remain stable, making the gate tube material exhibit excellent fatigue properties and cycle life.

[0021] In some possible implementations, the element A is Zn, and 0.45≤x≤0.55. This is more beneficial for enhancing the thermal stability of the gate tube material, reducing the leakage current of the gate tube material, and improving the cycle life of the gate tube material, so that the electrical properties of the gate tube material remain stable after multiple cycles, showing excellent fatigue characteristics and cycle life.

[0022] On the other hand, an embodiment of the present disclosure further provides a phase-change memory chip, the phase-change memory chip comprising a plurality of memory sub-units, each of the memory sub-units comprising a gate tube unit and a phase-change memory unit connected in series;

[0023] Each of the gate tube units includes a gate layer, and the gate layer is made of any of the above-mentioned gate tube materials.

[0024] Phase-change memory chips, also known as phase-change memories, utilize gate transistors as switching devices within these cells, effectively suppressing leakage current generated during the operation of the phase-change memory chip. The phase-change memory chip provided by the disclosed embodiments has a gate layer fabricated using the gate transistor material provided by the disclosed embodiments, possessing all the advantages of the gate transistor material. This enables the phase-change memory chip to combine advantages such as low leakage current, strong thermal stability, long cycle life, and stable electrical performance.

[0025] In some possible implementations, the gate tube unit and the phase change memory unit are integrated.

[0026] In some possible implementations, the gate tube unit and the phase change memory unit are independent of each other.

[0027] In some possible implementations, at least one of the gate tube unit and the phase-change memory unit further includes a buffer layer, and at least one of the gate layer and the phase-change material layer of the phase-change memory unit is stacked with the buffer layer;

[0028] The buffer layer material is selected from at least one of amorphous carbon materials, MoTe2, MoS2, MnTe, HfO2 / TaO, HfO2 / HfZrO / TaO, Al2O3, WTe2, WS2, and TiNO.

[0029] The buffer layer prepared using the above-mentioned buffer material can effectively prevent the element migration or segregation of the gate tube material and the phase change material in the direction of the electric field, reduce the diffusion of elements in the gate tube material and the phase change material, and ensure the thermal stability and cycle life of the gate layer and the phase change material layer.

[0030] On the other hand, an embodiment of the present disclosure further provides a storage device, which includes a controller and at least one phase-change memory chip, the phase-change memory chip being any of the above-described ones, and the controller being configured to store data in the phase-change memory chip.

[0031] On the other hand, an embodiment of the present disclosure further provides an electronic device, which includes a processor and the above-mentioned storage device, and the processor is used to store data generated by the electronic device in the storage device.

[0032] Exemplarily, the electronic device includes but is not limited to: computers, mobile phones, music playing devices, digital broadcasting devices, messaging devices, game control devices, medical devices, fitness equipment, personal digital assistants, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] FIG1 is a schematic structural diagram of an exemplary gate tube unit provided in an embodiment of the present disclosure;

[0034] FIG2 is a schematic structural diagram of another exemplary gate tube unit provided by an embodiment of the present disclosure;

[0035] FIG3 is a schematic structural diagram of another exemplary gate tube unit provided in an embodiment of the present disclosure;

[0036] FIG4 is a schematic structural diagram of an exemplary storage subunit provided in an embodiment of the present disclosure;

[0037] FIG5 is a schematic structural diagram of another exemplary storage subunit provided by an embodiment of the present disclosure;

[0038] FIG6 is a schematic structural diagram of another exemplary storage subunit provided in an embodiment of the present disclosure;

[0039] FIG7 is a schematic diagram of the structure of an exemplary storage device provided by an embodiment of the present disclosure;

[0040] FIG8 is a leakage current distribution diagram of the gate tube unit provided in Example 1 after annealing;

[0041] FIG9 is a cycle characteristic diagram of the gate tube unit provided in Example 1 after annealing;

[0042] FIG10 is a schematic diagram showing the distribution relationship between the threshold voltage and the number of cycles of the gate transistor unit after annealing provided in Example 1;

[0043] FIG11 is a diagram showing the threshold voltage distribution of the gate transistor unit after annealing provided in Example 2;

[0044] FIG12 is a leakage current distribution diagram of the gate tube unit provided in Example 2 after annealing;

[0045] FIG13 is a cycle characteristic diagram of the gate tube unit provided in Example 2 after annealing;

[0046] FIG14 is a schematic diagram showing the distribution relationship between the threshold voltage and the number of cycles of the gate transistor unit provided in Example 2 after annealing;

[0047] FIG15 is a current-voltage characteristic curve of the gate tube unit provided in Example 3 after annealing;

[0048] FIG16 is a leakage current distribution diagram of the gate tube unit provided in Example 3 after annealing;

[0049] FIG17 is a cycle characteristic diagram of the gate tube unit provided in Example 3 after annealing;

[0050] FIG18 is a schematic diagram showing the distribution relationship between the threshold voltage and the number of cycles of the gate tube unit provided in Example 3 after annealing.

[0051] In the above-mentioned leakage current distribution diagram and threshold voltage distribution diagram, the horizontal axis BEC SIZE (nm) refers to the diameter of the bottom electrode in the corresponding gate tube device, the vertical axis OTS loff (μA) refers to the leakage current of the OTS type gate tube device, and the vertical axis OTS Vth (V) refers to the threshold voltage of the OTS type gate tube device.

[0052] In the cycle characteristic graphs mentioned above, the horizontal axis is the logarithmic coordinate of the cycle number, expressed as Log(cycle number) to the base 10, and the vertical axis is the current, in uA. The upper broken line shows the current distribution in the on state, and the lower broken line shows the current distribution in the off state.

[0053] In the above diagram of the distribution relationship between the threshold voltage and the number of cycles, the horizontal axis is the logarithmic coordinate of the number of cycles, expressed as Log(number of cycles) with a base of 10, and the vertical axis is the threshold voltage, in V.

[0054] The reference numerals represent:

[0055] 100, gating layer; 200, bottom electrode; 300, top electrode; 400, insulating medium;

[0056] 500, substrate; 600, buffer layer; 700, phase change material layer; 800, intermediate electrode;

[0057] 001. Controller; 002. Phase-change memory chip. DETAILED DESCRIPTION

[0058] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0059] In the description of the embodiments of the present disclosure, the terms "upper" and "lower" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in FIG1 , and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0060] Phase Change Memory (PCM) is a solid-state semiconductor non-volatile memory, also known as a phase change memory chip. It uses phase change material as the storage medium. The phase change material can undergo reversible transformation between crystalline and amorphous states. By utilizing the difference in high resistivity and low resistivity of the phase change material in the amorphous and crystalline states, the phase change memory can store data "0" and "1".

[0061] The phase change memory includes multiple phase change memory cells, which include read, erase, and write operations. There is leakage current in the phase change memory cell during the read, erase, and write operations. In order to prevent the leakage current from affecting adjacent phase change memory cells and causing problems such as misreading and misoperation, a selection tube unit that acts as a switch is configured for each phase change memory cell.

[0062] The lower the leakage current of the gate tube unit, the stronger the leakage current in the phase change memory can be suppressed, which is conducive to improving the high storage density of the phase change memory. Since the gate tube unit is turned on when the phase change memory unit is read, written or erased, it is expected that the life of the phase change memory unit is long enough. The gate tube unit needs to be compatible with the complementary metal oxide semiconductor (CMOS) back-end process to withstand high temperatures. It can be seen that the gate tube unit is expected to have higher thermal stability.

[0063] However, in the related art, the materials used for the gate layer include GeTe6, GeAsSiTe, ZnTe, MgTe, etc. However, these gate tube materials cannot have the advantages of low leakage, strong thermal stability and long cycle life.

[0064] On the one hand, the embodiment of the present disclosure provides a gate tube material, the chemical formula of the gate tube material is (A x Te 1-x ) 1-y B y , wherein element A is selected from Zn or Ca, and element B is selected from at least one of Ge, B, C, N, O, Si, P, Al, Sn, Se, and S; wherein x and y are both atomic percentages, 0.3≤x<0.6, 0<y≤0.15.

[0065] In the gate tube material provided by the embodiment of the present disclosure, element A is selected from Zn element or Ca element, and Zn element or Ca element and element Te can exist in the form of ZnTe or CaTe, and ZnTe or CaTe is in a polycrystalline form, which has a stable structure and strong temperature resistance, which is conducive to improving the thermal stability of the gate tube material. Element B is selected from at least one of Ge, B, C, N, O, Si, P, Al, Sn, Se, and S. Element B can be a single element or multiple elements. Such B elements cooperate with ZnTe or CaTe to make the gate tube material have good gate characteristics. In particular, by limiting the atomic percentage of each element component in the gate tube material to the corresponding range shown above, it is not only conducive to improving the synergistic effect between the elements, thereby improving its gate performance, but also conducive to improving the thermal stability and cycle life of the gate tube material, which makes the gate tube material have the advantages of strong thermal stability, long cycle life, and excellent gate performance.

[0066] In addition, the gate tube material provided in the embodiment of the present disclosure does not contain toxic elements, which not only does not cause serious pollution to the environment, but also helps to reduce the preparation cost.

[0067] In some examples, the gate tube material provided by the embodiment of the present disclosure is a ternary system, element B is a single element, and the chemical formula of the gate tube material is as shown above, which is (A x Te 1-x ) 1-y B y ; wherein, element A is selected from Zn element or Ca element; element B is selected from one of Ge, B, C, N, O, Si, and P; x and y are both atomic percentages, 0.3≤x<0.6, 0<y≤0.15.

[0068] For the ternary system gate tube material, the element B is selected from one of Ge, B, C, N, O, Si, and P. When the above element B is doped into the ZnTe polycrystalline system or the CaTe polycrystalline system, the element B can aggregate at the grain boundaries and inhibit grain growth, thereby refining the large grains in the ZnTe or CaTe polycrystalline system, ensuring the presence of larger grains in the middle of the gate tube material to disrupt its structure, making the structure of the gate tube material more stable. It can be seen that when the element B is selected from one of Ge, B, C, N, O, Si, and P, and the Te element, Zn / Ca element, and B element are combined in the atomic percentages shown above, the thermal stability of the obtained ternary system gate tube material is stronger. Even after undergoing a high-temperature annealing process, the gate tube material itself can ensure that the material itself will not experience element volatilization, element separation, precipitation, etc. When the gate layer based on the gate tube material is used in the gate tube device, the gate tube device has both good gate performance and thermal stability, so that the gate tube device can withstand higher operating current and operating temperature, and improve its working reliability and stability. In addition, the gate tube device exhibits a long cycle life, and after multiple cycles (the number of cycles can reach 10 7 times), its electrical performance remains stable.

[0069] Examples of ternary gate materials include: (Zn x Te 1-x ) 1-y Ge y 、(Zn x Te 1-x ) 1-y B y 、(Zn x Te 1-x ) 1-y C y 、(Zn x Te 1-x ) 1-y N y 、

[0070] (Zn x Te 1-x ) 1-y O y 、(Zn x Te 1-x ) 1-y Si y 、(Zn x Te 1-x ) 1-y P y 、(Ca x Te 1-x ) 1-y Ge y 、(Ca x Te1-x ) 1-y B y 、(Ca x Te 1-x ) 1-y C y 、

[0071] (Ca x Te 1-x ) 1-y N y 、(Ca x Te 1-x ) 1-y O y 、(Ca x Te 1-x ) 1-y Si y 、(Ca x Te 1-x ) 1-y P y .

[0072] Among them, the value of x includes but is not limited to: 0.31, 0.32, 0.33, 0.34, 0.35, 0.36, 0.37, 0.38, 0.39, 0.4, 0.41, 0.42, 0.43, 0.44, 0.45, 0.46, 0.47, 0.48, 0.49, 0.5, 0.51, 0.52, 0.53, 0.54, 0.55, 0.56, 0.57, 0.58, 0.59, etc.

[0073] The value of y includes but is not limited to: 0.01, 0.015, 0.02, 0.025, 0.03, 0.035, 0.04, 0.045, 0.05, 0.055, 0.06, 0.065, 0.07, 0.075, 0.08, 0.085, 0.09, 0.095, 0.1, 0.105, 0.11, 0.115, 0.12, 0.125, 0.13, 0.135, 0.14, 0.145, etc.

[0074] In some examples, the gate tube material provided by the embodiments of the present disclosure is a quaternary system, wherein element B includes element B1 and element B2. The chemical formula of the quaternary system gate tube material is (A x Te 1-x ) 1-y1-y2 B1 y1 B2 y2; wherein, x, y1 and y2 are all atomic percentages, element A is selected from Zn element or Ca element; element B1 is selected from one of Ge, B, C, N, O, Si, and P; element B2 is different from element B1, and element B2 is selected from one of Ge, Si, Al, Sn, Se, and S; 0.45≤x≤0.55, 0.01≤y1≤0.1, 0<y2≤0.05.

[0075] For the quaternary system of the gate tube material, the element B1 is selected from one of Ge, B, C, N, O, Si, and P. When the element B1 is doped into the ZnTe polycrystalline system or the CaTe polycrystalline system, the large grains in the polycrystalline system can be refined, making the structure of the gate tube material more stable. By further doping with the element B2, the element B2 is selected from one of Ge, Si, Al, Sn, Se, and S. Binary element doping effectively inhibits the generation of homogeneous bonds, which is beneficial to reducing the Vth drift of the gate tube device, further improving the operating reliability and stability of the gate tube device, and its electrical performance remains stable after multiple cycles. In addition, the presence of element B2 can also inhibit the aggregation of B1 elements such as C and B during the cycling process of the gate tube device to form clusters and cause performance degradation, thereby improving the fatigue characteristics and cycle life of the gate tube device and reducing the leakage current of the gate tube material.

[0076] In particular, when the Te element, the Zn / Ca element, the B1 element, and the B2 element are combined in the atomic percentages shown above, the quaternary gate tube material has at least the following advantages: on the one hand, the thermal stability of the gate tube material can be further enhanced. Even if the quaternary gate tube material undergoes a high-temperature annealing process, it can ensure that the material itself will not experience element volatilization, element separation, precipitation, etc., so that the gate tube device exhibits a longer cycle life (for example, the cycle life can be as high as 10 10 The material also has a lower leakage current, further optimizing its gating performance.

[0077] When the gating layer based on the gating tube material is used in a gating tube device, the gating tube device not only has good gating performance, but also has excellent thermal stability and fatigue resistance, so that the gating tube device can withstand higher operating current and operating temperature, thereby improving its operating reliability and stability.

[0078] Examples of gate materials for quaternary systems include but are not limited to: (Zn x Te 1-x ) 1-y1-y2 C y1 Ge y2 、(Zn x Te 1-x )1-y1-y2 B y1 Ge y2 、

[0079] (Zn x yourself 1-x ) 1-y1-y2 N y1 Ge y2 、(Zn x yourself 1-x ) 1-y1-y2 A y1 Ge y2 、(Zn x yourself 1-x ) 1-y1-y2 And y1 Ge y2 、(Zn x yourself 1-x ) 1-y1-y2 P y1 Ge y2 、

[0080] (That x yourself 1-x ) 1-y1-y2 Ge y1 it y2 ,(That x yourself 1-x ) 1-y1-y2 B y1 it y2 ,(That x yourself 1-x ) 1-y1-y2 C y1 it y2 ,(That x yourself 1-x ) 1-y1-y2 N y1 it y2 、

[0081] (That x yourself 1-x ) 1-y1-y2 A y1 it y2 ,(That x yourself 1-x ) 1-y1-y2 And y1 it y2 ,(That x yourself 1-x ) 1-y1-y2 P y1 it y2 ,(That x yourself 1-x ) 1-y1-y2 Gey1 Sn y2 、

[0082] (Ca x Te 1-x ) 1-y1-y2 B y1 Sn y2 、(Ca x Te 1-x ) 1-y1-y2 C y1 Sn y2 、(Ca x Te 1-x ) 1-y1-y2 N y1 Sn y2 、(Ca x Te 1-x ) 1-y1-y2 O y1 Sn y2 、

[0083] (Ca x Te 1-x ) 1-y1-y2 Si y1 Sn y2 、(Ca x Te 1-x ) 1-y1-y2 P y1 Sn y2 wait.

[0084] The values ​​of x include, but are not limited to, 0.45, 0.46, 0.47, 0.48, 0.49, 0.5, 0.51, 0.52, 0.53, and 0.54. The values ​​of y1 include, but are not limited to, 0.01, 0.015, 0.02, 0.025, 0.03, 0.035, 0.04, 0.045, 0.05, 0.055, 0.06, 0.065, 0.07, 0.075, 0.08, 0.085, 0.09, 0.095, and 0.1. The values ​​of y2 include, but are not limited to, 0.01, 0.015, 0.02, 0.025, 0.03, 0.035, 0.04, and 0.045.

[0085] In some possible implementations, for the various types of gate tube materials involved above, element A is Zn element, and 0.45≤x≤0.55. This is more beneficial for enhancing the thermal stability of the gate tube material, reducing the leakage current of the gate tube material, and improving the cycle life of the gate tube material, so that the electrical properties of the gate tube material remain stable after multiple cycles, showing excellent fatigue characteristics and cycle life.

[0086] The gate tube material provided in the embodiments of the present disclosure may exist in the following forms, including but not limited to: alloys, ternary compounds or quaternary compounds, combinations of a single substance and a compound, combinations of a single substance and an alloy, combinations of a single substance and a single substance, etc. The gate layer is prepared based on the various forms of the gate tube material described above.

[0087] One form of the gate tube material in the form of a ternary compound is a combination of an A-Te binary compound / alloy and a single substance or compound corresponding to element B. In this case, the atomic percentage of each element is determined according to the chemical formula of the gate tube material, and corresponding amounts of the A-Te binary compound / alloy and the single substance or compound of element B are provided in combination according to the ratio. The A-Te binary compound / alloy and the single substance or compound of element B do not need to be mixed, so they are independent of each other and can be stored in the same container for future use. Alternatively, the A-Te binary compound / alloy and the single substance or compound of element B can also be mixed and formed into a ternary compound or alloy gate tube material by smelting.

[0088] Another form of the gate tube material in the form of a ternary compound is a combination of a B-Te binary compound / alloy and a single substance or compound corresponding to element A. In this case, the atomic percentage of each element is determined according to the chemical formula of the gate tube material, and corresponding amounts of the B-Te binary compound / alloy and the single substance or compound of element A are provided in combination according to the ratio. The B-Te binary compound / alloy and the single substance or compound of element A do not need to be mixed, so that they are independent of each other and can be stored in the same container for future use. Alternatively, the B-Te binary compound / alloy and the single substance or compound of element A can also be mixed and formed into a gate tube material in the form of a ternary compound or alloy by smelting.

[0089] Another form of the gate tube material in the form of a ternary compound is a combination of Te, A, and B. The atomic percentages of each element are determined based on the chemical formula of the gate tube material. According to the matching ratios, corresponding amounts of Te, A, and B are provided. These specific amounts of elements do not need to be mixed and can be independent of each other. Alternatively, corresponding amounts of Te, A, and B can be mixed and smelted to form a ternary compound or alloy gate tube material.

[0090] One form of the gate tube material in the form of a quaternary compound is a combination of an A-Te binary compound / alloy, a single substance or compound corresponding to the B1 element, and a single substance or compound corresponding to the B2 element. In this case, the atomic percentage of each element is determined according to the chemical formula of the gate tube material, and corresponding amounts of the A-Te binary compound / alloy, the B1 element single substance or compound, and the B2 element single substance or compound are provided in combination according to the ratio. The A-Te binary compound / alloy, the B1 element single substance or compound, and the B2 element single substance or compound do not need to be mixed, so that they are independent of each other and can be stored in the same container for future use. Alternatively, the A-Te binary compound / alloy, the B1 element single substance or compound, and the B2 element single substance or compound can also be mixed and formed into a quaternary compound or alloy gate tube material by smelting.

[0091] Another form of the gate tube material in the form of a quaternary compound is a combination of a B1-Te binary compound / alloy, a single substance or compound corresponding to element A, and a single substance or compound corresponding to element B2. In this case, the atomic percentage of each element is determined according to the chemical formula of the gate tube material, and corresponding amounts of the B1-Te binary compound / alloy, the single substance or compound of element A, and the single substance or compound of element B2 are provided in accordance with the ratio. They do not need to be mixed, but are kept independent of each other and can be stored in the same container for future use. Alternatively, they can be mixed and smelted to form a gate tube material in the form of a ternary compound or alloy.

[0092] Another form of the gate tube material in the form of a quaternary compound is a combination of Te element, A element, B1 element and B2 element. The atomic percentage of each element is determined according to the chemical formula of the gate tube material, and corresponding amounts of Te element, A element, B1 element and B2 element are provided according to the ratio. These specific amounts of elements do not need to be mixed, can be independent of each other, and can be stored in the same container for future use. Alternatively, corresponding amounts of Te element, A element, B1 element and B2 element can also be mixed and formed into a quaternary compound or alloy gate tube material by smelting.

[0093] In another aspect, embodiments of the present disclosure further provide a phase-change memory chip comprising a plurality of memory subunits, each of which comprises a gate transistor unit and a phase-change memory unit connected in series. Each gate transistor unit comprises a gate layer made from any of the aforementioned gate transistor materials.

[0094] Phase-change memory chips, also known as phase-change memories, utilize gate transistors as switching devices within these cells, effectively suppressing leakage current generated during the operation of the phase-change memory chip. The phase-change memory chip provided by the disclosed embodiments has a gate layer fabricated using the gate transistor material provided by the disclosed embodiments, possessing all the advantages of the gate transistor material. This enables the phase-change memory chip to combine advantages such as low leakage current, strong thermal stability, long cycle life, and stable electrical performance.

[0095] A plurality of memory sub-units cooperate to form a phase change memory array. Each memory sub-unit is connected to a word line via a top electrode and to a bit line via a bottom electrode.

[0096] The structures of the phase-change memory chips provided in the embodiments of the present disclosure include, but are not limited to, 1S1R (One Selector One Resistor) structures and 1SnR (One Selector n Resistor) structures. For a 1S1R phase-change memory chip, one gate transistor unit controls one phase-change memory cell. For a 1SNR phase-change memory chip, one gate transistor unit controls N phase-change memory cells simultaneously.

[0097] The gate transistor unit involved in the embodiment of the present disclosure is an Ovonic Threshold Switching (OTS) type. The OTS type gate transistor unit is widely used in phase change memory due to its advantages such as high on-state current and low leakage current.

[0098] For the phase-change memory chip provided in the embodiments of the present disclosure, the gate tube unit may be integrated with the phase-change memory unit, or the gate tube unit may be arranged independently of the phase-change memory unit. The following describes these two implementations in an exemplary manner:

[0099] In some examples, the gate transistor unit and the phase change memory unit are independent of each other, that is, an electrode layer of the gate transistor unit and an electrode layer of the corresponding phase change memory unit can be connected in series by means such as a wire, such as a copper interconnect line.

[0100] FIG1 illustrates a gate tube unit with a restriction structure arranged independently of a phase change memory unit. The gate tube unit may include a substrate 500, a bottom electrode 200, a gate layer 100, a top electrode 300, and an insulating dielectric 400. The substrate 500, the bottom electrode 200, the gate layer 100, and the top electrode 300 are stacked in sequence from bottom to top, and the insulating dielectric 400 at least covers the gate layer 100. For example, the insulating dielectric 400 may cover the side of the gate layer 100, or the insulating dielectric 400 may simultaneously cover the gate layer 100 and the sides of each electrode.

[0101] FIG2 illustrates a gate transistor unit with a confinement structure that is arranged independently of a phase-change memory cell. The gate transistor unit may include a substrate 500, a bottom electrode 200, a gate layer 100, a buffer layer 600, a top electrode 300, and an insulating dielectric 400. The substrate 500, the bottom electrode 200, the gate layer 100, the buffer layer 600, and the top electrode 300 are stacked in sequence from bottom to top, and the insulating dielectric 400 at least covers the gate layer 100. For example, the insulating dielectric 400 may cover the sides of the gate layer 100 and the buffer layer 600, or, as shown in FIG2 , the insulating dielectric 400 may cover the sides of the gate layer 100, the buffer layer 600, and each electrode at the same time.

[0102] The gate transistor unit can also be arranged in a T-type structure. FIG3 illustrates a T-type gate transistor unit arranged independently of the phase change memory unit. The gate transistor unit includes a substrate 500, a bottom electrode 200, a gate layer 100, a top electrode 300, and an insulating dielectric 400. The insulating dielectric 400 is stacked on the substrate 500 and has a receiving hole. The bottom electrode 200 is received in the receiving hole and is flush with the insulating dielectric 400. The gate layer 100 is stacked on the bottom electrode 200 and supported by the insulating dielectric 400. The top electrode 300 is stacked on the gate layer 100. Furthermore, the T-type gate transistor unit may further include a buffer layer 600, which is stacked between the gate layer 100 and the top electrode 300.

[0103] In some examples, the gate tube unit is integrated with the phase change memory unit, and the gate layer of the gate tube unit and the phase change material layer of the phase change memory unit are arranged in the same layer structure unit and share a top electrode and a bottom electrode.

[0104] FIG4 illustrates the structure of a memory subunit in which a gate transistor unit and a phase-change memory unit are integrated. As shown in FIG4 , the memory subunit includes a substrate 500, a bottom electrode 200, a gate layer 100, a buffer layer 600, a phase-change material layer 700, a top electrode 300, and an insulating dielectric 400. The substrate 500, the bottom electrode 200, the gate layer 100, the buffer layer 600, the phase-change material layer 700, and the top electrode 300 are stacked in sequence from bottom to top. The insulating dielectric 400 can be coated on the sides of each functional layer, or can be coated on the sides of both the functional layer and each electrode. For example, FIG4 illustrates an example in which the insulating dielectric 400 is entirely coated on the bottom electrode 200, the gate layer 100, the buffer layer 600, the phase-change material layer 700, and the top electrode 300.

[0105] In some examples, in the phase change memory chip provided by the embodiments of the present disclosure, at least one of the gate tube unit and the phase change memory unit further includes a buffer layer 600, and at least one of the gate layer 100 and the phase change material layer 700 of the phase change memory unit is stacked with the buffer layer 600.

[0106] For the gate tube unit, a buffer layer 600 can be laminated on at least one of the top and bottom surfaces of the gate layer 100. In one example, the buffer layer 600 isolates the gate layer 100 from the phase-change material layer 700. In another example, the buffer layer 600 isolates the gate layer 100 from the corresponding electrode. The buffer layer 600 prepared using the above-mentioned buffer material can effectively prevent element migration or segregation in the gate tube material in the direction of the electric field, reduce diffusion between the gate tube material and the electrode or the phase-change material layer 700, and ensure the thermal stability and cycle life of the gate layer 100.

[0107] For a phase-change memory cell, the buffer layer 600 may be stacked on at least one of the top surface and the bottom surface of the phase-change material layer 700. One example is that the buffer layer 600 isolates the phase-change material layer 700 from the gating layer 100. Another example is that the buffer layer 600 isolates the phase-change material layer 700 from the corresponding electrode.

[0108] The number of buffer layers 600 and their arrangement between the layers can be determined according to the relative arrangement of the gate layer 100 , the phase change layer and the electrodes in the memory sub-unit.

[0109] For example, Figure 5 illustrates the structure of a memory subunit, which includes a gate layer 100, a buffer layer 600, a phase-change material layer 700, a top electrode 300, a bottom electrode 200, an insulating dielectric 400, and a substrate 500. There are three buffer layers 600. From top to bottom, the top electrode 300, buffer layer 600, phase-change material layer 700, buffer layer 600, gate layer 100, buffer layer 600, bottom electrode 200, and substrate 500 are stacked in sequence.

[0110] Figure 6 illustrates the structure of another memory sub-cell, which includes a gate layer 100, a buffer layer 600, a phase-change material layer 700, a top electrode 300, a bottom electrode 200, an intermediate electrode 800, an insulating dielectric 400, and a substrate 500. Four buffer layers 600 are provided. From top to bottom, the top electrode 300, buffer layer 600, phase-change material layer 700, buffer layer 600, intermediate electrode 800, buffer layer 600, gate layer 100, buffer layer 600, bottom electrode 200, and substrate 500 are stacked in sequence.

[0111] In the embodiment of the present disclosure, the buffer layer material is selected from at least one of amorphous carbon materials, MoTe2, MoS2, MnTe, HfO2 / TaO, HfO2 / HfZrO / TaO, Al2O3, WTe2, WS2, and TiNO.

[0112] Amorphous carbon substances can be pure amorphous carbon or amorphous carbon compounds including amorphous carbon and doping elements, such as Si, Te, S, etc. For example, a compound composed of amorphous carbon and Si elements can be defined as a C-Si compound, and a compound composed of amorphous carbon and Te and S elements can be defined as a C-(Te, S) compound.

[0113] The buffer layer prepared using the above-mentioned buffer material can effectively prevent the element migration or segregation of the gate tube material and the phase change material in the direction of the electric field, reduce the diffusion of elements in the gate tube material and the phase change material, and ensure the thermal stability and cycle life of the gate layer and the phase change material layer.

[0114] The thickness of the gate layer in the phase-change memory chip can be determined according to the size of the operating voltage or operating current corresponding to the gate transistor unit. Exemplarily, the thickness of the gate layer is 5nm-100nm, including but not limited to: 5nm, 10nm, 15nm, 20nm, 21nm, 22nm, 23nm, 24nm, 25nm, 26nm, 27nm, 28nm, 29nm, 30nm, 31nm, 32nm, 33nm, 34nm, 35nm, 36nm, 37nm, 38nm, 39nm, 40nm, 41nm, 42nm, 43nm, 44nm, 45nm, 46nm, 47nm, 48nm, 49nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, etc.

[0115] The thickness of the buffer layer in the phase change memory chip can be determined based on factors such as resistance, leakage current, and threshold voltage. For example, the thickness of the buffer layer is 5nm-20nm, including but not limited to: 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm, 20nm, etc.

[0116] The phase change materials used in the phase change material layer mentioned above are, for example, Ge-Te binary compounds, Sb-Te binary compounds (for example, Sb2Te3), Bi-Te binary compounds, Ge-Sb-Te ternary compounds, Ti-Sb-Te ternary compounds, Ga-Sb binary compounds, Sb, etc.

[0117] The substrate mentioned above may be a semiconductor substrate, and its material includes but is not limited to: silicon dioxide, silicon carbide, silicon wafer, sapphire, diamond, etc.

[0118] The electrode materials used for the top electrode, bottom electrode, and middle electrode mentioned above include, but are not limited to, at least one of platinum (Pt), tungsten (W), gold (Au), Ru (ruthenium), aluminum (Al), titanium tungsten (TiW), titanium nitride (TiN), TaN (tantalum nitride), IrO2 (iridium dioxide), ITO (indium tin oxide), and IY2O (indium zinc oxide). The electrode materials used for the top electrode, bottom electrode, and middle electrode may be the same or different.

[0119] The insulating materials used in the above-mentioned insulating medium include but are not limited to: silicon dioxide (SiO2), silicon nitride (Si3N4), etc.

[0120] In some examples, the phase-change memory chip provided by the embodiments of the present disclosure is a memory-level phase-change memory chip.

[0121] On the other hand, the embodiments of the present disclosure also provide a method for preparing any of the above-mentioned phase change memory chips, wherein other layers in the phase change memory chip except the substrate, such as the selection layer, the buffer layer, the phase change material layer, the top electrode and the bottom electrode, can all be formed by a thin film deposition process.

[0122] Some applicable thin film deposition processes include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), etc.

[0123] Magnetron sputtering is a common physical vapor deposition process. In the embodiments of the present disclosure, the magnetron sputtering process can be used to prepare various layers in the phase change memory chip.

[0124] The magnetron sputtering parameters corresponding to each layer are determined according to the specific layer. Taking the preparation of the gating layer as an example, some applicable magnetron sputtering parameters are as follows: the background vacuum degree is 1×10 -4 Pa~5×10 -5Pa; sputtering gas pressure is 0.4 Pa to 0.8 Pa, for example, 0.5 Pa to 0.6 Pa; RF power is 30 W to 100 W; sputtering power is 7 W to 50 W; sputtering gas includes but is not limited to at least one of argon, krypton, xenon, neon, and nitrogen, for example, argon Ar is selected as the sputtering gas. The magnetron sputtering method can be DC magnetron sputtering or RF magnetron sputtering.

[0125] For the preparation of the gating layer, according to the existing form of the gating tube material, one or more combinations of alloy targets, compound targets, and single-substance targets can be used for co-sputtering to obtain a gating layer with a desired composition.

[0126] On the other hand, an embodiment of the present disclosure further provides a storage device, as shown in FIG7 , which includes a controller 001 and at least one phase-change memory chip 002 , where the phase-change memory chip 002 is as shown above, and the controller 001 is used to store data in the phase-change memory chip 002 .

[0127] The controller 001 reads and writes data stored in the storage device and communicates with the external interface. The storage device (also known as memory) can be configured to store various types of data, such as contact data, phone book data, messages, pictures, videos, etc., as well as instructional data.

[0128] The storage devices involved in the embodiments of the present disclosure can be configured into various types, for example, including but not limited to: memory, hard disk, magnetic disk, optical disk, etc.

[0129] On the other hand, an embodiment of the present disclosure further provides an electronic device, which includes a processor and the above-mentioned storage device, and the processor is used to store data generated by the electronic device in the storage device.

[0130] In some examples, the electronic device includes, but is not limited to, computers, mobile phones, music playing devices, digital broadcasting devices, messaging devices, game control devices, medical devices, fitness equipment, personal digital assistants, and the like.

[0131] The present disclosure will be further described below through more specific examples. Although some specific embodiments are described below, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the examples set forth herein. Where specific techniques or conditions are not specified in the examples, the techniques or conditions described in the literature in the art or in accordance with the product instructions are used. Where the manufacturer of the reagents or instruments is not specified, they may be conventional products that can be obtained commercially.

[0132] Example 1

[0133] This embodiment 1 provides a gate tube material and a series of gate tube devices prepared based on the gate tube material, wherein the chemical formula of the gate tube material is (Zn 0.3775 Te 0.6225 ) 0.959 Ge 0.041 .

[0134] The gate transistor device (i.e., the gate transistor unit described above) has a T-shaped structure, as shown in FIG3 , and includes: a substrate 500, a bottom electrode 200, a gate layer 100, a buffer layer 600, a top electrode 300, and an insulating dielectric 400. The insulating dielectric 400 is stacked on the substrate 500 and has a receiving hole. The bottom electrode 200 is received in the receiving hole and is flush with the insulating dielectric 400. The gate layer 100 is stacked on the bottom electrode 200 and supported by the insulating dielectric 400. The buffer layer 600 is stacked on the gate layer 100, and the top electrode 300 is stacked on the buffer layer 600.

[0135] Among them, the substrate is a silicon wafer, the bottom electrode and the top electrode are both made of metal W, the thickness of the top electrode is 80nm, the thickness of the bottom electrode is 300nm, the material of the insulating medium is silicon dioxide, the thickness of the gate layer is 25nm, and the material of the buffer layer is pure amorphous carbon.

[0136] The preparation method of a series of gate tube devices in Example 1 is as follows:

[0137] An insulating dielectric is deposited on a cleaned silicon wafer substrate using a plasma-enhanced chemical vapor deposition process. The dielectric is then etched using an inductively coupled plasma etching system to form a receiving hole. The hole has a diameter of 80nm-300nm and a depth of 300nm, corresponding to gate devices with different bottom electrode sizes. The bottom electrode material is deposited into the hole using a physical vapor deposition process to fill the hole. Chemical mechanical polishing is then used to level the bottom electrode material with the insulating dielectric layer, forming the bottom electrode.

[0138] Based on the gate tube material (Zn 0.3775 Te 0.6225 ) 0.959 Ge 0.041 , using Zn target and Ge5Te in atomic percentage 95 A 25nm-thick gate layer is deposited on the surface of the bottom electrode and the insulating dielectric by co-sputtering. A buffer layer and a top electrode layer are then sequentially deposited on the gate layer by physical vapor deposition. A square top electrode is formed by photolithography and etching to fabricate each gate transistor device.

[0139] The prepared series of gate transistor devices were annealed at 400° C. for 30 minutes, and electrical tests were performed on the annealed gate transistor devices. The test results are shown in FIG8 to FIG10 .

[0140] FIG8 is a leakage current distribution diagram of a series of gate transistor devices provided in Example 1 after annealing. As shown in FIG8 , the average value of the leakage current of this series of gate transistor devices is mainly at 10 -1 About μA, which meets the operating requirements of the gate tube device.

[0141] FIG9 is a cycle characteristic diagram of the gate transistor device with a bottom electrode diameter of 100 nm in Example 1 after annealing. As shown in FIG9 , the number of cycles of the gate transistor device after annealing can reach 10 7 It can be seen that the gate tube device has excellent cycle life and high fatigue characteristics, which enables it to match the repeated erase and write process of the phase change memory unit and ensure the long life of the phase change memory chip.

[0142] FIG10 is a schematic diagram showing the distribution relationship between the threshold voltage and the number of cycles of the gate transistor device having a bottom electrode diameter of 100 nm after annealing in Example 1. As shown in FIG10 , after the gate transistor device undergoes the annealing operation, its threshold voltage can remain stable during the cycling process. It can be seen that the gate transistor device has strong electrical stability, and its threshold voltage is conducive to matching with the phase change memory unit or the peripheral CMOS circuit, making the gate transistor device potentially applicable to integration.

[0143] Example 2

[0144] This embodiment 2 provides another gate tube material and a series of gate tube devices with different bottom electrode sizes prepared based on the gate tube material. In terms of atomic percentage, the chemical formula of the gate tube material is (Zn 0.5016 Te 0.4984 ) 0.929 C 0.042 Ge 0.029 .

[0145] The structure of the gate transistor device in Example 2 is the same as that in Example 1, except that the material of the gate layer is different. The material of the gate layer in the gate transistor device is (Zn 0.5016 Te 0.4984 ) 0.929 C 0.042 Ge 0.029 Material.

[0146] The preparation method of the gate tube device in Example 2 can refer to the preparation method of the gate tube device described in Example 1, except that when depositing the gate layer, based on the gate tube material being (Zn 0.5016 Te 0.4984) 0.929 C 0.042 Ge 0.029 , using Zn target, Ge5Te in atomic percentage 95 The target material and the C single-element target material are used to deposit a gating layer into the receiving hole based on a co-sputtering process.

[0147] The prepared series of gate transistor devices were annealed at 400° C. for 30 minutes, and electrical tests were performed on the annealed gate transistor devices. The test results are shown in FIG11 to FIG14 .

[0148] FIG11 is a threshold voltage distribution diagram of a series of gate transistor devices provided in Example 2 after annealing. As shown in FIG11 , the threshold voltage of the gate transistor device is mainly distributed between 4V and 5V. This threshold voltage range enables the gate transistor device to meet the requirement of matching the threshold voltage of the phase change memory cell.

[0149] FIG12 is a leakage current distribution diagram of a series of gate transistor devices provided in Example 2 after annealing. As shown in FIG12 , the leakage current of the gate transistor device is mainly distributed in 10 -2 The leakage current is low, which enables the gate transistor device to effectively suppress the leakage current in the phase change memory array to ensure the realization of high-density memory chips.

[0150] FIG13 is a cycle characteristic diagram of the gate transistor device with a bottom electrode diameter of 100 nm in Example 2 after annealing. As shown in FIG13 , the number of cycles of the gate transistor device after annealing can reach 10 7 It can be seen that the gate tube device has excellent cycle life and high fatigue characteristics, which enables it to match the repeated erase and write process of the phase change memory unit and ensure the long life of the phase change memory chip.

[0151] FIG14 is a schematic diagram showing the distribution relationship between the threshold voltage and the number of cycles of the gate transistor device having a bottom electrode diameter of 100 nm after annealing in Example 2. As shown in FIG14 , after the gate transistor device undergoes the annealing operation, its threshold voltage can remain stable during the cycling process. It can be seen that the gate transistor device has strong electrical stability, and its threshold voltage is conducive to matching with the phase change memory unit or the peripheral CMOS circuit, making the gate transistor device potentially applicable to integration.

[0152] Example 3

[0153] This embodiment 3 provides a gate tube material and a gate tube device prepared based on the gate tube material, wherein the chemical formula of the gate tube material is (Zn 0.4963 Te 0.5037 ) 0.939 C 0.031 Ge0.03 .

[0154] The structure of the gate transistor device in Example 3 is the same as that in Example 1, except that the material of the gate layer is different. The material of the gate layer in the gate transistor device is (Zn 0.4963 Te 0.5037 ) 0.939 C 0.031 Ge 0.03 Furthermore, the diameter of the bottom electrode of the gate device in Example 3 is 100 nm.

[0155] The preparation method of the gate tube device in Example 3 can refer to the preparation method of the gate tube device described in Example 1, except that when depositing the gate layer, based on the gate tube material being (Zn 0.4963 Te 0.5037 ) 0.939 C 0.031 Ge 0.03 , using Zn target, Ge5Te in atomic percentage 95 The target material and the C single-element target material are used to deposit a gating layer into the receiving hole based on a co-sputtering process.

[0156] The prepared gate transistor device was annealed at 400° C. for 30 minutes, and electrical tests were performed on the annealed gate transistor device. The test results are shown in FIG. 15 to FIG. 18 .

[0157] FIG15 is a current-voltage characteristic curve of the gate transistor device provided in Example 3 after annealing treatment, wherein the horizontal axis represents the threshold voltage in V, and the vertical axis represents the current in μA. As can be seen from FIG15 , the threshold voltage of the gate transistor device is 3.2 V. This threshold voltage range enables the gate transistor device to meet the requirement of matching the threshold voltage of the phase change memory cell.

[0158] FIG16 is a leakage current distribution diagram of the gate transistor device provided in Example 3 after annealing. As shown in FIG16 , the average leakage current of the gate transistor device is less than 10 nA. The low leakage current enables the gate transistor device to effectively suppress the leakage current in the phase change memory array to ensure the realization of a high-density memory chip.

[0159] FIG17 is a cycle characteristic diagram of the gate transistor device provided in Example 3 after annealing. As shown in FIG17 , the number of cycles of the gate transistor device after annealing can reach 10. 10 It can be seen that the gate tube device has excellent cycle life and high fatigue characteristics, which enables it to match the repeated erase and write process of the phase change memory unit and ensure the long life of the phase change memory chip.

[0160] FIG18 is a schematic diagram showing the distribution relationship between the threshold voltage and the number of cycles of the gate transistor device provided in Example 3 after annealing. As shown in FIG18 , after the gate transistor device undergoes the annealing operation, its threshold voltage can remain stable during the cycle process. It can be seen that the gate transistor device has strong electrical stability, and its threshold voltage is conducive to matching with the phase change memory unit or the peripheral CMOS circuit, making the gate transistor device potentially applicable to integration.

[0161] Example 4

[0162] This embodiment 4 provides a series of gate tube materials and gate tube devices prepared based on these gate tube materials, wherein, in terms of atomic percentage, the chemical formulas of this series of gate tube materials are: (Zn 0.4575 Te 0.5425 ) 0.935 B 0.065 ;(Zn 0.5101 Te 0.4899 ) 0.922 C 0.07 ;(Zn 0.4711 Te 0.5289 ) 0.912 B 0.065 Sn 0.023 ;(Zn 0.55 Te 0.45 ) 0.904 C 0.069 Si 0.027 ;(Ca 0.357 Te 0.643 ) 0.928 Ge 0.072 ;(Ca 0.344 Te 0.656 ) 0.9 O 0.1 ;(Ca 0.31 Te 0.69 ) 0.95 C 0.05 ;(Ca 0.41 Te 0.59 ) 0.92 B 0.08 ;(Ca 0.45 Te 0.55 ) 0.928 C 0.044 Se 0.028 ;(Ca 0.461 Te 0.539 ) 0885 O 0.085 Se 0.03 ;(Ca 0.471 Te 0.529 ) 0.9 B 0.08 Ge 0.02.

[0163] The manufacturing methods of the above-mentioned gate transistor devices can refer to the manufacturing method of the gate transistor device described in Example 1, except that different gate transistor materials are used when depositing the gate layer. In addition, the diameter of the bottom electrode of the gate transistor device in Example 4 is 100 nm.

[0164] The prepared gate transistor devices were annealed at 400℃ for 30 minutes and then subjected to electrical testing. The test results showed that this series of gate transistor devices all met the following requirements: the leakage current density values ​​were all lower than 250A / cm 2 ; The number of cycles is greater than 10 7 Secondly, it can match the repeated erasing and writing process of the phase change memory unit, ensuring the long life of the phase change memory chip; the threshold voltage can remain stable during the cycle process, and the electrical stability is strong.

[0165] The above description is only for the purpose of facilitating those skilled in the art to understand the technical solutions of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A gate tube material, wherein: The chemical formula of the gate tube material is (A x Te 1-x ) 1-y B y ; The element A is selected from Zn or Ca; the element B is selected from at least one of Ge, B, C, N, O, Si, P, Al, Sn, Se, and S; Wherein, x and y are both atomic percentages, 0.3≤x<0.6, 0<y≤0.

15.

2. The gate tube material according to claim 1, wherein: The element B is a single element, and the element B is selected from one of Ge, B, C, N, O, Si, and P.

3. The gate tube material according to claim 1, wherein: The element B includes element B1 and element B2. The chemical formula of the gate tube material is (A x Te 1-x ) 1-y1-y2 B1 y1 B2 y2 ; The element B1 is selected from one of Ge, B, C, N, O, Si and P; The element B2 is different from the element B1, and the element B2 is selected from one of Ge, Si, Al, Sn, Se, and S; x, y1 and y2 are all atomic percentages, 0.45≤x≤0.55, 0.01≤y1≤0.1, 0<y2≤0.

05.

4. The gate tube material according to any one of claims 1 to 3, wherein: The element A is a Zn element, and 0.45≤x≤0.

55.

5. A phase change memory chip, wherein: The phase-change memory chip comprises a plurality of memory sub-units, each of which comprises a gate tube unit and a phase-change memory unit connected in series; Each of the gate tube units comprises a gate layer, and the gate layer is prepared by using the gate tube material according to any one of claims 1 to 4.

6. The phase change memory chip according to claim 5, wherein: The gate tube unit is integrated with the phase change memory unit.

7. The phase change memory chip according to claim 5, wherein: The gate tube unit and the phase change memory unit are independent of each other.

8. The phase change memory chip according to any one of claims 5 to 7, wherein: At least one of the gate tube unit and the phase change memory unit further comprises a buffer layer, and at least one of the gate layer and the phase change material layer of the phase change memory unit is stacked with the buffer layer; The buffer layer material is selected from at least one of amorphous carbon materials, MoTe2, MoS2, MnTe, HfO2 / TaO, HfO2 / HfZrO / TaO, Al2O3, WTe2, WS2, and TiNO.

9. A storage device, wherein: The storage device includes a controller and at least one phase change memory chip, wherein the phase change memory chip is as described in any one of claims 5 to 8, and the controller is used to store data in the phase change memory chip.

10. An electronic device, wherein: The electronic device comprises a processor and the storage device according to claim 9, wherein the processor is used to store data generated by the electronic device in the storage device.

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