Pseudo-synchronous successive approximation register (SAR) analog-to-digital converter

Abstract

A system includes an analog-to-digital converter (ADC). The ADC includes a comparator having a first output and a second output, a successive approximation register (SAR) coupled to at least one of the first output of the comparator and the second output of the comparator, one or more digital-to-analog converters (DACs) coupled between the SAR and the comparator, and a compare detector coupled to the first output of the comparator, the second output of the comparator, and a reset input of the comparator. The system also includes an enable control circuit coupled to an enable input of the comparator.

Description

PSEUDO-SYNCHRONOUS SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERCROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to and the benefit of Application Serial No. 20230100707 filed in the Greece Patent Office on September 4, 2023, the entire content of which is incorporated herein as if fully set forth below in its entirety and for all applicable purposes.BACKGROUNDField

[0002] Aspects of the present disclosure relate generally to analog-to-digital converters (ADCs), and more particularly, to successive approximation register (SAR) ADCs.Background

[0003] An analog-to-digital converter (ADC) is used to convert an analog signal into a digital signal. One type of ADC is the successive approximation register (SAR) ADC, which converts an analog input signal into a digital signal using successive digital approximation.SUMMARY

[0004] The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations and is intended to neither identify key or critical elements of all implementations nor delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later.

[0005] A first aspect relates to a system. The system includes an analog-to-digital converter (ADC). The ADC includes a comparator having a first output and a second output, a successive approximation register (SAR) coupled to at least one of the first output of the comparator and the second output of the comparator, one or more digital-to-analog converters (DACs) coupled between the SAR and the comparator, and a compare detector coupled to the first output of the comparator, the second output of the comparator, and areset input of the comparator. The system also includes an enable control circuit coupled to an enable input of the comparator.

[0006] A second aspect relates to a system. The system includes multiple analog-to-digital converters (ADCs). Each one of the ADCs includes a respective comparator having a first output and a second output, a respective successive approximation register (SAR) coupled to at least one of the first output of the respective comparator and the second output of the respective comparator, respective one or more digital-to-analog converters (DACs) coupled between the respective SAR and the respective comparator, and a respective compare detector coupled to the first output of the respective comparator, the second output of the comparator, and a reset input of the respective comparator. The system also includes an enable control circuit coupled to the ADCs, wherein the enable control circuit is configured to enable the respective comparator of each of the ADCs.

[0007] A third aspect relates to a method of operating an analog-to-digital converter (ADC). The ADC includes a comparator, a successive approximation register (SAR) coupled to the comparator, and one or more digital-to-analog converters (DACs) coupled to the SAR and the comparator. The method includes receiving a clock signal, enabling the comparator multiple times to perform multiple comparisons during a conversion period based on the clock signal, detecting comparison completions for the multiple comparisons during the conversion period, and resetting the comparator for each of the detected comparison completions.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1A shows an example of a system including an ADC according to certain aspects of the present disclosure.

[0009] FIG. IB shows another example of a system including an ADC according to certain aspects of the present disclosure.

[0010] FIG. 2 shows an example of a SAR ADC according to certain aspects of the present disclosure.

[0011] FIG. 3 is a plot showing an example of a digital-to-analog converter (DAC) voltage in the SAR ADC over multiple cycles according to certain aspects of the present disclosure.

[0012] FIG. 4 shows an example of a synchronous SAR ADC according to certain aspects of the present disclosure.

[0013] FIG. 5 is a timing diagram showing exemplary signals in the synchronous SAR ADC according to certain aspects of the present disclosure.

[0014] FIG. 6 shows an example of an asynchronous SAR ADC according to certain aspects of the present disclosure.

[0015] FIG. 7 is a timing diagram showing an example of an enable signal in the asynchronous SAR ADC according to certain aspects of the present disclosure.

[0016] FIG. 8 shows an example of a pseudo-synchronous SAR ADC according to certain aspects of the present disclosure.

[0017] FIG. 9 shows an exemplary implementation of a compare detector according to certain aspects of the present disclosure.

[0018] FIG. 10 shows an exemplary implementation of a comparator according to certain aspects of the present disclosure.

[0019] FIG. 11 A is a timing diagram showing an example of an enable signal in the comparator of FIG. 10 according to certain aspects of the present disclosure.

[0020] FIG. 1 IB is a timing diagram showing an example in which a comparison is not done within a time delay according to certain aspects of the present disclosure.

[0021] FIG. 12 shows an example in which the SAR ADC includes an edge detector according to certain aspects of the present disclosure.

[0022] FIG. 13 shows an example in which a DAC in the SAR ADC is implemented with a capacitive DAC according to certain aspects of the present disclosure.

[0023] FIG. 14 shows an example of a differential SAR ADC according to certain aspects of the present disclosure.

[0024] FIG. 15 shows an example in which multiple instances of a SAR ADC are coupled to an enable control circuit according to certain aspects of the present disclosure.

[0025] FIG. 16 is a flowchart illustrating an exemplary method of operating an ADC according to certain aspects of the present disclosure.

[0026] FIG. 17 is a flowchart illustrating another exemplary method of operating an ADC according to certain aspects of the present disclosure.DETAILED DESCRIPTION

[0027] The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. Thedetailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0028] An analog-to-digital converter (ADC) may be used in a system to convert an analog signal into a digital signal. For example, FIG. 1A shows an example of a system 110 including an ADC 140 according to certain aspects. The ADC 140 is configured to convert an analog signal at an input 142 of the ADC 140 into a digital signal at an output 144 of the ADC 140. The system 110 also includes a receiver 130 coupled to the input 142 of the ADC 140, and a processor 150 coupled to the output 144 of the ADC 140. In this example, the system 110 may be part of a wireless communication device (e.g., a handset). Although one ADC 140 is shown in FIG. 1A for simplicity, it is to be appreciated that the system 110 may include multiple ADCs.

[0029] The receiver 130 may be coupled to one or more antennas 120, and may be configured to receive a radio frequency (RF) signal via the one or more antennas 120. The RF signal may be transmitted from a base station, an access point, or another wireless communication device. The receiver 130 may be configured to process the received RF signal into an analog baseband signal, and output the analog baseband signal to the ADC 140 for digital conversion. Processing performed by the receiver 130 may include frequency down-conversion, filtering, amplification, etc. The ADC 140 converts the analog baseband signal into a digital signal, and outputs the digital signal to the processor 150. The processor 150 may process the digital signal to recover data from the digital signal and process the recovered data. Processing performed by the processor 150 may include demodulation, decoding, etc. The processor 150 may include a processor core, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, or any combination thereof. In this example, the processor 150 may also be referred to as a modem, a baseband processor, or another term.

[0030] It is to be appreciated that the system 110 is not limited to wireless communications. In this regard, FIG. IB shows an example in which the receiver 130 is coupled to wireline 165 (i.e., wired link), and is configured to receive an analog signal via the wireline 165. The wireline 165 may include one or more metal traces, one or more metal wires, a cable, an optical fiber, or any combination thereof. In this example, the wireline 165 may beused to provide communication between a device 160 and the processor 150, in which a transmit driver (not shown) in the device 160 transmits the analog signal to the receiver 130 over the wireline 165. The device 160 may include a peripheral device, a sensor device, or another type of device.

[0031] In this example, the receiver 130 may process the analog signal from the wireline 165 into a processed analog signal, and output the processed analog signal to the ADC 140 for digital conversion. In this example, processing performed by the receiver 130 may include amplification, equalization, etc. The ADC 140 converts the processed analog signal into a digital signal, and outputs the digital signal to the processor 150. The processor 150 may then process the digital signal to recover data from the digital signal and process the recovered data.

[0032] The ADC 140 in FIGS. 1A and IB may be implemented with a successive approximation register (SAR) ADC. In this regard, FIG. 2 shows a simplified block diagram of an example of a SAR ADC 210 according to aspects of the present disclosure. The SAR ADC 210 is configured to receive an analog input voltage (labeled “Vin”) at an input 212, convert the analog input voltage Vin into a digital signal, and output the digital signal at an output 215. The digital signal includes bits providing a digital representation of the analog input voltage Vin. For the example where the SAR ADC 210 implements the ADC 140 shown in FIG. 1, the input 212 corresponds to the input 142 and the output 215 corresponds to the output 144.

[0033] The SAR ADC 210 includes a sample and hold circuit 220, a comparator 230, an SAR 240 (also referred to as SAR logic or another term), and a digital-to-analog converter (DAC) 250. The comparator 230 has a first input 232, a second input 234, and an output 236. The comparator 230 is configured to compare the voltage at the first input 232 with the voltage at the second input 234, and output a compare signal at the output 236 based on the comparison, as discussed further below. The first input 232 and the second input 234 may also be referred to as a first compare input and a second compare input, respectively, since the comparator 230 is configured to compare the voltages at the first and second inputs 232 and 234.

[0034] The sample and hold circuit 220 has an input 222 coupled to the input 212 of the SAR ADC 210 and an output 224 coupled to the second input 234 of the comparator 230. The sample and hold circuit 220 is configured to sample the analog input voltage Vin at the input 212 of the SAR ADC 210, and hold the sampled input voltage Vin at the second input 234 of the comparator 230.

[0035] The SAR 240 has an input 242 coupled to the output 236 of the comparator 230, a first output 244 coupled to the output 215 of the SAR ADC 210, and a second output 246. TheDAC 250 has an input 252 coupled to the second output 246 of the SAR 240 and an output 254 coupled to the first input 232 of the comparator 230. The DAC 250 may be an n-bit DAC configured to receive an n-bit digital signal from the SAR 240 at the input 252, convert the n-bit digital signal into a DAC voltage (labeled “Vdac”), and output the DAC voltage Vdac to the first input 232 of the comparator 230 via the output 254. The DAC250 may receive a reference voltage Vref, and generate the DAC voltage Vdac based on the reference voltage Vref and the digital signal based on the following:where Vref is the reference voltage, and bn-i to bo are the n bits of the digital signal from the SAR 240. In this example, bn-i is the most significant bit (MSB) and bo is the least significant bit (LSB). It is to be appreciated that the DAC voltage Vdac is not limited to the example given in equation (1). The DAC 250 may be implemented with a capacitive DAC (C-DAC) or another type of DAC. For the example of a C-DAC, the sample and hold function may be incorporated into the C-DAC. In this example, the sample and hold circuit 220 shown in FIG. 2 may be omitted.

[0036] The comparator 230 is configured to compare the sampled input voltage Vin with the DAC voltage Vdac, and output a compare signal at the output 236, in which the logic value (i.e., logic state) of the compare signal indicates whether the sampled input voltage Vin is greater than or less than the DAC voltage Vdac. In one example, the compare signal is one if the sampled input voltage Vin is greater than the DAC voltage Vdac, and the compare signal is zero if the sampled input voltage Vin is less than the DAC voltage Vdac. The SAR 240 is configured to convert the sampled input voltage Vin into a digital value at the output 215 using the comparator 230 and the DAC 250, as discussed further below.

[0037] The SAR ADC 210 is configured to convert the input voltage Vin into a digital signal in an analog-to-digital conversion operation. To convert the input voltage Vin into the digital signal, the sample and hold circuit 220 samples the input voltage Vin at the input 212 of the SAR ADC 210. The sample and hold circuit 220 then holds the sampled input voltage Vin at the second input 234 of the comparator 230 during a conversion period (also referred to as a conversion phase).

[0038] During the conversion period, the SAR 240 converts the sampled input voltage Vin into a digital signal at the output 215 using the comparator 230 and the DAC 250. To do this, the SAR 240 may output a digital signal to the DAC 250, and sequentially resolve the bits bn-i to bo of the digital signal over n cycles during the conversion period based on the compare signal from the output 236 of the comparator 230 utilizing a binary search. The SAR 240 starts the binary search with the MSB bn-i.

[0039] The SAR 240 resolves the MBS bn-i during a first one of the cycles. To resolve the MSB bn-i, the SAR 240 sets the MSB bn-i to one and the remaining bits bn-2 to bo to zero. This causes the DAC 250 to output a voltage of VzVref to the first input 232 of the comparator 230 (i.e., Vdac = l^Vref). The SAR 240 then resolves the MSB bn-i based on the output of the comparator 230. If the compare signal is one (i.e., the sampled input voltage Vin is greater than Vi V ref), then the SAR 240 resolves the MSB bn-i to a bit value of one. If the compare signal is zero (i.e., the sampled input voltage Vin is less than ViVref), then the SAR 240 resolves the MSB bn-i to a bit value of zero.

[0040] After resolving the MSB bn-i, the SAR 240 resolves the second most significant bit bn-2 during a second one of the cycles. To resolve bit bn-2, the SAR 240 sets the MSB bn-i to its resolved bit value, sets bit bn-2 to one, and sets the remaining bits bn-3 to bo to zero. The SAR 240 then resolves bit bn-2 based on the output of the comparator 230. If the compare signal is one, then the SAR 240 resolves bit bn-2 to a bit value of one. If the compare signal is zero, then the SAR 240 resolves bit bn-2 to a bit value of zero.

[0041] The SAR 240 may repeat the above process for each of the remaining bits bn-3 to bo to resolve the remaining bits bn-3 to bn. In this example, the SAR 240 resolves all n bits bn-i to bo over the n cycles during the conversion period. After all n bits bn-i to bo have been resolved, the SAR 240 may output a digital signal (also referred to as a digital code) at the output 215 including the resolved bits bn-i to bo. The SAR ADC 210 may perform the analog-to-digital conversion discussed above periodically to track the input voltage Vin over time.

[0042] FIG. 3 shows an example of the DAC voltage Vdac over n cycles for an exemplary input voltage Vin. For simplicity, the digital signal has four bits (i.e., n=4) in this example where bit b3 is the MSB and bit bo is the LSB. However, it is to be appreciated that the digital signal may have a larger number of bits (i.e., n > 4). As shown in FIG. 3, the SAR ADC 210 resolves one bit of the digital signal during each one of the n cycles starting with the MSB and ending with the LSB. At the end of the n cycles, the DAC voltage Vdac is close to the input voltage Vin.

[0043] In certain aspects, the SAR ADC 210 may be synchronous in which operations of the SAR ADC 210 are timed based on a timing signal (e.g., clock signal). In this regard, FIG. 4 shows an example in which the SAR ADC 210 includes a control circuit 410 configured to receive a clock signal (labeled “elk”), and operate the SAR ADC 210 synchronously based on the clock signal elk (also referred to as the root ADC clock, the sampling clock, or another term).

[0044] In the example shown in FIG. 4, the control circuit 410 is coupled to the sample and hold circuit 220 and the SAR 240. The control circuit 410 is also coupled to an enable input 412 of the comparator 230 to control enabling of the comparator 230 using an enable signal. For example, the comparator 230 may be enabled when the enable signal is high (i.e., logic one) and disabled when the enable signal is low (i.e., logic zero), or vice versa. When the comparator 230 is disabled, the comparator 230 may reset for the next comparison.

[0045] During each period of the clock signal elk, the control circuit 410 is configured to cause the sample and hold circuit 220 to sample the input voltage Vin, and hold the sampled input voltage Vin at the second input 234 of the comparator 230. In this example, the conversion period discussed above is within one period of the clock signal elk.

[0046] While the sample and hold circuit 220 holds the sampled input voltage Vin at the second input 234 of the comparator 230 during the conversion period, the control circuit 410 enables the comparator 230 during each one of the n cycles discussed above. Since there are n cycles during the conversion period, the control circuit 410 sequentially enables the comparator 230 n times during the conversion period. Each time the control circuit 410 enables the comparator 230 for one of the n cycles, the SAR 240 configures the DAC voltage (labeled “Vdac”) output by the DAC 250 and resolves one of the n bits bn-i to bo of the digital signal based on the compare signal from the comparator 230.

[0047] FIG. 5 shows a timing diagram illustration an example of synchronous operation of the SAR ADC 210 according to certain aspects. FIG. 5 shows an example of one conversion period, which may be within one period of the clock signal elk. FIG. 5 also shows an example of the enable signal from the control circuit 410. In this example, the enable signal includes n pulses within the conversion period where each one of the n pulses corresponds to one of the n cycles discussed above. The comparator 230 is enabled during each one of the pulses and the comparator 230 is reset between the pulses. Each time the comparator 230 is enabled by the enable signal, the comparator 330 compares the sampledinput voltage Vin with the DAC voltage Vdac, and outputs the compare signal based on the comparison to the SAR 240.

[0048] In the example in FIG. 5, the SAR 240 updates the DAC control (and hence updates the DAC voltage Vdac) after each pulse of the enable signal based on the compare signal from the comparator 230. As shown in FIG. 5, the DAC voltage Vdac is close to the sampled input voltage after the last pulse of the enable signal, which corresponds to the last one of the n cycles.

[0049] As shown in FIG. 5, the control circuit 410 enables the comparator 230 n times during the conversion period, and therefore, runs n times faster than the clock signal elk (also referred to as the root ADC clock). Because the control circuit 410 runs n times faster than the clock signal elk, the control circuit 410 is power hungry. This can lead to a large amount of power consumption when the system 110 includes multiple instances (i.e., copies) of the SAR ADC 210 where each instance of the SAR ADC 210 includes a separate instance (i.e., copy) of the control circuit 410. In this example, the multiple instances (i.e., copies) of the control circuit 410 running at n times the frequency of the clock signal elk reduce the power efficiency of the system 110.

[0050] In certain aspects, the SAR ADC 210 may be asynchronous in which operations of the comparator 230 is controlled asynchronously instead of timing operations of the comparator 230 based on a clock signal. In this regard, FIG. 6 shows an example in which the SAR ADC 210 includes a compare detector 630 and a control circuit 640 configured to operate the comparator 230 asynchronously, as discussed further below.

[0051] In this example, the output 236 of the comparator 230 includes a first output 612 and a second output 614. When the comparator 230 is done (i.e., finished) performing a comparison of the sampled input voltage Vin and the DAC voltage Vdac, the first output 612 and the second output 614 are complementary. For example, when the comparison is done, the first output 612 may be high (i.e., logic one) and the second output 614 may be low (i.e., logic zero) if the sampled input voltage Vin is greater than the DAC voltage Vdac, and the first output 612 may be low (i.e., logic zero) and the second output 614 may be high (i.e., logic one) if sampled input voltage Vin is less than the DAC voltage Vdac. In this example, both outputs 612 and 614 may be low when the comparator 230 resets. Alternately, both outputs 612 and 614 may be high when the comparator 230 resets.

[0052] In the example shown in FIG. 6, the input 242 of the SAR 240 may include a first input 622 and a second input 624, in which the first input 622 is coupled to the first output 612of the comparator 230 and the second input 624 is coupled to the second output 614 of the comparator 230. In this example, each time the comparator 230 performs a comparison of the sampled input voltage Vin and the DAC voltage Vdac, the SAR 240 may determine whether the sampled voltage Vin is greater than or less than the DAC voltage Vdac based on the first output 612 and / or the second output 614 of the comparator 230. For example, the SAR 240 may determine the sampled voltage Vin is greater than the DAC voltage Vdac if the first output 612 is high and the second output 614 is low.

[0053] Although the SAR 240 is coupled to both outputs 612 and 614 of the comparator 230 in the example shown in FIG. 6, it is to be appreciated that the SAR 240 may be coupled to just one of the outputs 612 and 614 of the comparator 230 in some implementations. This is because the SAR 240 may be able to determine whether the sampled voltage Vin is greater than the DAC voltage Vdac based on just one of the outputs 612 and 614 of the comparator 230 since the outputs 612 and 614 are complementary when the comparator 230 is done with a comparison. In other implementations, the SAR 240 may be coupled to both outputs 612 and 614 and use both outputs 612 and 614 to determine when the comparator 230 is done with a comparison.

[0054] In this example, the compare detector 630 and the control circuit 640 control the comparator 230 in an asynchronous manner, as discussed further below. The compare detector 630 is coupled the first output 612 and the second output 614 of the comparator 230. The control circuit 640 is coupled to the compare detector 630 and the enable input 412 of the comparator 230.

[0055] In this example, the compare detector 630 is configured to detect when the comparator 230 is done (i.e., finished) with a comparison based on the first output 612 and the second output 614 of the comparator 230. For example, the compare detector 630 may detect the comparison is done by detecting when the first output 612 and the second output 614 have different logic states (i.e., complementary logic states) using an exclusive or (XOR) gate or another type of logic gate. For the implementation where both outputs 612 and 614 are low (i.e., logic zero) when the comparator 230 is reset, the compare detector 630 may detect the comparison is done by detecting when one of the first output 612 and the second output 614 is high (i.e., logic one) using an OR gate, a NOR gate, or another type of logic gate. It is to be appreciated that the compare detector 630 is not limited to the examples given above.

[0056] When the compare detector 630 detects the comparator 230 is done with a comparison, the compare detector 630 outputs a signal to the control circuit 640 indicating thecomparison is done. In response to the signal, the control circuit 640 resets the comparator 230 for the next comparison. For the example where the comparator 230 is reset when the enable signal is low, the control circuit 640 may reset the comparator 230 by generating a falling edge of the enable signal. The compare detector 630 may also output the signal indicating the comparison is done to the SAR 240 so the SAR 240 can update the DAC 250 and resolve a bit of the digital signal based on the comparison.

[0057] In the example in FIG. 6, the control circuit 640 includes a delay circuit 645 configured to provide a time delay (e.g., programmable time delay). The delay circuit 645 may be implemented with multiple delay buffers coupled in a chain, or implemented with another type of delay circuit. In this example, when the control circuit 640 receives the signal from the compare detector 630 indicating the comparison is done, the control circuit 640 enables the comparator 230 after the time delay of the delay circuit 645 has elapsed. For the example where the comparator 230 is enabled when the enable signal is high, the control circuit 640 may enable the comparator 230 by generating a rising edge of the enable signal.

[0058] FIG. 7 shows a timing diagram illustrating an example of the enable signal in the exemplary implementation of the SAR ADC 210 shown in FIG. 6. In this example, each time the compare detector 630 detects a comparison is done, the control circuit 640 generates a falling edge of the enable signal to reset the comparator 230. Each time the comparator 230 is reset by a falling edge, the control circuit 640 generates the next rising edge of the enable signal to enable the comparator 230 after the time delay (labeled “At”) of the delay circuit 645 has elapsed. As shown in FIG. 7, each falling edge of the enable signal is separated from the next rising edge of the enable signal by the time delay of the delay circuit 645. Thus, in this example, the control circuit 640 times the enabling and resetting of the comparator 230 based on the comparator done detection signal from the compare detector 630 and the time delay of the delay circuit 645.

[0059] The control circuit 640 (which includes the delay circuit 645) can take up a relatively large area of the SAR ADC 210 and consumes current. When the system 110 includes multiple instances (i.e., copies) of the SAR ADC 210, each instance of the SAR ADC 210 includes a separate instance (i.e., copy) of the control circuit 640. In this case, the system 110 includes multiple instances of the control circuit 640, which can take up a large chip area and consume a large amount of current.

[0060] Aspects of the present disclosure provide a novel pseudo-synchronous SAR ADC in which the comparator 230 is enabled in a pseudo synchronous manner while thecomparator 230 is reset in an asynchronous manner depending on the speed of the comparator 230. The novel SAR ADC provides an additional degree of freedom when designing SAR ADCs. The novel SAR ADC also allows multiple instances (i.e., copies) of the SAR ADCs to share common control circuitry, which reduces area and reduces power consumption for low power applications. The above features and other features of the present disclosure are discussed further below.

[0061] FIG. 8 shows an exemplary pseudo-synchronous SAR ADC 810 according to aspects of the present disclosure. In this example, the SAR ADC 810 includes the comparator 230, the DAC 250, the SAR 240, and the sample and hold circuit 220 discussed above. As discussed above, the SAR 240 uses the DAC 250 and the output 236 of the comparator 230 to perform analog-to-digital conversion using successive approximation. Since the SAR 240, the comparator 230, and the DAC 250 are described in detail above, a detailed description of these components is not repeated here for brevity.

[0062] In this example, the comparator 230 has an enable input 812 and a reset input 814. In some implementations, the comparator 230 may be enabled when the comparator 230 receives a rising edge at the enable input 812 and reset when comparator 230 receives a falling edge at the reset input 814. However, it is to be appreciated that the present disclosure is not limited to this example. As used herein, an enable input is an input that controls enabling of the comparison function of a comparator (e.g., comparator 230), and a reset input is an input that controls resetting of the comparator.

[0063] In this example, the system 110 includes an enable control circuit 820 coupled to the enable input 812 of the comparator 230. The enable control circuit 820 is configured to control enabling of the comparator 230 in a pseudo-synchronous manner, as discussed further below. The enable control circuit 820 may be coupled to multiple instances of the SAR ADC 810, and therefore shared by the multiple instances of the SAR ADC 810. This allows common control circuitry to be used to control enabling of the multiple instances of the SAR ADC 810, which reduces area and power consumption.

[0064] During each conversion period, the enable control circuit 820 is configured to generate and output n rising edges to the enable input 812 of the comparator 230 to enable the comparator 230 n times. In certain aspects, the enable control circuit 820 receives the clock signal elk and triggers the first one of the rising edges based on the clock signal elk. For example, the enable control circuit 820 may trigger the first one of the rising edges on an edge (e.g., rising edge or falling edge) of the clock signal elk. The enable control circuit 820 may then space apart the remaining rising edges by a time delay. In this regard,the enable control circuit 820 may include a delay circuit 825 (e.g., a delay chain) to generate the time delay. In this example, the rising edges may be evenly spaced apart by the time delay. The time delay is shorter than one period of the clock signal elk so that the enable control circuit 820 is able to output the n rising edges within the conversion period.

[0065] In the example in FIG. 8, the SAR ADC 810 includes a compare detector 830 configured to control resetting of the comparator 230 in an asynchronous manner, as discussed further below. The compare detector 830 has a first input 832, a second input 834, and an output 836. The first input 832 is coupled to the first output 612 of the comparator 230, the second input 834 is coupled to the second output 614 of the comparator 230, and the output 836 is coupled to the reset input 814 of the comparator 230.

[0066] In this example, the compare detector 830 is configured to detect when the comparator 230 is done with a comparison (i.e., detect comparison completion) based on the first output 612 and the second output 614 of the comparator 230. For example, the compare detector 830 may detect the comparison is done by detecting when the first output 612 and the second output 614 are different (i.e., complementary) using an exclusive or (XOR) gate or another type of logic gate. For the implementation where both outputs 612 and 614 are low (i.e., logic zero) when the comparator 230 is reset, the compare detector 830 may detect the comparison is done by detecting when one of the first output 612 and the second output 614 is high (i.e., logic one) using an OR gate, a NOR gate, or another type of logic gate. For the implementation where both outputs 612 and 614 are high (i.e., logic one) when the comparator 230 is reset, the compare detector 830 may detect the comparison is done by detecting when one of the first output 612 and the second output 614 is low (i.e., zero one) using an AND gate, a NAND gate, or another type of logic gate. It is to be appreciated that the compare detector 630 is not limited to the examples given above.

[0067] When the compare detector 830 detects the comparator 230 is done with a comparison (i.e., comparison completion), the compare detector 830 may output the falling edge to the reset input 814 of the comparator 230 to reset the comparator 230. Since the comparator 230 performs n comparison during the conversion period, the compare detector 830 may detect comparison done n times (i.e., detect n comparison completions) during the conversion period and therefore output the falling edge n times to reset the comparator 230 n times. Since comparison completion detection by the compare detector830 depends on the speed of the comparator 230, the timings of the falling edges (and hence resets of the comparator 230) depend on the speed of the comparator 230.

[0068] Thus, in this example, the enable control circuit 820 enables the comparator 230 in a pseudo synchronous manner based on the clock signal elk and the time delay of the delay circuit 825 while the compare detector 830 resets the comparator 230 in an asynchronous manner depending on the speed of the comparator 230.

[0069] It is to be appreciated that the present disclosure is not limited to the above example in which the enable control circuit 820 outputs rising edges to the enable input 812 of the comparator 230 to enable the comparator 230 and the compare detector 830 outputs falling edges to the reset input 814 of the comparator 230 to reset the comparator 230. For example, in other implementations, the comparator 230 may be enabled when the comparator 230 receives a falling edge at the enable input 812 and reset when the comparator 230 receives a rising edge at the reset input 814. In these implementations, the enable control circuit 820 may be configured to output falling edges to the enable input 812 of the comparator 230 to enable the comparator 230 instead of rising edges, in which the first falling edge is triggered by an edge of the clock signal elk and the remaining falling edges are spaced apart by the time delay of the delay circuit 825. Also, in these implementations, the compare detector 830 may be configured to output rising edges to the reset input 824 of the comparator 230 to reset the comparator 230 in which the rising edges are output asynchronously based on the speed of the comparator 230. In general, the enable control circuit 820 may be configured to output first edges (e.g., rising edges or falling edges) to the enable input 812 of the comparator 230 to enable the comparator 230, in which the first one of the first edges is triggered by an edge of the clock signal elk and the remaining first edges are spaced apart by the time delay of the delay circuit 825. Also, in these implementations, the compare detector 830 may be configured to output second edges (e.g., falling edges or rising edges) to the reset input 824 of the comparator 230 to reset the comparator 230 in which the second edges are output asynchronously based on the speed of the comparator 230.

[0070] FIG. 9 shows an exemplary implementation of the compare detector 830 according to certain aspects. In this example, the compare detector 830 includes a NOR gate 910 having a first input coupled to the first output 612 of the comparator 230, a second input coupled to the second output 614 of the comparator 230, and an output coupled to the reset input 814 of the comparator 230. In this example, both outputs 612 and 614 may be low (i.e., logic zero) when the comparator 230 is reset. Thus, in this example, the outputof the NOR gate 910 is high when the comparator 230 is reset. When the comparator 230 is done with a comparison, one of the outputs 612 and 614 of the comparator 230 becomes high based on the comparison. This causes the output of the NOR gate 910 to transition from high to low, and therefore causes the NOR gate 910 to output a falling edge to the reset input 814 of the comparator 230 to reset the comparator 230. It is to be appreciated that the compare detector 830 is not limited to the NOR gate 910 shown in the example FIG. 9, and that the compare detector 830 may be implemented with another type of logic gate and / or a combination of logic gates.

[0071] FIG. 10 shows an exemplary implementation of the comparator 230 according to certain aspects. In this example, the comparator 230 includes a latch 1020 (e.g., a strong-arm latch) and a combiner 1010. The combiner 1010 is coupled to the enable input 812 and the reset input 814. In some implementations, the combiner 1010 is configured to combine the rising edges at the enable input 812 and the falling edges at the reset input 814 to generate an internal enable signal (labeled “En”). In these implementations, the enable signal En may transition from low to high on a rising edge at the enable input 812, and transition from high to low on a falling edge at the reset input 814. However, it is to be appreciated that the present disclosure is not limited to this example.

[0072] The latch 1020 includes a first transistor 1022 and second transistors 1024. The gate of the first transistor 1022 is coupled to the second input 234 and the gate of the second transistor 1024 is coupled to the first input 232. In the example in FIG. 10, each of the first and second transistors 1022 and 1024 is implemented with a respective n-type field effect transistor (NFET).

[0073] The latch 1020 also includes a third transistor 1030 and a fourth transistor 1032 that are cross crossed with each other, in which the gate of the third transistor 1030 is coupled to the drain of the fourth transistor 1032, and the gate of the fourth transistor 1032 is coupled to the drain of the third transistor 1030. The source of the third transistor 1030 is coupled to the drain of the first transistor 1022, and the source of the fourth transistor 1032 is coupled to the drain of the second transistor 1024. In the example in FIG. 10, each of the third and fourth transistors 1030 and 1032 is implemented with a respective NFET.

[0074] The latch 1020 also includes a fifth transistor 1040 and a sixth transistor 1042 that are cross crossed with each other, in which the gate of the fifth transistor 1040 is coupled to the drain of the sixth transistor 1042, and the gate of the sixth transistor 1042 is coupled to the drain of the fifth transistor 1040. The drain of the fifth transistor 1040 is coupled to the drain of the third transistor 1030, and the drain of the sixth transistor 1042 is coupledto the drain of the fourth transistor 1032. The source of the fifth transistor 1040 and the source of the sixth transistor 1042 are coupled to a supply rail. In the example in FIG. 10, each of the fifth and sixth transistors 1040 and 1042 is implemented with a respective p-type field effect transistor (PFET).

[0075] In this example, the latch 1020 also includes a seventh transistor 1026, an eighth transistor 1036, a ninth transistor 1050, a tenth transistor 1055, an eleventh transistor 1060, and a twelfth transistor 1065 for enabling and resetting the comparator 230 based on the enable signal En from the combiner 1010. In the example in FIG. 10, the seventh transistor 1026 is implemented with an NFET, and each of the eighth transistor 1036, the ninth transistor 1050, the tenth transistor 1055, the eleventh transistor 1060, and the twelfth transistor 1065 is implemented with a respective PFET. In this example, the gate of each of the transistors 1026, 1036, 1050, 1055, 1060, and 1065 is driven by the enable signal En.

[0076] The drain of the seventh transistor 1026 is coupled to the sources of the first and second transistors 1022 and 1024, and the source of the seventh transistor 1026 is coupled to ground (or some reference potential). The eighth transistor 1036 is coupled between internal nodes 1027 and 1028, in which the internal node 1027 is between the drain of the first transistor 1022 and the source of the third transistor 1030, and the internal node 1028 is between the drain of the second transistor 1024 and the source of the fourth transistor 1032.

[0077] The source of the ninth transistor 1050 is coupled to the supply rail and the drain of the ninth transistor 1050 is coupled to the internal node 1027. The source of the tenth transistor 1055 is coupled to the supply rail and the drain of the tenth transistor 1055 is coupled to the internal node 1028. The source of the eleventh transistor 1060 is coupled to the supply rail and the drain of the eleventh transistor 1060 is coupled to internal node 1044, which is between the drains of the third transistor 1030 and the fifth transistor 1040. The source of the twelfth transistor 1065 is coupled to the supply rail and the drain of the twelfth transistor 1065 is coupled to internal node 1046, which is between the drains of the fourth transistor 1032 and the sixth transistor 1042.

[0078] In the example in FIG. 10, the latch 1020 also includes a first inverter 1070 coupled between the internal node 1044 and the first output 612, and a second inverter 1075 coupled between the internal node 1046 and the second output 614. The inverters 1070 and 1075 may be used, for example, to help provide rail-to-rail signals at the outputs 612 and 614 of the comparator 230. The inverters 1070 and 1075 may be omitted to some implementations .

[0079] Exemplary operations of the latch 1020 will now be described according to certain aspects. In this example, the latch 1020 is reset when the enable signal En goes low. In this case, the transistors 1036, 1050, 1055, 1060, and 1065 turn on and the transistor 1026 turns off. This causes the eighth transistor 1036 to couple the internal nodes 1027 and 1028 through the eighth transistor 1036, and causes the ninth transistor 1050 and the tenth transistor 1055 to pull the internal nodes 1027 and 1028 high (i.e., to approximately the supply voltage of the supply rail). This also causes the eleventh transistor 1060 and the twelfth transistor 1065 to pull the internal nodes 1044 and 1046 high (i.e., to approximately the supply voltage of the supply rail), which causes the outputs 612 to 614 to go low due to the inverters 1070 and 1075. Thus, in this example, the outputs 612 and 614 are both low when the comparator 230 is reset.

[0080] The latch 1020 is enabled when the enable signal En goes high. In this case, the transistors 1036, 1050, 1055, 1060, and 1065 turn off and the transistor 1026 turns on. This causes the latch 1020 to pull one of the outputs 612 and 614 of the comparator 230 high depending on whether the voltage at the first input 232 of the comparator 230 is greater than or less than the voltage at the second input 234 of the comparator 230.

[0081] FIG. 11A is a timing diagram showing an example of the enable signal En according to certain aspects. In this example, the comparator 230 is enabled on the rising edges of the enable signal En and is reset on the falling edges of the enable signal En. The rising edges of the enable signal En correspond to the rising edges received at the enable input 812 from the enable control circuit 820 shown in FIG. 8, and the falling edges of the enable signal En correspond to the falling edges received at the reset input 814 from the compare detector 830. As shown in FIG. 11 A, the rising edges of the enable signal En are spaced apart by the time delay (labeled “At” in FIG. 11 A) of the delay circuit 825 in the enable control circuit 820. In the example in FIG. 11 A, the timings of the falling edges of the enable signal En depend on the detection of comparison completions by the compare detector 830, which depends on the speed of the comparator 230.

[0082] In the example in FIG. 11 A, when the comparator 230 is enabled by the rising edge 1110, the comparator 230 completes the corresponding comparison before the next rising edge 1130 and the compare detector 830 resets the comparator 230 with the falling edge 1120 before the comparator 230 is enabled by the next rising edge 1130 for the next comparison. In other words, in this example, the comparison is done within the time delay At.

[0083] In some cases, the comparison is not done within the time delay At. For example, under some conditions, the speed of the comparator 230 may not be fast enough to complete the comparison within the time delay At. In this regard, FIG. 1 IB shows an example in which the comparison corresponding to the rising edge 1110 is not done within the time delay At. Because the comparison is not done within the time delay, the reset input 814 does not receive a falling edge within the time delay. As a result, the comparator 230 is not reset within the time delay and the enable signal En continues to stay high past the time delay to allow the comparator 230 to finish the comparison. This gives the comparator 230 more time to resolve meta- stability. In the example in FIG. 11B, the comparison is done within the next time delay, and the comparator 230 is reset within the next time delay by falling edge 1120. As shown in FIG. 11B, the enable control circuit 820 continues to output a rising edge 1150 after each time delay At. In the example in FIG. 1 IB, the enable signal En does not rise at the rising edge 1150 since the enable signal En is already high in this example due to the comparison not being done within the time delay. In this example, the number of time delays may be increased until reaching a maximum allowed conversion period.

[0084] FIG. 12 shows an example in which the SAR ADC 810 also includes an edge detector 1210. In this example, the edge detector 1210 is coupled to the enable input 812, the reset input 814, and the enable control circuit 820. In operation, the edge detector 1210 detects the falling edges going to the reset input 814 and / or detects rising edges going to the enable input 812. For example, the edge detector 1210 may check whether there is sufficient time between a falling edge and the next rising edge for the comparator 230 to reset. This is because the comparator 230 needs some time to reset. If there is insufficient time for the reset, then the time delay At may be increased. For example, the edge detector 1210 may send a signal to the enable control circuit 820 to increase the time delay At by increasing the delay of the delay circuit 825. In this example, the time delay At may only be increased to a maximum allowed time delay given by the conversion period divided by the number of comparisons.

[0085] As discussed above, when the DAC 250 is implemented with a capacitive DAC (C-DAC), the sample and hold function of the sample and hold circuit 220 may be incorporated into the C-DAC. In this regard, FIG. 13 shows an example in which the DAC 250 is implemented with a C-DAC that includes sample and hold functionality, and the sample and hold circuit 220 is omitted. C-DACs with sample and hold functionality are known in the art, and may include an array of switchable capacitors (e.g., switchable binary-weighted capacitors) in the which the array of switchable capacitors is utilized to both sample the input voltage Vin and generate the DAC voltage Vdac.

[0086] In the example in FIG. 13, the DAC 250 has a second input 1315 coupled to the input 212 to receive the analog input voltage Vin. The DAC 250 may also receive the clock signal elk for timing the sampling of the input voltage Vin. Also, in this example, the second input 234 of the comparator 230 may be coupled to a comparison voltage. The comparison voltage may be at a ground potential (shown in the example in FIG. 13) or another voltage. As discussed below, the comparator 230 compares the comparison voltage with the output of the DAC 250.

[0087] In operation, the DAC 250 may sample the input voltage Vin on an edge (e.g., rising edge or falling edge) of the clock signal elk and hold the sampled input voltage Vin during a conversion period. The DAC 250 may then generate the DAC voltage Vdac under the control of the SAR 240, and output a voltage at the output 254 approximately equal to the DAC voltage Vdac minus the sampled input voltage Vin (i.e., Vdac - Vin). However, it is to be appreciated that the present disclosure is not limited to this example.

[0088] In this example, the comparator 230 compares Vdac - Vin from the DAC 250 with the comparison voltage (e.g., ground potential) at the second input 234 of the comparator 230, and outputs the compare signal at the output 236 based on the comparison. For example, the comparator 230 may output a logic one at the first output 612 and a logic zero at the second output 614 when the comparison voltage is greater than Vdac -Vin. For the example where the comparison voltage is at ground potential (i.e., zero volts), this occurs when the sampled input voltage Vin is greater than the DAC voltage Vdac. Thus, in this example, comparator 230 may output a logic one at the first output 612 and a logic zero at the second output 614 when the sampled input voltage Vin is greater than the DAC voltage Vdac. However, it is to be appreciated that the present disclosure is not limited to this example. The SAR 240 receives the compare signal from the comparator 230 and successively resolves the bits of the digital signal in the manner discussed above with reference to FIG. 8.

[0089] In certain aspects, the SAR ADC 810 may be implemented as a differential SAR ADC as shown in the example in FIG. 14. In this example, the SAR ADC 810 includes a second DAC 1450 (e.g., C-DAC) coupled to the second input 234 of the comparator 230. The second DAC 1450 has a first input 1452 coupled to output 1446 of the SAR 240, a second input 1415 coupled to a second input 1412 of the SAR ADC 810, and an output 1454 coupled to the second input 234 of the comparator 230. In the discussion below, the DAC250 is referred to as the first DAC 250 and the input 212 is referred to as the first input 212. Although not shown in FIG. 14, it is to be appreciated that the SAR ADC 810 may include the edge detector 1210 discussed above.

[0090] In this example, the SAR ADC 810 is configured to convert a differential input voltage including a first input voltage Vinp and a second input voltage Vinn into a digital signal. More particularly, the SAR ADC 810 is configured to receive the first input voltage Vinp at the first input 212, receive the second input voltage Vinn at the second input 1412, convert the difference between the first input voltage Vinp and the second input voltage Vinn into a digital signal, and output the digital signal at an output 215.

[0091] In operation, the first DAC 250 samples the first input voltage Vinp on an edge (e.g., rising edge or falling edge) of the clock signal elk and holds the sampled first input voltage Vinp during a conversion period. The second DAC 1450 samples the second input voltage Vinn on the edge of the clock signal elk and holds the sampled second voltage Vinn during the conversion period. Thus, together the first DAC 250 and the second DAC 1450 sample and hold the differential input voltage.

[0092] The first DAC 250 and the second DAC 1450 output a differential voltage to the inputs 232 and 234 of the comparator 230 equal to the sampled differential input voltage minus the DAC voltage or equal to the DAC voltage minus the sampled differential input voltage. As a result, the compare signal of the comparator 230 indicates whether the sampled differential input voltage is greater than or less than the DAC voltage. During each cycle in the conversion period, the SAR 240 may resolve one of the bits of the digital signal based on the compare signal from the comparator 230 and update the DAC voltage accordingly.

[0093] As discussed above, the enable control circuit 820 may be coupled to multiple instances of the SAR ADC 810 to reduce area and power consumption. In this regard, FIG. 15 shows an example in which the enable control circuit 820 is coupled to a first SAR ADC 810-1, a second SAR ADC 810-2, and a third SAR ADC 810-3 in which each of the first SAR ADC 810-1, the second SAR ADC 810-2, and the third SAR ADC 810-3 is a sperate instance (i.e., copy) of the SAR ADC 810 discussed above. The first SAR ADC 810-1, the second SAR ADC 810-2, and the third SAR ADC 810-3 may be used to convert input voltages Vin_l, Vin_2, and Vin_3, respectively, into digital signals.

[0094] In this example, the enable control circuit 820 generates and outputs rising edges to the first SAR ADC 810-1, the second SAR ADC 810-2, and the third SAR ADC 810-3 to control enabling of the respective instance of the comparator 230 in the first SAR ADC810-1, the respective instance of the comparator 230 in the second SAR ADC 810-2, and the respective instance of the comparator 230 in the third SAR ADC 810-3. Each of the first SAR ADC 810-1, the second SAR ADC 810-2, and the third SAR ADC 810-3 controls resetting of the respective instance of the comparator 230 based on falling edges generated locally by the respective instance of the compare detector 830.

[0095] FIG. 16 shows an exemplary method 1600 of operating an analog-to-digital converter (ADC) according to certain aspects. The ADC (e.g., SAR ADC 810) includes a comparator (e.g., comparator 230), a successive approximation register (SAR) (e.g., SAR 240) coupled to the comparator, and a digital-to-analog converter (DAC) (e.g., DAC 250) coupled to the SAR and the comparator.

[0096] At block 1610, a clock signal (e.g., clock signal elk) is received. For example, the enable control circuit 820 may receive the clock signal.

[0097] At block 1620, the comparator is enabled. For example, the enable control circuit 820 may enable the comparator for the first time during the conversion cycle based on an edge (e.g., rising edge) of the clock signal.

[0098] At block 1630, a time delay At is elapsed. The time delay At may be generated by the delay circuit 825.

[0099] At block 1640, a determination is made whether the number of comparisons in the current conversion period has reached n where n corresponds to the number of bits in the digital signal. For example, the determination may be made by the enable control circuit 1820.

[0100] If the number of comparisons has not been reached n, then the method 1500 returns to block 1620 to enable the comparator to perform another comparison. This may be done to generate the next compare signal for the SAR 240 to resolve the next bit in the digital signal.

[0101] If the number of comparisons has reached n, then the current conversion period is done at block 1650.

[0102] At block 1660, the comparator 230 is done with a comparison.

[0103] At block 1670, if the current comparison completed before the time delay At, then the comparator 230 is reset at block 1680. If the current comparison is not completed before the time delay At, then the comparator 230 is not reset within the time delay. In this case, the comparator 230 may be reset in the next time delay if the comparison is done within the next time delay.

[0104] FIG. 17 shows another exemplary method 1700 of operating an analog-to-digital converter (ADC) according to certain aspects. The ADC (e.g., SAR ADC 810) includesa comparator (e.g., comparator 230), a successive approximation register (SAR) (e.g., SAR 240) coupled to the comparator, and one or more digital-to-analog converters (DACs) (e.g., DAC 250 and / or the second DAC 1450) coupled to the SAR and the comparator.

[0105] At block 1710, a clock signal is received. For example, the enable control circuit 820 may receive the clock signal (e.g., clock signal elk).

[0106] At block 1720, the comparator is enabled multiple times to perform multiple comparisons during a conversion period based on the clock signal. For example, the conversion period may be within one period of the clock signal. The comparator may be enabled by the enable control circuit 820.

[0107] At block 1730, comparison completions for the multiple comparisons are detected during the conversion period. For example, the comparison completions may be detected by the compare detector 830.

[0108] At block 1740, the comparator is reset for each of the detected comparison completions. For example, the comparator may be reset by the compare detector 830.

[0109] In certain aspects, enabling the comparator multiple times to perform multiple comparisons during the conversion period based on the clock signal may include outputting first edges to an enable input (e.g., enable input 812) of the comparator based on the clock signal. The first edges may include rising edges.

[0110] In certain aspects, outputting the first edges to the enable input of the comparator based on the clock signal may include outputting a first one of the first edges to the enable input of the comparator based on an edge of the clock signal, and spacing the first edges apart from one another by a time delay. For example, the first one of the first edges (e.g., rising edges) may be triggered by the edge (e.g., rising edge) of the clock signal, and the first edges may be spaced apart from one another by the time delay (e.g., time delay At in FIG. 11 A).

[0111] In certain aspects, the method 1700 includes determining whether each of the multiple comparisons is completed within the time delay. For example, the determination may be made by the edge detector 1210. In these aspects, the method 1700 may also include increasing the time delay if at least one of the multiple comparisons is not completed within the time delay.

[0112] In certain aspects, resetting the comparator for each of the detected comparison completions includes outputting second edges to a reset input (e.g., reset input 814) of the comparator.

[0113] In certain aspects, detecting the comparison completions includes detecting the comparison completions based on a first output (e.g., first output 612) of the comparator and a second output (e.g., second output 614) of the comparator.

[0114] In certain aspects, detecting the comparison completions based on the first output of the comparator and the second output of the comparator includes detecting when the first output of the comparator and the second output of the comparator have complementary logic states (i.e., different logic states). For example, the complementary logic states at the first and second outputs of the comparator may be detected by the compare detector 830, which may be implemented with an XOR gate, a NOR gate, an OR gate, an AND gate, a NAND gate, or another type of gate.

[0115] Implementation examples are described in the following numbered clauses:

[0116] 1. A system comprising: an analog-to-digital converter (ADC), wherein the ADC comprises: a comparator having a first output and a second output; a successive approximation register (SAR) coupled to at least one of the first output of the comparator and the second output of the comparator; one or more digital-to-analog converters (DACs) coupled between the SAR and the comparator; and a compare detector coupled to the first output of the comparator, the second output of the comparator, and a reset input of the comparator; and an enable control circuit coupled to an enable input of the comparator.

[0117] 2. The system of clause 1, wherein the enable control circuit is configured to output first edges to the enable input of the comparator, wherein the first edges are spaced apart from one another by a time delay.

[0118] 3. The system of clause 2, wherein the first edges comprise rising edges.

[0119] 4. The system of clause 2 or 3, wherein the enable control circuit includes a delay circuit configured to generate the time delay.

[0120] 5. The system of clause 4, wherein the enable control circuit is configured to: receive a clock signal; and output a first one of the first edges based on an edge of the clock signal.

[0121] 6. The system of clause 5, wherein the time delay is shorter than a period of the clock signal.

[0122] 7. The system of any one of clauses 2 to 6, wherein the compare detector is configured to:detect comparison completions by the comparator based on the first output of the comparator and the second output of the comparator; and output second edges to the reset input of the comparator based on the detected comparison completions.

[0123] 8. The system of clause 7, wherein the first edges comprise rising edges and the second edges comprise falling edges.

[0124] 9. The system of clause 7 or 8, wherein the compare detector comprises a NOR gate, an OR gate, an XOR gate, an AND gate, or a NAND gate.

[0125] 10. The system of any one of clauses 1 to 9, wherein the one or more DACs includes a DAC coupled between the SAR and a first input of the comparator, and the ADC further comprises a sample and hold circuit coupled to a second input of the comparator.

[0126] 11. The system of any one of clauses 1 to 9, wherein the one or more DACs comprise a capacitive DAC coupled between the SAR and a first input of the comparator, and a second input of the comparator is coupled to a compare voltage.

[0127] 12. The system of clause 11, wherein the compare voltage is at a ground potential.

[0128] 13. The system of any one of clauses 1 to 9, wherein the one or more DACs include a first DAC coupled between the SAR and a first input of the comparator, and a second DAC coupled between the SAR and a second input of the comparator.

[0129] 14. A system comprising: multiple analog-to-digital converters (ADCs), wherein each one of the ADCs comprises: a respective comparator having a first output and a second output; a respective successive approximation register (SAR) coupled to at least one of the first output of the respective comparator and the second output of the respective comparator; respective one or more digital-to-analog converters (DACs) coupled between the respective SAR and the respective comparator; and a respective compare detector coupled to the first output of the respective comparator, the second output of the comparator, and a reset input of the respective comparator; and an enable control circuit coupled to the ADCs, wherein the enable control circuit is configured to enable the respective comparator of each of the ADCs.

[0130] 15. The system of clause 14, wherein the enable control circuit is configured to output first edges to an enable input of the respective comparator of each of the ADCs, wherein the first edges are spaced apart from one another by a time delay.

[0131] 16. The system of clause 15, wherein the first edges comprise rising edges.

[0132] 17. The system of clause 15 or 16, wherein the enable control circuit includes a delay circuit configured to generate the time delay.

[0133] 18. The system of any one of clauses 15 to 17, wherein the enable control circuit is configured to: receive a clock signal; and output a first one of the first edges based on an edge of the clock signal.

[0134] 19. The system of any one of clauses 15 to 18, wherein the respective compare detector of each of the ADCs is configured to: detect comparison completions by the respective comparator based on the first output of the respective comparator and the second output of the respective comparator; and output second edges to the reset input of the respective comparator based on the detected comparison completions.

[0135] 20. The system of clause 19, wherein the first edges comprise rising edges and the second edges comprise falling edges.

[0136] 21. The system of any one of clauses 14 to 20, wherein the respective compare detector of each of the ADCs comprises a respective NOR gate, a respective OR gate, a respective XOR gate, a respective AND gate, or a respective NAND gate.

[0137] 22. A method of operating an analog-to-digital converter (ADC), the ADC including a comparator, a successive approximation register (SAR) coupled to the comparator, and one or more digital-to-analog converters (DACs) coupled to the SAR and the comparator, the method comprising: receiving a clock signal; enabling the comparator multiple times to perform multiple comparisons during a conversion period based on the clock signal; detecting comparison completions for the multiple comparisons during the conversion period; and resetting the comparator for each of the detected comparison completions.

[0138] 23. The method of clause 22, wherein enabling the comparator multiple times to perform the multiple comparisons during the conversion period based on the clock signalcomprises outputting first edges to an enable input of the comparator based on the clock signal.

[0139] 24. The method of clause 23, wherein outputting the first edges to the enable input of the comparator based on the clock signal comprises: outputting a first one of the first edges to the enable input of the comparator based on an edge of the clock signal; and spacing the first edges apart from one another by a time delay.

[0140] 25. The method of clause 24, further comprising, if a comparison is not done within the time delay, skipping reset of the comparator within the time delay and using a next time delay for the comparison.

[0141] 26. The method of clause 25, further comprising increasing time delays until reaching a maximum allowed conversion period.

[0142] 27. The method of any one of clauses 24 to 26, wherein resetting the comparator for each of the detected comparison completions comprises outputting second edges to a reset input of the comparator.

[0143] 28. The method of clause 27, wherein the first edges comprise rising edges and the second edges comprise falling edges.

[0144] 29. The method of any one of clauses 22 to 28, wherein detecting the comparison completions for the multiple comparisons during the conversion period comprises detecting the comparison completions based on a first output of the comparator and a second output of the comparator.

[0145] 30. The method of clause 29, wherein detecting the comparison completions based on the first output of the comparator and the second output of the comparator comprises detecting when the first output of the comparator and the second output of the comparator have complementary logic states.

[0146] The enable control circuit 820 may be implemented with discrete hardware components (e.g., logic gates), a state machine, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, or any combination thereof designed to perform the functions described herein. The delay circuit 825 may be implemented with a programmable delay circuit to program the time delay, and may include delay buffers (e.g., inverters) coupled in a chain. A delay circuit may also be referred to as a delay line or another term.

[0147] Within the present disclosure, the word “exemplary” is used to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as“exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term “aspects” does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term “coupled” is used herein to refer to the direct or indirect electrical coupling between two structures.

[0148] Any reference to an element herein using a designation such as “first,” “second,” and so forth does not generally limit the quantity or order of those elements. Rather, these designations are used herein as a convenient way of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements can be employed, or that the first element must precede the second element.

[0149] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

CLAIMS1. A system comprising: an analog-to-digital converter (ADC), wherein the ADC comprises: a comparator having a first output and a second output; a successive approximation register (SAR) coupled to at least one of the first output of the comparator and the second output of the comparator; one or more digital-to-analog converters (DACs) coupled between the SAR and the comparator; and a compare detector coupled to the first output of the comparator, the second output of the comparator, and a reset input of the comparator; and an enable control circuit coupled to an enable input of the comparator.

2. The system of claim 1, wherein the enable control circuit is configured to output first edges to the enable input of the comparator, wherein the first edges are spaced apart from one another by a time delay.

3. The system of claim 2, wherein the first edges comprise rising edges.

4. The system of claim 2, wherein the enable control circuit includes a delay circuit configured to generate the time delay.

5. The system of claim 4, wherein the enable control circuit is configured to: receive a clock signal; and output a first one of the first edges based on an edge of the clock signal.

6. The system of claim 5, wherein the time delay is shorter than a period of the clock signal.

7. The system of claim 2, wherein the compare detector is configured to: detect comparison completions by the comparator based on the first output of the comparator and the second output of the comparator; and output second edges to the reset input of the comparator based on the detected comparison completions.

8. The system of claim 7, wherein the first edges comprise rising edges and the second edges comprise falling edges.

9. The system of claim 7, wherein the compare detector comprises a NOR gate, an OR gate, an XOR gate, an AND gate, or a NAND gate.

10. The system of claim 1, wherein the one or more DACs includes a DAC coupled between the SAR and a first input of the comparator, and the ADC further comprises a sample and hold circuit coupled to a second input of the comparator.

11. The system of claim 1 , wherein the one or more DACs comprise a capacitive DAC coupled between the SAR and a first input of the comparator, and a second input of the comparator is coupled to a compare voltage.

12. The system of claim 11, wherein the compare voltage is at a ground potential.

13. The system of claim 1, wherein the one or more DACs include a first DAC coupled between the SAR and a first input of the comparator, and a second DAC coupled between the SAR and a second input of the comparator.

14. A system comprising: multiple analog-to-digital converters (ADCs), wherein each one of the ADCs comprises: a respective comparator having a first output and a second output; a respective successive approximation register (SAR) coupled to at least one of the first output of the respective comparator and the second output of the respective comparator; respective one or more digital-to-analog converters (DACs) coupled between the respective SAR and the respective comparator; and a respective compare detector coupled to the first output of the respective comparator, the second output of the comparator, and a reset input of the respective comparator; andan enable control circuit coupled to the ADCs, wherein the enable control circuit is configured to enable the respective comparator of each of the ADCs.

15. The system of claim 14, wherein the enable control circuit is configured to output first edges to an enable input of the respective comparator of each of the ADCs, wherein the first edges are spaced apart from one another by a time delay.

16. The system of claim 15, wherein the first edges comprise rising edges.

17. The system of claim 15, wherein the enable control circuit includes a delay circuit configured to generate the time delay.

18. The system of claim 15, wherein the enable control circuit is configured to: receive a clock signal; and output a first one of the first edges based on an edge of the clock signal.

19. The system of claim 15, wherein the respective compare detector of each of the ADCs is configured to: detect comparison completions by the respective comparator based on the first output of the respective comparator and the second output of the respective comparator; and output second edges to the reset input of the respective comparator based on the detected comparison completions.

20. The system of claim 19, wherein the first edges comprise rising edges and the second edges comprise falling edges.

21. The system of claim 14, wherein the respective compare detector of each of the ADCs comprises a respective NOR gate, a respective OR gate, a respective XOR gate, a respective AND gate, or a respective NAND gate.

22. A method of operating an analog-to-digital converter (ADC), the ADC including a comparator, a successive approximation register (SAR) coupled to the comparator, andone or more digital-to-analog converters (DACs) coupled to the SAR and the comparator, the method comprising: receiving a clock signal; enabling the comparator multiple times to perform multiple comparisons during a conversion period based on the clock signal; detecting comparison completions for the multiple comparisons during the conversion period; and resetting the comparator for each of the detected comparison completions.

23. The method of claim 22, wherein enabling the comparator multiple times to perform the multiple comparisons during the conversion period based on the clock signal comprises outputting first edges to an enable input of the comparator based on the clock signal.

24. The method of claim 23, wherein outputting the first edges to the enable input of the comparator based on the clock signal comprises: outputting a first one of the first edges to the enable input of the comparator based on an edge of the clock signal; and spacing the first edges apart from one another by a time delay.

25. The method of claim 24, further comprising, if a comparison is not done within the time delay, skipping reset of the comparator within the time delay and using a next time delay for the comparison.

26. The method of claim 25, further comprising increasing time delays until reaching a maximum allowed conversion period.

27. The method of claim 24, wherein resetting the comparator for each of the detected comparison completions comprises outputting second edges to a reset input of the comparator.

28. The method of claim 27, wherein the first edges comprise rising edges and the second edges comprise falling edges.

29. The method of claim 22, wherein detecting the comparison completions for the multiple comparisons during the conversion period comprises detecting the comparison completions based on a first output of the comparator and a second output of the comparator.

30. The method of claim 29, wherein detecting the comparison completions based on the first output of the comparator and the second output of the comparator comprises detecting when the first output of the comparator and the second output of the comparator have complementary logic states.

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