Defectivity redundancy for memory arrays

Abstract

In a general aspect, a circuit includes a memory array having a plurality of memory cells configured to store a plurality of data words in a plurality of rows and in a plurality of columns. The plurality of data words are respectively addressable. The circuit further includes an interface configured to receive a request to access a data word of the plurality of data words, including an address of the data word. The circuit further includes an address comparator configured to compare the address of the request with a stored address identifying a defective memory cell, and a redundancy circuit that is configured to, in response to the address comparator determining that the address of the request matches the stored address, redirect processing of the request from the memory array to a plurality of latches that are external to the memory array.

Description

DEFECTIVITY REDUNDANCY FOR MEMORY ARRAYSCROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to U.S. Provisional Application No. 63 / 580,514, filed on September 5, 2023, and entitled “DEFECTIVITY REDUNDANCY FOR MEMORY ARRAYS,” the disclosure of which is incorporated by reference herein in its entirety.TECHNICAL FIELD

[0002] This description relates to electronic memory structures that can be included in an integrated circuit. More specifically, this disclosure relates to approaches for providing redundancy for entries of an electronic memory structure that have a defective memory cell.BACKGROUND

[0003] Memory structures (memories, etc.) are used extensively in electronic systems, such as computers (servers, desktop computers, laptop computers, etc.), smartphones, tablets, smartwatches, gaming systems, etc. For instance, memories can be used to implement system memory, cache memory, instruction memory, register files, etc., such as in microprocessors, processors, central processing units, graphics processing units, tensor processing units, accelerators, and the like, or in memory chips (e.g., standalone memory chips) that are included in electronic systems.

[0004] Such memories typically include a plurality of densely packed memory cells that are arranged in an array of rows and columns, in which a plurality of respectively addressable data words is implemented, where each data word includes a number of the memory cells, e.g., eight memory cells for an eight-bit data word. Depending on the particular implementation, a memory array can have a single data word entry per row (e.g., one data word per row), or can have multiple data word entries per row. Memories with multiple entries per row of the array can be implemented using column muxing, where each bitline, e.g., write bitline and read bitline, is multiplexed or demultiplexed to / from multiple columns of the memory array. For instance, a memory array with 4-to-l column muxing will have four data word entries per row, with the bits of those four data words being interleaved (e.g., logically interleaved) in the row.

[0005] Due, at least in part, to the densely packed structure of memory cells in a memory array, they can be particularly susceptible to semiconductor processingmanufacturing defects, where a single defective memory cell (e.g., data bit) can result in an associated circuit failing functional testing, e.g., memory pattern testing, thus reducing manufacturing yield and, as a result, increasing manufacturing costs. In previous approaches, redundancy in memory arrays has been achieved by including one or more redundant rows of memory cells that each can be used respectively to replace rows of memory cells that have at least one defective bit. However, such approaches have drawbacks. For instance, use of such redundant rows can increase setup and hold timing for associated memory accesses, for example, due to the additional required decode circuitry for the redundant rows, the increased signal path lengths to accommodate the redundant rows, the increased parasitic capacitance on associated bitlines due to the redundant rows, etc. Furthermore, such redundant rows increase leakage current of an associated memory array, which can also impact performance of the memory.SUMMARY

[0006] In a general aspect, a circuit includes a memory array having a plurality of memory cells configured to store a plurality of data words in a plurality of rows and in a plurality of columns. The plurality of data words are respectively addressable. The circuit further includes an interface configured to receive a request to access a data word of the plurality of data words, including an address of the data word. The circuit further includes an address comparator configured to compare the address of the request with a stored address identifying a defective memory cell, and a redundancy circuit that is configured to, in response to the address comparator determining that the address of the request matches the stored address, redirect processing of the request from the memory array to a plurality of latches that are external to the memory array.

[0007] Implementations can include one or more of the following features, alone or in combination. For example, the request to access the data word can be a write request to write data to the memory array, and processing the request to access the data word can include writing the write data to the plurality of latches.

[0008] Writing the write data to the plurality of latches can include writing the write data from respective data input latches. The respective data input latches can be configured to write to the memory array.

[0009] The plurality of latches can be positive edge triggered latches. The respective data input latches can be negative edge triggered latches. Each latch of the plurality of latches and its respective data input latch can define a flop configured to store a data bit.

[0010] The request to access the data word can be a read request to read data from the memory array. Processing the request to access the data word includes reading the requested data from the plurality of latches.

[0011] A latch of the plurality of latches can be coupled to a data input latch to define a flop configured to store a data bit. The data input latch can be configured to selectively write the data bit to the latch or to a memory cell of the plurality of memory cells of the memory array.

[0012] The plurality of latches can be included in a global input and output circuitry block of the circuit. The plurality of latches can be repurposed from boundary scan flops of the circuit.

[0013] The stored address can be a first stored address, the plurality of latches can be a first plurality of latches, and the defective memory cell can be a first defective memory cell. The address comparator can be configured to compare the address of the request with a second stored address identifying a second defective memory cell. The redundancy circuit can be configured to, in response to the address comparator determining that the address of the request does not match the first stored address and the address of the request matches the second stored address, redirect processing of the request from the memory array to a second plurality of latches that are external to the memory array.

[0014] The request to access the data word can be one of a write request to write data to the memory array, or a read request to read data from the memory array. Processing the write request can include writing the write data to the second plurality of latches. Processing the read request can include reading the requested data from the second plurality of latches.

[0015] The circuit can include a memory built in self-test (MBIST) module configured to, in response to execution of one or more memory tests implemented by the MBIST module identifying the defective memory cell, write the stored address in a fuse block of the circuit.

[0016] The stored address can correspond with a row of the memory array including the defective memory cell. The stored address can correspond with a data word of the plurality of data words that includes the defective memory cell.

[0017] Processing the request can exclude accessing the memory array.

[0018] Determining that the address of the request matches the stored address can be based on a bit-wise XOR of the address of the request with the stored address.

[0019] The redundancy circuit can be configured to generate a first clock signal that is used for performing data writes to the memory array, to generate a second clock signal thatis used for performing data reads from the memory array, to generate a third clock signal that is used for performing data writes to the plurality of latches, and to generate a fourth clock signal that is used for performing data reads from the plurality of latches. The second clock signal and the fourth clock signal can be a same clock signal.

[0020] In another general aspect, a method includes receiving a request to access a data word in a memory array, the memory array including a plurality of memory cells configured to store a plurality of respectively addressable data words in a plurality of rows and a plurality of columns. The data word is included in the plurality of respectively addressable data words, and the request includes an address of the data word. The method further includes comparing the address of the request with a stored address identifying a defective memory cell. In response to a determination that the address of the request matches the stored address, the method includes processing the request to access the data word using a plurality of latches that are external to the memory array.

[0021] The request to access the data word can be a write request to write data to the memory array. Processing the request to access the data word can include writing the write data to the plurality of latches.

[0022] Writing the write data can include writing the write data to the plurality of latches from respective data input latches that are also configured to write to the memory array.

[0023] The request to access the data word is a read request to read data from the memory array. Processing the request to access the data word can include reading the requested data from the plurality of latches.

[0024] The stored address can be a first stored address, the plurality of latches can be a first plurality of latches, and the defective memory cell can be a first defective memory cell. The method can include, in response to determining that the address of the request does not match the first stored address, comparing the address of the request with a second stored address identifying a second defective memory cell. In response to determining that the address of the request matches the second stored address, the method can include processing the request to access the data word using a second plurality of latches that are external to the memory array. The request to access the data word can be one of a write request to write data to the memory array, or a read request to read data from the memory array. Processing the write request can include writing the write data to the second plurality of latches. Processing the read request can include reading the requested data from the second plurality of latches.

[0025] Comparing the address of the request with the stored address can include comparing the address of the request with an address that is stored in a fuse block in response to execution of one or more memory built in self-tests implemented by the circuit that identify the defective memory cell.

[0026] Processing the request can exclude accessing the memory array.

[0027] Determining that the address of the request matches the stored address can be based on a bit-wise XOR of the address of the request with the stored address.

[0028] The method can include generating a first clock signal that is used by the circuit to performing data writes to the memory array, generating a second clock signal that is used by the circuit for performing data reads from the memory array, generating a third clock signal that is used by the circuit for performing data writes to the plurality of latches, and generating a fourth clock signal that is used by the circuit for performing data reads from the plurality of latches. The second clock signal and the fourth clock signal can be a same clock signal.BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG. l is a block diagram illustrating an example circuit that implements flopbased memory array redundancy.

[0030] FIG. 2 is a is block diagram illustrating an example memory with flop-based redundancy.

[0031] FIG. 3 is a diagram illustrating an example memory column slice of a column- muxed memory with flop-based redundancy.

[0032] FIG. 4 is a flowchart illustrating a method of operation of a memory with flop- based redundancy.

[0033] FIG. 5 is a diagram illustrating an example architecture of a computing device, which can be used to implement aspects according to the present disclosure.

[0034] Like reference symbols in the various drawings indicate like and / or similar elements.DETAILED DESCRIPTION

[0035] This disclosure relates to apparatuses and associated methods for implementing redundancy for memory arrays, which overcome at least some of the drawbacks of prior approaches discussed above. Such memory arrays, and associated memory structures, can be used in electronic systems, such as systems including processors,microprocessors, central processing units, graphics processing units, tensor processing units, and accelerators, etc. (hereafter “processor(s)”). Such systems can include computing systems, consumer electronics, e.g., smart devices, etc.

[0036] In described implementations, memory redundancy is implemented using flops (redundancy flops, redundancy flip-flops, shared flops, etc.) that are implemented using shared data-input latches (referred to herein as data-in latches, LI latches, negative edge triggered latches, master latches, etc.) in combination with latches that are external to the memory (referred to herein as L2 latches, positive edge triggered latches, slave latches, etc.). For instance, L2 latches of redundancy flops can be used for one-to-one replacement of memory cells of a data word of the memory array in which a defective memory cell (bit) is identified, rather than the entire row being replaced by a redundant row of memory cells included in an associated memory array, where memory read and write operations are redirected to the redundancy flops when a memory access request is made for a defective address, e.g., a memory data word with at least one defective bit. In some implementations, the L2 latches can be included in a global input / output (I / O) circuitry block of an integrated circuit (circuit), such as a processor. In other implementations, the L2 latches can be implemented using L2 latches (slave latches) that are repurposed from flops used for other functions of an associated circuit, such as boundary scan flops, general purpose I / O flops, etc.

[0037] Because flop-based redundancy, as described herein, allows implementing memory redundancy for a single data word entry, the described approaches can have further advantages over prior approaches in which an entire row of memory cells is replaced to achieve redundancy. For instance, flop-based redundancy can reduce the number of redundant bits used for memory redundancy in large memory arrays that are implemented using column muxing, e.g., where each row includes multiple data word entries (i.e., for achieving a describe physical aspect ratio, for achieving desired operational performance, etc.).

[0038] As an example, in a memory with 512 logical entries of 40 bits per entry implemented using 8-to-l column muxing, the primary portion of the memory cell array implementing the 512 logical entries will have 64 physical rows (i.e., 512 divided by 8) and will have 320 physical columns. If two rows of redundancy are implemented, the memory cell array will include 514 physical rows, e.g., the 512 rows of the primary portion of the array plus the two redundant rows. In this example, there are eight data word entries per physical row, or 320 bits per row (i.e., 40 times 8). Accordingly, by using such replacementrows, implementing redundancy for a 40 bit data word entry with a single defective bit is implemented by logically swapping in a redundant row of 320 bits.

[0039] In comparison, using the flop-based redundancy approaches described herein, redundancy for a 40-bit data word entry with a single defective bit is implemented using 40 redundant flops, e.g., 40 LI latches and 40 corresponding L2 latches, rather than a redundant memory cell row of 320 bits. In some implementations, the additional integrated circuit area used for implementing redundancy flops can be offset by the integrated circuit area saved by the omission of redundant rows of memory cells, even though a single redundant flop has a larger area than a single memory cell. That is, depending on the size of an array and its column muxing ratio, the integrated circuit area used for implementing redundancy flops for two redundant data word entries can be approximately equal to the area used for two redundant memory cell rows. In large arrays using larger column muxing ratios (e.g., 4-to-l or greater), the area used for implementing redundancy flops may be less that that used by redundant memory cell rows, resulting in a net reduction in integrated circuit area using flopbased redundancy.

[0040] In implementations described herein, data-in (LI -phase) latches can be shared between the memory array and the redundancy flops. That is, the LI latches used in the redundancy flops can be configured to write to both the memory array, e.g., for data words of the array without a defective bit, and to write to the L2-phase latches of the redundancy flops, e.g., for data words of the array with a defective bit. In other implementations, the LI latches of the redundancy flops can be shared with other functions of the circuit. For instance, the LI latches can be LI latches (master latches) of boundary scan flops, general purpose I / O flops, etc. In some implementations, the LI latches of the redundancy flops can be included in a global I / O block of a corresponding circuit.

[0041] Accordingly, in the implementations disclosed herein, the use of flop-based redundancy allows the implementation of memory array redundancy without the inclusion of redundant rows of memory cells, which eliminates associated increases in signal trace lengths and parasitics associated with those rows. As a result, operating performance of an associated memory, and / or a circuit including the memory can be improved, as parasitic capacitance and leakage of the redundant rows can be eliminated. For instance, incremental setup and hold times for memory array access can be avoided. Furthermore, in some implementations, redundancy flops, e.g., the LI and associated L2 latches, can be built using core logic devices, such as data latches included in global input-output circuitry, and / or general purpose data latches included in other portions of circuitry. Accordingly, such redundancy flops canbe less prone to defects than densely packed memory cells of a memory array, e.g., static random access memory (SRAM) cells.

[0042] FIG. 1 is a block diagram illustrating an example integrated circuit 100 implementing flop-based memory array redundancy. In some examples, the integrated circuit 100 can be a memory device, a processor including a memory, a micro-controller, etc. As shown in FIG. 1, the integrated circuit 100 includes a memory 110 (e.g., a memory structure), an address comparator 120, defective address storage 130, a global input and output circuit block (global VO 140), a redundancy circuit 150, and a memory built-in-self test module (MBIST 160). The arrangement of the integrated circuit 100 is given by way of example, and for purposes of illustration. In some implementations, other arrangements are possible. For example, one or more elements of the integrated circuit 100 can be combined, portions of one or more elements of the integrated circuit 100 can be implemented as separate elements, and / or additional or fewer elements can be included. For instance, in some example implementations, the MBIST 160 can be included in the memory 110, the defective address storage 130 can be included in the address comparator 120, the address comparator 120 and the defective address storage 130 can be included in the redundancy circuit 150, elements of the global I / O 140 can be implemented as separate circuit blocks, an instruction processing pipeline can be added, and so forth.

[0043] The memory 110 of the integrated circuit 100 includes a memory cell array 112 and a memory controller 114. The memory controller 114 can include an interface for receiving requests for accessing the memory cell array 112, e.g., write and read requests. The memory cell array 112 can include a plurality of memory cells, e.g., SRAM cells or other memory cells, which are arranged in a plurality of physical rows and a plurality of physical columns, and can operate, in conjunction with the memory controller 114, as a plurality of logical rows and logical columns. Depending on the particular implementation, the arrangement of physical rows and columns of the memory cell array 112 may differ from the arrangement of logical rows and columns as implemented in the memory cell array 112 by the memory controller 114.

[0044] The memory controller 114 can include an address decoder, e.g., a row decoder and / or a column decoder, which determines which of the memory cells are accessed based on a given memory address, e.g., an address of a data word included in a memory write request or a memory read request. For instance, in an example implementation, the memory 110 can be configured to implement entries (data words) of 40 bits each. An address, within a valid address range of the memory 110, can be provided to the memory controller 114, e.g.,as part of a memory access request, which the memory controller 114 can then decode to access (read or write) the 40 bits of the data word corresponding with that address.

[0045] The address comparator 120 and the defective address storage 130 can be configured to cooperatively determine when redundancy for memory reads and / or writes should be used. For instance, the defective address storage 130 can store one or more addresses, e.g., within the valid address range of the memory 110, where an address stored in the defective address storage 130 corresponds to a data word that has been determined, e.g., by functional testing of the memory 110, to have at least one defective memory cell. In some implementations, the defective address storage 130 can be configured to store more than one address. Accordingly, in this example, the integrated circuit 100 can implement flop-based redundancy for more than one data word, where each of the addresses stored in the defective address storage 130 corresponds with a respective data word that was identified as having one or more defective bits. Accordingly, addresses stored in the defective address storage 130 can be referred to as defective addresses.

[0046] In an example implementation, the defective address storage 130 can be implemented using a block of programmable fuses that are programmed with identified defective addresses of the memory 110. If no defective bits are identified for the memory 110 of the integrated circuit 100, a fuse block of the defective address storage 130 can remain unprogrammed. For instance, if no defective addresses are identified, the defective address storage 130 can include default values for each available storage location for storing defective addresses, which can be values outside a valid address range of the memory 110.

[0047] In this example, when a request (e.g., a write request or a read request) to access a data word in the memory 110 is received, the address comparator 120 can compare an address included in the request to any defective addresses stored in the defective address storage 130. In some implementations, this comparison can be a bit-wise XOR comparison. If the address comparator 120 determines that the received address matches a defective address stored in the defective address storage 130, the address comparator 120 can generate a respective indication signal, e.g., a respective redundancy hit signal (R HIT), to indicate that redundancy flops should be accessed to process the request, e.g., without accessing the memory cell array 112.

[0048] That is, in this situation, the match between the address in the memory access request with an address stored in the defective address storage 130 indicates that the request to access the memory 110 is for a data word at an address of the memory cell array 112 that was determined to have at least one defective bit. Then, to process the request, accessing thememory cell array 112 having the defective bit is bypassed, and the request is processed using redundancy flops, as described herein. That is, the request to access a defective address of the memory cell array 112 can be processed by writing data to, or reading previously written data from, L2 latches of redundancy flops.

[0049] As shown in FIG. 1, the global I / O 140 is illustrated as overlapping with the redundancy circuit 150. For instance, in this example, the redundancy circuit 150 can include circuitry that is configured to generate write clock signals and / or read clock signals, as well as one or more control signals that are used for processing memory requests for defective addresses of the memory 110 (as indicated by the addresses saved in the defective address storage 130) with redundancy flops. Furthermore, redundancy flops of the redundancy circuit 150 can be implemented using circuit elements that are included in the global I / O, e.g., LI latches and L2 latches. Depending on the particular implementation, the LI latches and / or the L2 latches of the redundancy flops can be repurposed (e.g., shared) latches. That is, the LI and / or L2 latches of the redundancy flops can be used for multiple functions in the integrated circuit 100, such as those described herein.

[0050] In the integrated circuit 100, the MBIST 160 can be configured to perform functional tests (e.g., pattern tests) on the memory 110. For instance, during testing of the integrated circuit 100, the MBIST 160 can run a plurality of functional pattern tests on the memory 110 of the integrated circuit 100 to verify that the memory cells of the memory cell array 112 operate properly, e.g., are able to both properly store and retain data. For instance, such functional pattern testing can include use of a checkerboard pattern, a checkerboard# pattern, all Is, all 0s, marching Is, marching 0s, and so forth. If the MBIST 160 detects a defective bit, or multiple defective bits, the MBIST 160 can be configured to store the data word address(es) corresponding with the defective bit(s) in the defective address storage 130. That is, the MBIST 160 can program defective addresses in a fuse block of the defective address storage 130. The stored defective addresses can then be used later (e.g., by the address comparator 120) to determine when corresponding redundancy flops should be used for writing to, and reading from, those defective addresses in response to a memory access request.

[0051] In example implementations, if one or more defective addresses are identified, a redundancy enable signal (R enable) is asserted, e.g., by programming a fuse. The R enable signal then can be provided to the address comparator 120, the memory 110, the redundancy circuit 150, and / or the MBIST 160 to indicate that flop-based redundancy is enabled. That is, the R enable signal can be used to indicate to the different portions of theintegrated circuit 100 associated with operation of the memory 110 that flop-based redundancy is active, and memory access requests should be processed accordingly, e.g., with memory access requests for defective addresses stored in the defective address storage 130 being processed using redundancy flops.

[0052] FIG. 2 is a block diagram illustrating an example memory 200 with flop-based redundancy. In some implementations, the memory 200 can be used to implement the memory 110, as well as other elements of the integrated circuit 100. As shown in FIG. 2, the memory 200 includes a memory cell array 212, which includes a plurality of rows 212a, that are ordered left to right in the view of FIG. 2, and a plurality of columns 212b, that are ordered bottom to top in the view of FIG. 2. A memory slice of multiple columns of the plurality of columns 212b is indicated in FIG. 2. Each row 212a of the memory cell array 212 includes a memory cell per column 212b. Likewise each column 212b includes a memory cell per row 212a. That is, in the memory cell array 212, there is a respective memory cell at the intersection of each row 212a and each column 212b.

[0053] The memory 200 further includes an address decoder 214, an address comparator 220, a global I / O block (global I / O slice 240) that corresponds with the columns of the indicated memory, a redundancy clock and control circuit 250, and a data output selection multiplexer (mux 270). In this example, the address decoder 214 can be included in a memory controller, such as the memory controller 114 of FIG. 1, where the memory controller includes an interface for receiving memory access requests, e.g., write and read requests. In this example, the address comparator 220 and the redundancy clock and control circuit 250 are included in a global control block 260 of the memory 200. The address decoder 214 can decode a received address of a request to determine a corresponding row of the memory cell array 212, e.g., for non-redundant memory accesses. In implementations using column muxing, the memory cell array 212 can also decode a received address to determine which columns of the memory cell array 212 should be accessed for writing or reading a data word corresponding with the requested address. In some implementations, separate address and column decoders can be included in the address decoder 214. The arrangement of the memory 200 in FIG. 2 is given by way of example, and for purposes of illustration. In some implementations, other arrangements are possible. For instance, global I / O and global control could be implemented in a single block, additional circuits / block could be included, the circuits / blocks illustrated in FIG. 2 can be arranged in different configurations, and so forth.

[0054] As shown in FIG. 2, the address comparator 220, when enabled by an R enable signal, such as described above, can receive an address included in a memory access request, and also receive any defective addresses that have been identified in the memory cell array 212, e.g., where, based on the identification of one or more defective memory cells by functional patterning testing, the defective address(es) can be stored in a fuse block, such as in the defective address storage 130 of FIG. 1. The address comparator 220 of the memory 200 is configured to compare a received address of a request to any identified defective addresses provided to the address comparator 220. The received address of the request can be received directly by the address comparator 220, or can be provided by a memory controller, etc. If there is no match between the received address and any provided defective address(es), the memory access request is processed using the memory cell array 212 to complete a write or read of a requested data word address. If there is a match between the requested address and a defective address, the address comparator 220 generates a respective redundancy hit signal (R HITx), where x represents a respective defective address. For instance, if there are two defective addresses identified for the memory 200, a match between a requested address and a first defective address can result in a R HIT0 being asserted, while a match between a requested address and a second defective address can result in a R HITl being asserted. The specific R HITx signal that is asserted, in this example, is used by the memory 200 to determine a corresponding set of redundancy flops that should be used for processing memory accesses for respective defective address matches identified by the address comparator 220.

[0055] As shown in FIG. 2, the global I / O block (global I / O slice 240) includes read and write multiplexers (R / W muxes 242), DIN (LI) latches 244 and redundant (L2) latches 246. In this example, the R / W muxes 242 are configured to select between memory read and memory write operations. The R / W muxes 242 in the memory 200 are used to select between read and write operations for both normal operations performed in the memory cell array 212, and for redundant memory operations performed using redundant flops.

[0056] In this example, a respective set of redundant flops for providing memory redundancy for a given defective address can include a respective DI latch of the DIN (LI) latches 244, and the DIN (LI) latches 244 can be shared with the memory array. That is, the DIN (LI) latches 244 can be configured to write to the memory cell array 212 for nondefective addresses, and to write to respective latches of the redundant (L2) latches 246 for defective addresses. As discussed above, the redundant (L2) latches 246 can be latches included in the global I / O block (global I / O slice 240) for use as redundant L2 latches, or canbe latches that are repurposed from flops having other functions, such as general I / O flops, boundary scan flops, etc. As discussed herein, the DIN (LI) latches 244 of the redundant flops can be negative edge latches, while the redundant (L2) latches 246 of the redundant flops can be positive edge latches. Accordingly, for data writes to the redundant flops, the data being written, for each redundant flop, can be captured in the LI latch on a falling edge of a redundancy write clock (R WCLK), and written from the LI to the L2 latch of the redundancy flop on a next rising of R WCLK. In this example, R WCLK for a redundant flop can be generated in response to a write enable (WrEn) signal being asserted and a corresponding R HITx signal being asserted. In this situation, the WrEn signal indicates that a memory write request has been made, while the R HITx signal indicates the address of the write request matched a corresponding defective address, as determined by the address comparator 220.

[0057] In the example of FIG. 2, the mux 270 is used to select between data output from the memory cell array 212 and data output from the redundant flops. That is, the mux 270 is used to select an entry in the memory cell array 212, or select a plurality of LI latch and L2 latch combinations. This selection, as shown in FIG. 2, can be based, e.g., directly, or indirectly, on a corresponding R HITx signal. In other words, if an address of a memory read request matches a defective address, the address comparator 220 asserts the corresponding R HITx signal and, in response, the mux 270 selects data output from the associated redundant flops for that defective address.

[0058] FIG. 3 is a diagram illustrating an example of a memory column slice 300 of a column-muxed memory with flop-based redundancy. In this example, FIG. 3 illustrates an example redundant flop corresponding with a single column mux. The memory column slice 300 includes a memory slice 305 and an associated redundant flop 310. In this example, for purpose of illustration, elements and / or signals of an associated redundant clock and control block, e.g., the redundancy clock and control circuit 250 of FIG. 2, are shown in the associated redundant flop 310 of the memory column slice 300.

[0059] In this example, the memory column slice 300 can be replicated to correspond to a number of bits in each data word of a corresponding memory cell array. For instance, in the previous example of 40-bit entries, the memory column slice 300 is replicated 40 times, i.e., once for each redundant data bit that is used for replacing a single memory cell array entry. That is, the associated redundant flop 310 is replicated once for each associated column mux and corresponding memory slice 305.

[0060] In this example, the redundant flop 310 includes an LI latch 344 and a corresponding L2 latch 346, where an output of the LI latch 344 is coupled to an input of the L2 latch 346. An output of the L2 latch 346 is coupled to an input of a column mux 370a, and the output of the mux 370a is coupled to an input of a 2-to-l mux 370b, that is used to multiplex between a data output of the memory slice 305 and a data output of the L2 latch 346 of the redundancy flop 310, e.g., via the mux 370a.

[0061] In an example implementation using 8-to-l column muxing, the memory slice 305 includes eight columns of an associated memory cell array that are multiplexed from a corresponding write bit line for a memory array write, and demultiplexed to a corresponding read bit line for a memory read, where selection between write and read operations can be controlled by an associated R / W mux, such as described above with respect to FIG. 2.

[0062] When performing a redundant data write to the associated redundant flop 310 for the memory column slice 300, the following occurs in this example. A request to write to a defective address corresponding with the memory column slice 300 is received. An address comparator (120, 220) then determines that a defective address match has occurred and asserts a corresponding R HITx signal to indicate that match, and that the redundant flop 310 (and corresponding redundant flops for that address) should be used for the data write. Additionally in response to receiving the write request, the WrEn signal can be asserted, e.g., by a corresponding memory controller.

[0063] In this example, in response to the WrEn signal and the R HITx signal being asserted, a redundancy clock and control block 350 can generate an internal write- enable redundancy clock signal (WrEN Rclock), which is then buffered and provided to the L2 latch 346 as the R WCLK signal. The data bit (DIN) being written to the associated redundant flop 310 is clocked into the LI latch 344 on a negative edge of a WCLK, which can be a shared clock between normal memory array writes and redundant flop writes. After being clocked into the LI latch 344, the data DIN is written from the LI latch 344 to the L2 latch 346 on the next rising edge of R WCLK, e.g., during contemporaneous assertion of WrEN and R HITx, indicating a write request for a defective address.

[0064] When performing a redundant data read from the associated redundant flop 310 for the memory column slice 300, the following occurs in this example. If an address included in a read request matches a defective address, a corresponding R HITx signal is generated, e.g., by an address comparator (120, 220). Corresponding column select signals R COLSEL and MEM COLSEL signals for each column mux are also generated. In this example, for a redundancy flop read, R COLSEL is asserted and MEM COLSEL is de-asserted. During the redundant read operation, a read enable signal (RdEn) (not specifically shown in FIG. 3), is also asserted to indicate a read operation is being performed. In this situation, the stored data (e.g., previously written data) in the L2 latch 346 (RED DATA) is selected by the column mux 370a based on RR COLSEL signal and an output of the mux 370a is Q RED.

[0065] Further in this example, the MEM COLSEL and R COLSEL signals are mutually exclusive to one another. That is, if R COLSEL is asserted, or logic 1, then MEM COLSEL is de-asserted, or logic 0. Accordingly, if MEM COLSEL is de-asserted (for a redundancy flop read), then the output Q RED from the mux 370a is selected and output as Q from the mux 370b. Otherwise, e.g., during a non-redundant, normal read operation, MEM COLSEL is asserted, R COLSEL is de-asserted, and the output from the memory slice 305 (Q_MEM) is read out as Q via the mux 370b.

[0066] FIG. 4 is a flowchart illustrating a method 400 of operation of a memory with flop-based redundancy. The method 400 can be implemented using the circuits described herein, such as using implementations of the circuits illustrated in FIGs. 1 to 3. For purposes of illustration, and by way of example, the method 400 is described with further reference to illustrated elements and described aspects of FIGs. 1 to 3. In some implementations, the method 400 can be implemented using circuits having other configurations.

[0067] Initially, while not specifically shown in FIG. 4, the method 400 can include generating clock signals, e.g., read and write clock signals, and control signals that can be used for processing memory access requests in either a memory array (for non-defective addresses) or using flop-based redundancy (for defective addresses), as described herein. For instance, such clock and control signals for processing memory access requests using redundancy flops can be generated by the redundancy circuit 150 of FIG. 1 and / or the redundancy clock and control circuit 250 of FIG. 2, where the control signals can include, e.g., a write enable signal(s) and a read enable signal(s). In some implementations, a same clock signal can be used for performing reads from a memory and for performing reads from corresponding redundant flops.

[0068] The method 400 includes, at block 410, receiving a request to access a memory location. The request can be received, e.g., by a memory controller (114), and / or an address comparator (120, 220). In some implementations, the memory controller can be configured to receive the request and then provide the request to the address comparator. At block 420, the method 400 includes comparing, by the address comparator, an address of a data word that is included in the request, e.g., the data word the request is seeking to access.Based on the comparison at block 420, at block 430, the method includes determining if the address included in the request matches a defective address stored in defective address storage (130), such as in a fuse block of the defective address storage. If a match is not detected, the method 400 proceeds to block 440 and the memory access request (read or write) is processed from memory cells in the memory cell array using corresponding clock and control signals.

[0069] However, if a match is detected at block 430 (based on the comparison of block 420), a respective R HIT signal corresponding with the matched defective address can be generated and the method 400 proceeds to block 450. At block 450, a determination is made whether the request of block 410 is a write request, e.g., by examining a write enable signal (WrEn). If the request is a write request, e.g., WrEn is asserted, the method 400 proceeds to block 460, and the request of block 410 is processed by writing data included in the request to redundancy flops associated with the defective address detected at block 430.

[0070] If it is determined at block 450, that the request of block 410 is not a write request, e.g., WrEn is not asserted, the method 400 proceeds to block 470, and a mux (270, 370b) is used to select redundant flops as a read source, e.g., in response to a read . The method 400 then proceeds to block 480, and previously written data is read from the redundancy flops, using and / or in response to clock and control signals, e.g., a read enable signal (RdEn), the corresponding R HIT signal, etc.. In example implementations, the clock and control signals of block 470 and block 480 can be generated by and / or provided by a redundancy circuit (150, 250).

[0071] FIG. 5 is a schematic diagram of an example architecture of a computing device 550 that can be used to implement aspects of the present disclosure, including any of the plurality of computing devices described herein, such as a computing device of that includes the integrated circuit 100, or any other computing devices that may be utilized in the various possible embodiments.

[0072] The computing device illustrated in FIG. 5 can be used to execute the operating system, application programs, and software modules described herein.

[0073] The computing device 550 includes, in some embodiments, at least one processing device 560, such as a central processing unit (CPU). A variety of processing devices are available from a variety of manufacturers, for example, Intel or Advanced Micro Devices. In this example, the computing device 550 also includes a system memory 562, and a system bus 564 that couples various system components including the system memory 562 to the processing device 560. The system bus 564 is one of any number of types of busstructures including a memory bus, or memory controller; a peripheral bus; and a local bus using any of a variety of bus architectures.

[0074] Examples of computing devices suitable for the computing device 550 include a desktop computer, a laptop computer, a tablet computer, a mobile computing device (such as a smart phone, an iPod® or iPad® mobile digital device, or other mobile devices), or other devices configured to process digital instructions.

[0075] The system memory 562 includes read only memory 566 and random access memory 568. A basic input / output system 570 containing the basic routines that act to transfer information within computing device 550, such as during start up, is typically stored in the read only memory 566.

[0076] The computing device 550 also includes a secondary storage device 572 in some embodiments, such as a hard disk drive, for storing digital data. The secondary storage device 572 is connected to the system bus 564 by a secondary storage interface 574. The secondary storage devices 572 and their associated computer readable media provide nonvolatile storage of computer readable instructions (including application programs and program modules), data structures, and other data for the computing device 550.

[0077] Although the example environment described herein employs a hard disk drive as a secondary storage device, other types of computer readable storage media are used in other embodiments. Examples of these other types of computer readable storage media include magnetic cassettes, flash memory cards, digital video disks, Bernoulli cartridges, compact disc read only memories, digital versatile disk read only memories, random access memories, or read only memories. Some embodiments include non-transitory computer- readable media. Additionally, such computer readable storage media can include local storage or cloud-based storage.

[0078] A number of program modules can be stored in secondary storage device 572 or system memory 562, including an operating system 576, one or more application programs 578, other program modules 580 (such as the software engines described herein), and program data 582. The computing device 550 can utilize any suitable operating system, such as Microsoft Windows™, Google Chrome™ OS or Android, Apple OS, Unix, or Linux and variants and any other operating system suitable for a computing device. Other examples can include Microsoft, Google, or Apple operating systems, or any other suitable operating system used in tablet computing devices.

[0079] In some embodiments, a user provides inputs to the computing device 550 through one or more input devices 584. Examples of input devices 584 include a keyboard586, mouse 588, microphone 590, and touch sensor 592 (such as a touchpad or touch sensitive display). Other embodiments include other input devices 584. The input devices are often connected to the processing device 560 through an input / output interface 594 that is coupled to the system bus 564. These input devices 584 can be connected by any number of input / output interfaces, such as a parallel port, serial port, game port, or a universal serial bus. Wireless communication between input devices and the interface 594 is possible as well, and includes infrared, BLUETOOTH® wireless technology, 802.11a / b / g / n, cellular, ultra- wideband (UWB), ZigBee, or other radio frequency communication systems in some possible embodiments.

[0080] In this example embodiment, a display device 596, such as a monitor, liquid crystal display device, projector, or touch sensitive display device, is also connected to the system bus 564 via an interface, such as a video adapter 598. In addition to the display device 596, the computing device 550 can include various other peripheral devices (not shown), such as speakers or a printer.

[0081] When used in a local area networking environment or a wide area networking environment (such as the Internet), the computing device 550 is typically connected to the network through a network interface 599, such as an Ethernet interface or WiFi interface. Other possible embodiments use other communication devices. For example, some embodiments of the computing device 550 include a modem for communicating across the network.

[0082] The computing device 550 typically includes at least some form of computer readable media. Computer readable media includes any available media that can be accessed by the computing device 550. By way of example, computer readable media include computer readable storage media and computer readable communication media.

[0083] Computer readable storage media includes volatile and nonvolatile, removable, and non-removable media implemented in any device configured to store information such as computer readable instructions, data structures, program modules or other data. Computer readable storage media includes, but is not limited to, random access memory, read only memory, electrically erasable programmable read only memory, flash memory or other memory technology, compact disc read only memory, digital versatile disks or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and that can be accessed by the computing device 550.

[0084] Computer readable communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media. The term “modulated data signal” refers to a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, computer readable communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, radio frequency, infrared, and other wireless media. Combinations of any of the above are also included within the scope of computer readable media.

[0085] The computing device illustrated in FIG. 5 is also an example of programmable electronics, which may include one or more such computing devices, and when multiple computing devices are included, such computing devices can be coupled together with a suitable data communication network so as to collectively perform the various functions, methods, or operations disclosed herein.

[0086] In a general aspect, a circuit includes a memory array having a plurality of memory cells configured to store a plurality of data words in a plurality of rows and in a plurality of columns. The plurality of data words are respectively addressable. The circuit further includes an interface configured to receive a request to access a data word of the plurality of data words, including an address of the data word. The circuit further includes an address comparator configured to compare the address of the request with a stored address identifying a defective memory cell, and a redundancy circuit that is configured to, in response to the address comparator determining that the address of the request matches the stored address, redirect processing of the request from the memory array to a plurality of latches that are external to the memory array.

[0087] Implementations can include one or more of the following features, alone or in combination. For example, the request to access the data word can be a write request to write data to the memory array, and processing the request to access the data word can include writing the write data to the plurality of latches.

[0088] Writing the write data to the plurality of latches can include writing the write data from respective data input latches. The respective data input latches can be configured to write to the memory array.

[0089] The plurality of latches can be positive edge triggered latches. The respective data input latches can be negative edge triggered latches. Each latch of the plurality of latches and its respective data input latch can define a flop configured to store a data bit.

[0090] The request to access the data word can be a read request to read data from the memory array. Processing the request to access the data word includes reading the requested data from the plurality of latches.

[0091] A latch of the plurality of latches can be coupled to a data input latch to define a flop configured to store a data bit. The data input latch can be configured to selectively write the data bit to the latch or to a memory cell of the plurality of memory cells of the memory array.

[0092] The plurality of latches can be included in a global input and output circuitry block of the circuit. The plurality of latches can be repurposed from boundary scan flops of the circuit.

[0093] The stored address can be a first stored address, the plurality of latches can be a first plurality of latches, and the defective memory cell can be a first defective memory cell. The address comparator can be configured to compare the address of the request with a second stored address identifying a second defective memory cell. The redundancy circuit can be configured to, in response to the address comparator determining that the address of the request does not match the first stored address and the address of the request matches the second stored address, redirect processing of the request from the memory array to a second plurality of latches that are external to the memory array.

[0094] The request to access the data word can be one of a write request to write data to the memory array, or a read request to read data from the memory array. Processing the write request can include writing the write data to the second plurality of latches. Processing the read request can include reading the requested data from the second plurality of latches.

[0095] The circuit can include a memory built in self-test (MBIST) module configured to, in response to execution of one or more memory tests implemented by the MBIST module identifying the defective memory cell, write the stored address in a fuse block of the circuit.

[0096] The stored address can correspond with a row of the memory array including the defective memory cell. The stored address can correspond with a data word of the plurality of data words that includes the defective memory cell.

[0097] Processing the request can exclude accessing the memory array.

[0098] Determining that the address of the request matches the stored address can be based on a bit-wise XOR of the address of the request with the stored address.

[0099] The redundancy circuit can be configured to generate a first clock signal that is used for performing data writes to the memory array, to generate a second clock signal thatis used for performing data reads from the memory array, to generate a third clock signal that is used for performing data writes to the plurality of latches, and to generate a fourth clock signal that is used for performing data reads from the plurality of latches. The second clock signal and the fourth clock signal can be a same clock signal.

[0100] In another general aspect, a method includes receiving a request to access a data word in a memory array, the memory array including a plurality of memory cells configured to store a plurality of respectively addressable data words in a plurality of rows and a plurality of columns. The data word is included in the plurality of respectively addressable data words, and the request includes an address of the data word. The method further includes comparing the address of the request with a stored address identifying a defective memory cell. In response to a determination that the address of the request matches the stored address, the method includes processing the request to access the data word using a plurality of latches that are external to the memory array.

[0101] The request to access the data word can be a write request to write data to the memory array. Processing the request to access the data word can include writing the write data to the plurality of latches.

[0102] Writing the write data can include writing the write data to the plurality of latches from respective data input latches that are also configured to write to the memory array.

[0103] The request to access the data word is a read request to read data from the memory array. Processing the request to access the data word can include reading the requested data from the plurality of latches.

[0104] The stored address can be a first stored address, the plurality of latches can be a first plurality of latches, and the defective memory cell can be a first defective memory cell. The method can include, in response to determining that the address of the request does not match the first stored address, comparing the address of the request with a second stored address identifying a second defective memory cell. In response to determining that the address of the request matches the second stored address, the method can include processing the request to access the data word using a second plurality of latches that are external to the memory array. The request to access the data word can be one of a write request to write data to the memory array, or a read request to read data from the memory array. Processing the write request can include writing the write data to the second plurality of latches. Processing the read request can include reading the requested data from the second plurality of latches.

[0105] Comparing the address of the request with the stored address can include comparing the address of the request with an address that is stored in a fuse block in response to execution of one or more memory built in self-tests implemented by the circuit that identify the defective memory cell.

[0106] Processing the request can exclude accessing the memory array.

[0107] Determining that the address of the request matches the stored address can be based on a bit-wise XOR of the address of the request with the stored address.

[0108] The method can include generating a first clock signal that is used by the circuit to performing data writes to the memory array, generating a second clock signal that is used by the circuit for performing data reads from the memory array, generating a third clock signal that is used by the circuit for performing data writes to the plurality of latches, and generating a fourth clock signal that is used by the circuit for performing data reads from the plurality of latches. The second clock signal and the fourth clock signal can be a same clock signal.

Claims

What is claimed is:

1. A circuit comprising: a memory array including a plurality of memory cells configured to store a plurality of data words in a plurality of rows and in a plurality of columns, the plurality of data words being respectively addressable; an interface configured to receive a request to access a data word of the plurality of data words, the request including an address of the data word; an address comparator configured to compare the address of the request with a stored address identifying a defective memory cell; and a redundancy circuit configured to, in response to the address comparator determining that the address of the request matches the stored address, redirect processing of the request from the memory array to a plurality of latches that are external to the memory array.

2. The circuit of claim 1, wherein: the request to access the data word is a write request to write data to the memory array; and processing the request to access the data word includes writing the write data to the plurality of latches.

3. The circuit of claim 2, wherein writing the write data to the plurality of latches includes writing the write data from respective data input latches, wherein the respective data input latches are configured to write to the memory array.

4. The circuit of claim 3, wherein: the plurality of latches are positive edge triggered latches, the respective data input latches are negative edge trigger latches, and each latch of the plurality of latches and its respective data input latch define a flop configured to store a data bit.

5. The circuit of claim 1, wherein: the request to access the data word is a read request to read data from the memory array; andprocessing the request to access the data word includes reading the requested data from the plurality of latches.

6. The circuit of claim 5, wherein a latch of the plurality of latches is coupled to a data input latch to define a flop configured to store a data bit, the data input latch being configured to selectively write the data bit to the latch or to a memory cell of the plurality of memory cells of the memory array.

7. The circuit of any one of the previous claims, wherein the plurality of latches are included in a global input and output circuitry block of the circuit.

8. The circuit of any one of claims 1 to 6, wherein the plurality of latches are repurposed from boundary scan flops of the circuit.

9. The circuit of any one of the previous claims, wherein: the stored address is a first stored address, the plurality of latches is a first plurality of latches, and the defective memory cell is a first defective memory cell; the address comparator is further configured to compare the address of the request with a second stored address identifying a second defective memory cell; and the redundancy circuit is further configured to, in response to the address comparator determining that the address of the request does not match the first stored address and the address of the request matches the second stored address, redirect processing of the request from the memory array to a second plurality of latches that are external to the memory array.

10. The circuit of claim 9, wherein: the request to access the data word is one of a write request to write data to the memory array, or a read request to read data from the memory array, processing the write request includes writing the write data to the second plurality of latches, and processing the read request includes reading the requested data from the second plurality of latches.

11. The circuit of claim any one of the previous claims, further comprising a memory built in self-test (MBIST) module configured to, in response to execution of one or more memory tests implemented by the MBIST module identifying the defective memory cell, write the stored address in a fuse block of the circuit.

12. The circuit of claim any one of the previous claims, wherein the stored address corresponds with a row of the memory array including the defective memory cell.

13. The circuit of claim any one of the previous claims, wherein the stored address corresponds with a data word of the plurality of data words including the defective memory cell.

14. The circuit of claim any one of the previous claims, wherein processing the request excludes accessing the memory array.

15. The circuit of claim any one of the previous claims, wherein determining that the address of the request matches the stored address is based on a bit-wise XOR of the address of the request with the stored address.

16. The circuit of claim any one of the previous claims, wherein the redundancy circuit is further configured to: generate a first clock signal that is used for performing data writes to the memory array; generate a second clock signal that is used for performing data reads from the memory array; generate a third clock signal that is used for performing data writes to the plurality of latches; and generate a fourth clock signal that is used for performing data reads from the plurality of latches.

17. The circuit of claim 16, wherein the second clock signal and the fourth clock signal are a same clock signal.

18. A method comprising: receiving, at a memory controller of a circuit, a request to access a data word in a memory array, the memory array including a plurality of memory cells configured to store a plurality of respectively addressable data words in a plurality of rows and a plurality of columns, the data word being included in the plurality of respectively addressable data words, the request including an address of the data word; comparing, by an address comparator, the address of the request with a stored address identifying a defective memory cell; and in response to a determination by the address comparator that the address of the request matches the stored address, processing the request to access the data word using a plurality of latches that are external to the memory array.

19. The method of claim 18, wherein: the request to access the data word is a write request to write data to the memory array; and processing the request to access the data word includes writing the write data to the plurality of latches.

20. The method of claim 19, wherein writing the write data includes writing the write data to the plurality of latches from respective data input latches that are configured to write to the memory array.

21. The method of claim 18, wherein: the request to access the data word is a read request to read data from the memory array; and processing the request to access the data word includes reading the requested data from the plurality of latches.

22. The method of claim 18, wherein the stored address is a first stored address, the plurality of latches is a first plurality of latches, and the defective memory cell is a first defective memory cell, the method further comprising: in response to the address comparator determining that the address of the request does not match the first stored address, comparing, by the address comparator,the address of the request with a second stored address identifying a second defective memory cell; and in response to determining, by the address comparator, that the address of the request matches the second stored address, processing the request to access the data word using a second plurality of latches that are external to the memory array.

23. The method of claim 22, wherein: the request to access the data word is one of a write request to write data to the memory array, or a read request to read data from the memory array, processing the write request includes writing the write data to the second plurality of latches, and processing the read request includes reading the requested data from the second plurality of latches.

24. The method of any one of claims 18 to 23, wherein comparing the address of the request with the stored address includes comparing the address of the request with an address that is stored in a fuse block in response to execution of one or more memory built in self-tests implemented by the circuit that identify the defective memory cell.

25. The method of any one of claims 18 to 23, wherein processing the request excludes accessing the memory array.

26. The method of any one of claims 18 to 23, wherein determining that the address of the request matches the stored address is based on a bit-wise XOR of the address of the request with the stored address.

27. The method of any one of claims 18 to 23, further comprising: generating a first clock signal that is used by the circuit to performing data writes to the memory array; generating a second clock signal that is used by the circuit for performing data reads from the memory array; generating a third clock signal that is used by the circuit for performing data writes to the plurality of latches; andgenerating a fourth clock signal that is used by the circuit for performing data reads from the plurality of latches.

28. The method of claim 27, wherein the second clock signal and the fourth clock signal are a same clock signal.

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