Display substrate and manufacturing method therefor, and display apparatus

Abstract

A display substrate, comprising: a base (101) and a circuit structure layer (102) arranged on the base (101). The circuit structure layer (102) comprises at least a plurality of circuit units, wherein at least one circuit unit comprises a pixel driving circuit, the pixel driving circuit comprising a plurality of driving transistors (T3). First terminals of the plurality of driving transistors (T3) are connected to each other, second terminals of the plurality of driving transistors (T3) are connected to each other, and gate electrodes of the plurality of driving transistors (T3) are connected to each other.

Description

Display substrate and manufacturing method thereof, and display device Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, the present disclosure provides a display substrate, including a base and a circuit structure layer arranged on the base, the circuit structure layer including at least a plurality of circuit units, at least one circuit unit including a pixel driving circuit, the pixel driving circuit including: a plurality of driving transistors; the first electrodes of the plurality of driving transistors are interconnected, the second electrodes of the plurality of driving transistors are interconnected, and the gate electrodes of the plurality of driving transistors are interconnected.

[0006] In an exemplary embodiment, the pixel driving circuit further includes: a storage capacitor, the storage capacitor including: a first plate and a second plate, the second plate being located on a side of the first plate away from the substrate; the orthographic projection of the first plate on the substrate at least partially overlaps with the orthographic projection of the second plate on the substrate; the first plate including: a plurality of first sub-plates, a single first sub-plate serving as a gate electrode of at least one of the driving transistors.

[0007] In an exemplary embodiment, the plurality of first sub-plates of the first electrode plate are independently provided and electrically connected via a second connecting electrode; the second connecting electrode is located on a side of the second electrode plate away from the substrate.

[0008] In an exemplary embodiment, the pixel driving circuit further includes: a first initialization transistor and a threshold compensation transistor; the first electrode of the first initialization transistor is connected to the first initial signal line, and the second electrode of the first initialization transistor is connected to the gate electrodes of the multiple driving transistors; the second electrode of the threshold compensation transistor is connected to the gate electrodes of the multiple driving transistors, and the first electrode of the threshold compensation transistor is connected to the second electrode of the multiple driving transistors; the first initial transistor and the threshold compensation transistor are connected to the gate electrodes of the multiple driving transistors through the second connecting electrode.

[0009] In an exemplary embodiment, in a direction perpendicular to the display substrate, the circuit structure layer includes at least: a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer arranged in sequence on the base; the first plate of the storage capacitor is located in the first conductive layer, the second plate is located in the second conductive layer, and the second connecting electrode is located in the third conductive layer.

[0010] In an exemplary embodiment, the plurality of driving transistors are arranged sequentially along a second direction, the second plate of the storage capacitor extends along the second direction, and the second plate has a first end and a second end along the second direction; the first end and the second end of the second plate are respectively connected to a first power line; and the first power line is located on a side of the second plate away from the substrate.

[0011] In an exemplary embodiment, the circuit structure layer also includes: a data line connected to the pixel driving circuit and extending along the second direction, a first data transfer line extending along the first direction, and a second data transfer line extending along the second direction; the first direction intersects the second direction; the data line is connected to the second data transfer line through the first data transfer line; the first data transfer line is located on the side of the data line close to the substrate, and the second data transfer line is arranged on the same layer as the data line.

[0012] In an exemplary embodiment, the circuit structure layer further includes: a first power line connected to the pixel driving circuit; the data line and the first power line are provided in the same layer and are spaced apart in the first direction.

[0013] In an exemplary embodiment, the pixel driving circuit further includes: a first initialization transistor, a first electrode of the first initialization transistor being connected to a first initial signal line, and a second electrode of the first initialization transistor being connected to gate electrodes of the plurality of driving transistors; the first initial signal line extending along a first direction, the first initial signal line being connected to a first initial signal connecting line extending along a second direction, the first direction intersecting the second direction; the first initial signal connecting line being located on a side of the first initial signal line away from the substrate.

[0014] In an exemplary embodiment, the pixel driving circuit further includes: a second initialization transistor, a first electrode of the second initialization transistor being connected to a second initial signal line, and a second electrode of the second initialization transistor being connected to a first electrode of a light-emitting device connected to the pixel driving circuit; the second initial signal line extending along the first direction, and the second initial signal line being connected to a second initial signal connection line extending along the second direction; the second initial signal line and the first initial signal line being arranged on the same layer, and the second initial signal connection line and the first initial signal connection line being arranged on the same layer.

[0015] In an exemplary embodiment, the pixel driving circuit further includes: a first initialization transistor and a threshold compensation transistor; the first electrode of the first initialization transistor is connected to the first initial signal line, and the second electrode of the first initialization transistor is connected to the gate electrodes of the plurality of driving transistors; the second electrode of the threshold compensation transistor is connected to the gate electrodes of the plurality of driving transistors, and the first electrode of the threshold compensation transistor is connected to the second electrodes of the plurality of driving transistors; the first initial signal line is connected to a shielding electrode, and a conductorized area of ​​the shielding electrode between the orthographic projection of the substrate and the channel region of the active layer of the threshold compensation transistor at least partially overlaps with the orthographic projection of the substrate; the shielding electrode and the first initial signal line are arranged on the same layer and are located on the side of the gate electrode of the threshold compensation transistor away from the substrate.

[0016] In an exemplary embodiment, the first initialization signal line is connected to the shielding electrode and the first initialization transistor through a first connection electrode; the first connection electrode is located on a side of the first initialization signal line away from the substrate.

[0017] In an exemplary embodiment, the multiple circuit units are divided into multiple circuit unit groups, each circuit unit group includes three pixel driving circuits arranged in sequence along a first direction, and each pixel driving circuit in the circuit unit group is electrically connected to a first power line extending along a second direction; the circuit structure layer also includes: at least one first connecting ring, the first connecting ring is electrically connected to the three first power lines connected to the three pixel driving circuits in the circuit unit group, and the orthographic projection of the first connecting ring on the substrate surrounds the periphery of the three pixel driving circuits; the first connecting ring is located on the side of the first power line away from the substrate.

[0018] In an exemplary embodiment, the circuit structure layer further includes: at least one first transmission ring, which is arranged in the same layer as the first connecting ring and is located outside the first connecting ring; the first transmission ring and the first connecting ring are configured to transmit different voltage signals.

[0019] In an exemplary embodiment, it also includes: a light-emitting structure layer located on a side of the circuit structure layer away from the substrate, the light-emitting structure layer including a plurality of light-emitting devices; three first pixel driving circuits in a circuit unit group are electrically connected to the three light-emitting devices in a one-to-one correspondence; the light-emitting structure layer includes an anode layer, the anode layer includes: anodes of the plurality of light-emitting devices, and at least one second transmission ring; the second transmission ring is electrically connected to the first transmission ring, and the orthographic projection of the second transmission ring on the substrate at least partially overlaps with the orthographic projection of the first transmission ring on the substrate; the second transmission ring is located at the periphery of the anodes of the three light-emitting devices connected to the three first pixel driving circuits of the circuit unit group.

[0020] In an exemplary embodiment, it also includes: a light-emitting structure layer located on a side of the circuit structure layer away from the substrate, the light-emitting structure layer including a plurality of light-emitting devices; wherein the circuit structure layer also includes: a plurality of anode pads electrically connected to the first power line; the anode pads are located on a side of the anode of the light-emitting device close to the substrate, and the orthographic projection of the anode pads on the substrate includes the orthographic projection of the anode of at least one light-emitting device on the substrate; the plurality of anode pads located on the inner side of the first connecting ring are interconnected with the first connecting ring as an integral structure.

[0021] In an exemplary embodiment, at least one of the anode spacers is provided with a plurality of through holes arranged in an array.

[0022] On the other hand, the present disclosure provides a display device including the aforementioned display substrate.

[0023] On the other hand, the present disclosure provides a method for preparing a display substrate, comprising: forming a circuit structure layer on a base; the circuit structure layer comprises at least a plurality of circuit units, at least one circuit unit comprises a pixel driving circuit, and the pixel driving circuit comprises: a plurality of driving transistors; the first electrodes of the plurality of driving transistors are connected to each other, the second electrodes of the plurality of driving transistors are connected to each other, and the gate electrodes of the plurality of driving transistors are connected to each other.

[0024] On the other hand, the present disclosure provides a display substrate, comprising: a base and a circuit structure layer arranged on the base, the circuit structure layer comprising at least: a plurality of circuit units, each circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising: a storage capacitor and a plurality of driving transistors; the storage capacitor comprising: a first electrode plate and a second electrode plate, the first electrode plate serving as a gate electrode of the plurality of driving transistors; the second electrode plate being located on a side of the first electrode plate away from the base; the second electrode plate having a plurality of first openings, the orthographic projection of the first electrode plate on the base covering the orthographic projection of the plurality of first openings of the second electrode plate on the base; a second connecting electrode located on a side of the second electrode plate away from the base is connected to the first electrode plate through a via hole arranged in the plurality of first openings.

[0025] In an exemplary embodiment, within a single circuit unit, the first electrode plate includes multiple first sub-plates, and the single first sub-plate serves as a gate electrode of at least one driving transistor; the multiple circuit units include at least: a first circuit unit, a second circuit unit, and a third circuit unit; the area of ​​the orthographic projection of the first sub-plate in the third circuit unit on the substrate is smaller than the area of ​​the orthographic projection of the first sub-plate in the second circuit unit on the substrate; the area of ​​the orthographic projection of the first sub-plate in the third circuit unit on the substrate is smaller than the area of ​​the orthographic projection of the first sub-plate in the first circuit unit on the substrate.

[0026] In an exemplary embodiment, within a single circuit unit, the second electrode plate has multiple first openings; the multiple circuit units include at least: a first circuit unit, a second circuit unit, and a third circuit unit; the area of ​​the orthographic projection of the first opening of the second electrode plate in the third circuit unit on the substrate is larger than the area of ​​the orthographic projection of the first opening of the second electrode plate in the first circuit unit on the substrate; the area of ​​the orthographic projection of the first opening of the second electrode plate in the third circuit unit on the substrate is larger than the area of ​​the orthographic projection of the first opening of the second electrode plate in the second circuit unit on the substrate.

[0027] In an exemplary embodiment, the plurality of circuit units include at least a first circuit unit, a second circuit unit, and a third circuit unit; the number of first openings in the second plate in the third circuit unit is different from the number of first openings in the second plate in the first circuit unit; and the number of first openings in the second plate in the first circuit unit is the same as the number of first openings in the second plate in the second circuit unit.

[0028] In an exemplary embodiment, the pixel driving circuit in the first circuit unit is connected to the light-emitting device emitting red light, the pixel driving circuit in the second circuit unit is connected to the light-emitting device emitting green light, and the pixel driving circuit in the third circuit unit is connected to the light-emitting device emitting blue light.

[0029] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0030] Summary of the Figures

[0031] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0032] FIG1 is a schematic structural diagram of a display device;

[0033] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0034] FIG3 is a schematic diagram of a partial cross-sectional structure of a display substrate;

[0035] FIG4 is an equivalent circuit diagram of a pixel driving circuit according to at least one embodiment of the present disclosure;

[0036] FIG5 is a timing diagram of an operation of a pixel driving circuit;

[0037] FIG6 is a partial top view of a display substrate according to at least one embodiment of the present disclosure;

[0038] FIG7 is a schematic diagram of the planar structure of the dotted area C in FIG6 ;

[0039] FIG8 is a schematic diagram of the display substrate after the semiconductor layer is formed in FIG7;

[0040] FIG9A is a schematic diagram of the display substrate after the first conductive layer is formed in FIG7 ;

[0041] FIG9B is a schematic diagram of the first conductive layer in FIG9A ;

[0042] FIG9C is a schematic diagram of a first conductive layer in another embodiment;

[0043] FIG10A is a schematic diagram of the display substrate after forming the second conductive layer in FIG7 ;

[0044] FIG10B is a schematic diagram of the second conductive layer in FIG10A ;

[0045] FIG11 is a schematic diagram of the display substrate after the third insulating layer is formed in FIG7 ;

[0046] FIG12A is a schematic diagram of the display substrate after forming the third conductive layer in FIG7;

[0047] FIG12B is a schematic diagram of the third conductive layer in FIG12A;

[0048] FIG13 is a schematic diagram of the display substrate after the fifth insulating layer is formed in FIG7;

[0049] FIG14A is a schematic diagram of the display substrate after forming the fourth conductive layer in FIG7;

[0050] FIG14B is a schematic diagram of the fourth conductive layer in FIG14A;

[0051] FIG15 is a schematic diagram of the display substrate after the sixth insulating layer is formed in FIG7 ;

[0052] FIG16 is a schematic diagram of the anode layer in FIG7 ;

[0053] FIG17A is a schematic diagram of a display substrate after a pixel definition layer is formed on the structure shown in FIG7 ;

[0054] FIG17B is a schematic diagram of the pixel definition layer in FIG17A;

[0055] FIG18 is a schematic diagram of a partial structure of the first circuit unit in FIG7 .

[0056] DESCRIPTION OF NUMERALS: 11—first active layer; 12—second active layer; 13—third active layer; 14—fourth active layer; 15—fifth active layer; 16—sixth active layer; 17—seventh active layer; 21—first scan line; 21-1—first scan protrusion; 22—second scan line; 23—third scan line; 24—light-emitting control line; 25—first data transfer line; 25-1—first data transfer portion; 26—first electrode plate; 26-1, 26-2, 26-3—first sub-plate; 31—first initial signal line; 31-1—first notch; 32—second initial signal line; 32-1—second notch; 33—shielding electrode; 34—second electrode plate; 35-1, 35-2, 35-3—first opening; 38—first auxiliary connection line; 39—second auxiliary connection line; 40—second initial signal connection line; 41—first connection electrode; 42—second connection electrode; 43—third connection electrode; 44—fourth connection electrode; 45—fifth connection electrode; 46—sixth connection electrode; 47—first power line; 47-1—first power connection block; 47-2—second power connection block; 47-3—third power connection block; 48—data line; 48-1—data connection block; 49—first initial signal connection line; 50—second data transfer line; 50-1—second data transfer portion; 51—first connection ring; 52—first anode connection electrode; 53—second anode connection electrode; 54—third anode connection electrode; 55—first anode pad; 55-1—first pad protrusion; 55-2—second pad protrusion; 56—second anode pad; 56-1—third pad protrusion; 56-2—fourth pad protrusion; 57—third anode pad; 57-1—fifth pad protrusion; 58—first transmission ring; 59—first transmission structure;71 — first anode; 71-1 — first anode connection block; 72 — second anode; 72-1 — second anode connection block; 73 — third anode; 73-1 — third anode connection block; 74 — second transmission ring; 81 — first anode opening; 82 — second anode opening; 83 — third anode opening; 101 — substrate; 102 — circuit structure layer; 103 — light-emitting structure layer; 104 — packaging structure layer; 581 — first transmission line segment; 582 — second transmission line segment; 591 — first transmission line; 592 — second transmission line; 741 — third transmission line; 742 — fourth transmission line.

[0057] Details

[0058] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0059] In the accompanying drawings, the size of one or more components, the thickness of a layer, or the area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to this size, and the shape and size of one or more components in the accompanying drawings do not reflect the true proportions. In addition, the accompanying drawings schematically illustrate ideal examples, and one embodiment of the present disclosure is not limited to the shapes or numerical values ​​shown in the accompanying drawings. The proportions of the drawings in the present disclosure can be used as a reference in actual processes, but are not limited to this. For example: the width-to-length ratio of the channel, the thickness and spacing of the film layer, and the width and spacing of the signal line can be adjusted according to actual needs.

[0060] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0061] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0062] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate piece, or a connection between the two elements. For those of ordinary skill in the art, the meaning of the above terms in this disclosure can be understood according to the circumstances. Among them, "electrical connection" includes the situation where constituent elements are connected together through an element with some electrical function. There is no special restriction on "elements with some electrical function" as long as they can transmit electrical signals between connected constituent elements. Examples of "elements with some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with one or more functions.

[0063] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to the region through which current primarily flows.

[0064] In this specification, in order to distinguish the two poles of a transistor other than the gate, one of the electrodes is referred to as the first electrode and the other electrode is referred to as the second electrode. For example, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In cases where transistors with opposite polarities are used or where the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchangeable. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchangeable, and the "source terminal" and the "drain terminal" can be interchangeable.

[0065] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0066] In this specification, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0067] The term "about" in this specification refers to a numerical value that is not strictly limited and allows for process and measurement errors.

[0068] In this specification, "A extends along direction B" means that A can include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In the following description, "A extends along direction B" means "the main portion of A extends along direction B."

[0069] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the display device may include: a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller may be connected to the data driver, the scan driver, and the light-emitting driver, respectively. The data driver is respectively connected to a plurality of data lines (e.g., D1 to Dp), the scan driver is respectively connected to a plurality of scan lines (e.g., S1 to Sm), and the light-emitting driver is respectively connected to a plurality of light-emitting control lines (e.g., E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit may be respectively connected to the scan lines, the light-emitting control lines, and the data lines. The light-emitting unit may include a light-emitting device. The light-emitting device may be electrically connected to the pixel driving circuit of the circuit unit.

[0070] In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver; may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver; and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light emitting driver to the light emitting driver. The data driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be supplied to data lines D1, D2, D3, ..., and Dp. For example, the data driver may use the clock signal to sample the grayscale values ​​and apply data voltages corresponding to the grayscale values ​​to data lines D1 to Dp on a pixel row basis, where p may be a natural number. The scan driver may generate scan signals to be supplied to scan lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver may sequentially supply scan signals having on-level pulses to scan lines S1 to Sm, where m may be a natural number. For example, the scan driver can be constructed in the form of a shift register and can generate a scan signal by sequentially transmitting a scan start signal provided in the form of an on-level pulse to the next-level circuit under the control of a clock signal. The light-emitting driver can generate an emission signal to be provided to the light-emitting control lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the light-emitting driver can sequentially provide an emission signal with an off-level pulse to the light-emitting control lines E1 to Eo, where o can be a natural number. For example, the light-emitting driver can be constructed in the form of a shift register and can generate an emission signal by sequentially transmitting an emission stop signal provided in the form of an off-level pulse to the next-level circuit under the control of a clock signal. In an exemplary embodiment, the pixel array can be provided on a display substrate.

[0071] Figure 2 is a schematic diagram of a planar structure of a display substrate. In an exemplary embodiment, the display substrate may include a display area and a frame area located around the display area. As shown in Figure 2, the display area of ​​the display substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, and a third sub-pixel P3 that emits a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit may be connected to a scan line, a data line, and a light-emitting control line, respectively. The pixel driving circuit may be configured to receive a data voltage transmitted by the data line under the control of the scan line and the light-emitting control line and output a corresponding current to the light-emitting unit. The light-emitting unit may include at least a light-emitting device. The light-emitting device may be connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device may be configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0072] In some examples, the pixel driving circuit may include multiple transistors and at least one capacitor. For example, the pixel driving circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, and C refers to a capacitor. The number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0073] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) emitting red light, the second subpixel P2 may be a blue subpixel (B) emitting blue light, and the third subpixel P3 may be a green subpixel (G) emitting green light.

[0074] In an exemplary embodiment, the shape of the light-emitting device may be rectangular, rhombus, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the light-emitting devices of the three sub-pixels may be arranged in parallel horizontally, vertically, or in a triangle. When a pixel unit includes four sub-pixels, the light-emitting devices of the four sub-pixels may be arranged in parallel horizontally, vertically, or in a square. This disclosure is not limited hereto.

[0075] FIG3 is a schematic diagram of a partial cross-sectional structure of a display substrate. FIG3 illustrates the structure of three sub-pixels in the display substrate. In some examples, as shown in FIG3 , in a direction perpendicular to the display substrate, the display area of ​​the display substrate may include: a substrate 101, a circuit structure layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on a side of the circuit structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in this disclosure.

[0076] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The circuit structure layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit, and the pixel driving circuit may include a plurality of transistors and at least one capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include at least a light-emitting device. The encapsulation structure layer 104 may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0077] In an exemplary embodiment, the light-emitting device may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting device may be an OLED, and the light-emitting device may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel driving circuit. The color of the light emitted by the light-emitting device may be determined as needed. In some examples, the light-emitting device may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting device may be electrically connected to the corresponding pixel driving circuit, the organic light-emitting layer may be connected to the anode, and the cathode may be connected to the organic light-emitting layer. The organic light-emitting layer may emit light of corresponding colors when driven by the anode and the cathode. However, this embodiment is not limited to this.

[0078] In an exemplary embodiment, the organic light-emitting layer may include an emission layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0079] An exemplary embodiment of the present disclosure provides a display substrate, comprising: a base and a circuit structure layer disposed on the base, the circuit structure layer comprising at least a plurality of circuit units, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising: a plurality of driving transistors; the first electrodes of the plurality of driving transistors being interconnected, the second electrodes of the plurality of driving transistors being interconnected, and the gate electrodes of the plurality of driving transistors being interconnected.

[0080] The display substrate provided in the embodiments of the present disclosure increases the drive current provided by the pixel drive circuit by providing multiple drive transistors in a pixel drive circuit, with the first electrodes, gate electrodes, and second electrodes of the multiple drive transistors being interconnected. This improves the display quality of the display substrate. In some examples, the display substrate of this embodiment can be used in a tiled display screen.

[0081] In some exemplary embodiments, the pixel driving circuit may further include: a storage capacitor. The storage capacitor includes: a first plate and a second plate, the second plate being located on a side of the first plate away from the substrate; the orthographic projection of the first plate on the substrate at least partially overlaps with the orthographic projection of the second plate on the substrate. The first plate includes: a plurality of first sub-plates, a single first sub-plate can serve as a gate electrode of at least one driving transistor. For example, a plurality of first sub-plates can be independently provided and electrically connected through a second connecting electrode, and the second connecting electrode can be located on a side of the second plate away from the substrate. In this example, the electrical connection between the storage capacitor and the driving transistor is ensured by providing the first sub-plate of the first plate and the gate electrode of the driving transistor as an integrated structure, and the size of the storage capacitor can be adjusted by adjusting the number or size of the first sub-plates.

[0082] In some exemplary embodiments, the pixel driving circuit may further include: a first initialization transistor and a threshold compensation transistor. A first electrode of the first initialization transistor is connected to a first initial signal line, and a second electrode of the first initialization transistor is connected to gate electrodes of multiple driving transistors; a second electrode of the threshold compensation transistor is connected to second electrodes of multiple driving transistors, and a first electrode of the threshold compensation transistor is connected to gate electrodes of multiple driving transistors; the first initialization transistor and the threshold compensation transistor are connected to the gate electrodes of the multiple driving transistors via a second connecting electrode. In this example, the second connecting electrode enables full connectivity of all connection objects of the first node of the pixel driving circuit, facilitating a rational arrangement of transistors in the pixel driving circuit.

[0083] In some exemplary embodiments, the plurality of driving transistors of the pixel driving circuit may be arranged sequentially along a second direction, and the second plate of the storage capacitor may extend along the second direction, the second plate having a first end and a second end along the second direction. The first end and the second end of the second plate are respectively connected to a first power line; the first power line is located on a side of the second plate away from the substrate. In this exemplary design, the second plate of the storage capacitor and the first power line have two overlapping locations, which ensures uniformity in the transmission of the first voltage signal by the second plate.

[0084] In some exemplary embodiments, the circuit structure layer may further include: a data line connected to the pixel driving circuit and extending along a second direction, a first data transfer line extending along the first direction, and a second data transfer line extending along the second direction; the first direction intersects the second direction. The data line is connected to the second data transfer line via the first data transfer line; the first data transfer line is located on the side of the data line closest to the substrate, and the second data transfer line is provided on the same layer as the data line. In this example, by providing the first and second data transfer lines, a FIAA structure can be implemented, which facilitates a narrow-frame design.

[0085] In some exemplary embodiments, the pixel driving circuit further includes: a first initialization transistor, wherein a first electrode of the first initialization transistor is connected to a first initial signal line, and a second electrode of the first initialization transistor is connected to gate electrodes of the plurality of driving transistors. The first initial signal line extends along a first direction, and the first initial signal line is connected to a first initial signal connection line extending along a second direction, wherein the first direction intersects the second direction. The first initial signal connection line is located on a side of the first initial signal line away from the substrate. In this example, by cross-connecting the first initial signal line and the first initial signal connection line, a mesh structure for transmitting the first initial signal is implemented, thereby ensuring transmission consistency of the first initial signal.

[0086] In some exemplary embodiments, the pixel driving circuit further includes: a second initialization transistor, wherein the first electrode of the second initialization transistor is connected to the second initial signal line, and the second electrode of the second initialization transistor is connected to the first electrode of the light-emitting device connected to the pixel driving circuit; the second initial signal line extends along the first direction, and the second initial signal line is connected to the second initial signal connection line extending along the second direction; the second initial signal line and the first initial signal line are arranged on the same layer, and the second initial signal connection line and the first initial signal connection line are arranged on the same layer. In this example, the second initial signal line and the second initial signal connection line are cross-connected to achieve a mesh structure for transmitting the second initial signal, thereby ensuring the transmission consistency of the second initial signal. The display substrate of the present disclosure is illustrated below with some exemplary embodiments.

[0087] FIG4 is an equivalent circuit diagram of a pixel driving circuit according to at least one embodiment of the present disclosure. The pixel driving circuit of this example may have a 7T1C structure and may include seven transistors (e.g., first to seventh transistors T1 to T7) and one capacitor (e.g., storage capacitor C). The pixel driving circuit may be electrically connected to eight signal lines (e.g., a first scan line GL1, a second scan line GL2, a third scan line GL3, an emission control line E, a first initial signal line INIT1, a second initial signal line INIT2, a data line D, and a first power line VDD).

[0088] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , ie, the first end of the storage capacitor C is connected to the control electrode of the third transistor T3 , and a second end of the storage capacitor C is connected to the first power line VDD.

[0089] The control electrode of the first transistor T1 is connected to the second scan line GL2, the first electrode of the first transistor T1 is connected to the first initialization signal line INIT1, and the second electrode of the first transistor T1 is connected to the first node N1. When an on-level scan signal is applied to the second scan line GL2, the first transistor T1 transmits a first initialization voltage to the control electrode of the third transistor T3, thereby initializing the charge amount of the control electrode of the third transistor T3.

[0090] The control electrode of the second transistor T2 is connected to the first scan line GL1, the first electrode of the second transistor T2 is connected to the third node N3, and the second electrode of the second transistor T2 is connected to the first node N1. When an on-level scan signal is applied to the first scan line GL1, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.

[0091] The control electrode of the third transistor T3 is connected to the first node N1, that is, the control electrode of the third transistor T3 is connected to the first end of the storage capacitor C. The first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a drive transistor (DTFT). The third transistor T3 determines the amount of drive current flowing between the first power line VDD and the second power line VSS based on the potential difference between its control electrode and the first electrode. The first power line VDD can be configured to transmit a first voltage signal, and the second power line VSS can be configured to transmit a second voltage signal. The first voltage signal can be greater than the second voltage signal.

[0092] The control electrode of the fourth transistor T4 is connected to the first scan line GL1, the first electrode of the fourth transistor T4 is connected to the data line D, and the second electrode of the fourth transistor T4 is connected to the second node N2. The fourth transistor T4 can be referred to as a data write transistor. When an on-level scan signal is applied to the first scan line GL1, the fourth transistor T4 inputs the data voltage of the data line D to the pixel driving circuit.

[0093] The control electrode of the fifth transistor T5 is connected to the light-emission control line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2. The control electrode of the sixth transistor T6 is connected to the light-emission control line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When an on-level light-emitting signal is applied to the light-emission control line E, the fifth transistor T5 and the sixth transistor T6 form a drive current path between the first power line VDD and the second power line VSS, thereby causing the light-emitting device to emit light.

[0094] A control electrode of the seventh transistor T7 is connected to the third scan line GL3, a first electrode of the seventh transistor T7 is connected to the second initialization signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4. When an on-level scan signal is applied to the third scan line GL3, the seventh transistor T7 transmits a second initialization voltage to the first electrode of the light-emitting device to initialize or release the charge accumulated in the first electrode of the light-emitting device.

[0095] In an exemplary embodiment, the second electrode of the light-emitting device is connected to the second power line VSS. The signal on the second power line VSS is a low-level signal, while the signal on the first power line VDD is a high-level signal. The first scan line GL1 is a scan line in the pixel driver circuit for the current display row, and the second scan line GL2 is a scan line in the pixel driver circuit for the previous display row. That is, for the nth display row, the first scan line GL1 is GL(n), and the second scan line GL2 is GL(n-1). The second scan line GL2 of the current display row and the first scan line GL1 of the pixel driver circuit for the previous display row are the same signal line. This can reduce the number of signal lines on the display panel and achieve a narrow bezel on the display panel. The third scan line GL3 can transmit the same signal as the first scan line GL1.

[0096] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0097] In some examples, as shown in FIG4 , the first node N1 can be connected to the second electrode of the first transistor T1, the second electrode of the second transistor T2, the control electrode of the third transistor T3, and the first end of the storage capacitor C, respectively. The second node N2 can be connected to the second electrode of the fifth transistor T5, the second electrode of the fourth transistor T4, and the first electrode of the third transistor T3, respectively. The third node N3 can be connected to the second electrode of the third transistor T3, the first electrode of the second transistor T2, and the first electrode of the sixth transistor T6, respectively. The fourth node N4 can be connected to the second electrode of the sixth transistor T6, the second electrode of the seventh transistor T7, and the first electrode of the light-emitting device EL, respectively.

[0098] In an exemplary embodiment, the light emitting device EL may be an organic electroluminescent diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0099] Figure 5 is an operating timing diagram of a pixel driving circuit. The following illustrates exemplary embodiments of the present disclosure using the operating process of the pixel driving circuit illustrated in Figure 4. The pixel driving circuit in Figure 4 includes seven transistors (first transistor T1 to seventh transistor T7) and one storage capacitor C. All seven transistors are P-type transistors.

[0100] In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0101] The first phase A1 is called the reset phase. The signal on the second scan line GL2 is a low-level signal, while the signals on the first scan line GL1 and the light-emission control line E are high-level signals. The low-level signal on the second scan line GL2 turns on the first transistor T1, and the signal on the first initial signal line INIT1 is supplied to the first node N1, initializing the storage capacitor C and clearing the existing data voltage in the storage capacitor. The high-level signals on the first scan line GL1 and the light-emission control line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. During this phase, the light-emitting device EL does not emit light.

[0102] The second phase A2 is called the data writing phase or the threshold compensation phase. The signal on the first scan line GL1 is a low-level signal, while the signals on the second scan line GL2 and the light-emitting control line E are high-level signals. The data line D outputs a data voltage. During this phase, since the first end of the storage capacitor C is at a low level, the third transistor T3 is turned on. The low-level signal on the first scan line GL1 turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The second and fourth transistors T2 and T4 are turned on, causing the data voltage output by the data line D to be supplied to the first node N1 via the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output by the data line D and the threshold voltage of the third transistor T3 is then charged into the storage capacitor C. The voltage at the first end of the storage capacitor C (the first node N1) is Vd-|Vth|, where Vd is the data voltage output by the data line D and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, supplying the initial voltage of the second initial signal line INIT2 to the first electrode of the light-emitting device EL. This initializes (resets) the first electrode of the light-emitting device EL, clearing the pre-stored voltage within the electrode, completing initialization, and ensuring that the light-emitting device EL does not emit light. The signal of the second scan line GL2 is a high-level signal, turning off the first transistor T1. The signal of the emission control line E is a high-level signal, turning off the fifth transistor T5 and the sixth transistor T6.

[0103] The third phase A3 is called the light-emitting phase. The signal on the light-emitting control line E is low, and the signals on the first scan line GL1 and the second scan line GL2 are high. The low signal on the light-emitting control line E turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage from the first power line VDD provides a driving voltage to the first electrode of the light-emitting device EL through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting device EL to emit light.

[0104] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is: I=K×(Vgs-Vth) 2 =K×[(Vdd-Vd+|Vth|)-Vth] 2 =K×[Vdd-Vd] 2

[0105] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting device EL, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0106] From the above formula, it can be seen that the current flowing through the light emitting element has nothing to do with the threshold voltage of the third transistor T3. Therefore, the pixel driving circuit of this embodiment can better compensate for the threshold voltage of the third transistor T3.

[0107] Figure 6 is a partial top view of a display substrate of at least one embodiment of the present disclosure, illustrating a plurality of pixel units, where one pixel unit may include three sub-pixels. In some examples, the display substrate may include: a circuit structure layer and a light-emitting structure layer sequentially arranged on a substrate. The circuit structure layer may include a plurality of circuit units, the light-emitting structure layer may include a plurality of light-emitting units, at least one circuit unit may include a pixel driving circuit, and at least one light-emitting unit may include a light-emitting device. The light-emitting device may include at least an anode, an organic light-emitting layer, and a cathode, and the anode of the light-emitting device may be connected to the pixel driving circuit in the corresponding circuit unit.

[0108] The term "circuit unit" as used herein refers to an area divided by a pixel driving circuit; the term "light-emitting unit" as used herein refers to an area divided by a light-emitting device. In some examples, the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0109] In some examples, a plurality of circuit units sequentially arranged along a first direction X may be referred to as a unit row, and a plurality of circuit units sequentially arranged along a second direction Y may be referred to as a unit column. The plurality of unit rows and the plurality of unit columns may constitute an array of circuit units arranged in an array. The first direction X and the second direction Y may intersect, for example, the first direction X may be perpendicular to the second direction Y.

[0110] In some examples, as shown in FIG6 , the circuit structure layer of the display substrate may further include: a first transmission structure 59. The first transmission structure 59 may be configured to transmit a second voltage signal. The first transmission structure 59 may be formed by connecting a plurality of first transmission lines 591 extending along a first direction X and a plurality of second transmission lines 592 extending along a second direction Y. For example, the plurality of first transmission lines 591 and the plurality of second transmission lines 592 may be an integrated structure connected to each other. The first transmission structure 59 may be a mesh structure located in the same conductive layer. However, this embodiment is not limited to this. In other examples, the first transmission line 591 and the second transmission line 592 may be located in different conductive layers; or, at least one of the first transmission line 591 and the second transmission line 592 may be a double-layer routing structure.

[0111] In some examples, as shown in FIG6 , the first transmission structure 59 may have multiple grids. Each grid may be formed by connecting and surrounding two adjacent second transmission lines 592 and two adjacent first transmission lines 591. A pixel unit (e.g., including three sub-pixels, each sub-pixel including an interconnected pixel driving circuit and a light-emitting device) may be provided within at least one grid. In some examples, as shown in FIG6 , the three pixel driving circuits within a single grid may include: a first pixel driving circuit Q1, a second pixel driving circuit Q2, and a third pixel driving circuit Q3. The first pixel driving circuit Q1, the second pixel driving circuit Q2, and the third pixel driving circuit Q3 may be arranged sequentially along a first direction X. The three light-emitting devices within a single grid may include: a first light-emitting device 01, a second light-emitting device 02, and a third light-emitting device 03. The first light-emitting device 01 and the second light-emitting device 02 may be arranged sequentially along the first direction X, and the third light-emitting device 03 may be located on the same side of the first light-emitting device 01 and the second light-emitting device 02 in the second direction Y. The first light-emitting device 01 can be connected to the first pixel driving circuit Q1, the second light-emitting device 02 can be connected to the second pixel driving circuit Q2, and the third light-emitting device 03 can be connected to the third pixel driving circuit Q3. For example, the first light-emitting device 01 can be configured to emit red light, the second light-emitting device 02 can be configured to emit green light, and the third light-emitting device 03 can be configured to emit blue light. However, this embodiment is not limited to this.

[0112] In some examples, as shown in FIG6 , the first transmission structure 59 can be a mesh structure located in the same conductive layer and can include multiple first transmission rings 58 . Two first transmission rings 58 adjacent along the first direction X or the second direction Y can be interconnected integral structures. A single first transmission ring 58 can form a single mesh around. For example, the orthographic projection of the first transmission ring 58 on the substrate can be a roughly rectangular ring. However, this embodiment is not limited to this. In other examples, the multiple first transmission rings 58 of the first transmission structure 59 can be independently arranged, and the multiple first transmission rings 58 can be connected via electrodes or traces located in other conductive layers.

[0113] In some examples, at least one pixel driving circuit may include: a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light-emitting transistor, a sixth transistor T6 as a second light-emitting transistor, a seventh transistor T7 as a second initialization transistor, and a storage capacitor C.

[0114] In some examples, in a direction perpendicular to the display substrate, the circuit structure layer may include: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially arranged on a substrate. A first insulating layer may be provided between the semiconductor layer and the first conductive layer, a second insulating layer may be provided between the first conductive layer and the second conductive layer, a third insulating layer may be provided between the second conductive layer and the third conductive layer, a fourth insulating layer and a fifth insulating layer may be provided between the third conductive layer and the fourth conductive layer, and a sixth insulating layer may be provided on the side of the fourth conductive layer away from the substrate. In some examples, the first to fourth insulating layers may be inorganic insulating layers, and the fifth and sixth insulating layers may be organic insulating layers. However, this embodiment is not limited to this. In other examples, a buffer layer may be provided between the substrate and the semiconductor layer. In other examples, only the fifth insulating layer may be provided between the third conductive layer and the fourth conductive layer.

[0115] Fig. 7 is a schematic diagram of the planar structure of the dotted area C in Fig. 6. Fig. 7 illustrates the pixel driving circuits of three sub-pixels included in one pixel unit of the display substrate and the anode of the light-emitting device connected to the pixel driving circuit.

[0116] In an exemplary embodiment, as shown in FIG7 , the light-emitting structure layer of the display substrate may include at least an anode layer, which may include anodes of multiple light-emitting devices (e.g., a first anode 71 of a first light-emitting device 01, a second anode 72 of a second light-emitting device 02, and a third anode 73 of a third light-emitting device 03), and a second transmission structure. The second transmission structure may be a mesh structure located in the same conductive layer. The second transmission structure may include at least one second transmission ring 74. The second transmission ring 74 may be formed by connecting two adjacent third transmission lines 741 extending along a first direction X and two adjacent fourth transmission lines 742 extending along a second direction Y. For example, the plurality of third transmission lines 741 and the plurality of fourth transmission lines 742 may be interconnected integral structures. In some examples, adjacent second transmission rings 74 may be interconnected integral structures. However, this embodiment is not limited to this. In other examples, the plurality of second transmission rings may be independently provided and connected via electrodes or traces in the remaining conductive layers.

[0117] In some examples, as shown in FIG7 , a second transmission ring 74 of the second transmission structure can be configured to transmit a second voltage signal. The second transmission ring 74 can be electrically connected to the first transmission ring 58 of the first transmission structure 59 located in the circuit structure layer. In some examples, the orthographic projection of the second transmission ring 74 on the substrate can at least partially overlap with the orthographic projection of the first transmission ring 58 on the substrate. For example, the orthographic projection of the second transmission ring 74 on the substrate can cover the orthographic projection of the first transmission ring 58 on the substrate.

[0118] In some examples, as shown in FIG7 , anodes of three light-emitting devices may be disposed within the second transmission ring 74, including, for example, a first anode 71 of the first light-emitting device 01, a second anode 72 of the second light-emitting device 02, and a third anode 73 of the third light-emitting device 03. The second transmission ring 74 surrounds the periphery of the three light-emitting devices in a pixel unit.

[0119] In an exemplary embodiment, as shown in FIG7 , the circuit structure layer of the display substrate may include a first connecting ring 51. The orthographic projection of the first connecting ring 51 on the substrate may be in the shape of a square. The first connecting ring 51 may be provided on the same layer as the first transmission ring 58 of the first transmission structure 59 and may be configured to transmit different voltage signals. For example, the first connecting ring 51 may be configured to transmit a first voltage signal, while the first transmission ring 58 may be configured to transmit a second voltage signal. The orthographic projection of the first connecting ring 51 on the substrate may be located inward of the orthographic projections of the first transmission ring 58 and the second transmission ring 74 on the substrate.

[0120] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0121] As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0122] In this disclosure, the shape of A refers to the shape of the orthographic projection of A onto the substrate. The dimensions of A can represent the size of A. For example, if the shape of A is rectangular, the dimensions of A can include the length and width of the rectangle; if the shape of A is circular, the dimensions of A can include the radius of the circle.

[0123] In an exemplary embodiment, taking three circuit units in the nth unit row (eg, a first circuit unit, a second circuit unit, and a third circuit unit sequentially arranged along the first direction X) as an example, the preparation process of the display substrate of this embodiment may include the following operations.

[0124] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a semiconductor thin film on a substrate, and patterning the semiconductor thin film through a patterning process to form a semiconductor layer, as shown in FIG8 . FIG8 is a schematic diagram of the display substrate after the semiconductor layer is formed in FIG7 .

[0125] In an exemplary embodiment, within a cell row, the semiconductor layers in adjacent circuit cells can be independently arranged. The semiconductor layers of each circuit cell in the display substrate can include at least a first active layer 11 of a first transistor T1, a second active layer 12 of a second transistor T2, a plurality of third active layers 13 of a plurality of third transistors T3, a fourth active layer 14 of a fourth transistor T4, a fifth active layer 15 of a fifth transistor T5, a sixth active layer 16 of a sixth transistor T6, and a seventh active layer 17 of a seventh transistor T7. The first to seventh active layers 11 to 17 can be interconnected and integrated. FIG8 illustrates an example of six third active layers within a single circuit cell, which is not a limitation of the present disclosure.

[0126] In an exemplary embodiment, in a single circuit unit, six third active layers 13 may be arranged sequentially along the second direction Y, and the six third active layers 13 may be interconnected as an integral structure. In a single circuit unit in the nth unit row, the first active layer 11, the second active layer 12, and the fourth active layer 14 may be located on the side of the third active layer 13 that is closer to the (n-1)th unit row, i.e., the first active layer 11, the second active layer 12, and the fourth active layer 14 may be located on the side of the third active layer 13 of the circuit unit that is opposite to the second direction Y. The fifth active layer 15 to the seventh active layer 17 may be located on the side of the third active layer 13 that is closer to the (n+1)th unit row, i.e., the fifth active layer 15 to the seventh active layer 17 may be located on the side of the third active layer 13 of the circuit unit that is closer to the second direction Y.

[0127] In an exemplary embodiment, in a single circuit unit, the second active layer 12 can be located on the side of the third active layer 13 of the present circuit unit in the opposite direction of the second direction Y, the first active layer 11 can be located on the side of the second active layer 12 of the present circuit unit in the opposite direction of the second direction Y, the fourth active layer 14 can be located on the side of the third active layer 13 of the present circuit unit in the opposite direction of the second direction Y, the fifth active layer 15 can be located on the side of the third active layer 13 of the present circuit unit in the second direction Y, the sixth active layer 16 can be located on the side of the third active layer 13 of the present circuit unit in the second direction Y, and the seventh active layer 17 can be located on the side of the sixth active layer 16 of the present circuit unit in the second direction Y.

[0128] In an exemplary embodiment, within a single circuit unit, the fourth active layer 14 can be located on one side of the first active layer 11 and the second active layer 12 of the circuit unit in the first direction X (for example, on the side opposite to the first direction X), and the sixth active layer 16 and the seventh active layer 17 can be located on the other side of the fifth active layer 15 of the circuit unit in the first direction X (for example, on one side of the first direction X).

[0129] In an exemplary embodiment, the first active layer 11 may have an "n" shape, the second active layer 12, the fourth active layer 14, the fifth active layer 15, and the seventh active layer 17 may have an "L" shape, the third active layer 13 may have a "Z" shape, and the sixth active layer 16 may have an "I" shape.

[0130] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the first regions 13-1 of the six third active layers 13 within a single circuit unit may be directly connected, and the second regions 13-2 of the six third active layers 13 may be directly connected, so that the six third active layers 13 form an interconnected, integrated structure. The channel regions of the six third active layers may not be connected; for example, the channel regions of the six third active layers 13 may be parallel to each other. The second region 11-2 of the first active layer 11 and the second region 12-2 of the second active layer 12 may be directly connected, and the second region 11-2 of the first active layer 11 may serve as the second region 12-2 of the second active layer 12. The first regions 13-1 of the six third active layers 13, the second regions 14-2 of the fourth active layer 14, and the second region 15-2 of the fifth active layer 15 can be directly connected. The integrated structure of the first regions 13-1 of the six third active layers 13 can simultaneously serve as the second regions 14-2 of the fourth active layer 14 and the second region 15-2 of the fifth active layer 15. The first region 12-1 of the second active layer 12, the integrated structure of the second regions 13-2 of the six third active layers 13, and the first region 16-1 of the sixth active layer 16 can be directly connected. The integrated structure of the second regions 13-2 of the six third active layers 13 can simultaneously serve as the first region 12-1 of the second active layer 12 and the first region 16-1 of the sixth active layer 16, forming a third node N3 of the pixel driving circuit. The second region 16-2 of the sixth active layer 16 and the second region 17-2 of the seventh active layer 17 can be directly connected, and the second region 16-2 of the sixth active layer 16 can serve as the second region 17-2 of the seventh active layer 17, constituting a fourth node N4 of the pixel driving circuit. The first region 11-1 of the first active layer 11, the first region 14-1 of the fourth active layer 14, the first region 15-1 of the fifth active layer 15, and the first region 17-1 of the seventh active layer 17 can be provided separately.

[0131] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process to form a first insulating layer, and a first conductive layer pattern disposed on the first insulating layer, as shown in FIG9A , FIG9B , and FIG9C . FIG9A is a schematic diagram of the display substrate after the first conductive layer is formed in FIG7 ; FIG9B is a schematic diagram of the first conductive layer in FIG9A . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0132] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display substrate includes at least a first scan line 21, a second scan line 22, a third scan line 23, a light-emitting control line 24, a first data transfer line 25, and a first plate 26 of a storage capacitor. The first plate 26 of the storage capacitor can serve as both the lower plate of the storage capacitor and the gate electrode of the six third transistors T3.

[0133] In an exemplary embodiment, in at least one circuit unit (the first circuit unit and the second circuit unit shown in FIG9A ), the first electrode plate 26 of the storage capacitor may include multiple (e.g., six) separated first sub-plates. The number of first sub-plates may be equal to the number of third active layers, and a single first sub-plate may serve as the gate electrode of a single third transistor T3. Taking the first circuit unit shown in FIG9A as an example, the shape of the first sub-plate 26-1 may be rectangular, and the corners of the rectangle may be chamfered. The multiple separated first sub-plates 26-1 may be arranged sequentially along the second direction Y, with the orthographic projection of a single first sub-plate 26-1 on the substrate at least partially overlapping the orthographic projection of the third active layer 13 of a single third transistor T3 on the substrate. The six first sub-plates 26-1 may have the same shape and size. However, this embodiment is not limited to this. In other examples, the number of first sub-plates may be less than the number of third active layers. For example, at least one first sub-plate may simultaneously serve as the gate electrode of at least two third transistors. In other examples, some of the six first sub-plates 26-1 may have different shapes or sizes. The multiple first sub-boards 26 - 2 of the second circuit unit in FIG. 9A can refer to the above description of the first sub-board 26 - 1 in the first circuit unit, which will not be repeated here.

[0134] In an exemplary embodiment, the shape or size of the first sub-board 26-2 located in the second circuit unit can be the same as the shape or size of the first sub-board 26-1 in the first circuit unit aligned along the first direction X, and the number of first sub-boards 26-2 in the second circuit unit can be the same as the number of first sub-boards 26-1 in the first circuit unit, which is not limited in this disclosure.

[0135] In an exemplary embodiment, in at least one circuit unit (eg, the third circuit unit in FIG. 9A ), the six first sub-plates of the first electrode plate 26 may be provided as an integrated structure connected to each other.

[0136] In some examples, by adjusting the number of first sub-plates of the first electrode plate 26, the overlapping area between the first electrode plate 26 and the subsequently formed second electrode plate can be controlled, thereby adjusting the size of the storage capacitor in the pixel driving circuit. In some examples, the first light-emitting device connected to the pixel driving circuit in the first circuit unit emits red light, the second light-emitting device connected to the pixel driving circuit in the second circuit unit emits green light, and the third light-emitting device connected to the pixel driving circuit in the third circuit unit emits blue light. By setting the first electrode plate in this example, the differentiated design of the storage capacitor of the pixel driving circuit corresponding to the third light-emitting device emitting blue light and the first light-emitting device emitting red light and the second light-emitting device emitting green light can be met. For example, the capacitance of the storage capacitor of the pixel driving circuit corresponding to the third light-emitting device emitting blue light can be greater than the capacitance of the storage capacitor of the pixel driving circuit corresponding to the first light-emitting device and the second light-emitting device emitting red or green light. However, this embodiment is not limited to this. In other examples, the first electrode plates of the storage capacitors of multiple pixel driving circuits can adopt the same design.

[0137] In an exemplary embodiment, the shape of the first scan line 21 can be a line shape with a main portion extending along the first direction X, and can be located on the side of the first electrode 26 in the opposite direction of the second direction Y. The area where the first scan line 21 overlaps with the fourth active layer can serve as the gate electrode of the fourth transistor T4.

[0138] In an exemplary embodiment, a first scanning protrusion 21-1 may be provided on a side of the first scanning line 21 away from the first electrode plate 26. The first scanning protrusion 21-1 may be provided in each circuit unit. A first end of the first scanning protrusion 21-1 is connected to the first scanning line 21, and a second end of the first scanning protrusion 21-1 extends away from the first electrode plate 26. The first scanning line 21 and the plurality of first scanning protrusions 21-1 may be an interconnected, integral structure. The region where the first scanning line 21, the first scanning protrusion 21-1, and the second active layer overlap may serve as the gate electrode of the second transistor T2 of the dual-gate structure.

[0139] In an exemplary embodiment, the shape of the second scan line 22 can be a line shape in which the main portion extends along the first direction X, and can be located on the side opposite to the second direction Y of the first scan line 21. The area where the second scan line 22 overlaps with the first active layer can serve as the gate electrode of the first transistor T1 of the dual-gate structure.

[0140] In an exemplary embodiment, the shape of the light-emitting control line 24 can be a line shape in which the main portion extends along the first direction X, and can be located on one side of the first electrode 26 in the second direction Y. The area where the light-emitting control line 24 overlaps with the fifth active layer can serve as the gate electrode of the fifth transistor T5, and the area where the light-emitting control line 24 overlaps with the sixth active layer can serve as the gate electrode of the sixth transistor T6.

[0141] In an exemplary embodiment, the shape of the third scan line 23 can be a line shape with the main portion extending along the first direction X, and can be located on one side of the light emitting control line 24 in the second direction Y. The area where the third scan line 23 overlaps with the seventh active layer can serve as the gate electrode of the seventh transistor T7.

[0142] In an exemplary embodiment, the first data transfer line 25 may be in the shape of a line with a main portion extending along the first direction X, and may be located on a side of the second scan line 22 in the opposite direction of the second direction Y. The orthographic projection of the first data transfer line 25 on the substrate may not overlap with the orthographic projection of the semiconductor layer on the substrate.

[0143] In an exemplary embodiment, a first data transfer portion 25-1 may be provided on a side of the first data transfer line 25 away from the first electrode plate 26. The first data transfer portion 25-1 may be provided in each circuit unit. A first end of the first data transfer portion 25-1 may be connected to the first data transfer line 25, and a second end of the first data transfer portion 25-1 may extend to a side away from the second scan line 22. The first data transfer portion 25-1 may be configured to connect to a subsequently formed data line or a second data transfer line. The first data transfer line 25 and the plurality of first data transfer portions 25-1 may be an interconnected, integrated structure.

[0144] FIG9C is a schematic diagram of the first conductive layer in another embodiment. FIG9C differs from FIG9B in that the structure of the first sub-plate within the third circuit unit is different. As shown in FIG9C , the third circuit unit can be provided with six first sub-plates 26-3. The multiple, mutually separated first sub-plates 26-3 can be arranged sequentially along the second direction Y. The orthographic projection of a single first sub-plate 26-3 on the substrate at least partially overlaps with the orthographic projection of the third active layer 13 of a single third transistor T3 on the substrate. The six first sub-plates 26-3 can have the same shape and size. The shape of the first sub-plate 26-3 can be rectangular, and the corners of the rectangle can be chamfered. In other examples, the shape or size of some of the six first sub-plates 26-3 can be different. The remaining structure in FIG9C can refer to the above description of FIG9B and will not be repeated here.

[0145] In some examples, as shown in FIG9C , the shape of the first sub-board 26-3 located in the third circuit unit is the same as the shape of the first sub-board 26-1 located in the first circuit unit and the shape of the first sub-board 26-2 located in the second circuit unit. The size of the first sub-board 26-3 located in the third circuit unit can be smaller than the size of the first sub-board 26-1 located in the first circuit unit, and the size of the first sub-board 26-3 located in the third circuit unit can be smaller than the size of the first sub-board 26-2 located in the second circuit unit. In this example, the orthographic projection area of ​​the first sub-board 26-3 located in the third circuit unit on the substrate can be smaller than the orthographic projection area of ​​the first sub-board 26-1 located in the first circuit unit on the substrate, and the orthographic projection area of ​​the first sub-board 26-3 located in the third circuit unit on the substrate can be smaller than the orthographic projection area of ​​the first sub-board 26-2 located in the second circuit unit on the substrate. However, this embodiment is not limited to this.

[0146] In this example, by adjusting the orthographic projection area of ​​the first sub-plate of the first electrode plate 26, the overlapping area between the first electrode plate 26 and the subsequently formed second electrode plate can be controlled, thereby adjusting the size of the storage capacitor in the pixel driver circuit. In some examples, the first light-emitting device connected to the pixel driver circuit in the first circuit unit emits red light, the second light-emitting device connected to the pixel driver circuit in the second circuit unit emits green light, and the third light-emitting device connected to the pixel driver circuit in the third circuit unit emits blue light. The arrangement of the first electrode plate in this example can meet the differentiated design requirements of the storage capacitors of the pixel driver circuits corresponding to the third light-emitting device emitting blue light, the first light-emitting device emitting red light, and the second light-emitting device emitting green light.

[0147] In other examples, the shape and quantity of the first sub-board 26-3 of the third circuit unit may be different from the shape and quantity of the first sub-board 26-1 in the first circuit unit, and the shape and quantity of the first sub-board 26-3 of the third circuit unit may be different from the shape and quantity of the first sub-board 26-2 in the second circuit unit. The present disclosure does not limit this.

[0148] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the semiconductor layer. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the seventh transistor T7, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first region and the second region of the first active layer to the seventh active layer are both conductorized.

[0149] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a second insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the second insulating layer, as shown in FIG10A and FIG10B , FIG10A is a schematic diagram of the display substrate after the second conductive layer is formed in FIG7 , and FIG10B is a schematic diagram of the second conductive layer in FIG10A . In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0150] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display substrate includes at least a first initial signal line 31 , a second initial signal line 32 , a shielding electrode 33 and a second electrode plate 34 .

[0151] In an exemplary embodiment, the second plate 34 may have a rectangular outline, with chamfered corners. The longitudinal direction of the rectangle may be the second direction Y. The second plate 34 may be located on one side of the first scan line 21 in the second direction Y, and the second plate 34 may be located on the side of the light-emission control line 24 opposite to the second direction Y. That is, the second plate 34 may be located between the first scan line 21 and the light-emission control line 24 of the circuit unit. The end of the second plate 34 closest to the first scan line 21 may be referred to as the first end, and the end of the second plate 34 closest to the light-emission control line 24 may be referred to as the second end. The orthographic projection of the second plate 34 on the substrate at least partially overlaps with the orthographic projection of the first plate 26 on the substrate. The second plate 34 may serve as the upper plate of the storage capacitor, and the first plate 26 and the second plate 34 constitute the storage capacitor of the pixel driving circuit.

[0152] In an exemplary embodiment, a plurality of (e.g., six) first openings are provided on the second plate 34 of each circuit unit. Taking the first circuit unit shown in FIG10A as an example, the plurality of first openings 35-1 can be arranged in sequence along the second direction Y and located in the middle of the second plate 34 along the first direction X. The shape of the first opening 35-1 can be rectangular, and the plurality of first openings 35-1 can be arranged in a one-to-one correspondence with the plurality of first sub-plates 26-1 of the first plate 26. The first opening 35-1 exposes the second insulating layer covering the first sub-plate 26-1, and the orthographic projection of the first sub-plate 26-1 on the substrate includes the orthographic projection of the first opening 35-1 on the substrate. The size and shape of the six first openings 35-1 can be the same. However, this embodiment is not limited to this. In other examples, the shape or size of some of the six first openings 35-1 can be different. In an exemplary embodiment, first opening 35-1 is configured to accommodate a subsequently formed eighth via. The eighth via of the first circuit unit is located within first opening 35-1 and exposes first sub-board 26-1, allowing a subsequently formed second connection electrode to be connected to first sub-board 26-1. The multiple first openings 35-2 of the second circuit unit in FIG. 10A can be described with reference to the above description of first opening 35-1 in the first circuit unit, and will not be repeated here.

[0153] In an exemplary embodiment, the shape or size of the first opening 35-2 located in the second circuit unit can be the same as the shape or size of the first opening 35-1 in the first circuit unit aligned along the first direction X, and the number of the first openings 35-2 in the second circuit unit can be the same as the number of the first openings 35-1 in the first circuit unit, which is not limited in this disclosure.

[0154] In an exemplary embodiment, as shown in FIG10A , the size of the first opening 35-3 provided on the second electrode plate 34 in the third circuit unit can be greater than or equal to the size of the first opening in the first circuit unit or the second circuit unit. Since the multiple first sub-plates in the third circuit unit are interconnected as an integrated structure, by adjusting the size of the first opening 35-3 on the second electrode plate 34, the overlapping area between the first electrode plate 26 and the second electrode plate 34 can be adjusted to facilitate obtaining a suitable value of the storage capacitor size. The number and interconnection of the first sub-plates, as well as the size of the first opening 35-3 of the second electrode plate 34, can be set as needed, and this disclosure is not limited thereto.

[0155] In an exemplary embodiment, the first initial signal line 31 and the second initial signal line 32 may be in the shape of a line whose main portion extends along the first direction X. The first initial signal line 31 may be located on a side of the second electrode plate 34 opposite to the second direction Y, and the second initial signal line 32 may be located on a side of the second electrode plate 34 in the second direction Y. The second initial signal line 32 may be located on a side of the third scan line 23 in the second direction Y.

[0156] In an exemplary embodiment, the first initial signal line 31 may be located on a side of the second scan line 22 opposite to the second direction Y. The first initial signal line 31 may also be located on a side of the first data transfer line 25 in the second direction Y, that is, the first initial signal line 31 may be located between the second scan line 22 and the first data transfer line 25. A first recess 31-1 may be provided on a side of the first initial signal line 31 near the first data transfer line 25. The first recess 31-1 may expose the surface of the second insulating layer. The orthographic projection of a subsequently formed data line on the substrate may overlap with the orthographic projection of the first initial signal line 31 on the substrate at the first recess 31-1. Because the area of ​​the first initial signal line 31 at the first recess 31-1 is smaller, the overlapping area of ​​the first initial signal line 31 and the data line is also smaller, thereby reducing the coupling capacitance between the first initial signal line 31 and the data line.

[0157] In an exemplary embodiment, the second initial signal line 32 may be located on one side of the third scan line 23 in the second direction Y. A second recess 32-1 may be provided on the side of the second initial signal line 32 away from the third scan line 23. The second recess 32-1 may expose the surface of the second insulating layer. The orthographic projection of a subsequently formed data line on the substrate and the orthographic projection of the second initial signal line 32 on the substrate may overlap at the second recess 32-1. Because the area of ​​the second initial signal line 32 at the second recess 32-1 is smaller, the overlapping area of ​​the second initial signal line 32 and the data line is also smaller, thereby reducing the coupling capacitance between the second initial signal line 32 and the data line.

[0158] In an exemplary embodiment, the orthographic projection of the first initial signal line 31 on the substrate may at least partially overlap with the orthographic projection of the first active layer between the two gate electrodes of the first transistor T1 on the substrate. This can shield the first transistor T1 from the effects of data voltage jumps, preventing the data voltage jumps from affecting the normal operation of the pixel driver circuit, and improving display quality. In an exemplary embodiment, the shielding electrode 33 can be rectangular and located on the side of the first initial signal line 31 near the second electrode plate 34. The shielding electrode 33 can be provided in each circuit unit. The orthographic projection of the shielding electrode 33 on the substrate may at least partially overlap with the orthographic projection of the conductive region between the channel region of the second active layer of the second transistor T2 on the substrate. For example, the orthographic projection of the shielding electrode 33 on the substrate may at least partially overlap with the orthographic projection of the second active layer between the two gate electrodes of the second transistor T2 in this circuit unit. In an exemplary embodiment, the shielding electrode 33 is configured to protect the channel region of the second transistor T2 from interference. For example, it can shield the second transistor T2 from the effects of data voltage jumps, preventing the data voltage jumps from affecting the normal operation of the pixel driver circuit, and improving display quality.

[0159] (4) Forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, patterning the third insulating film using a patterning process to form a third insulating layer, wherein the third insulating layer in each circuit unit may be provided with a plurality of vias, as shown in FIG11 . FIG11 is a schematic diagram of the display substrate after the third insulating layer is formed in FIG7 .

[0160] In an exemplary embodiment, the multiple vias of each circuit unit in the display substrate may include at least: a first via V1, a first hole group K1, a third via V3, a fourth via V4, a second hole group K2, a third hole group K3, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, a fourth hole group K4, a fifth hole group K5, a thirteenth via V13, a sixth hole group K6, a fifteenth via V15 and a sixteenth via V16.

[0161] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the third insulating layer, the second insulating layer and the first insulating layer within the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed first connecting electrode to the first region of the first active layer through the via hole.

[0162] In an exemplary embodiment, the orthographic projection of the first hole group K1 on the substrate is located within the range of the orthographic projection of the second region of the first active layer (also the second region of the second active layer) on the substrate, the first hole group K1 may include at least two second via holes V2, the third insulating layer, the second insulating layer and the first insulating layer in the second via holes V2 are etched away to expose the surface of the second region of the first active layer (also the second region of the second active layer), and the first hole group K1 is configured to connect a subsequently formed second connecting electrode to the second region of the first active layer (also the second region of the second active layer) through the via hole group.

[0163] In an exemplary embodiment, the at least two second vias V2 may be arranged in an array. For example, the first hole group K1 may include two second vias V2 arranged in a row and two columns, with the row direction being the first direction and the column direction being the second direction. This hole group design can increase the contact area and the number of contact points between the subsequently formed second connection electrode and the second region of the first active layer (also the second region of the second active layer), resulting in better signal transmission and a tighter connection between the two. In other embodiments, the at least two second vias V2 may be distributed in other ways or in an irregular pattern, and this disclosure is not limited thereto.

[0164] In an exemplary embodiment, the orthographic projection of the third via V3 on the substrate is located within the orthographic projection of the first region of the third active layer (also the second region of the fourth active layer and the second region of the fifth active layer) on the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the third via V3 are etched away, exposing the surface of the first region of the third active layer. The third via V3 is configured to connect a subsequently formed third connection electrode to the first region of the third active layer (also the second region of the fourth active layer and the second region of the fifth active layer) through the via. Within a single circuit unit, the number of third vias V3 can be equal to the number of third transistors.

[0165] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is located within the orthographic projection of the second region of the third active layer (also the first region of the second active layer and the first region of the sixth active layer) on the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the fourth via V4 are etched away, exposing the surface of the second region of the third active layer. The fourth via V4 is configured to connect a subsequently formed fourth connection electrode to the second region of the third active layer (also the first region of the second active layer and the first region of the sixth active layer) through the via. Within a single circuit unit, the number of fourth vias V4 can be equal to the number of third transistors.

[0166] In an exemplary embodiment, the orthographic projection of the second hole group K2 on the substrate is located within the range of the orthographic projection of the first area of ​​the fifth active layer on the substrate, the second hole group K2 may include at least two fifth vias V5, the third insulating layer, the second insulating layer and the first insulating layer in the fifth vias V5 are etched away to expose the surface of the first area of ​​the fifth active layer, and the second hole group K2 is configured to connect a subsequently formed first power line to the first area of ​​the fifth active layer through the via group, so that the first electrode of the fifth transistor receives the first voltage signal.

[0167] In an exemplary embodiment, the at least two fifth vias V5 may be arranged in an array. For example, the second hole group K2 may include two fifth vias V5 arranged in a row and two columns. In other embodiments, the at least two fifth vias V5 may be distributed in other ways or irregularly, and this disclosure is not limited thereto.

[0168] In an exemplary embodiment, the orthographic projection of the third hole group K3 on the substrate is located within the range of the orthographic projection of the second region of the sixth active layer (also the second region of the seventh active layer) on the substrate, the third hole group K3 may include at least two sixth via holes V6, the third insulating layer, the second insulating layer and the first insulating layer in the sixth via holes V6 are etched away to expose the surface of the second region of the sixth active layer (also the second region of the seventh active layer), and the third hole group K3 is configured to connect a subsequently formed fifth connecting electrode to the second region of the sixth active layer (also the second region of the seventh active layer) through the via hole group.

[0169] In an exemplary embodiment, the at least two sixth vias V6 may be arranged in an array. For example, the third hole group K3 may include two sixth vias V6 arranged in a row and two columns. In other embodiments, the at least two sixth vias V6 may be distributed in other ways or irregularly, and this disclosure is not limited thereto.

[0170] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the seventh via hole V7 are etched away to expose the surface of the first region of the seventh active layer, and the seventh via hole V7 is configured to connect the subsequently formed sixth connecting electrode to the first region of the seventh active layer through the via hole.

[0171] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the first opening 35 of the second electrode plate 34 on the substrate, the third insulating layer and the second insulating layer within the eighth via V8 are etched away to expose the surface of the first sub-board, and the eighth via V8 is configured to connect the subsequently formed second connecting electrode to the first electrode plate 26 through the via.

[0172] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of one end of the second electrode 34 close to the first scan line 21 (i.e., the first end) on the substrate, and the third insulating layer in the ninth via V9 is etched away to expose the surface of the second electrode 34. The ninth via V9 is configured to connect the subsequently formed first power line to the second electrode 34 through the via, so that the second electrode 34 of the storage capacitor receives the first voltage signal.

[0173] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of one end of the second electrode plate 34 close to the light-emitting control line 24 (i.e., the second end) on the substrate, and the third insulating layer in the tenth via hole V10 is etched away to expose the surface of the second electrode plate 34. The tenth via hole V10 is configured to connect the subsequently formed first power line to the second electrode plate 34 through the via hole, so that the second electrode plate 34 of the storage capacitor receives the first voltage signal.

[0174] In an exemplary embodiment, the orthographic projection of the fourth hole group K4 on the substrate is located within the range of the orthographic projection of the first region of the fourth active layer on the substrate. The fourth hole group K4 may include at least two eleventh via holes V11. The third insulating layer, the second insulating layer, and the first insulating layer in the eleventh via hole V11 are etched away to expose the surface of the first region of the fourth active layer. The fourth hole group K4 is configured to connect a subsequently formed data line to the first region of the fourth active layer through the via hole group, so that the first electrode of the fourth transistor receives a data signal.

[0175] In an exemplary embodiment, the at least two eleventh via holes V11 may be arranged in an array. For example, the fourth hole group K4 may include three eleventh via holes V11 arranged in three rows and one column. In other embodiments, the at least two eleventh via holes V11 may be distributed in other ways or irregularly, and this disclosure is not limited thereto.

[0176] In an exemplary embodiment, the orthographic projection of the fifth hole group K5 on the substrate is located within the range of the orthographic projection of the first initial signal line 31 on the substrate. The fifth hole group K5 may include at least two twelfth via holes V12. The third insulating layer in the twelfth via holes V12 is etched away, exposing the surface of the first initial signal line 31. The fifth hole group K5 is configured to connect a subsequently formed first connection electrode to the first initial signal line 31 through this via hole group. In an exemplary embodiment, the orthographic projection of the fifth hole group K5 on the substrate may be located within the range of the orthographic projection of the channel region of the first active layer on the substrate.

[0177] In an exemplary embodiment, the at least two twelfth via holes V12 may be arranged in an array. For example, the fifth hole group K5 may include two twelfth via holes V12 arranged in a row and two columns. In other embodiments, the at least two twelfth via holes V12 may be distributed in other ways or irregularly, and this disclosure is not limited thereto.

[0178] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the shielding electrode 33 on the substrate, the fourth insulating layer in the thirteenth via hole V13 is etched away, exposing the surface of the shielding electrode 33, and the thirteenth via hole V13 is configured to connect a subsequently formed first connecting electrode to the shielding electrode 33 through the via hole, so that the shielding electrode 33 receives a constant first initial signal.

[0179] In an exemplary embodiment, the orthographic projection of the fourteenth via hole V14 of the sixth hole group K6 on the substrate is located within the range of the orthographic projection of the second initial signal line 32 on the substrate, the sixth hole group K6 may include at least two fourteenth via holes V14, the third insulating layer in the fourteenth via hole V14 is etched away to expose the surface of the second initial signal line 32, and the sixth hole group K6 is configured to connect the subsequently formed sixth connecting electrode to the second initial signal line 32 through the via hole group.

[0180] In an exemplary embodiment, the at least two fourteenth vias V14 may be arranged in an array. For example, the sixth hole group K6 may include three fourteenth vias V14 arranged in a row and three columns. In other embodiments, the at least two fourteenth vias V14 may be distributed in other ways or irregularly, and this disclosure is not limited thereto.

[0181] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is located within the range of the orthographic projection of the first data transfer portion 25-1 on the substrate, the third insulating layer and the second insulating layer in the fifteenth via V15 are etched away to expose the surface of the first data transfer portion 25-1, and the fifteenth via V15 is configured to connect a subsequently formed data line to the first data transfer portion 25-1 through the via.

[0182] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the first data transfer line 25 on the substrate, the third insulating layer and the second insulating layer in the sixteenth via V16 are etched away to expose the surface of the first data transfer line 25, and the sixteenth via V16 is configured to connect the subsequently formed second data transfer line to the first data transfer line 25 through the via.

[0183] In an exemplary embodiment, at least one circuit unit may further include a seventh hole group K7. The orthographic projection of the seventh hole group K7 on the substrate is located within the range of the orthographic projection of the first initial signal line 31 on the substrate. The seventh hole group K7 may include at least two seventeenth via holes V17. The third insulating layer within the seventeenth via holes V17 is etched away, exposing the surface of the first initial signal line 31. The seventh hole group K7 is configured to connect a subsequently formed first initial signal connection line to the first initial signal line 31 through this via hole group. In an exemplary embodiment, the seventh hole group K7 may be located on a side of the first circuit unit away from the second circuit unit.

[0184] In an exemplary embodiment, the at least two seventeenth vias V17 may be arranged in an array. For example, the seventh hole group K7 may include nine seventeenth vias V17 arranged in three rows and three columns. In other embodiments, the at least two seventeenth vias V17 may be distributed in other ways or in an irregular manner, and this disclosure is not limited thereto.

[0185] In an exemplary embodiment, at least one circuit unit may further include an eighth hole group K8. The orthographic projection of the eighth hole group K8 on the substrate is located within the range of the orthographic projection of the second initial signal line 32 on the substrate. The eighth hole group K8 may include at least two eighteenth via holes V18. The third insulating layer within the eighteenth via holes V18 is etched away, exposing the surface of the second initial signal line 32. The eighth hole group K8 is configured to connect a subsequently formed second initial signal connection line to the second initial signal line 32 through this via hole group. In an exemplary embodiment, the eighth hole group K8 may be located on a side of the third circuit unit away from the second circuit unit.

[0186] In an exemplary embodiment, the at least two eighteenth vias V18 may be arranged in an array. For example, the eighth hole group K8 may include nine eighteenth vias V18 arranged in three rows and three columns. In other embodiments, the at least two eighteenth vias V18 may be distributed in other ways or irregularly, and this disclosure is not limited thereto.

[0187] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the third insulating layer, as shown in FIG12A and FIG12B , where FIG12A is a schematic diagram of the display substrate after the third conductive layer is formed in FIG7 , and FIG12B is a schematic diagram of the third conductive layer in FIG12A . In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0188] In an exemplary embodiment, the third conductive layer patterns of multiple circuit units in the display substrate may include: a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45, a sixth connection electrode 46, a first power line 47, a data line 48 and a second data switching line 50.

[0189] In an exemplary embodiment, the first power line 47 may be in the shape of a line with a main portion extending along the second direction Y. The first power line 47 may be located on a side of the second electrode plate 34 opposite to the first direction X.

[0190] In an exemplary embodiment, a first power connection block 47-1 may be provided on a side of the first power line 47 near the second electrode plate 34. The first end of the first power connection block 47-1 is connected to the first power line 47, and the second end of the first power connection block 47-1 extends toward the side near the second electrode plate 34. The first power line 47 and the first power connection block 47-1 may be an integral structure connected to each other. The second end of the first power connection block 47-1 may be connected to the first end of the second electrode plate 34 via a ninth via V9, thereby connecting the second electrode plate 34 to the first power line 47.

[0191] In an exemplary embodiment, a second power connection block 47-2 may be provided on a side of the first power line 47 near the second electrode plate 34. The first end of the second power connection block 47-2 is connected to the first power line 47, and the second end of the second power connection block 47-2 extends toward the side near the second electrode plate 34. The first power line 47 and the second power connection block 47-2 may be an integral structure connected to each other. The second end of the second power connection block 47-2 may be connected to the second end of the second electrode plate 34 via a tenth via V10, thereby connecting the second electrode plate 34 to the first power line 47. Since the ninth via hole V9 and the tenth via hole V10 are respectively located on both sides of the second electrode plate 34 in the second direction Y, by setting the first power connection block 47-1 and the second power connection block 47-2 on the first power line 47, the first power connection block 47-1 is connected to the second electrode plate 34 through the ninth via hole V9, and the second power connection block 47-2 is connected to the second electrode plate 34 through the tenth via hole V10, so that the second electrode plate 34 can receive the first voltage signal at both ends of the second direction Y at the same time, thereby making the first voltage signal received by the storage capacitor more stable, which is conducive to the stable operation of the pixel circuit.

[0192] In an exemplary embodiment, a third power connection block 47-3 may be provided on a side of the first power line 47 near the second electrode plate 34. A first end of the third power connection block 47-3 is connected to the first power line 47, and a second end of the third power connection block 47-3 extends toward a side near the second electrode plate 34. The first power line 47 and the third power connection block 47-3 may be an integral structure connected to each other. A second end of the third power connection block 47-3 may be connected to the first region of the fifth active layer via a fifth via V5 of the second hole group K2, enabling the first electrode of the fifth transistor T5 to receive the first voltage signal.

[0193] In an exemplary embodiment, the first power line 47 can be designed with non-uniform widths, and the width of the first power line 47 passing through the pixel driving circuit portion can be smaller than the width of other portions. The non-uniform width design of the first power line 47 not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the first power line and the data line.

[0194] In an exemplary embodiment, the data line 48 may be in the shape of a line with a main portion extending along the second direction Y. The data line 48 may be located on the side of the first power line 47 opposite the first direction X, and the data lines 48 between adjacent circuit units are not adjacent. The orthographic projection of the data line 48 on the substrate may overlap with the orthographic projection of the first notch 31-1 provided on the first initial signal line 31 on the substrate. The orthographic projection of the data line 48 on the substrate may also overlap with the orthographic projection of the second notch 32-1 provided on the second initial signal line 32 on the substrate. This arrangement reduces the overlapping area between the data line 48 and the first and second initial signal lines 31 and 32, thereby helping to reduce coupling capacitance.

[0195] In an exemplary embodiment, the data line 48 may be connected to the first region of the fourth active layer through the eleventh via hole V11 of the fourth hole group K4 , so that the first electrode of the fourth transistor T4 can receive the data signal.

[0196] In an exemplary embodiment, a data connection block 48-1 may be provided on a side of the data line 48 near the first power line 47. A first end of the data connection block 48-1 is connected to the data line 48, and a second end of the data connection block 48-1 extends toward a side near the second electrode plate 34. The data line 48 and the data connection block 48-1 may be an integral structure connected to each other. The second end of the data connection block 48-1 may be connected to the first data transfer portion 25-1 via a fifteenth via V15, thereby connecting the data line 48 to the first data transfer line 25.

[0197] In an exemplary embodiment, the second data transfer line 50 may be in the shape of a line with a main portion extending along the second direction Y. The second data transfer line 50 may be located on one side of the second electrode plate 34 in the first direction X. By utilizing the first power line 47 and the second data transfer line 50, the data lines 48 of adjacent circuit units are separated from each other, thereby reducing signal crosstalk between the data lines of different circuit units and improving display quality.

[0198] In an exemplary embodiment, a second data transfer portion 50-1 may be provided on a side of the second data transfer line 50 close to the second electrode plate 34. The first end of the second data transfer portion 50-1 is connected to the second data transfer line 50. The second end of the second data transfer portion 50-1 extends to a side away from the second electrode plate 34 and is connected to the first data transfer line 25 through the sixteenth via V16. The second data transfer line 50 and the second data transfer portion 50-1 may be an integrated structure connected to each other. Since the data line 48 can be connected to the second data transfer line 50 through the first data transfer line 25, the second data transfer line 50 can extend from the display area to the lower frame along the second direction Y and be connected to the integrated circuit in the binding area of ​​the lower frame, forming a data fan-out line located in the display area (Fanout in AA, referred to as FIAA) structure. By adopting the FIAA structure, the arrangement width of the multiple fan-out lines of the lower frame in the first direction X can be reduced, thereby effectively reducing the size of the lower frame, which is conducive to realizing a display substrate with a narrow frame.

[0199] In an exemplary embodiment, the first connection electrode 41 may be L-shaped and may be located between the first power line 47 and the second data transfer line 50. The first connection electrode 41 may be connected to the first region of the first active layer via a first via V1 and to the first initial signal line 31 via a twelfth via V12, allowing the first electrode of the first transistor to receive the first initial signal. The first connection electrode 41 may also be connected to the shielding electrode 33 via a thirteenth via V13, allowing the shielding electrode 33 to receive a constant first initial signal, thereby preventing other signals (such as data voltage jumps) from affecting the potential of the second transistor and improving the display effect.

[0200] In an exemplary embodiment, the second connection electrode 42 may be in the shape of a strip extending along the second direction Y and may be located between the first power line 47 and the second data transfer line 50. The second connection electrode 42 may be connected to the second region of the first active layer (also the second region of the second active layer) via the second via hole V2 of the first hole group K1. It may also be connected to the plurality of first sub-plates 26-1 via the plurality of eighth via holes V8, thereby connecting the second connection electrode 42 to the first electrode plate 26. The second connection electrode 42 may serve as the first node N1 in the pixel circuit. The third transistor serves as a driving transistor in the pixel circuit. By providing multiple (e.g., six) driving transistors in the pixel driving circuit, with the first electrodes, gate electrodes, and second electrodes of the multiple driving transistors being interconnected, the driving current provided by the pixel driving circuit may be increased, thereby improving the display quality of the display substrate.

[0201] In an exemplary embodiment, the third connection electrode 43 may be in the shape of a strip extending along the second direction Y and may be located between the first power line 47 and the second connection electrode 42. The third connection electrode 43 may be connected to the first region of the third active layer (also the second region of the fourth active layer and the second region of the fifth active layer) through a third via hole V3. The third connection electrode 43 may serve as a second node N2 in the pixel circuit.

[0202] In an exemplary embodiment, the fourth connection electrode 44 may be in the shape of a strip extending along the second direction Y and may be located between the second connection electrode 42 and the second data transfer line 50. The fourth connection electrode 44 may be connected to the second region of the third active layer (also the first region of the second active layer and the first region of the sixth active layer) through a fourth via hole V4. The fourth connection electrode 44 may serve as a third node N3 in the pixel circuit.

[0203] In an exemplary embodiment, the fifth connection electrode 45 may be J-shaped and may be located between the fourth connection electrode 44 and the second data transfer line 50. The fifth connection electrode 45 may be connected to the second region of the sixth active layer (also the second region of the seventh active layer) via the sixth via hole V6 of the third hole group K3. The fifth connection electrode 45 may serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 and may be connected to an anode connection electrode formed subsequently.

[0204] In an exemplary embodiment, the sixth connection electrode 46 may be shaped like an inverted "T" and may be located between the first power line 47 and the fifth connection electrode 45. The sixth connection electrode 46 may be connected to the first region of the seventh active layer through the seventh via hole V7 and may be connected to the second initial signal line 32 through the fourteenth via hole V14 of the sixth hole group K6 so that the first electrode of the seventh transistor receives the second initial signal.

[0205] In an exemplary embodiment, the third conductive layer pattern of at least one circuit unit in the display substrate may further include a first initial signal connection line 49. The first initial signal connection line 49 may be in the shape of a line with a main portion extending along the second direction Y. The first initial signal connection line 49 may be located on a side of the first circuit unit away from the second circuit unit. The first initial signal connection line 49 may be connected to the first initial signal line 31 via the seventeenth via V17 of the seventh hole group K7. The first initial signal connection line 49 and the first initial signal line 31 may form a meshed interconnect structure for transmitting the first initial signal, thereby reducing the voltage drop of the first initial signal, facilitating improved transmission uniformity of the first initial signal, avoiding display defects on the display substrate, and ensuring the display quality of the display substrate.

[0206] In an exemplary embodiment, along the first direction X, a first initial signal connection line 49 may be provided for every three circuit units. More or fewer first initial signal connection lines 49 may be provided as needed, which is not limited in the present disclosure.

[0207] In an exemplary embodiment, the third conductive layer pattern of at least one circuit unit in the display substrate may further include a second initial signal connection line 40. The second initial signal connection line 40 may be in the shape of a line with a main portion extending along the second direction Y. The second initial signal connection line 40 may be located on a side of the third circuit unit away from the second circuit unit. The second initial signal connection line 40 may be connected to the second initial signal line 32 via the eighteenth via V18 of the eighth hole group K8. The second initial signal connection line 40 and the second initial signal line 32 may form a meshed interconnect structure for transmitting the second initial signal, thereby reducing the transmission voltage drop of the second initial signal, facilitating improved transmission uniformity of the second initial signal, avoiding display defects on the display substrate, and ensuring the display quality of the display substrate.

[0208] In an exemplary embodiment, along the first direction X, a second initial signal connection line 40 may be provided for every three circuit units. More or fewer second initial signal connection lines 40 may be provided as needed, which is not limited in the present disclosure.

[0209] In an exemplary embodiment, the plurality of circuit units of the display substrate may be divided into a plurality of circuit unit groups. For example, each circuit unit group may include three circuit units arranged in sequence along the first direction X. The first circuit unit, the second circuit unit, and the third circuit unit in this example may serve as a circuit unit group. The third conductive layer pattern of at least one circuit unit group may include: a first auxiliary connection line 38. The shape of the first auxiliary connection line 38 may be a line shape in which the main portion extends along the second direction Y. The first auxiliary connection line 38 may be located on a side of the first initial signal connection line 49 away from the first circuit unit. The first auxiliary connection line 38 is configured to be connected to a first connection ring formed subsequently, and may be used to transmit a first voltage signal.

[0210] In an exemplary embodiment, the third conductive layer pattern of at least one circuit unit group in the display substrate may further include a second auxiliary connection line 39. The second auxiliary connection line 39 may be in the shape of a line with a main portion extending along the second direction Y. The second auxiliary connection line 39 may be located on a side of the second initial signal connection line 40 away from the third circuit unit. The second auxiliary connection line 39 is configured to connect to a first connection ring formed later and may be used to transmit a first voltage signal.

[0211] In this example, multiple first power lines 47 , first auxiliary connection lines 38 and second auxiliary connection lines 39 are provided to achieve transmission of the first voltage signal along the second direction Y. Providing the first auxiliary connection lines 38 and second auxiliary connection lines 39 can help shield the influence between adjacent circuit unit groups.

[0212] (6) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer, coating a fifth insulating film on the fourth insulating layer, and patterning the fifth insulating film using a patterning process to form a fifth insulating layer, wherein the fifth insulating layer in each circuit unit may be provided with a plurality of vias, as shown in FIG13 . FIG13 is a schematic diagram of the display substrate after the fifth insulating layer is formed in FIG7 .

[0213] In an exemplary embodiment, the plurality of via holes in each circuit unit of the display substrate includes at least a ninth hole group K9, a tenth hole group K10, and a thirty-third via hole V33. The orthographic projections of the ninth hole group K9 and the tenth hole group K10 on the substrate may be within the range of the orthographic projection of the first power line 47 on the substrate.

[0214] In an exemplary embodiment, the orthographic projection of the ninth hole group K9 on the substrate may be located on a side of the first connection electrode 41 opposite to the second direction Y. The ninth hole group K9 may include at least two thirty-first via holes V31. The fourth and fifth insulating layers within the thirty-first via holes V31 are removed, exposing the surface of the first power line 47. The ninth hole group K9 is configured to connect a subsequently formed first connection ring to the first power line 47 through this via hole group. The number and distribution of the thirty-first via holes V31 within the ninth hole group K9 can be referred to the description of the aforementioned hole groups and will not be repeated here.

[0215] In an exemplary embodiment, the orthographic projection of the tenth hole group K10 on the substrate can be located on one side of the second direction Y of the sixth connecting electrode 46, the tenth hole group K10 can include at least two thirty-second via holes V32, the fourth insulating layer and the fifth insulating layer in the thirty-second via holes V32 are removed, exposing the surface of the first power line 47, and the tenth hole group K10 is configured to connect the subsequently formed first connecting ring to the first power line 47 through the via group.

[0216] In an exemplary embodiment, the orthographic projection of the thirty-third via V33 on the substrate can be located within the range of the orthographic projection of the fifth connecting electrode 45 on the substrate, the fourth insulating layer and the fifth insulating layer in the thirty-third via V33 are removed, exposing the surface of the fifth connecting electrode 45, and the thirty-third via V33 is configured to connect the subsequently formed first anode connecting electrode, second anode connecting electrode and third anode connecting electrode to the corresponding fifth connecting electrode 45 through the via hole respectively.

[0217] In an exemplary embodiment, the fifth insulating layer of at least one circuit unit group may be provided with an eleventh hole group K11 and a twelfth hole group K12. The orthographic projections of the eleventh hole group K11 and the twelfth hole group K12 on the substrate may be located within the orthographic projection of the first auxiliary connection line 38 on the substrate. The eleventh hole group K11 includes at least two thirty-fourth via holes V34, and the twelfth hole group K12 includes at least two thirty-fifth via holes V35. The fourth and fifth insulating layers within the thirty-fourth and thirty-fifth via holes V34 and V35 are removed, exposing the surface of the first auxiliary connection line 38. The eleventh and twelfth hole groups K11 and K12 are configured to connect a subsequently formed first connecting ring to the first auxiliary connection line 38 through these via groups. The twelfth hole group K12 may be located on one side of the eleventh hole group K11 in the second direction Y.

[0218] In an exemplary embodiment, the fifth insulating layer of at least one circuit unit group may be provided with a thirteenth hole group K13 and a fourteenth hole group K14. The orthographic projections of the thirteenth hole group K13 and the fourteenth hole group K14 on the substrate may be located within the orthographic projection of the second auxiliary connection line 39 on the substrate. The thirteenth hole group K13 may include at least two thirty-sixth via holes V36, and the fourteenth hole group K14 may include at least two thirty-seventh via holes V37. The fourth insulating layer and the fifth insulating layer within the thirty-sixth via holes V36 and the thirty-seventh via holes V37 are removed, exposing the surface of the second auxiliary connection line 39. The thirteenth hole group K13 and the fourteenth hole group K14 are configured to connect a subsequently formed first connecting ring to the second auxiliary connection line 39 through the via group. The fourteenth hole group K14 may be located on one side of the thirteenth hole group K13 in the second direction Y.

[0219] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the fifth insulating layer, as shown in Figures 14A and 14B, where Figure 14A is a schematic diagram of the display substrate after the fourth conductive layer is formed in Figure 7, and Figure 14B is a schematic diagram of the fourth conductive layer in Figure 14A. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0220] In an exemplary embodiment, the fourth conductive layer patterns of multiple circuit units in the display substrate may include: a first connecting ring 51, a first anode connecting electrode 52, a second anode connecting electrode 53, a third anode connecting electrode 54, a first anode pad 55, a second anode pad 56, a third anode pad 57, and a first transmission ring 58.

[0221] In an exemplary embodiment, the first connecting ring 51 may be annular, such as a rectangular ring. The orthographic projection of the first connecting ring 51 on the substrate may surround the periphery of the three pixel driving circuits. The first connecting ring 51 may be connected to the first power lines 47 within the first, second, and third circuit units via the ninth and tenth hole groups K9 and K10 located within the first, second, and third circuit units, interconnecting the first power lines 47 within the multiple circuit units. This helps reduce the voltage drop of the first voltage signal, ensures that different circuit units receive a stable first voltage signal, and improves the transmission uniformity of the first voltage signal.

[0222] In an exemplary embodiment, the orthographic projection of the first connecting ring 51 on the substrate may at least partially overlap with the orthographic projection of the first auxiliary connecting line 38 on the substrate. The first connecting ring 51 may be connected to the first auxiliary connecting line 38 via the eleventh hole group K11 and the twelfth hole group K12, allowing the first auxiliary connecting line 38 to transmit the first voltage signal, thereby helping to reduce the voltage drop of the first voltage signal. The orthographic projection of the first connecting ring 51 on the substrate may at least partially overlap with the orthographic projection of the second auxiliary connecting line 39 on the substrate. The first connecting ring 51 may be connected to the second auxiliary connecting line 39 via the thirteenth hole group K13 and the fourteenth hole group K14, allowing the second auxiliary connecting line 39 to transmit the first voltage signal, thereby helping to reduce the voltage drop of the first voltage signal.

[0223] In an exemplary embodiment, the first anode spacer 55, the second anode spacer 56, and the third anode spacer 57 can be located inside the first connecting ring 51. The first anode spacer 55, the second anode spacer 56, and the third anode spacer 57 can be rectangular in shape, and the corners of the rectangles can be chamfered. The first anode spacer 55 and the second anode spacer 56 can be located on the side of the third anode spacer 57 opposite to the second direction Y, and the first anode spacer 55 can be located on the side of the second anode spacer 56 opposite to the first direction X. Forming the first anode spacer 55, the second anode spacer 56, and the third anode spacer 57 helps ensure the flatness of the anode to be subsequently formed.

[0224] In an exemplary embodiment, a first block protrusion 55-1 may be provided on a side of the first anode spacer 55 away from the third anode spacer 57. A first end of the first block protrusion 55-1 may be connected to the first anode spacer 55, and a second end of the first block protrusion 55-1 may extend in a direction opposite to the second direction Y and then be connected to the first connecting ring 51. A second block protrusion 55-2 may be provided on a side of the first anode spacer 55 closer to the third anode spacer 57. A first end of the second block protrusion 55-2 may be connected to the first anode spacer 55, and a second end of the second block protrusion 55-2 may extend in the second direction Y and then be connected to the first connecting ring 51. The first anode spacer 55, the first block protrusion 55-1, and the second block protrusion 55-2 may be an integrated structure connected to each other.

[0225] In an exemplary embodiment, a third spacer protrusion 56-1 may be provided on a side of the second anode spacer 56 away from the third anode spacer 57. A first end of the third spacer protrusion 56-1 may be connected to the second anode spacer 56, and a second end of the third spacer protrusion 56-1 may extend in a direction opposite to the second direction Y and then be connected to the first connecting ring 51. A fourth spacer protrusion 56-2 may be provided on a side of the second anode spacer 56 closer to the third anode spacer 57. A first end of the fourth spacer protrusion 56-2 may be connected to the second anode spacer 56, and a second end of the fourth spacer protrusion 56-2 may extend in the second direction Y and then be connected to the third anode spacer 57. The second anode spacer 56, the third spacer protrusion 56-1, and the fourth spacer protrusion 56-2 may be an integrated structure connected to each other.

[0226] In an exemplary embodiment, a fifth spacer protrusion 57-1 may be provided on a side of the third anode spacer 57 away from the first anode spacer 55 and the second anode spacer 56. A first end of the fifth spacer protrusion 57-1 may be connected to the third anode spacer 57, and a second end of the fifth spacer protrusion 57-1 may be connected to the first connecting ring 51 after extending along the second direction Y. The third anode spacer 57 and the fifth spacer protrusion 57-1 may be an integral structure connected to each other.

[0227] In some examples, the first anode spacer 55, the second anode spacer 56, the third anode spacer 57, the first connecting ring 51, and the plurality of spacer protrusions can be interconnected as an integral structure. The orthographic projections of the first anode spacer and the second anode spacer on the substrate can cover the orthographic projections of the first connecting electrode 41, the second connecting electrode 42, the third connecting electrode 43, and the fourth connecting electrode 44 on the substrate, which can help shield interference with the pixel driving circuit.

[0228] In some examples, the first anode spacer 55, the second anode spacer 56, and the third anode spacer 57 may include multiple through holes that expose the surface of the fifth insulating layer. These multiple through holes may be arranged in an array. In this example, by providing through holes in the anode spacer, the organic film layer is facilitated to breathe. This embodiment does not limit the arrangement of the multiple through holes.

[0229] In an exemplary embodiment, the shape of the first anode connection electrode 52, the second anode connection electrode 53, and the third anode connection electrode 54 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projections of the first anode connection electrode 52, the second anode connection electrode 53, and the third anode connection electrode 54 on the substrate can at least partially overlap with the orthographic projections of the fifth connection electrode 45 in the circuit unit in which they are located on the substrate. The first anode connection electrode 52, the second anode connection electrode 53, and the third anode connection electrode 54 can be connected to the fifth connection electrode 45 in the circuit unit in which they are located through the thirty-third via V33. The first anode connection electrode 52 can be connected to the first anode formed subsequently, the second anode connection electrode 53 can be connected to the second anode formed subsequently, and the third anode connection electrode 54 can be connected to the third anode formed subsequently, so that the corresponding anodes are connected to the second electrode of the sixth transistor T6 (the second electrode of the seventh transistor T7) of the pixel driving circuit.

[0230] In some examples, the first anode connection electrode 52 , the second anode connection electrode 53 , and the third anode connection electrode 54 may include multiple through holes exposing the surface of the fifth insulating layer. The multiple through holes may be arranged in an array or distributed in other forms to facilitate air permeability of the organic film layer.

[0231] In an exemplary embodiment, the first transmission ring 58 may be annular, such as a rectangular ring. The first transmission ring 58 may be located outside the first connecting ring 51. The first transmission ring 58 may be formed by connecting two first transmission line segments 581 extending in a first direction X and two second transmission line segments 582 extending in a second direction Y end-to-end. The first transmission line segment 581 may be a portion of a first transmission line 591, and the second transmission line segment 582 may be a portion of a second transmission line 592. The first transmission ring 58 may be configured to transmit a second voltage signal.

[0232] (8) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming the sixth insulating layer pattern may include: coating a sixth insulating film on the substrate on which the aforementioned pattern is formed, patterning the sixth insulating film using a patterning process to form a sixth insulating layer, wherein the sixth insulating layer in each circuit unit may be provided with a plurality of vias, as shown in FIG15 . FIG15 is a schematic diagram of the display substrate after the sixth insulating layer is formed in FIG7 .

[0233] In an exemplary embodiment, the plurality of via holes of each circuit unit group in the display substrate includes at least a forty-first via hole V41 , a forty-second via hole V42 , and a forty-third via hole V43 .

[0234] In an exemplary embodiment, the orthographic projection of the forty-first via hole V41 on the substrate is located within the range of the orthographic projection of the first anode connecting electrode 52 on the substrate, the sixth insulating layer in the forty-first via hole V41 is removed, exposing the surface of the first anode connecting electrode 52, and the forty-first via hole V41 is configured to connect the subsequently formed first anode to the first anode connecting electrode 52 through the via hole.

[0235] In an exemplary embodiment, the orthographic projection of the forty-second via hole V42 on the substrate is located within the range of the orthographic projection of the second anode connecting electrode 53 on the substrate, the sixth insulating layer in the forty-second via hole V42 is removed, exposing the surface of the second anode connecting electrode 53, and the forty-second via hole V42 is configured to connect the subsequently formed second anode to the second anode connecting electrode 53 through the via hole.

[0236] In an exemplary embodiment, the orthographic projection of the forty-third via V43 on the substrate is located within the range of the orthographic projection of the third anode connecting electrode 54 on the substrate, the sixth insulating layer in the forty-third via V43 is removed, exposing the surface of the third anode connecting electrode 54, and the forty-third via V43 is configured to connect the subsequently formed third anode to the third anode connecting electrode 54 through the via.

[0237] In an exemplary embodiment, at least one circuit unit group may further include a first via bar F1 extending along a first direction X and a second via bar F2 extending along a second direction Y. The orthographic projections of the first via bar F1 and the second via bar F2 on the substrate may be located within the range of the orthographic projection of the first transmission ring 58 on the substrate. The sixth insulating layer in the first via bar F1 and the second via bar F2 may be removed to expose at least a portion of the surface of the first transmission ring 58. The first via bar F1 and the second via bar F2 may be configured so that the subsequently formed second transmission ring is connected to the first transmission ring 58 through the two via bars. In some examples, the first via bar F1 and the second via bar F2 may be interconnected. However, this embodiment is not limited to this. For example, the first via bar F1 and the second via bar F2 may not be interconnected.

[0238] (9) Forming an anode layer pattern. In an exemplary embodiment, forming the anode layer pattern may include: depositing an anode film on the substrate on which the aforementioned pattern is formed, and patterning the anode film using a patterning process to form an anode layer disposed on the sixth insulating layer, as shown in FIG. 16 , which is a schematic diagram of the anode layer in FIG. 7 .

[0239] In an exemplary embodiment, the anode layer patterns of the plurality of circuit unit groups in the display substrate may include: a first anode 71, a second anode 72, and a third anode 73. The first anode 71, the second anode 72, and the third anode 73 may be rectangular in shape, and the corners of the rectangle may be chamfered.

[0240] In an exemplary embodiment, a first anode connection block 71-1 may be provided on a side of the first anode 71 near the third anode 73. A first end of the first anode connection block 71-1 may be connected to the first anode 71, and a second end of the first anode connection block 71-1 may extend along the second direction Y and be connected to the first anode connection electrode 52 through a forty-first via hole V41 in the first circuit unit. The first anode 71 and the first anode connection block 71-1 may be an integral structure connected to each other.

[0241] In an exemplary embodiment, a second anode connection block 72-1 may be provided on a side of the second anode 72 near the third anode 73. A first end of the second anode connection block 72-1 may be connected to the second anode 72, and a second end of the second anode connection block 72-1 may extend along the second direction Y and be connected to the second anode connection electrode 53 through a forty-second via hole V42 in the second circuit unit. The second anode 72 and the second anode connection block 72-1 may be an integral structure connected to each other.

[0242] In an exemplary embodiment, a third anode connection block 73-1 may be provided on a side of the third anode 73 adjacent to the second anode 72. A first end of the third anode connection block 73-1 may be connected to the third anode 73, and a second end of the third anode connection block 73-1 may extend in a direction opposite to the second direction Y and be connected to the third anode connection electrode 54 through a forty-third via hole V43 in the third circuit unit. The third anode 73 and the third anode connection block 73-1 may be an integral structure connected to each other.

[0243] In an exemplary embodiment, the anode layer of at least one circuit unit group may further include a second transmission ring 74. The second transmission ring 74 may be formed by connecting two adjacent third transmission lines 741 extending along the first direction X and two adjacent fourth transmission lines 742 extending along the second direction Y. The second transmission ring 74 may be connected to the first transmission ring 58 via the first and second via bars F1 and F2. The first transmission ring 58 may be connected to the subsequently formed cathode layer via the second transmission ring 74, thereby facilitating transmission uniformity of the second voltage signal.

[0244] (10) Forming a pixel definition layer pattern. In an exemplary embodiment, forming the pixel definition layer pattern may include: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, and patterning the pixel definition film using a patterning process to form a pixel definition layer disposed on the anode layer, as shown in Figures 17A and 17B. Figure 17A is a schematic diagram of a display substrate after forming a pixel definition layer on the structure shown in Figure 7, and Figure 17B is a schematic diagram of the pixel definition layer in Figure 17A.

[0245] In an exemplary embodiment, the pixel definition layer pattern of one circuit unit group of the display substrate may be provided with a plurality of openings, for example, including a first anode opening 81 , a second anode opening 82 and a third anode opening 83 .

[0246] In an exemplary embodiment, the orthographic projection of the first anode opening 81 on the substrate can be located within the range of the orthographic projection of the first anode 71 on the substrate, and the pixel definition layer within the first anode opening 81 is removed to expose at least a portion of the surface of the first anode 71 so that the subsequently formed light-emitting layer can be connected to the first anode 71.

[0247] In an exemplary embodiment, the orthographic projection of the second anode opening 82 on the substrate can be located within the range of the orthographic projection of the second anode 72 on the substrate, and the pixel definition layer within the second anode opening 82 is removed to expose at least a portion of the surface of the second anode 72 so that the subsequently formed light-emitting layer can be connected to the second anode 72.

[0248] In an exemplary embodiment, the orthographic projection of the third anode opening 83 on the substrate can be located within the range of the orthographic projection of the third anode 73 on the substrate, and the pixel definition layer within the third anode opening 83 is removed to expose at least a portion of the surface of the third anode 73 so that the subsequently formed light-emitting layer can be connected to the third anode 73.

[0249] In an exemplary embodiment, the pixel definition layer of at least one circuit unit group may further be provided with a third through-hole bar F3 extending along the first direction X and a fourth through-hole bar F4 extending along the second direction Y. The orthographic projections of the third through-hole bar F3 and the fourth through-hole bar F4 on the substrate may be located within the orthographic projection range of the second transmission ring 74 on the substrate, and the pixel definition layer within the third through-hole bar F3 and the fourth through-hole bar F4 may be removed to expose at least a portion of the surface of the second transmission ring 74 so that the subsequently formed cathode layer can be connected to the second transmission ring 74. In some examples, the third through-hole bar F3 and the fourth through-hole bar F4 may be interconnected. However, this embodiment is not limited to this. For example, the third through-hole bar F3 and the fourth through-hole bar F4 may not be interconnected.

[0250] In an exemplary embodiment, the subsequent preparation process may include forming a light emitting layer pattern, a cathode layer pattern, and an encapsulation layer, etc., which will not be described in detail here.

[0251] At this point, the display substrate of this embodiment is prepared on the substrate. In a plane parallel to the display substrate, the circuit structure layer may include multiple circuit units, each of which may include a pixel driving circuit, and a first scan line, a second scan line, a third scan line, a light-emitting control line, a first initial signal line, a second initial signal line, a first power line, a second power line, and a data line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the display substrate may include at least a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer, an anode layer, and a pixel definition layer stacked in sequence on the substrate. The active layer of the first transistor T1 to the seventh transistor T7 can be set in the semiconductor layer, the first scan line 21, the second scan line 22, the third scan line 23, the light emitting control line 24, the first data transfer line 25 and the first plate 26 of the storage capacitor can be set in the first conductive layer, the first initial signal line 31, the second initial signal line 32, the shielding electrode 33 and the second plate 34 can be set in the second conductive layer, the first auxiliary connection line 38, the second auxiliary connection line 39, the second initial signal connection line 40, the first connection electrode 41, the second connection electrode 42, the third connection electrode 43, The fourth connecting electrode 44, the fifth connecting electrode 45, the sixth connecting electrode 46, the first power line 47, the data line 48, the first initial signal connecting line 49 and the second data switching line 50 can be arranged in the third conductive layer, the first connecting ring 51, the first anode connecting electrode 52, the second anode connecting electrode 53, the third anode connecting electrode 54, the first anode pad 55, the second anode pad 56, the third anode pad 57, and the first transmission ring 58 can be arranged in the fourth conductive layer, and the first anode 71, the second anode 72, the third anode 73, and the second transmission ring 74 can be arranged in the anode layer.

[0252] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0253] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the anode layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may have a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may have a single layer, a multi-layer structure, or a composite structure. The first and second insulating layers may be referred to as gate insulating (GI) layers, the third insulating layer may be referred to as an interlayer insulating (ILD) layer, and the fourth insulating layer may be referred to as a passivation (PVX) layer. The fifth and sixth insulating layers may be referred to as planarization (PLN) layers, and the planarization layers may be made of organic materials, such as resin. The active layer can be made of materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, or polythiophene. This means that the present disclosure is applicable to transistors manufactured using oxide, silicon, or organic technologies. The pixel definition film can be made of materials such as polyimide or acrylic.

[0254] FIG18 is a partial structural diagram of the first circuit unit in FIG7 , illustrating the structure from the semiconductor layer to the third conductive layer.

[0255] In an exemplary embodiment, the pixel driving circuit may include a plurality of (e.g., six) driving transistors arranged sequentially along a direction, wherein the first electrodes of the plurality of driving transistors are interconnected via a third connecting electrode 43, the second electrodes of the plurality of driving transistors are interconnected via a fourth connecting electrode 44, and the gate electrodes of the plurality of driving transistors are interconnected via a second connecting electrode 42. By providing a plurality of driving transistors in the pixel driving circuit, and connecting the first electrodes, gate electrodes, and second electrodes of the plurality of driving transistors to each other, it is possible to increase the driving current provided by the pixel driving circuit, thereby improving the display quality of the display substrate. For example, the second connecting electrode 42 can serve as the first node N1 in the pixel circuit. The third connecting electrode 43 can serve as the second node N2 in the pixel circuit. The fourth connecting electrode 44 can serve as the third node N3 in the pixel circuit.

[0256] In an exemplary embodiment, by providing at least one first initial signal connection line 49 extending along the second direction Y and connecting the first initial signal connection line 49 to the first initial signal line 31 extending along the first direction X, a mesh structure for transmitting the first initial signal can be formed to ensure the transmission consistency of the first initial signal.

[0257] In an exemplary embodiment, at least one second data transfer line 50 is provided extending along the second direction Y, and at least one first data transfer line 25 is provided extending along the first direction X. The second data transfer line 50 is connected to the first data transfer line 25, and the first data transfer line 25 is connected to the data line 48. This allows the data line 48 to extend from the display area to the bonding area of ​​the lower bezel via the second data transfer line 50 and connect to the integrated circuit, thereby forming a FIAA structure. By adopting the FIAA structure, the arrangement width of the multiple fan-out traces of the lower bezel in the first direction X can be reduced, thereby effectively reducing the size of the lower bezel and facilitating the realization of a narrow-bezel display substrate.

[0258] In an exemplary embodiment, by providing at least one first auxiliary connection line 38 extending along the second direction Y, the first auxiliary connection line 38 can be connected to the first connection ring 51, thereby reducing the voltage drop of the first voltage signal. In an exemplary embodiment, by providing an orthographic projection of the shielding electrode 33 on the substrate to at least partially overlap with the orthographic projection of the second active layer on the substrate between the two gate electrodes of the second transistor T2 in this circuit unit, and by utilizing the first connection electrode 41 to connect the shielding electrode 33 to the first initial signal line 31, the shielding electrode 33 receives a constant first initial signal, thereby preventing the influence of other signals (such as data voltage jumps) on the second transistor T2, thereby improving the display effect. The first connection electrode 41 can also be connected to the first electrode of the first transistor T1.

[0259] In an exemplary embodiment, by providing a first notch 31-1 on the first initial signal line 31, providing a second notch 32-1 on the second initial signal line 32, and making the orthographic projection of the data line 48 on the substrate overlap with the orthographic projection of the first notch 31-1 on the substrate and the orthographic projection of the second notch 32-1 on the substrate, the overlapping area between the first initial signal line 31 and the second initial signal line 32 and the data line 48 can be reduced, thereby reducing the coupling capacitance between the first initial signal line 31 and the second initial signal line 32 and the data line 48.

[0260] The structure and preparation process shown above in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0261] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0262] The present disclosure also provides a method for preparing a display substrate, so as to prepare the display substrate provided in the above embodiment.

[0263] In an exemplary embodiment, the method includes: forming a circuit structure layer on a substrate; the circuit structure layer includes at least a plurality of circuit units, at least one circuit unit includes a pixel driving circuit, and the pixel driving circuit includes: a plurality of driving transistors arranged in sequence along a direction; the first electrodes of the plurality of driving transistors are connected to each other, the second electrodes of the plurality of driving transistors are connected to each other, and the gate electrodes of the plurality of driving transistors are connected to each other.

[0264] The present disclosure also provides a display substrate, comprising: a substrate and a circuit structure layer disposed on the substrate, the circuit structure layer comprising at least: a plurality of circuit units, each circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising: a storage capacitor and a plurality of driving transistors. The storage capacitor comprises: a first electrode plate and a second electrode plate, the first electrode plate serving as a gate electrode for the plurality of driving transistors; the second electrode plate being located on a side of the first electrode plate away from the substrate; the second electrode plate having a plurality of first openings, the orthographic projection of the first electrode plate on the substrate covering the orthographic projection of the plurality of first openings of the second electrode plate on the substrate. The second connecting electrode located on the side of the second electrode plate away from the substrate is connected to the first electrode plate through vias provided in the plurality of first openings.

[0265] In some exemplary embodiments, within a single circuit unit, the first electrode plate includes multiple first sub-plates, with a single first sub-plate serving as a gate electrode for at least one driver transistor. The multiple circuit units include at least a first circuit unit, a second circuit unit, and a third circuit unit. The orthographic projection of the first sub-plate within the third circuit unit onto the substrate is smaller than the orthographic projection of the first sub-plate within the second circuit unit onto the substrate. The orthographic projection of the first sub-plate within the third circuit unit onto the substrate is smaller than the orthographic projection of the first sub-plate within the first circuit unit onto the substrate.

[0266] In some exemplary embodiments, within a single circuit unit, the second electrode plate has multiple first openings. The multiple circuit units include at least: a first circuit unit, a second circuit unit, and a third circuit unit. The area of ​​the orthographic projection of the first opening of the second electrode plate in the third circuit unit on the substrate is larger than the area of ​​the orthographic projection of the first opening of the second electrode plate in the first circuit unit on the substrate. The area of ​​the orthographic projection of the first opening of the second electrode plate in the third circuit unit on the substrate is larger than the area of ​​the orthographic projection of the first opening of the second electrode plate in the second circuit unit on the substrate. For example, the area of ​​the orthographic projection of a single first opening in the third circuit unit on the substrate may be larger than the area of ​​the orthographic projection of a single first opening in the first circuit unit on the substrate. In some examples, the total area of ​​the orthographic projections of the multiple first openings in the third circuit unit on the substrate may be larger than the total area of ​​the orthographic projections of the multiple first openings in the first circuit unit on the substrate.

[0267] In some exemplary embodiments, the plurality of circuit units include at least a first circuit unit, a second circuit unit, and a third circuit unit. The number of first openings of the second plate in the third circuit unit is different from the number of first openings of the second plate in the first circuit unit. The number of first openings of the second plate in the first circuit unit is the same as the number of first openings of the second plate in the second circuit unit.

[0268] In some exemplary embodiments, the pixel driving circuit in the first circuit unit is connected to the light-emitting device that emits red light, the pixel driving circuit in the second circuit unit is connected to the light-emitting device that emits green light, and the pixel driving circuit in the third circuit unit is connected to the light-emitting device that emits blue light.

[0269] The structure of the display substrate of this embodiment can be referred to the description of the above embodiments, and thus will not be described again here.

[0270] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0271] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the present invention. Any person skilled in the art may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the present invention shall still be based on the scope defined by the appended claims.

Claims

1. A display substrate, comprising: A substrate and a circuit structure layer arranged on the substrate, the circuit structure layer at least includes a plurality of circuit units, at least one circuit unit includes a pixel driving circuit, the pixel driving circuit includes: a plurality of driving transistors; the first electrodes of the plurality of driving transistors are connected to each other, the second electrodes of the plurality of driving transistors are connected to each other, and the gate electrodes of the plurality of driving transistors are connected to each other.

2. The display substrate according to claim 1, wherein: The pixel driving circuit further includes: a storage capacitor, the storage capacitor including: a first electrode plate and a second electrode plate, the second electrode plate is located on a side of the first electrode plate away from the substrate; the orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the second electrode plate on the substrate; The first electrode plate includes: a plurality of first sub-plates, and a single first sub-plate serves as a gate electrode of at least one of the driving transistors.

3. The display substrate according to claim 2, wherein: The plurality of first sub-plates of the first electrode plate are independently arranged and electrically connected via a second connecting electrode; the second connecting electrode is located on a side of the second electrode plate away from the substrate.

4. The display substrate according to claim 3, wherein: The pixel driving circuit further includes: a first initialization transistor and a threshold compensation transistor; The first electrode of the first initialization transistor is connected to the first initialization signal line, and the second electrode of the first initialization transistor is connected to the gate electrodes of the plurality of driving transistors; the second electrode of the threshold compensation transistor is connected to the gate electrodes of the plurality of driving transistors, and the first electrode of the threshold compensation transistor is connected to the second electrodes of the plurality of driving transistors; The first initial transistor and the threshold compensation transistor are connected to gate electrodes of the plurality of driving transistors through the second connection electrode.

5. The display substrate according to claim 4, wherein: In a direction perpendicular to the display substrate, the circuit structure layer at least includes: a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer sequentially arranged on the base; The first electrode of the storage capacitor is located in the first conductive layer, the second electrode is located in the second conductive layer, and the second connecting electrode is located in the third conductive layer.

6. The display substrate according to any one of claims 2 to 5, wherein: The plurality of driving transistors are arranged in sequence along a second direction, the second electrode plate of the storage capacitor extends along the second direction, and the second electrode plate has a first end and a second end along the second direction; The first end and the second end of the second electrode plate are respectively connected to a first power line; the first power line is located on a side of the second electrode plate away from the substrate.

7. The display substrate according to claim 1, wherein: The circuit structure layer further includes: a data line connected to the pixel driving circuit and extending along the second direction, a first data transfer line extending along the first direction, and a second data transfer line extending along the second direction; the first direction intersects the second direction; The data line is connected to the second data adapter line through the first data adapter line; the first data adapter line is located on a side of the data line close to the substrate, and the second data adapter line is arranged on the same layer as the data line.

8. The display substrate according to claim 7, wherein: The circuit structure layer further includes: a first power line connected to the pixel driving circuit; the data line and the first power line are arranged in the same layer and spaced apart in the first direction.

9. The display substrate according to claim 1, wherein: The pixel driving circuit further includes: a first initialization transistor, a first electrode of the first initialization transistor is connected to a first initial signal line, and a second electrode of the first initialization transistor is connected to gate electrodes of the plurality of driving transistors; The first initial signal line extends along a first direction, the first initial signal line is connected to a first initial signal connection line extending along a second direction, and the first direction intersects the second direction; The first initial signal connection line is located at a side of the first initial signal line away from the substrate.

10. The display substrate according to claim 9, wherein: The pixel driving circuit further includes: a second initialization transistor, a first electrode of the second initialization transistor is connected to a second initial signal line, and a second electrode of the second initialization transistor is connected to a first electrode of a light emitting device connected to the pixel driving circuit; The second initial signal line extends along the first direction, and the second initial signal line is connected to a second initial signal connection line extending along the second direction; The second initial signal line is disposed on the same layer as the first initial signal line, and the second initial signal connecting line is disposed on the same layer as the first initial signal connecting line.

11. The display substrate according to claim 1, wherein: The pixel driving circuit further includes: a first initialization transistor and a threshold compensation transistor; a first electrode of the first initialization transistor is connected to a first initial signal line, and a second electrode of the first initialization transistor is connected to gate electrodes of the plurality of driving transistors; a second electrode of the threshold compensation transistor is connected to gate electrodes of the plurality of driving transistors, and a first electrode of the threshold compensation transistor is connected to second electrodes of the plurality of driving transistors; The first initial signal line is connected to a shielding electrode, and a conductor region of the shielding electrode between an orthographic projection of the substrate and a channel region of an active layer of the threshold compensation transistor at least partially overlaps with the orthographic projection of the substrate; the shielding electrode and the first initial signal line are arranged in the same layer and are located on a side of the gate electrode of the threshold compensation transistor away from the substrate.

12. The display substrate according to claim 11, wherein: The first initial signal line is connected to the shielding electrode and the first initialization transistor through a first connecting electrode; the first connecting electrode is located at a side of the first initial signal line away from the substrate.

13. The display substrate according to claim 1, wherein: The plurality of circuit units are divided into a plurality of circuit unit groups, each circuit unit group comprises three pixel driving circuits sequentially arranged along the first direction, and each pixel driving circuit in the circuit unit group is electrically connected to a first power line extending along the second direction; The circuit structure layer further includes: at least one first connection ring, the first connection ring being electrically connected to three first power lines connected to three pixel driving circuits in the circuit unit group, and the first connection ring being projected on the substrate around the periphery of the three pixel driving circuits; The first connecting ring is located at a side of the first power line away from the substrate.

14. The display substrate according to claim 13, wherein: The circuit structure layer also includes: at least one first transmission ring, which is arranged in the same layer as the first connecting ring and is located at the periphery of the first connecting ring; the first transmission ring and the first connecting ring are configured to transmit different voltage signals.

15. The display substrate according to claim 14, further comprising: A light emitting structure layer located on a side of the circuit structure layer away from the substrate, the light emitting structure layer comprising a plurality of light emitting devices; The three first pixel driving circuits in one circuit unit group are electrically connected to the three light emitting devices in a one-to-one correspondence; The light emitting structure layer comprises an anode layer, and the anode layer comprises: anodes of the plurality of light emitting devices, and at least one second transmission ring; The second transmission ring is electrically connected to the first transmission ring, and the second transmission ring is on the base The orthographic projection of the first transmission ring at least partially overlaps with the orthographic projection of the first transmission ring on the substrate; the second transmission ring is located at the periphery of the anodes of the three light-emitting devices connected to the three first pixel driving circuits of the circuit unit group.

16. The display substrate according to claim 13, further comprising: A light emitting structure layer located on a side of the circuit structure layer away from the substrate, the light emitting structure layer comprising a plurality of light emitting devices; The circuit structure layer further comprises: a plurality of anode pads electrically connected to the first power line; the anode pads are located on a side of the anode of the light-emitting device close to the substrate, and the orthographic projection of the anode pads on the substrate includes the orthographic projection of at least one anode of the light-emitting device on the substrate; The plurality of anode pads located inside the first connecting ring and the first connecting ring are interconnected as an integral structure.

17. The display substrate according to claim 16, wherein: At least one of the anode pads is provided with a plurality of through holes arranged in an array.

18. A display device comprising the display substrate according to any one of claims 1 to 17.

19. A method for preparing a display substrate, comprising: forming a circuit structure layer on a substrate; The circuit structure layer includes at least a plurality of circuit units, at least one of which includes a pixel driving circuit, and the pixel driving circuit includes: a plurality of driving transistors; The first electrodes of the plurality of driving transistors are connected to each other, the second electrodes of the plurality of driving transistors are connected to each other, and the gate electrodes of the plurality of driving transistors are connected to each other.

20. A display substrate, comprising: A substrate and a circuit structure layer arranged on the substrate, wherein the circuit structure layer at least comprises: a plurality of circuit units, each circuit unit comprises a pixel driving circuit, and the pixel driving circuit comprises: a storage capacitor and a plurality of driving transistors; The storage capacitor comprises: a first electrode plate and a second electrode plate, wherein the first electrode plate serves as a gate electrode of the plurality of driving transistors; the second electrode plate is located on a side of the first electrode plate away from the substrate; the second electrode plate has a plurality of first openings, and the orthographic projection of the first electrode plate on the substrate covers the orthographic projection of the plurality of first openings of the second electrode plate on the substrate; The second connecting electrode located at a side of the second electrode plate away from the substrate is connected to the first electrode plate through via holes arranged in the plurality of first openings.

21. The display substrate according to claim 20, wherein: In a single circuit unit, the first electrode plate includes a plurality of first sub-plates, and a single first sub-plate serves as a gate electrode of at least one driving transistor; The plurality of circuit units at least include: a first circuit unit, a second circuit unit and a third circuit unit; The area of ​​the orthographic projection of the first sub-board in the third circuit unit on the substrate is smaller than the area of ​​the orthographic projection of the first sub-board in the second circuit unit on the substrate; An area of ​​an orthographic projection of the first sub-board in the third circuit unit on the substrate is smaller than an area of ​​an orthographic projection of the first sub-board in the first circuit unit on the substrate.

22. The display substrate according to claim 20, wherein: In a single circuit unit, the second electrode plate has a plurality of first openings; The plurality of circuit units at least include: a first circuit unit, a second circuit unit and a third circuit unit; The area of ​​the orthographic projection of the first opening of the second electrode plate in the third circuit unit on the substrate is larger than the area of ​​the orthographic projection of the first opening of the second electrode plate in the first circuit unit on the substrate; An area of ​​an orthographic projection of the first opening of the second electrode plate in the third circuit unit on the substrate is larger than an area of ​​an orthographic projection of the first opening of the second electrode plate in the second circuit unit on the substrate.

23. The display substrate according to claim 20, wherein: The plurality of circuit units at least include: a first circuit unit, a second circuit unit and a third circuit unit; The number of the first openings of the second plate in the third circuit unit is different from the number of the first openings of the second plate in the first circuit unit; The number of the first openings of the second plate in the first circuit unit is the same as the number of the first openings of the second plate in the second circuit unit.

24. The display substrate according to any one of claims 21 to 23, wherein: The pixel driving circuit in the first circuit unit is connected to the light emitting device emitting red light, the pixel driving circuit in the second circuit unit is connected to the light emitting device emitting green light, and the pixel driving circuit in the third circuit unit is connected to the light emitting device emitting blue light.

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