Display panel and electronic device

Abstract

The present application provides a display panel and an electronic device. A first organic layer of the display panel is provided with barrier grooves within a frame region, each first signal wire is provided with a first wiring portion at a corresponding barrier groove, and the first wiring portion is provided with multiple openings, so as to increase the area of the exposed side surface of the first wiring portion and then reduce the side etching depth of the first wiring portion. The problem in existing display panels of severe side etching of metal signal wires is mitigated.

Description

Display panel and electronic device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and an electronic device. Background Art

[0002] In the display panel array manufacturing process, a yellow light process is usually used to form the required pattern. However, when etching some film layers, some exposed metal signal traces will also suffer from severe undercutting. SUMMARY OF THE INVENTION

[0003] The present application provides a display panel and an electronic device to alleviate the technical problem of severe side engraving of metal signal traces in existing display panels.

[0004] To solve the above problems, the technical solutions provided by this application are as follows:

[0005] In a first aspect, an embodiment of the present application provides a display panel comprising a display area and a frame area located on one side of the display area, wherein the frame area comprises an effective packaging area and a bending area located on a side of the effective packaging area away from the display area; the display panel further comprises:

[0006] substrate;

[0007] A first signal trace is provided on one side of the substrate, at least a portion of the first signal trace is located within the border area;

[0008] a first organic layer, disposed on a side of the first signal trace away from the substrate and extending from the display area to the frame area along a first direction, the first organic layer having a blocking groove in the effective encapsulation area, the blocking groove exposing at least a portion of a side surface of the first signal trace; and

[0009] The first signal wiring includes a first wiring portion arranged corresponding to the blocking groove, and a plurality of openings are provided on the first wiring portion.

[0010] In a second aspect, embodiments of the present application further provide an electronic device comprising a housing and a display panel mounted within the housing, the display panel comprising a display area and a frame area located on one side of the display area, the frame area comprising an effective packaging area and a bending area located on a side of the effective packaging area away from the display area; the display panel further comprising:

[0011] substrate;

[0012] A first signal trace is provided on one side of the substrate, at least a portion of the first signal trace is located within the border area;

[0013] a first organic layer, disposed on a side of the first signal trace away from the substrate and extending from the display area to the frame area along a first direction, the first organic layer having a blocking groove in the effective encapsulation area, the blocking groove exposing at least a portion of a side surface of the first signal trace; and

[0014] an encapsulation layer, disposed on a side of the first organic layer away from the substrate, and extending from the display area to the frame area along a first direction, and the encapsulation layer is also located in the blocking groove;

[0015] The first signal wiring includes a first wiring portion arranged corresponding to the blocking groove, and a plurality of openings are provided on the first wiring portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] FIG1 is a schematic diagram of a top view of the structure of a display panel provided in an embodiment of the present application.

[0018] FIG2 is a schematic diagram of the cross-sectional structure along the N-N' direction in FIG1 .

[0019] FIG. 3 is a schematic diagram of the display panel in FIG. 1 after the first organic layer is removed.

[0020] FIG4 is a schematic diagram of the detailed structure of the first signal routing in FIG3 .

[0021] FIG5 is a schematic diagram of the cross-sectional structure along the PP' direction in FIG4.

[0022] FIG6 is another schematic diagram of a top view of the structure of a display panel provided in an embodiment of the present application.

[0023] FIG. 7 is a schematic diagram of a top view of the structure of a display panel provided in an embodiment of the present application.

[0024] FIG8 is a schematic diagram of a cross-sectional structure of an electronic device provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0025] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be implemented in. The directional terms mentioned in this application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present application, rather than to limit the present application. In the figures, units with similar structures are represented by the same reference numerals. In the accompanying drawings, the thickness of some layers and areas is exaggerated for clarity of understanding and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited to this.

[0026] To address the severe side-etching problem of metal signal traces in existing display panels, the inventors of this application discovered through research that, in order to achieve a larger screen-to-body ratio and reduce the non-display area, the industry has attempted to compress the display panel's lower bezel to the extreme. This compression of the lower bezel makes it easy for the cathode on the display panel to come into contact with power lines (such as the VDD signal line), causing a short circuit. Related art involves adding an inorganic passivation layer (PV) between the cathode and the power line to isolate them. However, adding an inorganic passivation layer is not conducive to increasing production capacity and reducing costs.

[0027] To address this issue, a narrow-frame, inorganic passivation-free technology has emerged. This solution uses an organic planarizing layer (PLN) to isolate the cathode from the power line. The organic planarizing layer is made of an organic material, which is easily permeable to water and oxygen. To prevent external water and oxygen from entering the display area of ​​the display panel through the organic planarizing layer, the organic planarizing layer needs to be disconnected in the lower frame area to block the external water and oxygen transmission path. However, the disconnection of the organic planarizing layer exposes part of the power line. Consequently, when etching some film layers in subsequent processes, the exposed power line will also be severely etched. For example, the depth of the exposed power line can exceed 0.55 microns. Severe etched power lines can cause cracks in the encapsulation layer in subsequent processes, leading to package failure.

[0028] To this end, the present application provides a display panel and an electronic device to solve the above problems.

[0029] An embodiment of the present application provides a display panel, comprising a display area and a frame area located on one side of the display area, wherein the frame area comprises an effective packaging area and a bending area located on a side of the effective packaging area away from the display area; the display panel further comprises:

[0030] substrate;

[0031] A first signal trace is provided on one side of the substrate, at least a portion of the first signal trace is located within the border area;

[0032] a first organic layer, disposed on a side of the first signal trace away from the substrate and extending from the display area to the frame area along a first direction, the first organic layer having a blocking groove in the effective encapsulation area, the blocking groove exposing at least a portion of a side surface of the first signal trace; and

[0033] The first signal wiring includes a first wiring portion arranged corresponding to the blocking groove, and a plurality of openings are provided on the first wiring portion.

[0034] In the display panel provided in an embodiment of the present application, the first signal line includes a first conductive layer, a second conductive layer and a third conductive layer that are stacked, the third conductive layer is located on a side of the first conductive layer away from the substrate, and the multiple openings penetrate at least the third conductive layer and the second conductive layer.

[0035] In the display panel provided in the embodiment of the present application, the plurality of openings are arranged at intervals in the extending direction of the blocking groove.

[0036] In the display panel provided in the embodiment of the present application, in the extension direction of the blocking groove, the width of the first wiring portion between two adjacent openings is greater than or equal to the width of the opening.

[0037] In the display panel provided in the embodiment of the present application, in the first direction, the length of the opening is smaller than the width of the blocking groove.

[0038] In the display panel provided in an embodiment of the present application, the first signal routing line further includes a second routing line portion connected to the first routing line portion, the second routing line portion is located on a side of the first routing line portion close to the display area, and the first organic layer covers the second routing line portion.

[0039] In the display panel provided by the embodiment of the present application, in the extension direction of the blocking groove, the width of the first wiring portion is greater than the width of the second wiring portion.

[0040] In the display panel provided in the embodiment of the present application, in the extension direction of the blocking groove, the cross-sectional area of ​​the first wiring portion is greater than or equal to the cross-sectional area of ​​the second wiring portion.

[0041] In the display panel provided in the embodiment of the present application, the display panel further includes a floating electrode located on one side of the first signal line, the floating electrode is spaced apart from the first signal line, and the floating electrode is arranged corresponding to the blocking groove.

[0042] In the display panel provided in the embodiment of the present application, the display panel further includes a second signal line located on one side of the first signal line, and the blocking groove further exposes a portion of the second signal line.

[0043] In the display panel provided in the embodiment of the present application, the display panel further includes a dam located in the effective encapsulation area. The dam is arranged on a side of the first organic layer away from the substrate and on a side of the blocking groove close to the display area.

[0044] In the display panel provided in an embodiment of the present application, the encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer stacked together, the organic encapsulation layer is located on the side of the dam close to the display area, and the first inorganic encapsulation layer and the second inorganic encapsulation layer cover the dam.

[0045] An embodiment of the present application further provides an electronic device, which includes a housing and a display panel assembled in the housing, wherein the display panel includes the display panel of one of the aforementioned embodiments.

[0046] The beneficial effects of the present application are as follows: in the display panel and electronic device provided by the present application, the display panel includes a display area and a frame area located on one side of the display area, the display panel also includes a substrate and a first signal line and a first organic layer arranged on one side of the substrate, at least part of the first signal line is located in the frame area; the first organic layer is arranged on the side of the first signal line away from the substrate, and extends from the display area to the frame area along a first direction, the first organic layer is provided with a blocking groove in the frame area, the blocking groove exposes at least part of the side of the first signal line; the first signal line includes a first line portion arranged corresponding to the blocking groove, and the first line portion is provided with multiple openings; the present application increases the exposed side area of ​​the first line portion by providing multiple openings on the first line portion, thereby reducing the side engraving depth of the first line portion, thereby alleviating the serious side engraving problem of metal signal lines in existing display panels.

[0047] The various embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0048] Please refer to Figures 1 to 5. Figure 1 is a schematic diagram of a top view of the display panel provided in an embodiment of the present application; Figure 2 is a schematic diagram of the cross-sectional structure along the N-N' direction in Figure 1; Figure 3 is a schematic diagram of the display panel in Figure 1 after removing the first organic layer; Figure 4 is a schematic diagram of the detailed structure of the first signal line in Figure 3; and Figure 5 is a schematic diagram of the cross-sectional structure along the P-P' direction in Figure 4. Referring to Figures 1 and 2, the display panel 100 includes a display area AA and a border area BA located on one side of the display area AA. The display area AA is used to display an image, and the border area BA is used to set various signal lines to transmit external drive signals to the display panel 100. The border area BA includes an effective packaging area FA and a bending area PA located on a side of the effective packaging area FA away from the display area AA.

[0049] 1 , the display panel 100 further includes a substrate 10 and a first signal line 20 and a first organic layer 30 arranged on one side of the substrate 10. At least part of the first signal line 20 is located in the border area BA, that is, the first signal line 20 can be partially located in the border area BA, or entirely located in the border area BA. When the first signal line 20 is entirely located in the border area BA, the first signal line 20 can be connected to the signal line in the display area AA through a switching line of other layers. This embodiment takes the example of part of the first signal line 20 being located in the border area BA. When part of the first signal line 20 is located in the border area BA, another part of the first signal line 20 is located in the display area AA, that is, the first signal line 20 extends from the display area AA to the border area BA.

[0050] The first organic layer 30 is disposed on a side of the first signal trace 20 away from the substrate 10 and extends along a first direction X from the display area AA to the border area BA. For ease of description, this application defines the extension direction of the first organic layer 30 as the first direction X. That is, the first direction X is the direction from the display area AA to the border area BA, and the first direction X is parallel to the plane of the substrate 10. Both the first signal trace 20 and the first organic layer 30 extend along the first direction X.

[0051] The first organic layer 30 is provided with a blocking groove 301 in the effective encapsulation area FA within the border area BA. The blocking groove 301 extends along a second direction Y. The blocking groove 301 divides the border area BA into two sub-areas along the extension direction of the blocking groove 301: one sub-area close to the display area AA, and the other sub-area away from the display area AA. The second direction Y is different from the first direction X. For example, the second direction Y may be perpendicular to the first direction X and parallel to the plane of the substrate 10.

[0052] The barrier groove 301 penetrates the first organic layer 30, dividing the first organic layer 30 in the border area BA into two parts. One part of the first organic layer 30 is close to the display area AA, and the other part of the first organic layer 30 is far away from the display area AA. The first organic layer 30 close to the display area AA is separated from the first organic layer 30 far away from the display area AA, thereby cutting off the water and oxygen transmission path in the first organic layer 30, preventing external water and oxygen from entering the display area AA through the first organic layer 30.

[0053] The blocking groove 301 exposes at least a portion of the side surface of the first signal trace 20. Specifically, the first signal trace 20 includes a first trace portion 21 corresponding to the blocking groove 301, and the blocking groove 301 exposes the first trace portion 21. The length of the first trace portion 21 in the first direction X is equal to the width of the blocking groove 301 in the first direction X. The first trace portion 21 is provided with a plurality of openings 210, which are arranged at intervals.

[0054] The first signal trace 20 also includes a second trace portion 22 connected to the first trace portion 21. The second trace portion 22 is located on a side of the first trace portion 21 closer to the display area AA. The first trace portion 21 and the second trace portion 22 are integrally formed, that is, they are integrally formed using the same lithography process. The first organic layer 30 covers the second trace portion 22, while exposing the first trace portion 21.

[0055] Optionally, the first signal trace 20 may further include a third trace portion 23 located on a side of the first trace portion 21 away from the second trace portion 22. The third trace portion 23 is also connected to the first trace portion 21. The third trace portion 23 is also covered by the first organic layer 30. That is, the first organic layer 30 near the display area AA covers the second trace portion 22, and the first organic layer 30 away from the display area AA covers the third trace portion 23.

[0056] It should be noted that since the second wiring portion 22 and the third wiring portion 23 are covered by the first organic layer 30, they are obscured by the first organic layer 30 when viewed from above. Therefore, the second wiring portion 22 and the third wiring portion 23 covered by the first organic layer 30 are indicated by dashed lines in the drawings of this application, as shown in FIG1 . Furthermore, to clearly illustrate the relationship between the first organic layer 30 and the first signal wiring 20, the structures above the first organic layer 30 and the first wiring portion 21 are not depicted in the drawings. The fact that the blocking groove 301 in the first organic layer 30 exposes the first wiring portion 21 indicates that the first organic layer 30 is not covering the first wiring portion 21, but this does not prevent other structures from being disposed on the first wiring portion 21. Furthermore, FIG1 schematically illustrates two first signal wirings 20, spaced apart in the second direction Y. However, this application is not limited to this, and the display panel 100 of this application may include more first signal wirings 20.

[0057] Furthermore, the display panel 100 further includes a second signal line 40 located on one side of the first signal line 20. Optionally, the second signal line 40 is located between two adjacent first signal lines 20 and is spaced apart from the adjacent first signal lines 20. The first signal line 20 and the second signal line 40 are both power lines that transmit voltage signals, and the voltage transmitted by the first signal line 20 is lower than the voltage transmitted by the second signal line 40. For example, the first signal line 20 is a VSS signal line, and the second signal line 40 is a VDD signal line.

[0058] The second signal trace 40 is disposed on the same layer as the first signal trace 20 and also extends along the first direction X. That is, the second signal trace 40 also extends from the display area AA to the border area BA. The first organic layer 30 covers a portion of the second signal trace 40, and the blocking groove 301 exposes another portion of the second signal trace 40.

[0059] In this embodiment, multiple openings 210 are provided in the first wiring portion 21. These openings 210 expose multiple side surfaces of the first wiring portion 21, thereby increasing the exposed side surfaces of the first wiring portion 21 and thereby increasing the area of ​​the exposed side surfaces of the first wiring portion 21. This, in turn, reduces the depth of the side engraving of each exposed side surface of the first wiring portion 21. For example, the side engraving depth of each exposed side surface of the first wiring portion 21 can be reduced to less than 0.1 microns. This alleviates the severe side engraving problem of metal signal wiring in the existing display panel 100. Furthermore, the second signal wiring 40 is located on one side of the first signal wiring 20. Within the unit area formed by the adjacent second signal wiring 40 and the first signal wiring 20, the area of ​​the exposed side surfaces of the first wiring portion 21 is increased, which is equivalent to increasing the total area of ​​the exposed side surfaces of the second signal wiring 40 and the first signal wiring 20 within the unit area. The total side surface area refers to the sum of the area of ​​the exposed side surfaces of the first signal wiring 20 and the area of ​​the exposed side surfaces of the second signal wiring 40 and the first signal wiring 20. Therefore, by providing a plurality of openings 210 on the first wiring portion 21 , not only the side engraving depth of each exposed side surface of the first wiring portion 21 can be reduced, but also the side engraving depth of each exposed side surface of the second signal wiring 40 can be reduced.

[0060] The specific positions of the first signal wiring 20 and the first organic layer 30 on the display panel 100 will be described in detail below.

[0061] 2 , the display panel 100 further includes a thin-film transistor 50 disposed on the substrate 10 and a light-emitting device 60 located on a side of the thin-film transistor 50 away from the substrate 10. Optionally, the substrate 10 may be a rigid substrate or a flexible substrate. When the substrate 10 is a rigid substrate, it may include a rigid substrate such as a glass substrate; when the substrate 10 is a flexible substrate, it may include a flexible substrate such as a polyimide (PI) film or an ultra-thin glass film. Using a flexible substrate as the substrate 10 allows for the manufacture of a flexible display panel 100, enabling special features such as bending and curling of the display panel 100.

[0062] In the embodiment of the present application, the substrate 10 is a flexible substrate. The substrate 10 may include flexible films and inorganic films alternately stacked. For example, the substrate 10 may include a first polyimide film, a first inorganic film, and a second polyimide film stacked together. This ensures the substrate 10 is flexible while also enhancing its water and oxygen barrier properties.

[0063] Optionally, a buffer layer 11 may be disposed between the substrate 10 and the thin film transistor 50. The buffer layer 11 covers the substrate 10 and extends from the display area AA to the border area BA. The buffer layer 11 may be made of inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). The buffer layer 11 can further prevent unwanted impurities or contaminants (such as moisture and oxygen) from diffusing from the substrate 10 into devices that may be damaged by these impurities or contaminants, while also providing a flat top surface.

[0064] The thin film transistor 50 is disposed on the buffer layer 11 and is located in the display area AA. The thin film transistor 50 includes a semiconductor layer 51, a first gate electrode 52, a second gate electrode 53, a first source electrode 54, and a first drain electrode 55. The light-emitting device 60 is electrically connected to the thin film transistor 50 and is located in the display area AA. The light-emitting device 60 includes a first electrode 61, a second electrode 62, and a light-emitting layer 63 sandwiched between the first electrode 61 and the second electrode 62. Specifically, the first electrode 61 is electrically connected to the first source electrode 54 or the first drain electrode 55. This embodiment uses the electrical connection between the first electrode 61 and the first drain electrode 55 as an example.

[0065] Optionally, the first electrode 61 can be electrically connected to the first drain 55 through multiple transition electrodes. For example, the display panel 100 also includes a first transition electrode 56 and a second transition electrode 57. The second transition electrode 57 is electrically connected to the first drain 55 through the first transition electrode 56, and the first electrode 61 is electrically connected to the first transition electrode 56 through the second transition electrode 57, thereby electrically connecting the first electrode 61 to the first drain 55.

[0066] Of course, the display panel 100 also includes an inorganic insulating layer located between the layers of the thin film transistor 50 and an organic insulating layer located between the light-emitting device 60 and the thin film transistor 50. The inorganic insulating layer includes a first gate insulating layer 12, a second gate insulating layer 13, and an interlayer insulating layer 14 stacked on the buffer layer 11. The organic insulating layer includes a first planarization layer 15, a second planarization layer 16, a pixel definition layer 17, and a support layer 18 stacked in sequence. The first organic layer 30 may be located between the first planarization layer 15 and the second planarization layer 16.

[0067] The inorganic insulating layer is made of inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). The organic insulating layer is made of organic materials. Part of the inorganic insulating layer extends from the display area AA into the border area BA, and part of the organic insulating layer also extends from the display area AA into the border area BA. However, the organic insulating layer needs to be disconnected in the border area BA to cut off the water and oxygen transmission path and prevent external water and oxygen from entering the display area AA through the organic insulating layer. This is an example of the barrier groove 301 in the first organic layer 30.

[0068] Specifically, the semiconductor layer 51 is disposed on the buffer layer 11. The semiconductor layer 51 includes a channel region 511 and a source region 512 and a drain region 513 located on either side of the channel region 511. The first gate insulating layer 12 covers the semiconductor layer 51 and the buffer layer 11. The first gate 52 is disposed on the first gate insulating layer 12, corresponding to the channel region 511 of the semiconductor layer 51. The second gate insulating layer 13 covers the first gate 52 and the first gate insulating layer 12. The second gate 53 is disposed on the second gate insulating layer 13, corresponding to the first gate 52. The interlayer insulating layer 14 covers the second gate 53 and the second gate insulating layer 13. The first source electrode 54 and the first drain electrode 55 are disposed on the interlayer insulating layer 14. The first source electrode 54 is electrically connected to the source region 512 of the semiconductor layer 51, and the first drain electrode 55 is electrically connected to the drain region 513 of the semiconductor layer 51.

[0069] It should be noted that, in the display area AA, the display panel 100 further includes a variety of signal lines, such as data lines, gate scan lines, and other signal lines. Furthermore, the structure of the thin film transistor 50 of the present application is not limited to that shown in this embodiment. The thin film transistor 50 of the present application may also adopt a single-gate, single-source-drain, or bottom-gate structure.

[0070] The first planarization layer 15 overlies the interlayer insulating layer 14. The first transfer electrode 56 is disposed on the first planarization layer 15 and is electrically connected to the first drain electrode 55. The first signal trace 20 and the first transfer electrode 56 are disposed on the same layer, and the first signal trace 20 and the second signal trace 40 are also disposed on the same layer. The second signal trace 40 and the first transfer electrode 56 are also disposed on the same layer. The first organic layer 30 overlies the first transfer electrode 56, the first signal trace 20, the second signal trace 40, and the first planarization layer 15. The second transfer electrode 57 is disposed on the first organic layer 30 and is electrically connected to the first transfer electrode 56. The third planarization layer 42 overlies the second transfer electrode 57 and the first organic layer 30.

[0071] It should be noted that the term "same-layer arrangement" in this application refers to the situation where, during the manufacturing process, a film layer formed of the same material is patterned to obtain at least two different structures, and the at least two different structures are arranged in the same layer. For example, in this embodiment, the first signal trace 20 and the first transfer electrode 56 are obtained by patterning the same conductive film layer, and the first signal trace 20 and the first transfer electrode 56 are arranged in the same layer. In addition, the first signal trace 20 in this application is not limited to being arranged in the same layer as the first transfer electrode 56. For example, the first signal trace 20 in this application can also be arranged in the same layer as a metal layer such as the second transfer electrode 57 or the first drain electrode 55. Accordingly, the first organic layer 30 can also be adjusted accordingly.

[0072] The first electrode 61 is arranged on the second planarization layer 16, the pixel definition layer 17 covers the first electrode 61 and the second planarization layer 16, and the pixel definition layer 17 is provided with a pixel opening 210 at a position corresponding to the first electrode 61, the light-emitting layer 63 is arranged on the first electrode 61 within the pixel opening 210, and the second electrode 62 is arranged on the light-emitting layer 63. Optionally, the first electrode 61 is an anode and the second electrode 62 is a cathode, but the present application is not limited to this. The second electrode 62 is arranged on the entire surface, that is, the second electrode 62 is not only arranged in the display area AA, but also extends from the display area AA to the border area BA. In the border area BA, the first organic layer 30 is located between the second electrode 62 and the first signal trace 20 and the second signal trace 40, thereby avoiding a short circuit between the second electrode 62 and the second signal trace 40.

[0073] The light-emitting layer 63 emits light under the action of the first electrode 61 and the second electrode 62. The light-emitting layer 63 can be formed by vacuum evaporating light-emitting materials of different colors within the pixel opening 210. The different colored light-emitting materials emit light of different colors under the action of the first electrode 61 and the second electrode 62, thereby achieving color display of the display panel 100. A fine mask is required when evaporating the light-emitting material. The support layer 18 is used to support the fine mask to prevent the fine mask from contacting the display panel 100 and damaging the structures on the display panel 100.

[0074] In order to protect the light-emitting device 60 and prevent the light-emitting device 60 from failing due to the intrusion of water and oxygen, the display panel 100 further includes an encapsulation layer (not shown in the figure), which covers the light-emitting device 60 and extends from the display area AA to the border area BA. Specifically, the encapsulation layer is arranged on the side of the first organic layer 30 away from the substrate 10, and extends from the display area AA to the border area BA along the first direction X, and the encapsulation layer is also located in the blocking groove 301. The encapsulation layer can be encapsulated by a thin film. For example, the encapsulation layer can be a laminated structure formed by stacking three thin films, a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer, in sequence, or a laminated structure of more layers. The material of the organic encapsulation layer includes one or more organic materials such as epoxy and acrylic. The organic encapsulation layer can be coated on the first inorganic encapsulation layer by one of the coating processes such as ink jet printing (IJP) and spraying.

[0075] When the organic encapsulation layer is printed using an inkjet printing process, the printed ink is fluid. Therefore, the display panel 100 further includes a dam 70 disposed in the active encapsulation area FA. The dam 70 is disposed on the side of the first organic layer 30 away from the substrate 10 and on the side of the blocking groove 301 closer to the display area AA. The organic encapsulation layer is located on the side of the dam 70 closer to the display area AA, and the first and second inorganic encapsulation layers cover the dam 70. The dam 70 is used to prevent overflow of the printed ink. Optionally, the dam 70 is formed on the first organic layer 30 and is formed by stacking the second planarization layer 16 and the support layer 18.

[0076] The dam 70 extends in the same direction as the barrier trench 301, blocking the organic encapsulation layer. This allows the first and second inorganic encapsulation layers within the encapsulation layer to overlie the dam 70 and extend into the barrier trench 301, covering the walls of the first organic layer 30 forming the barrier trench 301, as well as the first and second signal traces 20 and 40 within the barrier trench 301. This cuts off the water and oxygen transmission path and prevents external water and oxygen from entering the display area AA through the first organic layer 30. Furthermore, within the barrier trench 301, a plurality of openings 210 are provided on the first signal trace 20. This reduces the depth of the undercut on each exposed side surface of the first trace portion 21 and the second signal trace 40, thereby preventing the first and second inorganic encapsulation layers covering the first and second signal traces 20 and 40 from cracking and causing encapsulation failure.

[0077] The specific structure of the first signal trace 20 is described in detail below.

[0078] 3 and 4 , adjacent first signal traces 20 are spaced apart, and the second signal trace 40 is located within the space between adjacent first signal traces 20. The first signal trace 20 includes a first trace portion 21, a second trace portion 22 located at one end of the first trace portion 21, and a third trace portion 23 located at the other end of the first trace portion 21. In the extending direction of the blocking groove 301, i.e., in the second direction Y, the width D2 of the first trace portion 21 is greater than the width D1 of the second trace portion 22. The width D1 of the second trace portion 22 may be equal to the width of the third trace portion 23.

[0079] The first routing portion 21 is provided with a plurality of openings 210 . The plurality of openings 210 are arranged at intervals in the extension direction of the blocking groove 301 , that is, the plurality of openings 210 are arranged at intervals in the second direction Y. In the extension direction of the blocking groove 301 , that is, in the second direction Y, the width D3 of the first routing portion 21 between two adjacent openings 210 is greater than or equal to the width D4 of the openings 210 . This allows more openings 210 to be provided on the limited first routing portion 21 , further increasing the total area of ​​the exposed side surfaces of the first signal routing 20 and the second signal routing 40 , thereby further reducing the side engraving depth of each exposed side surface of the first signal routing 20 and the second signal routing 40 .

[0080] In the first direction X, the length L1 of the opening 210 is smaller than the width of the blocking groove 301, and the width of the blocking groove 301 is equal to the length L2 of the first routing portion 21, so that the length L1 of the opening 210 is smaller than the length L2 of the first routing portion 21, so that the first routing portions 21 between adjacent openings 210 can be connected together to ensure the cross-sectional area of ​​the first routing portion 21.

[0081] In the extending direction of the blocking groove 301, that is, in the second direction Y, the cross-sectional area of ​​the first wiring portion 21 is greater than or equal to the cross-sectional area of ​​the second wiring portion 22, so as to provide a second wiring portion 22 with a larger area, thereby allowing more openings 210 to be provided on the second wiring portion 22. The cross-sectional area of ​​the first wiring portion 21 refers to the area of ​​a cross section taken on the openings 210 along the arrangement direction of the openings 210, that is, the cross section passes through each of the openings 210.

[0082] Optionally, the multiple openings 210 are of the same size, that is, the length L1 and width of each opening 210 are the same. However, the present application is not limited thereto, and the multiple openings 210 of the present application may also be of different sizes. For example, the length L1 of the opening 210 located near the second routing portion 22 is greater than the length L1 of the opening 210 located away from the second routing portion 22. In this way, the area of ​​the exposed side surface of the first signal routing portion 20 can be further increased without affecting the connection of the first routing portions 21 between adjacent openings 210. The opening 210 near the second routing portion 22 refers to the opening 210 that overlaps with the second routing portion 22 in the extension direction of the first signal routing portion 20.

[0083] Optionally, the shapes of the multiple openings 210 may be the same or different. In the drawings of this embodiment, each opening 210 is illustrated as a rectangle, but the present application is not limited to this. The shape of the opening 210 of the present application may also be other irregular long strips. For example, the surface shape of the opening 210 may also be an S-shape, a broken line shape, a wavy line shape, or other non-linear shapes to increase the area of ​​the side of the first routing portion 21 exposed by the opening 210.

[0084] 5 , the first signal trace 20 includes a stacked first conductive layer 211, a second conductive layer 212, and a third conductive layer 213. The third conductive layer 213 is located on a side of the first conductive layer 211 away from the substrate 10. Optionally, the material of the first conductive layer 211 and the third conductive layer 213 is the same, the material of the second conductive layer 212 is different from the material of the first conductive layer 211, and the etching rate of the second conductive layer 212 is greater than the etching rate of the first conductive layer 211. For example, the material of the first conductive layer 211 and the third conductive layer 213 are both titanium or molybdenum, while the material of the second conductive layer 212 is aluminum. The material and stacked structure of the second signal trace 40 are the same as those of the first signal trace 20.

[0085] The plurality of openings 210 penetrate at least the third conductive layer 213 and the second conductive layer 212 to expose the side surfaces of the second conductive layer 212. By not penetrating the first conductive layer 211, the first conductive layer 211 can be retained, thereby improving the stability of the connection between the first wiring portions 21 between adjacent openings 210. This allows for more openings 210 and / or longer openings 210 to be provided on the first wiring portion 21. Of course, the present application is not limited thereto; the openings 210 of the present application can also penetrate the first conductive layer 211, so that the openings 210 extend through the entire first wiring portion 21.

[0086] In one embodiment, referring to Figures 1 to 6 , Figure 6 is a schematic top view of another display panel structure according to an embodiment of the present application. Unlike the above embodiment, the display panel 101 further includes a floating electrode 80 located on one side of the first signal trace 20 . The floating electrode 80 is spaced apart from the first signal trace 20 and is disposed corresponding to the blocking groove 301 .

[0087] 6 , the floating electrode 80 is located between the first signal trace 20 and the second signal trace 40. There may be multiple floating electrodes 80, and the specific number of floating electrodes 80 is determined by the spacing between the first signal trace 20 and the second signal trace 40. Along the extension of the first organic layer 30, that is, in the first direction X, the length of the floating electrode 80 is greater than or equal to the length L1 of the first opening 210. For example, the length of the floating electrode 80 may be equal to the length L2 of the first trace portion 21, thereby increasing the exposed side surface area of ​​the floating electrode 80.

[0088] Optionally, the surface shape of the floating electrode 80 may be a non-linear electrode such as an S-shape, a zigzag shape, or a wavy shape, so as to further increase the area of ​​the exposed side surface of the floating electrode 80 .

[0089] In this embodiment, by disposing the floating electrode 80 on one side of the first signal trace 20, the total area of ​​the exposed side surfaces of the first signal trace 20 and the second signal trace 40 can be further increased, thereby further reducing the side engraving depth of each exposed side surface of the first signal trace 20 and the second signal trace 40. Furthermore, the floating electrode 80, located between the first signal trace 20 and the second signal trace 40, can also serve as a shielding line to prevent signal interference between the first signal trace 20 and the second signal trace 40. Furthermore, the floating electrode 80 is located within the border area BA and does not participate in the display function of the display panel 101. For other explanations, please refer to the above embodiment and will not be repeated here.

[0090] In one embodiment, please refer to Figures 1 to 7. Figure 7 is another schematic diagram of a top view of the display panel provided in an embodiment of the present application. Unlike the above embodiment, in the display panel 102 of this embodiment, the floating electrodes 80 are located on opposite sides of the first signal trace 20. A portion of the floating electrodes 80 is located between the first signal trace 20 and the second signal trace 40, and another portion of the floating electrodes 80 is located on the side of the first signal trace 20 away from the second signal trace 40. By providing more floating electrodes 80, the total area of ​​the exposed side surfaces of the first signal trace 20 and the second signal trace 40 can be further increased, thereby further reducing the side engraving depth of each exposed side surface of the first signal trace 20 and the second signal trace 40. For other explanations, please refer to the above embodiment and will not be repeated here.

[0091] Based on the same inventive concept, an embodiment of the present application also provides an electronic device, please refer to Figure 8, which is a schematic diagram of a cross-sectional structure of the electronic device provided in an embodiment of the present application. The electronic device 1000 includes a housing 200 and a display panel of one of the aforementioned embodiments. This embodiment takes the display panel 100 as an example. The housing 200 is formed with a receiving cavity 201, and the display panel 100 is assembled in the receiving cavity 201. The electronic device 1000 can be a wearable device, such as a smart bracelet, a smart watch or a virtual reality (VR) device, or a mobile phone, an e-book, an e-newspaper, a television or a personal portable computer, or a bendable and foldable flexible OLED display or lighting device. The embodiment of the present application does not specifically limit the specific form of the electronic device.

[0092] According to the above embodiments, it can be seen that:

[0093] The present application provides a display panel, which includes a display area and a frame area located on one side of the display area. The display panel also includes a substrate and a first signal line and a first organic layer arranged on one side of the substrate, at least part of the first signal line is located in the frame area; the first organic layer is arranged on a side of the first signal line away from the substrate and extends from the display area to the frame area along a first direction, the first organic layer is provided with a blocking groove in the frame area, the blocking groove exposes at least part of the side of the first signal line; the first signal line includes a first line portion arranged corresponding to the blocking groove, and the first line portion is provided with multiple openings; the present application provides multiple openings on the first line portion to increase the exposed side area of ​​the first line portion, thereby reducing the side engraving depth of the first line portion, thereby alleviating the serious side engraving problem of metal signal lines in existing display panels.

[0094] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0095] The above is a detailed introduction to the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, comprising a display area and a frame area located on one side of the display area, wherein the frame area comprises an effective encapsulation area and a bending area located on a side of the effective encapsulation area away from the display area; the display panel further comprises: substrate; A first signal wiring is arranged on one side of the substrate, and at least a portion of the first signal wiring is located in the border area; A first organic layer is provided on a side of the first signal wiring away from the substrate and extends from the display area to the frame area along a first direction, wherein the first organic layer is provided with a blocking groove in the effective encapsulation area, and the blocking groove exposes at least a part of the side surface of the first signal wiring; as well as An encapsulation layer is disposed on a side of the first organic layer away from the substrate and extends from the display area to the frame area along a first direction, and the encapsulation layer is also located in the blocking groove; The first signal wiring includes a first wiring portion arranged corresponding to the blocking groove, and a plurality of openings are arranged on the first wiring portion.

2. The display panel according to claim 1, wherein: The first signal trace includes a first conductive layer, a second conductive layer and a third conductive layer which are stacked, the third conductive layer is located on a side of the first conductive layer away from the substrate, and the plurality of openings at least penetrate the third conductive layer and the second conductive layer.

3. The display panel according to claim 1, wherein: The plurality of openings are arranged at intervals in the extending direction of the blocking groove.

4. The display panel according to claim 3, wherein: In the extending direction of the blocking groove, the width of the first routing portion between two adjacent openings is greater than or equal to the width of the opening.

5. The display panel according to claim 3, wherein: In the first direction, the length of the opening is smaller than the width of the blocking groove.

6. The display panel according to claim 1, wherein: The first signal wiring further includes a second wiring portion connected to the first wiring portion, the second wiring portion is located at a side of the first wiring portion close to the display area, and the first organic layer covers the second wiring portion.

7. The display panel according to claim 6, wherein: In the extending direction of the blocking groove, the width of the first routing portion is greater than the width of the second routing portion.

8. The display panel according to claim 6, wherein: In the extending direction of the blocking groove, the cross-sectional area of ​​the first routing portion is greater than or equal to the cross-sectional area of ​​the second routing portion.

9. The display panel according to claim 1, wherein: The display panel further includes a floating electrode located at one side of the first signal wiring. The floating electrode is spaced apart from the first signal wiring and is disposed corresponding to the blocking groove.

10. The display panel according to claim 1, wherein: in, The display panel further includes a second signal line located on one side of the first signal line, and the blocking groove further exposes a portion of the second signal line.

11. The display panel according to claim 1, wherein: The display panel further includes a dam located in the effective encapsulation area. The dam is disposed on a side of the first organic layer away from the substrate and is located on a side of the blocking groove close to the display area.

12. The display panel according to claim 11, wherein: The encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer which are stacked. The organic encapsulation layer is located on a side of the dam close to the display area. The first inorganic encapsulation layer and the second inorganic encapsulation layer cover the dam.

13. An electronic device, comprising a housing and a display panel mounted in the housing, the display panel comprising a display area and a frame area located on one side of the display area, the frame area comprising an effective packaging area and a bending area located on a side of the effective packaging area away from the display area; the display panel further comprising: substrate; A first signal wiring is arranged on one side of the substrate, and at least a portion of the first signal wiring is located in the border area; A first organic layer is provided on a side of the first signal wiring away from the substrate and extends from the display area to the frame area along a first direction, wherein the first organic layer is provided with a blocking groove in the effective encapsulation area, and the blocking groove exposes at least a part of the side surface of the first signal wiring; as well as An encapsulation layer is disposed on a side of the first organic layer away from the substrate and extends from the display area to the frame area along a first direction, and the encapsulation layer is also located in the blocking groove; The first signal wiring includes a first wiring portion arranged corresponding to the blocking groove, and a plurality of openings are arranged on the first wiring portion.

14. The electronic device according to claim 13, wherein: The first signal trace includes a first conductive layer, a second conductive layer and a third conductive layer which are stacked, the third conductive layer is located on a side of the first conductive layer away from the substrate, and the plurality of openings at least penetrate the third conductive layer and the second conductive layer.

15. The electronic device according to claim 13, wherein: The plurality of openings are arranged at intervals in the extending direction of the blocking groove.

16. The electronic device according to claim 15, wherein: In the extending direction of the blocking groove, the width of the first routing portion between two adjacent openings is greater than or equal to the width of the opening.

17. The electronic device according to claim 16, wherein: In the first direction, the length of the opening is smaller than the width of the blocking groove.

18. The electronic device according to claim 13, wherein: The first signal wiring further includes a second wiring portion connected to the first wiring portion, the second wiring portion is located at a side of the first wiring portion close to the display area, and the first organic layer covers the second wiring portion.

19. The electronic device according to claim 13, wherein: The display panel further includes a floating electrode located at one side of the first signal wiring. The floating electrode is spaced apart from the first signal wiring and is disposed corresponding to the blocking groove.

20. The electronic device according to claim 13, wherein: The display panel further includes a second signal line located on one side of the first signal line, and the blocking groove further exposes a portion of the second signal line.

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