Static random access memory array, memory, and electronic device

Abstract

The present application provides a static random access memory (SRAM) array and a preparation method therefor, a memory, and an electronic device. The present application relates to the technical field of memories. The purpose is to improve the storage density. The SRAM array comprises a semiconductor substrate, a front-end-of-line device layer formed in the semiconductor substrate, and a back-end-of-line device layer stacked on the front-end-of-line device layer; the SRAM array further comprises a plurality of memory cells, and each memory cell comprises at least one P-type field effect transistor and at least one N-type field effect transistor which are electrically connected, for example, the memory cell can be a 6T memory cell or an 8T memory cell; at least one P-type field effect transistor is formed in the front-end-of-line device layer; and at least one N-type field effect transistor is formed in the back-end-of-line device layer. According to the present application, by three-dimensionally stacking P-type field effect transistors and N-type field effect transistors, the storage density is improved.

Description

Static random access memory array, memory and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on September 13, 2023, with application number 202311183082.3 and invention name “Static Random Access Memory Array, Memory and Electronic Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of memory technology, and in particular to a static random access memory array, and a memory and electronic device including the static random access memory. Background Art

[0003] Static random-access memory (SRAM) is a type of random-access memory. Static means that the stored data remains permanently as long as the power is on. This type of memory is widely used in computer devices due to its high speed.

[0004] In the SRAM process, for example, a memory cell includes six transistors, all of which are fabricated in a silicon substrate using a front-end process. Because the conduction performance requirements for the six transistors are inconsistent—for example, the pull-down transistor has the highest conduction performance requirement, the access transistor has the second highest, and the pull-up transistor has the weakest—transistor size is a key factor affecting conduction performance. If the storage density is increased by reducing the size of these transistors, the conduction performance of the transistors and the storage performance of the memory will be affected.

[0005] Therefore, the size of transistors is strictly limited, preventing them from being further reduced as the process nodes are scaled down, and the storage density of SRAM is limited.

[0006] Summary of the Invention

[0007] The present application provides a static random access memory array, a method for preparing the static random access memory array, a memory, and an electronic device. The purpose is to provide a static random access memory array capable of improving storage density.

[0008] To achieve the above objectives, this application adopts the following technical solutions:

[0009] On the one hand, the present application provides an SRAM memory array, which includes a semiconductor substrate, a front-end device layer and a back-end device layer, the front-end device layer is arranged in the semiconductor substrate, and the back-end device layer is arranged above the front-end device layer; the SRAM memory array also includes a plurality of memory cells, each memory cell includes at least one P-type field-effect transistor and at least one N-type field-effect transistor electrically connected, for example, it can be a 3T memory cell, a 6T memory cell or an 8T memory cell; at least one P-type field-effect transistor is formed in the front-end device layer; at least one N-type field-effect transistor is formed in the back-end device layer.

[0010] The memory cells of the SRAM memory array provided in this application include P-type field effect transistors and N-type field effect transistors. The P-type field effect transistors are manufactured in the front-end device layer using a front-end process, while the N-type field effect transistors are manufactured in the back-end device layer using a back-end process. Instead of using the front-end process to manufacture all P-type field effect transistors and N-type field effect transistors in the prior art, in this application, multiple field effect transistors in a memory cell are formed in a three-dimensional stacking manner, which can improve storage density and storage capacity.

[0011] The N-type field-effect transistor in the memory cell can be used as a pull-down transistor with higher conductivity requirements and manufactured through the back-end process, while the P-type field-effect transistor can be used as a pull-up transistor with lower conductivity requirements and manufactured through the front-end process. Compared with existing methods that use only front-end processes, using the same process node not only ensures high conductivity of the pull-down transistor, but also allows more memory cells to be integrated per unit area, improving storage density.

[0012] In one implementation, an orthographic projection of the N-type field effect transistor on the semiconductor substrate at least partially overlaps with an orthographic projection of the P-type field effect transistor on the semiconductor substrate.

[0013] Using this process structure, the vertical projection area of ​​a memory cell can be reduced to 2 / N of the existing structure (all transistors of a memory cell are manufactured using the front-end process), which can significantly improve storage density.

[0014] In one implementation, the at least one N-type field effect transistor includes a first N-type field effect transistor and a second N-type field effect transistor, and the first N-type field effect transistor and the second N-type field effect transistor are located in the same back-end device layer.

[0015] The P-type field effect transistors are arranged in the same back-end device layer, and the N-type field effect transistors are arranged in the front-end device layer, which can simplify the preparation process of each device layer.

[0016] In one achievable embodiment, a first N-type field effect transistor and a second N-type field effect transistor are located in a first back-end device layer; a first interconnect routing layer is formed between the front-end device layer and the first back-end device layer; a second interconnect routing layer is formed on a side of the first back-end device layer away from the first interconnect routing layer; at least one P-type field effect transistor includes a first P-type field effect transistor and a second P-type field effect transistor; the first P-type field effect transistor is electrically connected to the second P-type field effect transistor through the first interconnect routing layer; and the first N-type field effect transistor is electrically connected to the second N-type field effect transistor through the second interconnect routing layer.

[0017] A first interconnect routing layer is used to electrically connect a first P-type field effect transistor and a second P-type field effect transistor located in a front-end device layer, and a second interconnect routing layer is used to electrically connect a first N-type field effect transistor and a second N-type field effect transistor located in the same back-end device layer.

[0018] In one achievable manner, the orthographic projection of the first N-type field-effect transistor on the semiconductor substrate at least partially overlaps with the orthographic projection of the first P-type field-effect transistor on the semiconductor substrate; the orthographic projection of the second N-type field-effect transistor on the semiconductor substrate at least partially overlaps with the orthographic projection of the second P-type field-effect transistor on the semiconductor substrate.

[0019] That is, the first N-type field-effect transistor can be located above the vertical projection of the first P-type field-effect transistor, and the second N-type field-effect transistor can be located above the vertical projection of the second P-type field-effect transistor. This can compress the projection area of ​​these transistors on the semiconductor substrate and improve storage density.

[0020] In one achievable manner, the gate of the first P-type field effect transistor is electrically connected to the first electrode of the second P-type field effect transistor through the first interconnect routing layer; the gate of the second P-type field effect transistor is electrically connected to the first electrode of the first P-type field effect transistor through the first interconnect routing layer; the second electrode of the first P-type field effect transistor is electrically connected to the second electrode of the second P-type field effect transistor through the first interconnect routing layer; the gate of the first N-type field effect transistor is electrically connected to the first electrode of the second N-type field effect transistor through the second interconnect routing layer; the gate of the second N-type field effect transistor is electrically connected to the first electrode of the first N-type field effect transistor through the second interconnect routing layer; the second electrode of the first N-type field effect transistor is electrically connected to the second electrode of the second N-type field effect transistor through the second interconnect routing layer; the first electrode is one of the source or the drain, and the second electrode is the other of the source or the drain.

[0021] The above examples illustrate the electrical connection relationships that can be achieved by four field-effect transistors in a 6T memory cell or an 8T memory cell.

[0022] In one achievable manner, the first electrode of the first P-type field effect transistor is electrically connected to the first electrode of the first N-type field effect transistor; the first electrode of the second P-type field effect transistor is electrically connected to the first electrode of the second N-type field effect transistor.

[0023] In some process structures, the first electrode of the first P-type field effect transistor can be interconnected with the first electrode of the first N-type field effect transistor, and the first electrode of the second P-type field effect transistor can be interconnected with the first electrode of the second N-type field effect transistor through a conductive through hole penetrating the dielectric layer.

[0024] In one achievable manner, the at least one N-type field effect transistor further includes: a third N-type field effect transistor and a fourth N-type field effect transistor; the third N-type field effect transistor and the fourth N-type field effect transistor are located in a second back-end device layer of the same back-end device layer; and the second interconnect routing layer is located between the first back-end device layer and the second back-end device layer.

[0025] This can form a 6T memory cell or an 8T memory cell. In this example, two of the six field-effect transistors (P-type field-effect transistors) are located in the front-end device layer, and the other four N-type field-effect transistors are distributed in two back-end device layers, with two N-type field-effect transistors in each back-end device layer.

[0026] For example, the channel materials of the third N-type field effect transistor and the fourth N-type field effect transistor can both be made of oxide semiconductor materials.

[0027] In one achievable manner, the orthographic projection of the third N-type field effect transistor on the semiconductor substrate at least partially overlaps with the orthographic projection of the first P-type field effect transistor on the semiconductor substrate; the orthographic projection of the fourth N-type field effect transistor on the semiconductor substrate at least partially overlaps with the orthographic projection of the second P-type field effect transistor on the semiconductor substrate.

[0028] In this way, the projected area of ​​each storage unit on the semiconductor substrate can be further compressed, thereby improving storage density and storage capacity.

[0029] In one achievable manner, the first electrode of the third N-type field effect transistor is electrically connected to the first electrode of the first N-type field effect transistor; the first electrode of the fourth N-type field effect transistor is electrically connected to the first electrode of the second N-type field effect transistor.

[0030] Field effect transistors located in different device layers can be electrically connected through interconnection wiring layers and conductive vias located in the device layers.

[0031] In one implementation, the static random access memory array also includes: a first electrode line, a second electrode line and a third electrode line; the first electrode of the third N-type field effect transistor is electrically connected to the first electrode of the first N-type field effect transistor; the first electrode of the fourth N-type field effect transistor is electrically connected to the first electrode of the second N-type field effect transistor; the gate of the third N-type field effect transistor and the gate of the fourth N-type field effect transistor are both electrically connected to the first electrode line; the second electrode of the third N-type field effect transistor is electrically connected to the second electrode line; the second electrode of the fourth N-type field effect transistor is electrically connected to the third electrode line; the first electrode line is located in a second back-end device layer; the second electrode line and the third electrode line are located in a third interconnect routing layer, and the second back-end device layer is located between the second interconnect routing layer and the third interconnect routing layer.

[0032] For example, the first electrode line may be a word line, and the second electrode line and the third electrode line may be a bit line.

[0033] In one achievable manner, at least one N-type field effect transistor further includes: a fifth N-type field effect transistor and a sixth N-type field effect transistor; the first electrode of the fifth N-type field effect transistor is electrically connected to the first electrode of the sixth N-type field effect transistor; and the fifth N-type field effect transistor and the sixth N-type field effect transistor are located in the same back-end device layer.

[0034] Such a memory cell may be an 8T memory cell.

[0035] In one implementation, the static random access memory array further includes: a fourth electrode line and a fifth electrode line; the second electrode of the sixth N-type field effect transistor is electrically connected to the fourth electrode line; and the gate of the sixth N-type field effect transistor is electrically connected to the fifth electrode line.

[0036] For example, the fourth electrode line is the electrode line RBL, and the fifth electrode line may be RWL.

[0037] In one achievable method, the fifth N-type field-effect transistor and the sixth N-type field-effect transistor are located in a third back-end device layer, and the third back-end device layer is closer to the first back-end device layer than the second back-end device layer; a fourth interconnect routing layer is formed between the third back-end device layer and the second back-end device layer; the first electrode of the fifth N-type field-effect transistor is electrically connected to the first electrode of the sixth N-type field-effect transistor through the fourth interconnect routing layer; the fifth electrode line is located in the fourth interconnect routing layer; and the fourth electrode line is located in the third interconnect routing layer.

[0038] In the above example, the third back-end device in which the fifth N-type field-effect transistor and the sixth N-type field-effect transistor are located is located between the second back-end device layer and the first back-end device layer. In other examples, the third back-end device layer may also be located above the second back-end device layer.

[0039] In one implementation, a channel material of the at least one N-type field effect transistor includes an oxide semiconductor material.

[0040] When manufacturing N-type field-effect transistors based on oxide semiconductor materials, it can be compatible with the back-end process and will not complicate the preparation process.

[0041] In one possible implementation, any storage unit includes a first inverter and a second inverter, the input end of the first inverter is electrically connected to the output end of the second inverter, and the output end of the first inverter is electrically connected to the input end of the second inverter; the first inverter includes a first P-type field effect transistor and a first N-type field effect transistor; the second inverter includes a second P-type field effect transistor and a second N-type field effect transistor.

[0042] The example given in this application may be a memory cell comprising six field-effect transistors or eight field-effect transistors, wherein the P-type field-effect transistors in the first inverter and the second inverter in the memory cell are both manufactured using the front-end process, and the N-type field-effect transistors are both manufactured using the back-end process.

[0043] On the other hand, the present application also provides a method for preparing a static random access memory array, the method comprising:

[0044] A front-end device layer is formed in a semiconductor substrate using a front-end process, wherein at least one P-type field effect transistor is formed in the front-end device layer;

[0045] A back-end device layer is formed on the front-end device layer using a back-end process, wherein at least one N-type field effect transistor is formed in the back-end device layer to obtain a memory cell including at least one P-type field effect transistor and at least one N-type field effect transistor.

[0046] In the preparation method provided in the present application, the P-type field effect transistor of the memory cell is manufactured using a front-end process, and the N-type field effect transistor of the memory cell is manufactured using a back-end process, so that the field effect transistors of the memory cell are three-dimensionally stacked, thereby improving the storage density.

[0047] In one achievable manner, when a front-end device layer is formed in a semiconductor substrate using a front-end process, the method includes:

[0048] When a front-end device layer is formed in a semiconductor substrate using a front-end process, it includes:

[0049] forming a first P-type field effect transistor and a second P-type field effect transistor in a semiconductor substrate by using a front-end process;

[0050] When a back-end device layer is formed on a front-end device layer using a back-end process, it includes:

[0051] A first N-type field effect transistor and a second N-type field effect transistor are formed on a front-end device layer using a back-end process. The first N-type field effect transistor and the second N-type field effect transistor are located in the same back-end device layer to produce a first inverter including a first P-type field effect transistor and a first N-type field effect transistor, and a second inverter including a second N-type field effect transistor electrically connected to the second P-type field effect transistor.

[0052] In this way, two cross-coupled inverters in a 6T memory cell or an 8T memory cell can be manufactured.

[0053] In one achievable embodiment, the first N-type field-effect transistor and the second N-type field-effect transistor are located in a first back-end device layer; after forming the front-end device layer and before forming the first back-end device layer, the preparation method further includes: forming a first interconnect routing layer, and the first P-type field-effect transistor is electrically connected to the second P-type field-effect transistor through the first interconnect routing layer; after forming the first back-end device layer, the preparation method further includes: forming a second interconnect routing layer, and the first N-type field-effect transistor is electrically connected to the second N-type field-effect transistor through the second interconnect routing layer.

[0054] A first interconnect routing layer is used to electrically connect a first P-type field effect transistor and a second P-type field effect transistor located in a front-end device layer, and a second interconnect routing layer is used to electrically connect a first N-type field effect transistor and a second N-type field effect transistor located in a first back-end device layer.

[0055] In one achievable manner, after forming the first N-type field effect transistor and the second N-type field effect transistor located in the same back-end device layer, the method further includes: forming a third N-type field effect transistor and a fourth N-type field effect transistor located in the same back-end device layer, the third N-type field effect transistor being electrically connected to the output end of the first inverter, and the fourth N-type field effect transistor being electrically connected to the output end of the second inverter.

[0056] In this way, a 6T memory cell can be manufactured, in which six field effect transistors can be arranged in a front-end device layer and two back-end device layers.

[0057] In one achievable method, a third N-type field effect transistor and a fourth N-type field effect transistor are formed within the same back-end device layer, including forming a first electrode line, wherein the gate of the third N-type field effect transistor and the gate of the fourth N-type field effect transistor are electrically connected to the first electrode line, and the first electrode line, the third N-type field effect transistor, and the fourth N-type field effect transistor are located within the same back-end device layer.

[0058] The first electrode line may be a word line WL.

[0059] In one achievable manner, after forming a third N-type field-effect transistor and a fourth N-type field-effect transistor located in the same back-end device layer, the preparation method further includes: forming a third interconnect routing layer, in which a second electrode line and a third electrode line are formed, so that the second electrode of the third N-type field-effect transistor is electrically connected to the second electrode line, and the second electrode of the fourth N-type field-effect transistor is electrically connected to the third electrode line.

[0060] The second electrode line and the third electrode line may be a bit line BL and a bit line BLB, respectively.

[0061] In one achievable manner, after forming the first N-type field effect transistor and the second N-type field effect transistor located in the same back-end device layer, the method further includes: forming a fifth N-type field effect transistor and a sixth N-type field effect transistor located in the same back-end device layer, the gate of the fifth N-type field effect transistor being electrically connected to the input end of the first inverter; and the first electrode of the fifth N-type field effect transistor being electrically connected to the first electrode of the sixth N-type field effect transistor.

[0062] On the other hand, the present application also provides a memory, including a controller and a static random access memory array in any of the above implementations, the controller being electrically connected to the static random access memory array, and the controller being used to control the reading and writing of the static random access memory array.

[0063] In the memory provided in the present application, since it includes the static random access memory array of the above example, the P-type field effect transistor of each memory cell in the static random access memory array is integrated in the front-end device layer, and the N-type field effect transistor is integrated in the back-end device layer, so that the multiple field effect transistors of the memory cell are stacked in three dimensions, thereby improving the storage density of the memory.

[0064] On the other hand, the present application also provides an electronic device, including a processor and the above-mentioned memory, wherein the processor is electrically connected to the memory, and the memory is used to store data generated by the processor.

[0065] The electronic device provided in the embodiment of the present application includes the memory in any of the above-mentioned implementation methods. Therefore, the electronic device provided in the embodiment of the present application and the memory of the above-mentioned technical solution can solve the same technical problems and achieve the same expected effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] FIG1 is a circuit diagram of an electronic device;

[0067] FIG2 is a circuit diagram of a memory;

[0068] FIG3A is a packaging structure diagram of a storage array and a controller;

[0069] FIG3B is a packaging structure diagram of a storage array and a controller;

[0070] FIG3C is a diagram showing a packaging structure of a storage array and a controller;

[0071] FIG4 is a simplified circuit diagram of a memory;

[0072] FIG5 is a circuit diagram of a 6T memory cell provided in an embodiment of the present application;

[0073] FIG6 is a circuit diagram of an 8T memory cell provided in an embodiment of the present application;

[0074] FIG7 is a simplified process structure diagram of a memory array provided in an embodiment of the present application;

[0075] FIG8A is a layout of a front-end device layer of a memory array provided in an embodiment of the present application;

[0076] 8B and 8C are layouts of a back-end device layer of a memory array provided in an embodiment of the present application;

[0077] FIG9A is a layout of a front-end device layer of a memory array provided in an embodiment of the present application;

[0078] 9B, 9C, and 9D are layouts of a back-end device layer of a memory array provided in an embodiment of the present application;

[0079] FIG10 is a flowchart of a method for preparing a memory array provided in an embodiment of the present application. DETAILED DESCRIPTION

[0080] Before introducing the embodiments given in this application, the relevant technical terms are first introduced.

[0081] Pull-up means clamping the signal at a high level.

[0082] Pull-down means clamping the signal at a low level.

[0083] Oxide semiconductor: A type of oxide with semiconductor properties.

[0084] The following embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0085] The technical solution of the present application can be applied to various electronic devices that use memory. For example, Figure 1 is a circuit block diagram of an electronic device 100 provided in an embodiment of the present application. The electronic device 100 can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc.

[0086] As shown in Figure 1, the electronic device 100 may include a bus 205 and a system on chip (SOC) 210 connected to the bus 205. The SOC 210 can be used to process data, such as processing application data, processing image data, and caching temporary data. In one embodiment, the SOC 210 may include an application processor (AP) 211 for processing applications, a graphics processing unit (GPU) 212 for processing image data, and a first random access memory (RAM) 213 for caching high-speed data. The first RAM 213 may be a static random access memory (SRAM) or an embedded flash memory (EFlash), etc. The above-mentioned AP 211, GPU 212 and first RAM 213 can be integrated into a die, or they can be set separately in multiple dies.

[0087] As shown in FIG1 , the electronic device 100 may further include a second RAM 220 connected to the SOC 210 via a bus 205. The second RAM 220 may be a dynamic random access memory (DRAM). The second RAM 220 may be used to store volatile data, such as temporary data generated by the SOC 210. The storage capacity of the second RAM 220 is generally greater than that of the first RAM 213, but the read speed is generally slower than that of the first RAM 213.

[0088] In addition, the electronic device 100 may further include a communication chip 230 and a power management chip 240 connected to the SOC 210 via the bus 205. The communication chip 230 may be used for processing the protocol stack, or for amplifying and filtering analog radio frequency signals, or for performing the above functions simultaneously. The power management chip 240 may be used to power other chips. In one embodiment, the SOC 210 and the second RAM 220 may be packaged in a single package structure, such as a 2.5D (dimension) or 3D package, to achieve a faster inter-chip data transmission rate.

[0089] As shown in FIG. 2 , the memory 300 includes a memory array 31 and a controller 32 for accessing the memory array 31 , wherein the controller 32 is used to control read and write operations of the memory array 31 .

[0090] The storage array 31 and the controller 32 shown in FIG. 2 have a variety of achievable packaging structures. For example, several achievable packaging structures are given below.

[0091] FIG3A illustrates one packaging structure for a memory array 31 and a controller 32 according to an embodiment of the present application. Specifically, the memory array 31 and the controller 32 are two independent chips, each integrated on a substrate 33. For example, the memory array 31 and the controller 32 can be electrically connected via metal traces arranged on the substrate 33. In this structure, since the memory array 31 and the controller 32 are two independent chips, the memory array 31 can be referred to as a stand-alone memory.

[0092] FIG3B is another packaging structure of the memory array 31 and the controller 32 provided in an embodiment of the present application. In this structure, similar to FIG3A above, the memory array 31 and the controller 32 are two independent chips, and thus the memory array 31 can also be referred to as an independent memory. Unlike FIG3A above, in FIG3B , the memory array 31 and the controller 32 are stacked. For example, the memory array 31 and the controller 32 can be connected via through silicon vias (TSVs) or redistribution layers (RDLs).

[0093] Figure 3C shows another packaging structure of a memory array 31 and a controller 32 according to an embodiment of the present application. In this exemplary structure, the memory array 31 and the controller 32 are integrated into the same chip 3, which is integrated on a substrate 33. Therefore, the memory array 31 can be called an embedded memory.

[0094] In one embodiment, the memory array 31 in the memory may include a plurality of memory cells 400 arranged in an array as shown in FIG4 , wherein each memory cell 400 may be used to store 1 bit (bit) or multiple bits of data. The memory array 31 may also include electrode lines such as word lines (WL) and bit lines (BL). Each memory cell 400 is electrically connected to the corresponding word line WL and bit line BL. Different memory cells 400 can be electrically connected through word lines WL and bit lines BL. One or more of the above-mentioned word lines WL and bit lines BL are used to select the memory cell 400 to be read or written in the memory array by receiving the control level output by the control circuit, thereby realizing the read and write operations of the data.

[0095] The controller 32 in the memory may include one or more circuit structures of the decoder 320 , the driver 330 , the timing controller 340 , the buffer 350 , or the input / output driver 360 shown in FIG. 4 .

[0096] In the memory 300 structure shown in Figure 4, the decoder 320 is used to decode the received address to determine the memory cell 400 to be accessed. The driver 330 is used to control the level of the signal line based on the decoding result generated by the decoder 320, thereby achieving access to the specified memory cell 400. The buffer 350 is used to cache the read data, for example, it can be cached using a first-in first-out (FIFO) method. The timing controller 340 is used to control the timing of the buffer 350 and control the driver 330 to drive the signal lines in the memory array 310. The input and output driver 360 is used to drive the transmission signal, such as the received data signal and the data signal to be sent, so that the data signal can be transmitted over a long distance.

[0097] The memory array 310 , decoder 320 , driver 330 , timing controller 340 , buffer 350 and input / output driver 360 may be integrated into one chip or integrated into multiple chips.

[0098] In some examples, the memory 300 may be electrically connected to the processor, and the memory is used to store data generated by the processor.

[0099] The memory involved in the embodiments of the present application may include a memory cell of the static random access memory array shown in Figure 5 or Figure 6. In a memory cell 400 of the static random access memory array shown in Figure 5, six field effect transistors (Oxide semiconductor based Field-Effect Transistor, OS-FET) are included, which can be called a 6T memory cell. In a memory cell 400 of the static random access memory array shown in Figure 6, eight field effect transistors are included, which can be called an 8T memory cell.

[0100] In some other examples, a memory cell may be a 3T memory cell, a 4T memory cell, a 5T memory cell, a 7T memory cell, a 9T memory cell, or a 10T memory cell, or a memory cell including more field effect transistors.

[0101] In an embodiment of the present application, a memory cell of a static random access memory array includes at least three field effect transistors, and the at least three field effect transistors may include a P-type field effect transistor and an N-type field effect transistor.

[0102] For example, the 6T memory cell 400 shown in FIG5 includes field effect transistors MP1, MN1, MP2, MN2, MA1, and MA2. Field effect transistors MP1 and MP2 are P-type field effect transistors, while the remaining ones are N-type field effect transistors.

[0103] For another example, the 8T memory cell 400 shown in FIG6 includes field effect transistors MP1, MN1, MP2, MN2, MA1, and MA2, as well as field effect transistors MR1 ​​and MR2. Field effect transistors MP1 and MP2 are P-type field effect transistors, and the remaining are N-type field effect transistors.

[0104] In some examples provided herein, such as those in Figures 5 and 6 , P-type field-effect transistors are fabricated in a semiconductor substrate using a front-end-of-the-line (FEOL) process. For example, field-effect transistors MP1 and MP2 in Figures 5 and 6 are fabricated using a front-end-of-the-line (FEOL) process, while the remaining N-type field-effect transistors are fabricated in a back-end-of-the-line (BEOL) device layer.

[0105] In the example of the present application, a P-type field effect transistor is manufactured in a semiconductor substrate using a front-end process FEOL, and an N-type field effect transistor is manufactured in a back-end device layer using a back-end process. This can be understood as follows: as shown in Figure 7, in the chip manufacturing process, a front-end process can be first used to manufacture a front-end device layer in a semiconductor substrate. The electronic devices in the front-end device layer can include P-type field effect transistors as shown in Figures 5 and 6. The source and drain of the P-type field effect transistor can be formed by doping in the semiconductor substrate. After the front-end device layer is manufactured, a back-end process can be used to manufacture a back-end device layer. For example, the N-type field effect transistor shown in Figures 5 and 6 can be formed in the back-end device layer using a back-end process.

[0106] As shown in Figure 7, the N-type field effect transistors shown in Figures 5 and 6 can be integrated in the back-end device layer. The interconnection routing layer is used to form metal routing to electrically connect the electronic devices in the back-end device layer. The back-end device layer and the interconnection routing layer are separated by a dielectric layer, and the back-end device layer and the interconnection routing layer can be electrically connected through conductive through holes (for example, silicon through vias) that pass through the dielectric layer.

[0107] The channel material of the N-type field effect transistor in the back-end device layer of the present application includes an oxide semiconductor material, which may include at least one of ZnO, CdO, TiO2, Al2O3, and SnO. Alternatively, the channel material of the N-type field effect transistor may include polysilicon.

[0108] The field-effect transistor (OS-FET) process using oxide semiconductor as the channel material is compatible with the back-end process, meaning that the active device, the N-type field-effect transistor, can be placed in the back-end device layer without complicating the process.

[0109] As shown in Figures 5 and 6, multiple field-effect transistors in a memory cell are formed in a three-dimensional stacking manner to form a three-dimensional stacked memory (3-Dimensions Memory, 3D Memory). Compared with the front-end process for manufacturing all field-effect transistors in a memory cell, this application can significantly improve the storage density.

[0110] In the example of this application, the P-type field effect transistor that can be used as a pull-up tube is manufactured using a front-end process, and the N-type field effect transistor that can be used as a pull-down tube is manufactured using a back-end process. Compared with the existing method in which both P-type field effect transistors and N-type field effect transistors are manufactured using the front-end process, when the same process node is used, this application can not only ensure the high conduction performance of the pull-down tube, but also improve the storage density.

[0111] This application takes 6T memory cells and 8T memory cells as examples to introduce the process structures that can be implemented for memory cells.

[0112] As shown in Figures 5 and 6, a 6T memory cell 400 or an 8T memory cell 400 includes a first inverter 501 and a second inverter 502. The input end of the first inverter 501 is electrically connected to the output end of the second inverter 502, and the output end of the first inverter 501 is electrically connected to the input end of the second inverter 502. The first inverter 501 and the second inverter 502 form a cross-coupling circuit structure.

[0113] The first inverter 501 includes a field effect transistor MP1 and a field effect transistor MN1 that are electrically connected, and the second inverter 502 includes a field effect transistor MP2 and a field effect transistor MN2 that are electrically connected.

[0114] Field effect transistor MP1 and field effect transistor MP2 are respectively arranged in the semiconductor substrate using the front-end process and are located in the front-end device layer of the semiconductor substrate; field effect transistor MN1 and field effect transistor MN2 are respectively manufactured in the back-end device layer above the semiconductor substrate using the back-end process.

[0115] In order to further improve the storage density, as shown in Figures 5 and 6, the field effect transistor MP1 and the field effect transistor MP2 are located in the front-end device layer, and the field effect transistor MN1 and the field effect transistor MN2 can be set in the same back-end device layer, for example, in the OSL1 device layer as shown in Figures 5 and 6.

[0116] In some examples, the channels of N-type field-effect transistors MN1 and MN2 can be made of oxide semiconductor materials. Placing MN1 and MN2 in the same back-end device layer not only improves storage density but also simplifies the manufacturing process due to the same channel material.

[0117] In some achievable process structures, in the first inverter 501, the field-effect transistor MN1 is formed using a back-end process on the side of the field-effect transistor MP1 that is away from the semiconductor substrate. In some examples, the orthographic projections of the field-effect transistor MN1 and the field-effect transistor MP1 on the semiconductor substrate partially overlap. In the second inverter 502, the field-effect transistor MN2 is formed using a back-end process on the side of the field-effect transistor MP2 that is away from the semiconductor substrate. In some examples, the orthographic projections of the field-effect transistor MN2 and the field-effect transistor MP2 on the semiconductor substrate partially overlap. This can further reduce the orthographic projection area of ​​each memory cell on the semiconductor substrate, further improving storage density.

[0118] 5 and 6 , the gate of the field effect transistor MP1 is electrically connected to the first electrode of the field effect transistor MP2, the gate of the field effect transistor MP2 is electrically connected to the first electrode of the field effect transistor MP1, and the second electrode of the field effect transistor MP1 is electrically connected to the second electrode of the field effect transistor MP2. For example, the second electrode of the field effect transistor MP1 and the second electrode of the field effect transistor MP2 can both be electrically connected to VDD.

[0119] The gate of field effect transistor MN1 is electrically connected to the first electrode of field effect transistor MN2, the gate of field effect transistor MN2 is electrically connected to the first electrode of field effect transistor MN1, and the second electrode of field effect transistor MN1 is electrically connected to the second electrode of field effect transistor MN2. For example, the second electrode of field effect transistor MN1 and the second electrode of field effect transistor MN2 can both be electrically connected to VSS.

[0120] The first electrode of the field effect transistor MP1 is electrically connected to the first electrode of the field effect transistor MN1, and the electrical connection node forms the output terminal of the first inverter 501; the gate of the field effect transistor MP1 is electrically connected to the gate of the field effect transistor MN1, and the electrical connection node forms the input terminal of the first inverter 501.

[0121] The first electrode of the field effect transistor MP2 is electrically connected to the first electrode of the field effect transistor MN2, and the electrical connection node forms the output terminal of the second inverter 502; the gate of the field effect transistor MP2 is electrically connected to the gate of the field effect transistor MN2, and the electrical connection node forms the input terminal of the second inverter 502.

[0122] In the example of the present application, the first electrode is one of the source and the drain, and the second electrode is the other of the source and the drain.

[0123] The following describes in detail the process structures that can be implemented for each field effect transistor in the first inverter 501 and the second inverter 502 , as well as the process connection structures between different electrodes, in conjunction with the process structure diagram.

[0124] FIG8A , FIG8B and FIG8C are the layout structures of each device layer given in the embodiment of the present application.

[0125] The memory array includes the stacked front-end device layer, interconnection routing layer 1, back-end device layer 1, interconnection routing layer 2, back-end device layer 2 and interconnection routing layer 3 as shown in FIG. 7 .

[0126] As shown in FIG8A , the field effect transistor MP1 and the field effect transistor MP2 are arranged along a first direction (eg, X direction) parallel to a surface of a semiconductor substrate (not shown).

[0127] In the first inverter 501, as shown in FIG8A , a first electrode 11A and a second electrode 12A of the field-effect transistor MP1 are arranged along a second direction (e.g., the Y direction) parallel to the surface of the semiconductor substrate. A channel of the field-effect transistor MP1 is formed between the first electrode 11A and the second electrode 12A. A gate 13A of the field-effect transistor MP1 is disposed above the channel and may be isolated from the channel by a gate dielectric layer.

[0128] In the second inverter 502, as shown in FIG8A , the first electrode 11B and the second electrode 12B of the field-effect transistor MP2 are arranged along the second direction, and a channel of the field-effect transistor MP2 is formed between the first electrode 11B and the second electrode 12B. The gate 13B of the field-effect transistor MP2 is disposed above the channel and may be isolated from the channel by a gate dielectric layer.

[0129] The source, drain, and channel of the field effect transistor MP1 are located in the front-end device layer, and the source, drain, and channel of the field effect transistor MP2 are also located in the front-end device layer. In some examples, the source and drain of the field effect transistor MP1 and the field effect transistor MP2 can be manufactured by ion implantation.

[0130] Because field-effect transistors MP1 and MP2 need to be electrically connected, in some process structures, an interconnect routing layer 1 can be provided above the front-end device layer of the semiconductor substrate. For example, as shown in FIG8A , gate 13A of field-effect transistor MP1 is electrically connected to first electrode 11B of field-effect transistor MP2 via metal routing 1, gate 13B of field-effect transistor MP2 is electrically connected to first electrode 11A of field-effect transistor MP1 via metal routing 2, and second electrode 12A of field-effect transistor MP1 is electrically connected to second electrode 12B of field-effect transistor MP2 via metal routing 3. Metal routing 1, metal routing 2, and metal routing 3 are part of the routing in interconnect routing layer 1.

[0131] There is a dielectric layer between the front-end device layer and the interconnection wiring layer 1. The metal wiring can be electrically connected to the corresponding structure through conductive vias (for example, silicon through vias) that penetrate the dielectric layer. For example, the gate 13A of the field effect transistor MP1 can be connected to the metal wiring 1 through the conductive via 11.

[0132] In the front-end device layer, multiple field-effect transistors MP1 and MP2 are integrated and arranged in an array. To electrically connect the second electrodes of the field-effect transistors MP1 and MP2 located in the same direction, as shown in FIG8A , a metal trace 3 can be extended along the X direction to electrically connect the second electrodes of the multiple field-effect transistors MP1 and MP2 located in the X direction. For example, the metal trace 3 can be electrically connected to VDD.

[0133] The field effect transistor MN1 of the first inverter 501 and the field effect transistor MN2 of the second inverter 502 are both disposed in the back-end device layer 1 . As shown in FIG8B , the field effect transistor MN1 and the field effect transistor MN2 are arranged along the X direction.

[0134] As shown in FIG8B , in the first inverter 501 , the first electrode 11C and the second electrode 12C of the field effect transistor MN1 are arranged along the Y direction. In the example of the present application, the field effect transistor MN1 is a ring gate structure. In other examples, a ring channel structure may also be used.

[0135] As shown in FIG8B , in the second inverter 502 , the first electrode 11D and the second electrode 12D of the field effect transistor MN2 are also arranged in the Y direction. The field effect transistor MN2 is similar to the field effect transistor MN1 in the example, both having a ring gate structure. Other structures may also be used.

[0136] The orthographic projection of field-effect transistor MN1 on the semiconductor substrate at least partially overlaps with the orthographic projection of field-effect transistor MP1 on the semiconductor substrate; that is, field-effect transistor MN1 is located above the vertical projection of field-effect transistor MP1. The orthographic projection of field-effect transistor MN2 on the semiconductor substrate at least partially overlaps with the orthographic projection of field-effect transistor MP2 on the semiconductor substrate, and field-effect transistor MN2 is located above the vertical projection of field-effect transistor MP2. In this way, the orthographic projection area of ​​the first and second inverters in the memory cell on the semiconductor substrate can be reduced by half compared to the prior art, thereby improving storage density and storage capacity.

[0137] As shown in FIG7 and FIG8B , an interconnection wiring layer 2 is provided above the back-end device layer 1 , and the field effect transistor MN1 can be electrically connected to the field effect transistor MN2 through the interconnection wiring layer 2 .

[0138] For example, gate 13C of field-effect transistor MN1 is electrically connected to first electrode 11D of field-effect transistor MN2 via metal trace 4, gate 13D of field-effect transistor MN2 is electrically connected to first electrode 11C of field-effect transistor MN1 via metal trace 5, and second electrode 12C of field-effect transistor MN1 is electrically connected to second electrode 12D of field-effect transistor MN2 via metal trace 6. Metal traces 4, 5, and 6 are part of the traces in the second interconnect trace layer.

[0139] There is a dielectric layer between the back-end device layer 1 and the interconnection routing layer 2. The metal routing in the interconnection routing layer 2 can be electrically connected to the corresponding structure in the back-end device layer 1 through conductive vias penetrating the dielectric layer.

[0140] The field effect transistor MP1 in the front-end device layer needs to be electrically connected to the field effect transistor MN1 in the back-end device layer. The field effect transistor MP2 in the front-end device layer needs to be electrically connected to the field effect transistor MN2 in the back-end device layer.

[0141] The first electrode 11A of the field effect transistor MP1 is electrically connected to the first electrode 11C of the field effect transistor MN1. In some examples, the first electrode 11A and the first electrode 11C may be interconnected via a conductive via penetrating the dielectric layer.

[0142] The first electrode 11B of the field effect transistor MP2 is electrically connected to the first electrode 11D of the field effect transistor MN2. In some structures, the first electrode 11B and the first electrode 11D may be interconnected via a conductive via 13 penetrating the dielectric layer.

[0143] In some other process structures, the first electrode 11A and the first electrode 11C are interconnected, and the first electrode 11B and the first electrode 11D are interconnected. Other routing methods may also be used.

[0144] As shown in the example of the 6T memory cell in FIG5 and the example of the 8T memory cell in FIG6, field effect transistors MA1 and MA2 are also included. Field effect transistors MA1 and MA2 can be N-type field effect transistors and can be manufactured using a back-end process. For example, the channel material of field effect transistors MA1 and MA2 includes an oxide semiconductor material.

[0145] In some examples, the field effect transistor MA1 and the field effect transistor MA2 can be formed in the same back-end device layer using a back-end process, for example, in the OSL2 device layer as shown in the examples of FIG. 5 and FIG. 6 .

[0146] The field effect transistor MA2 is electrically connected to the output terminal of the first inverter 501 , and the field effect transistor MA1 is electrically connected to the output terminal of the second inverter 502 .

[0147] The field effect transistor MA1 and the field effect transistor MA2 are provided in the back-end device layer 2 .

[0148] As shown in FIG8C , the field effect transistor MA1 and the field effect transistor MA2 are arranged along the X direction.

[0149] As shown in FIG8C , the first electrode 11E and the second electrode 12E of the field effect transistor MA1 are arranged along the Y direction. In the example of the present application, the field effect transistor MA1 is a ring gate structure. In other examples, a ring channel structure may also be used.

[0150] As shown in FIG8C , the first electrode 11F and the second electrode 12F of the field effect transistor MA2 are also arranged in the Y direction. The field effect transistor MA2 is similar to the field effect transistor MA1 in the example, both having a ring gate structure, and other structures may also be used.

[0151] As shown in FIG8C , gate 13E of field effect transistor MA1 and gate 13F of field effect transistor MA2 are electrically connected.

[0152] For example, the first electrode of the field effect transistor MA2 is electrically connected to the gate of the field effect transistor MN1 , or the first electrode of the field effect transistor MA2 is electrically connected to the first electrode of the field effect transistor MN2 .

[0153] The first electrode of the field effect transistor MA1 is electrically connected to the gate of the field effect transistor MN2 , or the first electrode of the field effect transistor MA1 is electrically connected to the first electrode of the field effect transistor MN1 .

[0154] Referring to the example 6T memory cell, the six field-effect transistors in a memory cell are distributed in three device layers, wherein two P-type field-effect transistors are arranged in the front-end device layer, and the other four N-type field-effect transistors are arranged in two back-end device layers, so that a memory cell can be made by three-dimensionally stacked three-layer device layers, and the interconnection wiring layer arranged between two adjacent device layers is used to realize the interconnection of different field-effect transistors.

[0155] As shown in the example of Figure 5, the 6T memory cell also includes electrode lines for controlling the reading and writing of the memory cell, for example, including a word line WL, a first bit line BL, and a second bit line BLB. Among them, the second electrode of the field effect transistor MA1 is electrically connected to the first bit line BL, the second electrode of the field effect transistor MA2 is electrically connected to the second bit line BLB, and the gates of the field effect transistor MA1 and the field effect transistor MA2 are both electrically connected to the word line WL.

[0156] In a feasible process structure, an interconnection routing layer 3 is provided above the back-end device layer 2 where the field effect transistor MA1 and the field effect transistor MA2 are located, the first bit line BL and the second bit line BLB are located in the interconnection routing layer 3, and the word line WL is located in the back-end device layer 2.

[0157] In some examples given in this application, the first bit line BL and the second bit line BLB may be parallel to each other, and the word line WL may be perpendicular to both the first bit line BL and the second bit line BLB.

[0158] 8A to 8C illustrate the process structure diagrams of a 6T memory cell, and FIG. 9A to 9D illustrate the layout of an 8T memory cell of the present application.

[0159] The memory array illustrated in Figures 9A to 9D includes the stacked front-end device layer, interconnect routing layer 1, back-end device layer 1, interconnect routing layer 2, back-end device layer 2, interconnect routing layer 3, back-end device layer 3, and interconnect routing layer 4 illustrated in Figure 7.

[0160] This example is the same as the above example. Each memory cell includes: a field effect transistor MP1, a field effect transistor MN1, a field effect transistor MP2, a field effect transistor MN2, and a field effect transistor MA1 and a field effect transistor MA2.

[0161] Field effect transistor MP1 and field effect transistor MP2 are located in the front-end device layer, field effect transistor MN1 and field effect transistor MN2 are located in the back-end device layer 1, field effect transistor MP1 and field effect transistor MP2 are electrically connected through interconnection wiring layer 1, and field effect transistor MN1 and field effect transistor MN2 are electrically connected through interconnection wiring layer 2.

[0162] The 8T memory cell of the example of the present application also includes field effect transistor MA1 and field effect transistor MA2, as well as field effect transistor MR1 and field effect transistor MR2. In some examples, as shown in Figure 6, field effect transistor MA1 and field effect transistor MA2 are set in the OSL2 device layer, and field effect transistor MR1 and field effect transistor MR2 can be set in the OSL3 device layer.

[0163] In some other examples, field effect transistors MR1 ​​and MR2 may be located in the OSL2 device layer, and field effect transistors MA1 and MA2 may be located in the OSL3 device layer. For example, field effect transistors MR1 ​​and MR2 may be located in the back-end device layer 2, and field effect transistors MA1 and MA2 may be located in the back-end device layer 3.

[0164] In the 8T memory cell process structure of the present application example, the process structure that can be implemented for field effect transistors MP1, FET MN1, FET MP2, and FET MN2, as well as the process connection structure between electrodes can refer to the above-mentioned 6T memory cell.

[0165] Figure 9C exemplarily illustrates a layout of the process structure of field-effect transistors MR1 ​​and MR2. First electrode 11G and second electrode 12G of field-effect transistor MR2 are arranged along the X direction, while first electrode 11H and second electrode 12H of field-effect transistor MR1 are arranged along the Y direction. First electrode 11G of field-effect transistor MR2 and first electrode 11H of field-effect transistor MR1 share the same electrode layer, achieving electrical connection between first electrode 11G and first electrode 11H.

[0166] Figure 9C shows a process structure in which the field effect transistor MR1 and the field effect transistor MR2 are electrically connected. In some other examples, an interconnection routing layer is provided above the back-end device layer where the field effect transistor MR1 and the field effect transistor MR2 are located, and the first electrode 11G and the first electrode 11H can be electrically connected through the metal routing of the interconnection routing layer.

[0167] The memory array further includes an electrode line RBL and an electrode line RWL. The second electrode of the field effect transistor MR2 is electrically connected to the electrode line RBL, and the gate of the field effect transistor MR2 is electrically connected to the electrode line RWL. The second electrode 12H of the field effect transistor MR1 can be electrically connected to VSS.

[0168] An electrode line RWL electrically connected to the gate of the field effect transistor MR2 may be located in the interconnect wiring layer 3 .

[0169] The electrode line RBL electrically connected to the second electrode of the field effect transistor MR2 can be set in the interconnection wiring layer 4 located above the field effect transistor MA1 and the field effect transistor MA2. That is, the first bit line BL, the second bit line BLB, and the electrode line RBL can be set in the same interconnection wiring layer. In some examples, the first bit line BL, the second bit line BLB, and the electrode line RBL can also be set parallel to each other. The electrode line RWL can be arranged perpendicular to the electrode line RBL.

[0170] The present application also provides a method for preparing a static random access memory array, as shown in FIG10 . FIG10 exemplarily shows a flow chart of the method for preparing a static random access memory array. The method includes:

[0171] Step S1: forming a front-end device layer in a semiconductor substrate by using a front-end process, wherein at least one P-type field effect transistor is formed in the front-end device layer.

[0172] In some feasible processes, a doping process can be used to manufacture a P-type field effect transistor.

[0173] Step S2: forming a back-end device layer on the front-end device layer using a back-end process, wherein at least one N-type field effect transistor is formed in the back-end device layer to obtain a memory cell including at least one P-type field effect transistor and at least one N-type field effect transistor.

[0174] This application utilizes a back-end process to fabricate an N-type field-effect transistor. In some examples, the N-type field-effect transistor may be fabricated using an oxide semiconductor material compatible with the back-end process. The oxide semiconductor material may include at least one of ZnO, CdO, TiO2, Al2O3, and SnO.

[0175] In some process technologies, a memory cell may include more field-effect transistors, such as a 6T memory cell or an 8T memory cell.

[0176] In each memory cell of the SRAM memory array manufactured using the preparation method given in this application, the P-type field-effect transistor is manufactured in the front-end device layer, and the N-type field-effect transistor is manufactured in the back-end interconnection layer. That is, the multiple field-effect transistors of the memory cell are integrated on the semiconductor substrate in a three-dimensional stacking manner, which can improve the storage density.

[0177] For example, when making a 6T memory cell, a front-end process can be first used to make a plurality of P-type field effect transistors arranged in an array in a semiconductor substrate (for example, pull-down transistors in the memory cell); then a back-end process is used to make an interconnection wiring layer for electrically connecting the P-type field effect transistors; then a back-end process is used to make a plurality of N-type field effect transistors arranged in an array (for example, pull-up transistors in the memory cell); then an interconnection wiring layer for electrically connecting the N-type field effect transistors is made; then a back-end process is used to make a plurality of N-type field effect transistors (for example, gate transistors in the memory cell); and then an interconnection wiring layer for electrically connecting the N-type field effect transistors to the gate transistor is made.

[0178] This application takes the preparation of a 6T memory cell as an example. When executing step S1, a first P-type field effect transistor and a second P-type field effect transistor in the 6T memory cell are prepared. The first P-type field effect transistor and the second P-type field effect transistor can be arranged in a direction parallel to the surface of the semiconductor substrate; when executing step S2, a first N-type field effect transistor and a second N-type field effect transistor in the 6T memory cell are prepared. The first P-type field effect transistor and the first N-type field effect transistor can form a first inverter, and the second N-type field effect transistor of the second P-type field effect transistor can form a second inverter.

[0179] Before forming the first N-type field effect transistor and the second N-type field effect transistor, an interconnection wiring layer may be formed to electrically connect the plurality of P-type field effect transistors located in the front-end device layer. For example, the first P-type field effect transistor and the second P-type field effect transistor may be electrically connected.

[0180] After the first P-type field effect transistor and the second P-type field effect transistor are fabricated, an interconnection wiring layer may be fabricated to electrically connect the plurality of N-type field effect transistors located in the front-end device layer, for example, to electrically connect the first N-type field effect transistor and the second N-type field effect transistor.

[0181] After the first and second inverters are fabricated, the third and fourth N-type field-effect transistors in the 6T memory cell can be fabricated, so that the third and fourth N-type field-effect transistors are located in the same back-end device layer. Furthermore, the word line WL, the first bit line BL, and the second bit line BLB can be fabricated.

[0182] In some examples, an 8T memory cell may be fabricated using the aforementioned process for fabricating a 6T memory cell, wherein two N-type field effect transistors are formed in each back-end device layer.

[0183] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0184] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A static random access memory array, characterized in that: include: Semiconductor substrate; A front-end device layer and a back-end device layer, wherein the front-end device layer is arranged in the semiconductor substrate, and the back-end device layer is arranged above the front-end device layer; The static random access memory array further comprises a plurality of memory cells, each of which comprises: at least one P-type field effect transistor and at least one N-type field effect transistor; The at least one P-type field effect transistor is formed in the front-end device layer; The at least one N-type field effect transistor is formed in the back-end device layer.

2. The static random access memory array according to claim 1, characterized in that: The orthographic projection of the N-type field effect transistor on the semiconductor substrate at least partially overlaps with the orthographic projection of the P-type field effect transistor on the semiconductor substrate.

3. The static random access memory array according to claim 1 or 2, characterized in that: The at least one N-type field effect transistor includes a first N-type field effect transistor and a second N-type field effect transistor, and the first N-type field effect transistor and the second N-type field effect transistor are located in the same back-end device layer.

4. The static random access memory array according to claim 3, characterized in that: The first N-type field effect transistor and the second N-type field effect transistor are located in a first back-end device layer; A first interconnection wiring layer is formed between the front-end device layer and the first back-end device layer; A second interconnection routing layer is formed on a side of the first back-end device layer away from the first interconnection routing layer; The at least one P-type field effect transistor includes a first P-type field effect transistor and a second P-type field effect transistor; The first P-type field effect transistor is electrically connected to the second P-type field effect transistor through the first interconnect wiring layer; The first N-type field effect transistor is electrically connected to the second N-type field effect transistor through the second interconnect wiring layer.

5. The static random access memory array according to claim 4, characterized in that: The orthographic projection of the first N-type field effect transistor on the semiconductor substrate at least partially overlaps with the orthographic projection of the first P-type field effect transistor on the semiconductor substrate; An orthographic projection of the second N-type field effect transistor on the semiconductor substrate at least partially overlaps with an orthographic projection of the second P-type field effect transistor on the semiconductor substrate.

6. The static random access memory array according to claim 4 or 5, characterized in that: The gate of the first P-type field effect transistor is electrically connected to the first electrode of the second P-type field effect transistor through the first interconnect wiring layer; The gate of the second P-type field effect transistor is electrically connected to the first electrode of the first P-type field effect transistor through the first interconnect wiring layer; The second electrode of the first P-type field effect transistor is electrically connected to the second electrode of the second P-type field effect transistor through the first interconnect wiring layer; The gate of the first N-type field effect transistor is electrically connected to the first electrode of the second N-type field effect transistor through the second interconnect wiring layer; The gate of the second N-type field effect transistor is electrically connected to the first electrode of the first N-type field effect transistor through the second interconnect wiring layer; The second electrode of the first N-type field effect transistor is electrically connected to the second electrode of the second N-type field effect transistor through the second interconnect wiring layer; The first electrode is one of a source and a drain, and the second electrode is the other of the source and the drain.

7. The static random access memory array according to any one of claims 4 to 6, characterized in that: The first electrode of the first P-type field effect transistor is electrically connected to the first electrode of the first N-type field effect transistor; The first electrode of the second P-type field effect transistor is electrically connected to the first electrode of the second N-type field effect transistor.

8. The static random access memory array according to any one of claims 4 to 7, characterized in that: The at least one N-type field effect transistor further comprises: a third N-type field effect transistor and a fourth N-type field effect transistor; The third N-type field effect transistor and the fourth N-type field effect transistor are located in the second back-end device layer of the same back-end device layer. In the device layer; The second interconnect routing layer is located between the first back-end device layer and the second back-end device layer; The orthographic projection of the third N-type field effect transistor on the semiconductor substrate at least partially overlaps with the orthographic projection of the first P-type field effect transistor on the semiconductor substrate; An orthographic projection of the fourth N-type field effect transistor on the semiconductor substrate at least partially overlaps with an orthographic projection of the second P-type field effect transistor on the semiconductor substrate.

9. The static random access memory array according to claim 8, characterized in that: The static random access memory array further includes: a first electrode line, a second electrode line and a third electrode line; The first electrode of the third N-type field effect transistor is electrically connected to the first electrode of the first N-type field effect transistor; The first electrode of the fourth N-type field effect transistor is electrically connected to the first electrode of the second N-type field effect transistor; The gate of the third N-type field effect transistor and the gate of the fourth N-type field effect transistor are both electrically connected to the first electrode line; The second electrode of the third N-type field effect transistor is electrically connected to the second electrode line; The second electrode of the fourth N-type field effect transistor is electrically connected to the third electrode line; The first electrode line is located in the second back-end device layer; The second electrode line and the third electrode line are located in a third interconnection wiring layer; The second back-end device layer is located between the second interconnect routing layer and the third interconnect routing layer.

10. The static random access memory array according to claim 8 or 9, characterized in that: The at least one N-type field effect transistor further comprises: a fifth N-type field effect transistor and a sixth N-type field effect transistor; The first electrode of the fifth N-type field effect transistor is electrically connected to the first electrode of the sixth N-type field effect transistor; The fifth N-type field effect transistor and the sixth N-type field effect transistor are located in the same back-end device layer.

11. The static random access memory array according to claim 10, characterized in that: The static random access memory array further includes: a fourth electrode line and a fifth electrode line; The second electrode of the sixth N-type field effect transistor is electrically connected to the fourth electrode line; A gate of the sixth N-type field effect transistor is electrically connected to the fifth electrode line.

12. The static random access memory array according to claim 11, characterized in that: The fifth N-type field effect transistor and the sixth N-type field effect transistor are located in a third back-end device layer, and the third back-end device layer is closer to the first back-end device layer than the second back-end device layer; A fourth interconnection routing layer is formed between the third back-end device layer and the second back-end device layer; The first electrode of the fifth N-type field effect transistor is electrically connected to the first electrode of the sixth N-type field effect transistor through the fourth interconnect wiring layer; The fifth electrode line is located in the fourth interconnection wiring layer; The fourth electrode line is located in the third interconnection wiring layer.

13. The static random access memory array according to any one of claims 1 to 12, characterized in that: A channel material of the at least one N-type field effect transistor includes an oxide semiconductor material.

14. A method for preparing a static random access memory array, characterized in that: The preparation method comprises: Forming a front-end device layer in a semiconductor substrate by a front-end process, wherein at least one P-type field effect transistor is formed in the front-end device layer; A back-end device layer is formed on the front-end device layer by a back-end process, wherein at least one N-type field effect transistor is formed in the back-end device layer, so as to obtain a storage unit including the at least one P-type field effect transistor and the at least one N-type field effect transistor.

15. The method for preparing a static random access memory array according to claim 14, characterized in that: When the back-end process is used to form the back-end device layer on the front-end device layer, the method includes: The N-type field effect transistor is manufactured in the back-end device layer so that an orthographic projection of the N-type field effect transistor on the semiconductor substrate at least partially overlaps with an orthographic projection of the P-type field effect transistor on the semiconductor substrate.

16. The method for preparing a static random access memory array according to claim 14 or 15, characterized in that: The method of forming a front-end device layer in a semiconductor substrate by using a front-end process comprises: Forming a first P-type field effect transistor and a second P-type field effect transistor in the semiconductor substrate by a front-end process; When the back-end process is used to form a back-end interconnect layer on the front-end device layer, the method includes: A first N-type field effect transistor and a second N-type field effect transistor are formed on the front-end device layer by a back-end process, and the first N-type field effect transistor and the second N-type field effect transistor are located in the same back-end device layer, so as to obtain a storage unit including the first P-type field effect transistor and the first N-type field effect transistor, and the second P-type field effect transistor and the second N-type field effect transistor.

17. The method for preparing a static random access memory array according to claim 16, characterized in that: The first N-type field effect transistor and the second N-type field effect transistor are located in a first back-end device layer; After forming the front-end device layer and before forming the first back-end device layer, the preparation method further includes: forming a first interconnection wiring layer, wherein the first P-type field effect transistor is electrically connected to the second P-type field effect transistor through the first interconnection wiring layer; After forming the first back-end device layer, the preparation method further includes: A second interconnection wiring layer is formed, and the first N-type field effect transistor is electrically connected to the second N-type field effect transistor through the second interconnection wiring layer.

18. The method for preparing a static random access memory array according to claim 16 or 17, characterized in that: After forming the first N-type field effect transistor and the second N-type field effect transistor located in the same back-end device layer, the method further includes: A third N-type field effect transistor and a fourth N-type field effect transistor are formed in the same back-end device layer.

19. A memory, characterized in that: include: A static random access memory array as claimed in any one of claims 1 to 13, or a memory array prepared by the method for preparing a static random access memory array as claimed in any one of claims 14 to 18; A controller is electrically connected to the static random access memory array, and is used to control the reading and writing of the static random access memory array.

20. An electronic device, characterized in that: include: processor; The memory according to claim 19, wherein the processor is electrically connected to the memory, and the memory is used to store data generated by the processor.

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