Display substrate and preparation method therefor, and display apparatus

By combining the TGBC structure and the Top Gate structure on the display substrate, and adopting a three-layer metal layout and a mesh power supply signal transmission structure, the problems of complex hole punching process and large area in the existing technology are solved, and higher display resolution and product yield are achieved.

WO2025055653A1 Publication Date: 2025-03-20BOE TECHNOLOGY GROUP CO LTD +1
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Patent Information

Application Number
PCT/CN2024/112303
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2023-09-14
Filing Date
2024-08-15
Publication Date
2025-03-20

AI Technical Summary

Technical Problem

The hole punching process of existing display substrates is complicated, resulting in a large area occupancy of pixel driving circuits, which limits the improvement of display resolution and affects product yield.

Method used

The display substrate design combining the top gate bottom layer connection (TGBC) structure and the Top Gate structure is adopted to reduce the number of vias in the adapter structure, increase the capacitance value of the storage capacitor through the three-layer metal-layout sandwich structure, and set power connection lines on the first conductive layer to form a mesh power supply signal transmission structure.

Benefits of technology

It effectively reduces the area occupied by the pixel driving circuit, improves the display resolution, reduces the complexity of the hole punching process, improves product yield, and improves display uniformity and quality.

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Abstract

A display substrate and a preparation method therefor, and a display apparatus. The display substrate comprises a plurality of circuit units, wherein each circuit unit comprises a pixel driving circuit, the pixel driving circuit comprising a plurality of transistors. In a direction perpendicular to a plane of the display substrate, the display substrate comprises a first conductive layer, a semiconductor layer, a second conductive layer and a third conductive layer, which are arranged on a base, wherein the first conductive layer comprises at least one first adapter electrode; the semiconductor layer comprises active layers of the plurality of transistors; the second conductive layer comprises at least one second adapter electrode; the third conductive layer comprises at least one third adapter electrode; and the second adapter electrode is simultaneously connected to the first adapter electrode and the active layer of one transistor through an adapter-structure via hole, and the third adapter electrode is connected to the active layer of another transistor through a single-hole-structure via hole. In the present disclosure, a top-gate bottom-layer connecting structure and a top gate structure are combined, thereby effectively improving the display resolution.
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