Chip, electronic device and chip manufacturing method

Abstract

A chip, an electronic device and a chip manufacturing method, which aim to solve the problem of the area of a chip being relatively large. In the chip, a pull-up tube is provided in a device layer, and the device layer is manufactured by using a front-end-of-line process; and a pull-down tube and a gating tube are provided in a metal interconnection layer, and the metal interconnection layer is manufactured by using a back-end-of-line process. Compared with the pull-up tube, the gating tube and the pull-down tube all being manufactured by using the front-end-of-line process, the number of devices manufactured by the front-end-of-line process can be reduced, and the area of the device layer is reduced, thus reducing the area of the chip.

Description

Chip, electronic device and chip manufacturing method

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on September 13, 2023, with application number 202311184415.4 and application name “Chips, electronic devices and chip manufacturing methods”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the technical field of storage devices, and specifically to a chip, an electronic device, and a chip manufacturing method. Background Art

[0003] Cache is a storage device located between the processor (e.g., the Central Processing Unit, or CPU) and the memory in a chip, typically consisting of static random access memory (SRAM). This memory and the logic circuits in the chip are both manufactured using front-end processes, resulting in a larger chip area.

[0004] Summary of the Invention

[0005] The embodiments of the present application provide a chip, an electronic device, and a chip manufacturing method, which can reduce the area of ​​the chip.

[0006] In a first aspect, an embodiment of the present application provides a chip comprising: a substrate, a device layer, and a metal interconnection layer; the device layer is arranged on the substrate, the device layer includes a logic circuit, and the device layer is configured to be manufactured in a front-end process; the metal interconnection layer is stacked on a side of the device layer away from the substrate, and the metal interconnection layer is configured to be manufactured in a back-end process; the chip also includes a static random access memory, the static random access memory includes: a gate tube, a pull-up tube, and a pull-down tube, the pull-up tube is arranged in the device layer, and the gate tube and the pull-down tube are arranged in the metal interconnection layer.

[0007] Through the above arrangement, the pull-up tube is arranged in the device layer, and the device layer is manufactured using the front-end process; the pull-down tube and the gate tube are arranged in the metal interconnection layer, and the metal interconnection layer is manufactured using the back-end process; compared with the case where the pull-up tube, the gate tube and the pull-down tube are all manufactured using the front-end process, the number of devices manufactured using the front-end process can be reduced, the area of ​​the device layer is reduced, and thus the area of ​​the chip is reduced.

[0008] In some embodiments that may include the above embodiments, the pull-up transistor includes a P-type transistor, and the gate transistor and the pull-down transistor are N-type transistors. Oxide semiconductor transistors manufactured in the back-end process are more easily made into N-type transistors, and the gate transistor and the pull-down transistor manufactured in the back-end process are N-type transistors, which can facilitate the manufacture of the gate transistor and the pull-down transistor.

[0009] In some embodiments that may include the above embodiments, the substrate is made of silicon, and the pull-up transistor comprises a silicon field-effect transistor. This arrangement further facilitates the fabrication of the pull-up transistor; in addition, the high uniformity of single-crystal silicon ensures high performance of the pull-up transistor.

[0010] In some embodiments that may include the above embodiments, the metal interconnect layer includes a first metal interconnect layer and a second metal interconnect layer, the first metal interconnect layer being located between the second metal interconnect layer and the device layer; and the gate transistor and the pull-down transistor are located within the first metal interconnect layer and the second metal interconnect layer. This arrangement can reduce the area of ​​the static random access memory and the chip compared to arrangements in which both the gate transistor and the pull-down transistor are located in the first metal interconnect layer or the second metal interconnect layer.

[0011] In some embodiments that may include the above embodiments, the gate transistor includes a first gate transistor and a second gate transistor, the pull-up transistor includes a first pull-up transistor and a second pull-up transistor, and the pull-down transistor includes a first pull-down transistor and a second pull-down transistor. The static random access memory includes a memory cell for storing data, and the memory cell is a 6T memory cell, comprising: a first gate transistor, a second gate transistor, a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, and a second pull-down transistor. With the above arrangement, a total of six transistors, namely, the first gate transistor, the second gate transistor, the first pull-up transistor, the second pull-up transistor, the first pull-down transistor, and the second pull-down transistor, constitute a memory cell for data storage. The first pull-up transistor and the first pull-down transistor constitute a first inverter, and the second pull-up transistor and the second pull-down transistor constitute a second inverter. The output of the first inverter is connected to the input of the second inverter to form a first storage node, and the output of the second inverter is electrically connected to the input of the first inverter to form a second storage node. The first inverter and the second inverter form a latch circuit.

[0012] In some embodiments that may include the above embodiments, one electrode of the first pull-up tube and the second pull-up tube are both connected to the first power line, the other electrode of the first pull-up tube is connected to the gate of the second pull-up tube, and the other electrode of the second pull-up tube is connected to the gate of the first pull-up tube; the gate of the first pull-up tube is also connected to one electrode of the second pull-down tube, the other electrode of the second pull-down tube is connected to the second power line, the gate of the second pull-down tube is also connected to the gate of the second pull-up tube, one electrode of the first pull-down tube is connected to the gate of the second pull-up tube, the other electrode of the first pull-down tube is connected to the second power line, and the gate of the first pull-down tube is connected to the gate of the first pull-up tube; the gate of the first pull-down tube is also connected to one electrode of the second selection tube, the other electrode of the second selection tube is connected to the inverted bit line, and the gate of the second selection tube is connected to the word line; one electrode of the first selection tube is connected to the gate of the second pull-down tube, the other electrode of the first selection tube is connected to the bit line, and the gate of the first selection tube is also connected to the word line.

[0013] In some embodiments that may include the above embodiments, the first gate transistor and the second gate transistor are located in the second metal interconnect layer, and the first pull-down transistor and the second pull-down transistor are located in the first metal interconnect layer. This arrangement ensures that the number of transistors in the first metal interconnect layer and the second metal interconnect layer is not excessive, thereby avoiding overly complex structures of the first metal interconnect layer and the second metal interconnect layer.

[0014] In some embodiments that may include the above embodiments, in the same memory cell, the gate of the first pull-up transistor and the gate of the second pull-up transistor are arranged parallel to and spaced apart from each other. The gate of the first pull-up transistor extends toward the second pull-up transistor, and the gate of the first pull-up transistor and the electrode of the second pull-up transistor are connected via a first contact structure. The gate of the second pull-up transistor extends toward the first pull-up transistor, and the gate of the second pull-up transistor and the electrode of the first pull-up transistor are connected via a second contact structure. With this arrangement, the first pull-up transistor and the second pull-up transistor form a structure that is substantially rotationally symmetrical around the center, and the center of symmetry can be the center of a line connecting the midpoint of the gate of the first pull-up transistor and the midpoint of the gate of the second pull-up transistor.

[0015] In some embodiments that may include the above embodiments, the gate of the first pull-down tube and the gate of the second pull-down tube are arranged parallel to and spaced apart from each other. The end of the gate of the first pull-down tube closest to the second pull-down tube is connected to the electrode of the second pull-down tube via a third contact structure, and the end of the gate of the second pull-down tube closest to the first pull-down tube is connected to the electrode of the second pull-down tube via a fourth contact structure. This arrangement allows the first and second pull-down tubes to form a substantially central rotationally symmetrical structure, with the center of symmetry being the center of a line connecting the midpoint of the gate of the first pull-down tube and the midpoint of the gate of the second pull-down tube.

[0016] In some embodiments that may include the above embodiments, the electrode of the first gate tube is connected to the fourth contact structure through the sixth contact structure, the fourth contact structure is also connected to the second contact structure, and the first storage node includes: the sixth contact structure, the fourth contact structure and the second contact structure; the electrode of the second gate tube is connected to the third contact structure through the seventh contact structure, the third contact structure is also connected to the first contact structure, and the second storage node includes: the seventh contact structure, the third contact structure and the first contact structure.

[0017] In some embodiments that may include the above embodiments, in each memory cell, the gate of the first gate tube and the gate of the second gate tube extend in the same direction within the second metal interconnect layer, so that the gate of the first gate tube and the gate of the second gate tube are arranged in parallel and spaced apart, thereby making the first gate tube and the second gate tube form a substantially centrally symmetrical structure, and the center of symmetry can be the center of a line connecting the midpoint of the gate of the first gate tube and the midpoint of the gate of the second gate tube.

[0018] In some embodiments that may include the above embodiments, the gates of the first gate transistors in the plurality of memory cells are integrally structured, and the gates of the second gate transistors in the plurality of memory cells are integrally structured. The gate of at least one first gate transistor in the plurality of memory cells is connected to the gate of at least one second gate transistor, and is also connected to a word line. In this configuration, the gates of the first and second gate transistors in the plurality of memory cells are connected to the word line, which can simplify the connection structure.

[0019] In some embodiments that may include the above embodiments, in the same memory cell, the gates of the first and second gate transistors are arranged parallel to and spaced apart from each other, and a first connection portion is further provided in the second metal interconnect layer. An end of the gate of the first gate transistor proximate to the second gate transistor is connected to an end of the gate of the second gate transistor proximate to the first gate transistor via the first connection portion, and the first connection portion is connected to a word line. With this arrangement, the gates of the first and second gate transistors in each memory cell are both connected to the word line via corresponding first connections. Compared to a case where the gates of the first and second gate transistors in multiple memory cells are all connected to the word line via the same fifth contact structure, this arrangement can reduce the parasitic resistance of the word line and improve the signal transmission response speed of the word line.

[0020] In some embodiments that may include the above embodiments, in the same memory cell, the gate of the first gate transistor and the gate of the second gate transistor are integrally formed, and a second connection portion is further provided within the second metal interconnect layer. The second connection portion is located between the first gate transistor and the second gate transistor, connected to the gate of the first gate transistor, and connected to a word line. In this configuration, the gates of the first gate transistor and the second gate transistor are integrally formed, simplifying the chip structure and facilitating chip fabrication. Furthermore, the gates of the first gate transistor and the second gate transistor in each memory cell are connected to the word line via a second connection portion, reducing parasitic resistance.

[0021] In some embodiments that may include the above embodiments, the word line is arranged on a side of the second metal interconnect layer away from the substrate, which facilitates the connection between the word line and the first gate transistor and the second gate transistor.

[0022] In some embodiments that may include the above embodiments, the first gate transistor and the first pull-down transistor are located in the first metal interconnect layer, and the second gate transistor and the second pull-down transistor are located in the second metal interconnect layer. This arrangement can also avoid overly complex structures of the first and second metal interconnect layers.

[0023] In some embodiments that may include the above-mentioned embodiments, the electrodes of the first gate tube and the first pull-down tube that are close to each other are an integral structure, and the electrodes of the second gate tube and the second pull-down tube that are close to each other are an integral structure. With this arrangement, there is no need to set up additional structures for connecting an electrode of the first gate tube and an electrode of the first pull-down tube, thereby simplifying the structure of the chip; in addition, an electrode of the first gate tube and an electrode of the first pull-down tube are an integral structure, and an electrode of the first gate tube and an electrode of the first pull-down tube can be formed simultaneously using the same process, thereby reducing the difficulty of chip manufacturing. Similarly, there is no need to set up additional structures for connecting an electrode of the second gate tube and an electrode of the second pull-down tube, thereby simplifying the structure of the chip; in addition, an electrode of the second gate tube and an electrode of the second pull-down tube are an integral structure, and an electrode of the second gate tube and an electrode of the second pull-down tube can be formed simultaneously using the same process, thereby reducing the difficulty of chip manufacturing.

[0024] In some embodiments that may include the above-mentioned embodiments, the metal interconnect layer includes a plurality of first dielectric layers and a plurality of second dielectric layers that are alternately stacked, and the dielectric constant of the first dielectric layer is less than the dielectric constant of the second dielectric layer. In other words, the first dielectric layer is a low-dielectric-constant material, and such a configuration can reduce the parasitic capacitance of the chip, thereby improving the performance of the chip. In addition, since the dielectric constant of the first dielectric layer is relatively low, its etching resistance is relatively poor (the etching selectivity is relatively large). By alternately stacking the first and second dielectric layers, and having different etching selectivities for the first and second dielectric layers, the etching of the metal interconnect layer can be facilitated, thereby reducing the difficulty of chip manufacturing.

[0025] In a second aspect, an embodiment of the present application further provides an electronic device, comprising: a mainboard and the chip as described above, wherein the chip is arranged on the mainboard.

[0026] The electronic device provided in the embodiments of the present application includes the chip in any of the above embodiments, so the two can solve the same technical problems and achieve the same technical effects.

[0027] In a third aspect, an embodiment of the present application further provides a chip manufacturing method, comprising:

[0028] A device layer and a pull-up tube located within the device layer are manufactured on a substrate using a front-end process. The device layer includes a logic circuit. A metal interconnect layer and a gate tube and a pull-down tube located within the metal interconnect layer are stacked and formed on the device layer using a back-end process. The static random access memory includes the gate tube, the pull-up tube, and the pull-down tube.

[0029] In some embodiments that may include the above embodiments, forming a metal interconnect layer and a gate transistor and a pull-down transistor located within the metal interconnect layer in a stacked manner on the device layer using a back-end process includes: forming a first metal interconnect layer and a second metal interconnect layer in a stacked manner on the device layer using a back-end process, with the first metal interconnect layer located between the second metal interconnect layer and the device layer; and disposing the gate transistor and the pull-down transistor within the first metal interconnect layer and the second metal interconnect layer. This arrangement can reduce the area of ​​the static random access memory and the chip compared to disposing both the gate transistor and the pull-down transistor in the first metal interconnect layer or the second metal interconnect layer.

[0030] In some embodiments that may include the above embodiments, the gate transistor includes a first gate transistor and a second gate transistor, the pull-up transistor includes a first pull-up transistor and a second pull-up transistor, and the pull-down transistor includes a first pull-down transistor and a second pull-down transistor; the static random access memory includes a storage unit for storing data, the storage unit being a 6T storage unit, the storage unit including: a first gate transistor, a second gate transistor, a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, and a second pull-down transistor; forming the first and second metal interconnect layers in a stacked manner on the device layer using a back-end process includes: forming the first metal interconnect layer and the first and second pull-down transistors located within the first metal interconnect layer in a stacked manner on the device layer using a back-end process; and forming the second metal interconnect layer in a stacked manner on the first metal interconnect layer and the first and second gate transistors located within the second metal interconnect layer in a back-end process. Such an arrangement ensures that the number of transistors in the first and second metal interconnect layers is not excessive, thereby preventing the structures of the first and second metal interconnect layers from being overly complex.

[0031] In some embodiments that may include the above embodiments, the gate transistor includes a first gate transistor and a second gate transistor, the pull-up transistor includes a first pull-up transistor and a second pull-up transistor, and the pull-down transistor includes a first pull-down transistor and a second pull-down transistor; the static random access memory includes a storage unit for storing data, the storage unit being a 6T storage unit, the storage unit including: a first gate transistor, a second gate transistor, a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, and a second pull-down transistor; and forming the first metal interconnect layer and the second metal interconnect layer in a stacked manner on the device layer using a back-end process includes: forming the first metal interconnect layer and the first pull-down transistor and the first gate transistor in the first metal interconnect layer in a stacked manner on the device layer using a back-end process; and forming the second metal interconnect layer and the second pull-down transistor and the second gate transistor in the second metal interconnect layer in a stacked manner on the first metal interconnect layer using a back-end process. This arrangement ensures that the number of transistors in the first metal interconnect layer and the second metal interconnect layer is not excessive, thereby preventing the structures of the first metal interconnect layer and the second metal interconnect layer from being overly complex.

[0032] In the chip manufactured by the chip manufacturing method provided in the embodiment of the present application, the pull-up tube is arranged in the device layer, and the device layer is manufactured using the front-end process; the pull-down tube and the gate tube are arranged in the metal interconnection layer, and the metal interconnection layer is manufactured using the back-end process; compared with the case where the pull-up tube, the gate tube and the pull-down tube are all manufactured using the front-end process, the number of devices manufactured by the front-end process can be reduced, the area of ​​the device layer is reduced, and thus the area of ​​the chip is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] FIG1 is a cross-sectional view of a chip provided in an embodiment of the present application;

[0034] FIG2 is a circuit diagram of a chip provided by an embodiment of the present application in which a gate transistor and a pull-down transistor are arranged on the same layer;

[0035] FIG3 is a schematic diagram showing the connection between a chip and a static random access memory in the related art;

[0036] FIG4 is a top view of a device layer in a chip provided by an embodiment of the present application when a gate transistor and a pull-down transistor are arranged on the same layer;

[0037] FIG5 is an exploded view of the same-layer arrangement of gate transistors and pull-down transistors in a chip according to an embodiment of the present application;

[0038] FIG6 is a top view of the first metal interconnect layer when the gate transistors and the pull-down transistors are arranged on the same layer in the chip according to an embodiment of the present application;

[0039] FIG7 is an enlarged view within the dotted box in FIG6 ;

[0040] FIG8 is a top view of the second metal interconnect layer when the gate transistors and the pull-down transistors are arranged on the same layer in the chip according to an embodiment of the present application;

[0041] FIG9 is an enlarged view within the dotted box in FIG8 ;

[0042] FIG10 is a cross-sectional view taken along line AA in FIG7 and FIG9;

[0043] FIG11 is a cross-sectional view taken along line BB in FIG8 ;

[0044] FIG12 is a top view of the second metal interconnect layer when the memory cell in the chip provided by an embodiment of the present application includes 8 transistors;

[0045] FIG13 is a top view of the third metal interconnect layer when a memory cell in a chip provided by an embodiment of the present application includes 8 transistors;

[0046] FIG14 is a circuit diagram of a memory cell in a chip provided by an embodiment of the present application including eight transistors;

[0047] FIG15 is a top view of the second metal interconnect layer when the gate of the first gate transistor and the gate of the second gate transistor are connected via the first connecting portion in the chip provided by an embodiment of the present application;

[0048] FIG16 is an enlarged view of the dotted box in FIG15 ;

[0049] FIG17 is a cross-sectional view taken along the CC line in FIG16 ;

[0050] FIG18 is a cross-sectional view taken along line DD in FIG16 ;

[0051] FIG19 is a top view of a first metal interconnect layer when the gate of a first gate transistor and the gate of a second gate transistor are integrated into one structure in a chip provided by an embodiment of the present application;

[0052] FIG20 is a top view of the second metal interconnect layer when the gate of the first gate transistor and the gate of the second gate transistor are an integrated structure in the chip provided by an embodiment of the present application;

[0053] FIG21 is a cross-sectional view taken along line EE in FIG20 ;

[0054] FIG22 is a top view of the first metal interconnect layer when the gate transistor and the pull-down transistor are arranged on the same layer in the chip according to an embodiment of the present application;

[0055] FIG23 is a top view of the second metal interconnect layer when the gate transistor and the pull-down transistor are arranged on the same layer in the chip according to an embodiment of the present application;

[0056] FIG24 is a cross-sectional view taken along the FF line in FIG22 and FIG23;

[0057] FIG25 is a circuit diagram of a chip provided by an embodiment of the present application in which a gate transistor and a pull-down transistor are arranged on the same layer;

[0058] Figure 26 is a block diagram of the chip provided in an embodiment of the present application.

[0059] Description of reference numerals:

[0060] 1: substrate; 10: core region; 20: peripheral region; 30: device layer; 40: metal interconnection layer; 41: first metal interconnection layer; 42: second metal interconnection layer; 43: gate; 110: chip; 120: static random access memory; 130: static random access memory; 140: logic circuit; 302: first conductive structure; 303: first conductive portion; 304: second conductive portion; 305: third dielectric layer; 306: fourth dielectric layer; 307: first contact structure; 308: second contact structure; 401: first dielectric layer; 402: second dielectric layer; 404: first connecting portion; 407: second conductive structure; 408: third contact structure; 409: fourth contact structure; 410: third conductive structure; 411: sixth contact structure; 412: seventh contact structure. DETAILED DESCRIPTION

[0061] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0062] In the following, the terms "first," "second," etc. are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the quantity of the technical features indicated. Therefore, a feature specified as "first," "second," etc. may explicitly or implicitly include one or more of the features.

[0063] In addition, in the embodiments of the present application, directional terms such as "up", "down", "left", "right", "horizontal" and "vertical" are defined relative to the orientation of the components in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they can change accordingly according to changes in the orientation of the components in the drawings.

[0064] In the embodiments of this application, unless otherwise specified or limited, the term "connection" should be understood in a broad sense. For example, "connection" can mean fixed connection, electrical connection, coupling connection, detachable connection, or integration; it can mean direct connection or indirect connection through an intermediate medium. Among them, coupling can be understood as direct coupling and / or indirect coupling, and "coupled connection" can be understood as direct coupling connection and / or indirect coupling connection.

[0065] An embodiment of the present application provides an electronic device, which may include a computer, a mobile phone, a server, etc. The electronic device includes a motherboard and a chip disposed on the motherboard. The chip is electrically connected to circuits on the motherboard and can perform data processing and calculations. The chip may be a central processing unit (CPU).

[0066] Referring to Figure 1 , in this embodiment of the present application, a chip includes a substrate 1 and a device layer 30 disposed on substrate 1. Substrate 1 serves as the foundation of the chip, supporting a film structure including device layer 30. For example, substrate 1 may be made of silicon, germanium, or the like, though this embodiment of the present application does not limit the material of substrate 1. Device layer 30 includes logic circuitry, which can be used for data processing, calculations, and the like.

[0067] In the above implementation, the chip further includes a metal interconnect layer 40, which is stacked on the side of the device layer 30 facing away from the substrate 1. The metal interconnect layer 40 is configured to be manufactured in a back-end process, and the device layer 30 is configured to be manufactured in a front-end process. It is understood that during manufacturing, the device layer 30 and the logic circuits within the device layer 30 can be first manufactured in a front-end process, and then the metal interconnect layer 40 can be manufactured on the device layer 30 in a back-end process. Exemplarily, the metal interconnect layer 40 may include a plurality of first dielectric layers 401 and a plurality of second dielectric layers 402 that are alternately stacked. The materials of the first dielectric layers 401 and the second dielectric layers 402 may include silicon oxide, silicon nitride, etc.

[0068] In some embodiments, the dielectric constant of the first dielectric layer 401 is lower than that of the second dielectric layer 402. In other words, the first dielectric layer 401 is made of a low-dielectric-constant material. This configuration can reduce the parasitic capacitance of the chip, thereby improving chip performance. Furthermore, because the dielectric constant of the first dielectric layer 401 is lower, its etching resistance is poor (the etching selectivity is relatively large). By alternately stacking the first and second dielectric layers 401, 402, and by having different etching selectivities, the etching of the metal interconnect layer 40 can be facilitated, thereby reducing the difficulty of chip manufacturing.

[0069] In some embodiments, the chip may further include at least one metal layer, which may be disposed on a first dielectric layer 401 or a second dielectric layer 402, and / or disposed within the device layer 30, and / or disposed on a side of the metal interconnect layer 40 facing away from the substrate 1. By patterning the metal layer, metal traces may be formed to facilitate circuit connections.

[0070] It is understandable that in the embodiment of the present application, logic circuits can also be provided in the metal interconnection layer 40 to prevent the logic circuits from being concentrated in the device layer 30. On the other hand, the density of the logic circuits can be increased, thereby improving the data calculation and processing capabilities of the chip.

[0071] As shown in FIG26 , the chip 110 in the embodiment of the present application further includes a static random access memory 130 (SRAM). The SRAM 130 can be used as a cache. The SRAM 130 is a memory between the logic circuit 140 and the memory, and is used to temporarily store data of the logic circuit 140. The chip 110 also includes an interface circuit 150 connected to the SRAM 130 and the logic circuit 140. The interface circuit 150 is used to connect to external devices. For example, in an implementation in which the chip 110 is a central processing unit, the interface circuit 150 can be electrically connected to the circuit on the motherboard to achieve a connection between the chip 110 and the motherboard.

[0072] As shown in Figure 2, in some embodiments, the static random access memory includes a storage unit, which is used to store data, wherein the storage unit may include a gate tube PG, a pull-up tube PU and a pull-down tube PD, the gate tube PG may include a first gate tube PG1 and a second gate tube PG2, the pull-up tube PU may include a first pull-up tube PU1 and a second pull-up tube PU2, and the pull-down tube PD may include a first pull-down tube PD1 and a second pull-down tube PD2.

[0073] Exemplarily, one electrode (source or drain) of the first pull-up tube PU1 and the second pull-up tube PU2 are both connected to the first power line VDD, the other electrode (drain or source) of the first pull-up tube PU1 is connected to the gate of the second pull-up tube PU2, and the other electrode (drain or source) of the second pull-up tube PU2 is connected to the gate of the first pull-up tube PU1; the gate of the first pull-up tube PU1 is also connected to one electrode of the second pull-down tube PD2, the other electrode of the second pull-down tube PD2 is connected to the second power line VSS, the gate of the second pull-down tube PD2 is also connected to the gate of the second pull-up tube PU2, one electrode of the first pull-down tube PD1 is connected to the gate of the second pull-up tube PU2, the other electrode of the first pull-down tube PD1 is connected to the second power line VSS, and the gate of the first pull-down tube PD1 is connected to the gate of the first pull-up tube PU1; the gate of the first pull-down tube PD1 is also connected to one electrode of the second gate tube PG2. The other electrode of the second gate transistor PG2 is connected to the inverted bit line BLB, and the gate of the second gate transistor PG2 is connected to the word line WL. One electrode of the first gate transistor PG1 is connected to the gate of the second pull-down transistor PD2, and the other electrode of the first gate transistor PG1 is connected to the bit line BL. The gate of the first gate transistor PG1 is also connected to the word line WL. The six transistors comprising the first gate transistor PG1, the second gate transistor PG2, the first pull-up transistor PU1, the second pull-up transistor PU2, the first pull-down transistor PD1, and the second pull-down transistor PD2 constitute a 6T memory cell (6T SRAM) for data storage. The first pull-up transistor PU1 and the first pull-down transistor PD1 form a first inverter, while the second pull-up transistor PU2 and the second pull-down transistor PD2 form a second inverter. The output of the first inverter is connected to the input of the second inverter to form a first storage node Q. The output of the second inverter is electrically connected to the input of the first inverter to form a second storage node QB. The first inverter and the second inverter form a latch circuit. In the above implementation, the first power line VDD can be configured to have a high level, and accordingly, the second power line VSS is configured to be grounded. It is understandable that the voltage of the first power line VDD can be reasonably set according to different situations so that the static random access memory can operate normally.

[0074] When writing data, exemplarily, the data stored in the initial state storage unit is "0". At this time, the second storage node QB can be a high level (storing "1"), the first storage node Q is a low level (storing "0"), the second pull-down tube PD2 and the first pull-up tube PU1 are cut off, the first pull-down tube PD1 and the second pull-up tube PU2 are turned on, and by setting the word line WL and the bit line BL to a high level and the inverted bit line BLB to a low level, the first selection tube PG1 and the second selection tube PG2 are both turned on, the bit line BL charges the first storage node Q through the first selection tube PG1, and the inverted bit line BLB discharges the second storage node QB through the second selection tube PG2, so that the second storage node QB is a low level and the first storage node Q is a high level, thereby completing the writing of "1".

[0075] When reading data, the bit line BL and the inverted bit line BLB are both in a high state. When the word line WL corresponding to the memory cell is high, the first gate transistor PG1 and the second gate transistor PG2 are both turned on, which is equivalent to connecting the first storage node Q to the bit line BL and the second storage node QB to the inverted bit line BLB. When reading "1", assuming that the first storage node Q stores "1", the second pull-down transistor PD2 and the first pull-up transistor PU1 are turned on, while the first pull-down transistor PD1 and the second pull-up transistor PU2 are turned off. The bit line BL remains in its original high state, while the inverted bit line BLB is discharged through the path formed by the second gate transistor PG2 and the second pull-down transistor PD2, thereby forming a voltage difference between the bit line BL and the inverted bit line BLB, thereby completing the reading of the data "1".

[0076] It can be understood that the number of transistors in the memory cell in the embodiment of the present application is not limited to 6. For example, the number of transistors in the memory cell can also be 8, 10, etc. The embodiment of the present application does not limit the number of transistors constituting the memory cell.

[0077] It will be appreciated that in the above implementation, the word lines WL, bit lines BL, bit line bar BLB, first power line VDD, and second power line VSS can be disposed within at least one metal layer. That is, the word lines WL, bit lines BL, bit line bar BLB, first power line VDD, and second power line VSS can be obtained by patterning the at least one metal layer. The embodiments of the present application do not limit the locations of the word lines WL, bit lines BL, bit line bar BLB, first power line VDD, and second power line VSS.

[0078] Continuing with FIG1 , in some embodiments, the device layer 30 may further include a first metal layer M1, which may be disposed adjacent to the metal interconnect layer 40. The pull-up transistor PU is disposed within the device layer 30. For example, the first power line VDD may be disposed within the device layer 30. Accordingly, the first power line VDD may be located within the first metal layer M1. That is, the first power line VDD may be obtained by patterning the first metal layer M1, thereby facilitating connection between the pull-up transistor PU and the first power line VDD.

[0079] In some embodiments, the pull-up tube PU includes a P-type transistor, the gate tube PG and the pull-down tube PD are N-type transistors, and the oxide semiconductor transistors produced in the back-end process are more easily made into N-type transistors. The gate tube PG and the pull-down tube PD produced in the back-end process are N-type transistors, which can facilitate the production of the gate tube PG and the pull-down tube PD.

[0080] In an implementation where substrate 1 is made of silicon, that is, substrate 1 is a silicon substrate, the pull-up transistor PU can accordingly be a silicon field-effect transistor (Si MOSFET), meaning the active region of the pull-up transistor PU can be made of single-crystal silicon. This arrangement further facilitates the fabrication of the pull-up transistor PU; in addition, the high uniformity of single-crystal silicon ensures high performance of the pull-up transistor PU.

[0081] The gate transistor PG and the pull-down transistor PD are disposed within the metal interconnect layer 40. Accordingly, a second power line VSS may be disposed within the metal interconnect layer 40 to facilitate connection of the pull-down transistor PD to the second power line VSS. In some implementations, the bit line BL, the bit line bar BLB, and the word line WL may be disposed on a side of the metal interconnect layer 40 facing away from the substrate 1.

[0082] As shown in Figure 1, in a chip provided by an embodiment of the present application, a device layer 30 is disposed on a substrate 1. Device layer 30 includes logic circuitry and is fabricated using a front-end process. A metal interconnect layer 40 is stacked on the side of device layer 30 facing away from substrate 1 and is fabricated using a back-end process. The static random access memory includes a gate transistor PG, a pull-up transistor PU, and a pull-down transistor PD. The pull-up transistor PU is disposed within device layer 30, while the gate transistor PG and the pull-down transistor PD are disposed within metal interconnect layer 40. This arrangement reduces the number of devices fabricated in the front-end process, reduces the area of ​​the device layer, and thus reduces the area of ​​the chip, compared to fabricating all the pull-up transistors PU, PG, and PD using a front-end process.

[0083] As shown in FIG3 , in the related art, the static random access memory 120 is covered on the chip 110, and the static random access memory 120 is connected to the chip 110 via through-silicon via technology. Through-silicon via technology requires bonding, resulting in a low yield rate. However, the chip provided in the embodiment of the present application (as shown in FIG1 ) sets the static random access memory inside the chip, and the static random access memory is connected to the circuit inside the chip without bonding, thereby improving the yield rate of the chip. In addition, the through-hole aperture in the through-silicon via technology is large, which will occupy a large chip area. However, in the processor in the embodiment of the present application, the static random access memory is set inside the chip, which can avoid occupying the surface space of the chip.

[0084] As shown in Figure 1, in some embodiments, the metal interconnect layer 40 includes a first metal interconnect layer 41 and a second metal interconnect layer 42, which are stacked together. The first metal interconnect layer 41 is located between the second metal interconnect layer 42 and the device layer 30, and the gate transistor PG and the pull-down transistor PD are located within the first metal interconnect layer 41 and the second metal interconnect layer 42. This arrangement can reduce the area of ​​the static random access memory and the chip compared to when both the gate transistor PG and the pull-down transistor PD are located in the first metal interconnect layer 41 or the second metal interconnect layer 42. Furthermore, the placement of the gate transistor PG and the pull-down transistor PD within the first metal interconnect layer 41 and the second metal interconnect layer 42 can reduce the impact on the existing back-end interconnect layer structure and reduce the impact of the addition of additional devices on manufacturing difficulty and chip performance.

[0085] In the embodiment of the present application, the gate transistor PG and the pull-down transistor PD are disposed in the first metal interconnect layer 41 and the second metal interconnect layer 42. Accordingly, the positional relationship between the gate transistor PG and the pull-down transistor PD can be various, which will be described below in multiple scenarios:

[0086] Scene 1

[0087] Continuing with reference to FIG1 , in this scenario, the gate tube PG can be set in the second metal interconnection layer 42, and correspondingly, the pull-down tube PD can be set in the first metal interconnection layer 41, so as to ensure that the number of transistors in the first metal interconnection layer 41 and the second metal interconnection layer 42 is not too large, thereby avoiding the structures of the first metal interconnection layer 41 and the second metal interconnection layer 42 being too complicated.

[0088] As shown in Figures 1 and 2, in an implementation in which the storage unit of the static random access memory includes 6 transistors, correspondingly, the gate tube PG includes a first gate tube PG1 and a second gate tube PG2, the pull-up tube PU includes a first pull-up tube PU1 and a second pull-up tube PU2, and the pull-down tube PD includes a first pull-down tube PD1 and a second pull-down tube PD2; the first gate tube PG1 and the second gate tube PG2 can both be arranged in the second metal interconnection layer 42, and the first pull-down tube PD1 and the second pull-down tube PD2 are both arranged in the first metal interconnection layer 41.

[0089] Please refer to Figure 4. In this scenario, the first pull-up tube PU1 and the second pull-up tube PU2 are arranged in the device layer 30 shown in Figure 1. The device layer 30 may include a third dielectric layer 305, a fourth dielectric layer 306 and a first metal layer M1 that are stacked, wherein the fourth dielectric layer 306 is located between the third dielectric layer 305 and the first metal layer M1, and the third dielectric layer 305 is arranged close to the substrate 1. The first pull-up tube PU1 and the second pull-up tube PU2 can be arranged in the third dielectric layer 305, and the first metal layer M1 can include a first power line VDD. Accordingly, the electrode (source or drain) of the first pull-up tube PU1 can be connected to the first power line VDD through the first conductive structure 302; illustratively, a first hole can be provided on the third dielectric layer 305, and the bottom of the first hole extends to the electrode of the first pull-up tube PU1. A second hole is provided on the fourth dielectric layer 306, and the second hole is connected to the first hole. The first conductive structure 302 may include a first conductive part 303 and a second conductive part 304. The first conductive part 303 is located in the first hole, and the second conductive part 304 is located in the second hole, and the second conductive part 304 is in contact with both the first conductive part 303 and the first power line VDD, and then the connection between the first pull-up tube PU1 and the first power line VDD can be achieved through the first conductive part 303 and the second conductive part 304. Similarly, the connection structure between the second pull-up tube PU2 and the first power line VDD is substantially similar to the connection structure between the first pull-up tube PU1 and the first power line VDD, and will not be described in detail here.

[0090] In some embodiments, the front-end process may include a process before forming the fourth dielectric layer 306. In the implementation method where the substrate 1 includes single crystal silicon, the front-end process may include a process for processing the single crystal silicon to form devices such as logic circuits and pull-up tubes PU; accordingly, the back-end process may include a process for forming the fourth dielectric layer 306 and a process after forming the fourth dielectric layer 306. An exemplary back-end process may include forming the fourth dielectric layer 306, the second conductive portion 304, the first metal layer M1, the pull-up tube PU, the second metal layer M2, the gate tube PG, the third metal layer M3 and the fourth metal layer M4, etc.

[0091] In other embodiments, the front-end process may include forming the fourth dielectric layer 306 and a process before forming the fourth dielectric layer 306. In an implementation in which the substrate 1 includes single crystal silicon, illustratively, the front-end process may include processing the single crystal silicon to form a logic circuit, a pull-up tube PU, a fourth dielectric layer 306, and a second conductive portion 304, etc.; accordingly, the back-end process may include a process after forming the fourth dielectric layer 306. illustratively, the back-end process may include forming a first metal layer M1, a pull-up tube PU, a second metal layer M2, a gate tube PG, a third metal layer M3, and a fourth metal layer M4, etc.

[0092] In the same storage unit, the gate 43 of the first pull-up tube PU1 and the gate 43 of the second pull-up tube PU2 extend in the same direction within the device layer 30 (vertical direction in Figure 4), and the gate 43 of the first pull-up tube PU1 and the gate 43 of the second pull-up tube PU2 are arranged in parallel and spaced apart. The gate 43 of the first pull-up tube PU1 extends toward the second pull-up tube PU2, and the gate 43 of the first pull-up tube PU1 is connected to the other electrode (drain or source) of the second pull-up tube PU2 through a first contact structure 307; similarly, the gate 43 of the second pull-up tube PU2 extends toward the first pull-up tube PU1, and the gate 43 of the second pull-up tube PU2 is connected to the other electrode of the first pull-up tube PU1 through a second contact structure 308. The first contact structure 307 and the second contact structure 308 can be disposed within the device layer 30, and the first contact structure 307 can contact the gate 43 of the first pull-up transistor PU1 or be connected to the gate 43 of the first pull-up transistor PU1 through a conductive via. The first contact structure 307 can contact or be connected to another electrode of the second pull-up transistor PU2 through a conductive via. Of course, a portion of the first contact structure 307 can also serve as another electrode of the second pull-up transistor PU2 to simplify the chip structure. Similarly, the second contact structure 308 can contact or be connected to the gate 43 of the second pull-up transistor PU2 through a conductive via. The second contact structure 308 can contact or be connected to another electrode of the first pull-up transistor PU1 through a conductive via. Of course, a portion of the second contact structure 308 can also serve as another electrode of the first pull-up transistor PU1. Through the above arrangement, the first pull-up transistor PU1 and the second pull-up transistor PU2 form a structure that is approximately rotationally symmetrical around the center (as shown in FIG. 5 ), with the center of symmetry being the center of a line connecting the midpoint of the gate 43 of the first pull-up transistor PU1 and the midpoint of the gate 43 of the second pull-up transistor PU2.

[0093] In the above implementation, the gate 43 of the first pull-up tube PU1 and the gate 43 of the second pull-up tube PU2 extend along the first direction (vertical direction in FIG. 4 ), and the width L1 of the gate 43 of the first pull-up tube PU1 and the gate 43 of the second pull-up tube PU2 along the second direction perpendicular to the first direction (horizontal direction in FIG. 4 ) is 5 nm-100 nm (such as 5 nm, 50 nm, 100 nm, etc.), and the distance L2 between the gate 43 of the first pull-up tube PU1 and the gate 43 of the second pull-up tube PU2 along the second direction can be 20 nm-200 nm (such as 20 nm, 100 nm, 200 nm, etc.). nm, etc.), the active area AA of the first pull-up tube PU1 and the active area AA of the second pull-up tube PU2 both extend along the second direction, and the width L4 of the active area AA of the first pull-up tube PU1 and the active area AA of the second pull-up tube PU2 along the first direction is 5nm-200nm (such as 5nm, 100nm, 200nm, etc.), the gate 43 of the first pull-up tube PU1 extends in a direction away from the second pull-up tube PU2, and the distance L5 beyond the active area of ​​the first pull-up tube PU1 is 5nm-50nm (such as 5nm, 10nm, 50nm, etc.), and the gate 43 of the second pull-up tube PU2 extends in a direction away from the second pull-up tube PU2. The distance L5 extending away from the first pull-up tube PU1 and exceeding the active area of ​​the second pull-up tube PU2 is 5nm-50nm (such as 5nm, 10nm, 50nm, etc.), the width L6 of the first conductive structure 302 along the first direction and along the second direction is 10nm-60nm (such as 10nm, 30nm, 60nm, etc.), the distance L7 between the gate 43 of the first pull-up tube PU1 and the second contact structure 308 along the second direction is 5nm-50nm (such as 5nm, 10nm, 50nm, etc.), and the distance L8 between the gate 43 of the second pull-up tube PU2 and the first contact structure 307 along the second direction is 5nm-50nm (such as 5nm, 10nm, 50nm, etc.). The distance L8 in the second direction is 5nm-50nm (such as 5nm, 10nm, 50nm, etc.), the distance L9 between the first contact structure 307 and the second contact structure 308 along the first direction is 20nm-100nm (such as 20nm, 50nm, 100nm, etc.), the width L10 of the first conductive structure 302 (such as the second conductive portion 304) along the second direction is 10nm-50nm (such as 10nm, 30nm, 50nm, etc.), and the width L6 of the first power line VDD along the second direction is 10nm-60nm (such as 10nm, 30nm, 60nm, etc.).

[0094] Referring to Figures 1, 6 and 7, in this scenario, the first pull-down tube PD1 and the second pull-down tube PD2 are located in the first metal interconnection layer 41 shown in Figure 1. Exemplarily, the first metal interconnection layer 41 may include at least one first dielectric layer 401 and at least one second dielectric layer 402 alternately stacked. The first pull-down tube PD1 and the second pull-down tube PD2 may be disposed in the same second dielectric layer 402; that is, the active regions, source electrodes, drain electrodes, and gate electrodes 43 of the first pull-down tube PD1 and the second pull-down tube PD2 may all be disposed in the same second dielectric layer 402. The first metal interconnect layer 41 may further include a second metal layer M2, the second metal layer M2 including a second power line VSS, the second power line VSS may be connected to one electrode (source or drain, such as S / D in FIG1 ) of the first pull-down tube PD1 through a second conductive structure 407, and similarly, the second power line VSS may be connected to one electrode of the second pull-down tube PD2 through another second conductive structure 407; the gate 43 of the first pull-down tube PD1 and the gate 43 of the second pull-down tube PD2 extend in the same direction within the first metal interconnect layer 41, and the gate 43 of the first pull-down tube PD1 and the gate 43 of the second pull-down tube PD2 are arranged in parallel and spaced apart, and an end of the gate 43 of the first pull-down tube PD1 close to the second pull-down tube PD2 may be connected to the other electrode of the second pull-down tube PD2 through a third contact structure 408, and an end of the gate 43 of the second pull-down tube PD2 close to the first pull-down tube PD1 may be connected through a fourth contact structure 409. Such arrangement enables the first pull-down tube PD1 and the second pull-down tube PD2 to form a substantially central rotationally symmetrical structure (as shown in FIG5 ), wherein the center of symmetry can be the center of the line connecting the midpoint of the gate 43 of the first pull-down tube PD1 and the midpoint of the gate 43 of the second pull-down tube PD2.

[0095] 6, 7 and 10, in some embodiments, the gate 43 of the first pull-down tube PD1 and the gate 43 of the second pull-down tube PD2 extend along a first direction (vertical direction in FIG. 7), and a width L11 of the gate 43 of the first pull-down tube PD1 and the gate 43 of the second pull-down tube PD2 along a second direction perpendicular to the first direction (horizontal direction in FIG. 7) is 5 nm-100 nm (e.g., 5 nm, 50 nm, 100 nm, etc.), the active area AA of the first pull-down tube PD1 and the active area AA of the second pull-down tube PD2 both extend along the second direction, and a width L12 of the active area AA of the first pull-down tube PD1 and the active area AA of the second pull-down tube PD2 along the first direction is 5 nm-200 nm (e.g., 5 nm, 100 nm, 200 nm, etc.), and the distance L12 of the active area AA of the first pull-down tube PD1 and the active area AA of the second pull-down tube PD2 along the first direction is 5 nm-200 nm. The distance L13 is 5nm-50nm (such as 5nm, 10nm, 50nm, etc.), the gate 43 of the first pull-down tube PD1 extends in a direction away from the second pull-up tube PU2, and the distance L14 beyond the active area AA of the first pull-down tube PD1 is 5nm-50nm (such as 5nm, 10nm, 50nm, etc.), the gate 43 of the second pull-down tube PD2 extends in a direction away from the first pull-down tube PD1, and the distance L14 beyond the active area AA of the second pull-down tube PD2 is 5nm-50nm (such as 5nm, 10nm, 50nm, etc.), the distance L15 between the gates 43 of the first pull-down tubes PD1 in adjacent storage cells is 5nm-80nm (such as 5nm, 40nm, 80nm, etc.), and the distance L15 between the gates 43 of the second pull-down tubes PD2 in adjacent storage cells is 5nm-80nm (such as 5nm, 40nm, 80nm, etc.).

[0096] Referring to Figures 8-10, in some implementations, the first gate transistor PG1 and the second gate transistor PG2 are disposed within the second metal interconnect layer 42 as shown in Figure 1. A third metal layer M3 and a fourth metal layer M4 are stacked on the side of the second metal interconnect layer 42 facing away from the substrate 1. The third metal layer M3 may be located between the fourth metal layer M4 and the second metal interconnect layer 42. A first dielectric layer 401 and / or a second dielectric layer 402 may be stacked between the third metal layer M3 and the fourth metal layer M4 to provide insulation between the third metal layer M3 and the fourth metal layer M4. For example, the third metal layer M3 may include a word line WL, and the fourth metal layer M4 may include a bit line BL and a bit bar BLB spaced apart from each other. The gates 43 of the first and second gate transistors PG1 and PG2 are both connected to the word line WL. Exemplarily, the gates 43 of the multiple first gate transistors PG1 in the multiple memory cells may be integrally formed, and correspondingly, the gates 43 of the second gate transistors PG2 in the multiple memory cells may be integrally formed. The gates 43 of at least one first gate transistor PG1 and the gates 43 of at least one second gate transistor PG2 in the multiple memory cells are connected via a fifth contact structure 428, and the fifth contact structure 428 is connected to the word line WL. In this configuration, the multiple memory cells can share a single fifth contact structure 428, i.e., the gates 43 of the first and second gate transistors PG1 and PG2 in the multiple memory cells are connected to the word line WL via a single fifth contact structure 428, thereby simplifying the connection structure. It can be understood that the fifth contact structure 428 can be an integral structure with the first gate 43 of the gate transistor PG1 and the second gate 43 of the gate transistor PG2, that is, the fifth contact structure 428 can be set on the same layer as the first gate 43 of the gate transistor PG1 and the second gate 43 of the gate transistor PG2 and formed at the same time. In this way, there is no need to additionally set the fifth contact structure 428, which can reduce the manufacturing difficulty and structural complexity.

[0097] Of course, in some implementations, the second metal interconnection layer 42 may include a third metal layer M3 , and the third metal layer M3 may be disposed away from the first metal interconnection layer 41 .

[0098] In the above implementation, one electrode of the first gate transistor PG1 is connected to the fourth contact structure 409 via the sixth contact structure 411, and the fourth contact structure 409 is further connected to the second contact structure 308, so that the sixth contact structure 411, the fourth contact structure 409, and the second contact structure 308 constitute a first storage node Q. The other electrode of the first gate transistor PG1 may be connected to the bit line BL via the third conductive structure 410. One electrode of the second gate transistor PG2 is connected to the third contact structure 408 via the seventh contact structure 412, and the third contact structure 408 is further connected to the first contact structure 307, so that the seventh contact structure 412, the third contact structure 408, and the first contact structure 307 constitute a second storage node QB. The other electrode of the second gate transistor PG2 is connected to the bar bit line BLB via another third conductive structure 410.

[0099] In some embodiments, the gate 43 of the first gate transistor PG1 and the gate 43 of the second gate transistor PG2 extend along a first direction (the vertical direction in FIG. 9 ). A width L16 of the gate 43 of the first gate transistor PG1 and the gate 43 of the second gate transistor PG2 along a second direction perpendicular to the first direction (the horizontal direction in FIG. 9 ) is 5 nm-100 nm (e.g., 5 nm, 50 nm, 100 nm, etc.). A distance L17 between the gate 43 of the first gate transistor PG1 and the seventh contact structure 412 along the second direction is 5 nm-50 nm (e.g., 5 nm, 30 nm, 50 nm, etc.). A distance L18 between the gate 43 of the second gate transistor PG2 and the sixth contact structure 411 along the second direction is 5 nm-50 nm (e.g., 5 nm, 30 nm, 50 nm, etc.). A width L19 of the sixth contact structure 411 and the seventh contact structure 412 along the second direction is 10 nm-60 nm (e.g., 10 nm, 30 nm, 60 nm, etc.).

[0100] In some implementations, in each memory cell, the gate 43 of the first gate transistor PG1 and the gate 43 of the second gate transistor PG2 extend in the same direction within the second metal interconnect layer 42, so that the gate 43 of the first gate transistor PG1 and the gate 43 of the second gate transistor PG2 are arranged in parallel and spaced apart. As a result, the first gate transistor PG1 and the second gate transistor PG2 form a substantially centrally symmetrical structure (as shown in FIG. 5 ), and the center of symmetry may be the center of a line connecting the midpoint of the gate 43 of the first gate transistor PG1 and the midpoint of the gate 43 of the second gate transistor PG2.

[0101] In this scenario, multiple memory cells can be arranged in an array. Accordingly, a first repeating unit array consisting of first pull-up transistors PU1 and second pull-up transistors PU2 is arranged in device layer 30, a second repeating unit array consisting of first pull-down transistors PD1 and second pull-down transistors PD2 is arranged in first metal interconnect layer 41, and a third repeating unit array consisting of first gate transistors PG1 and second gate transistors PG2 is arranged in second metal interconnect layer 42. The first pull-up transistors PU1 in each column can be connected to the same first power line VDD (sharing the first power line VDD), and similarly, the second pull-up transistors PU2 in each column can be connected to the same first power line VDD; the first pull-down transistors PD1 in each column can be connected to the same second power line VSS (sharing the second power line VSS), and similarly, the second pull-down transistors PD2 in each column can be connected to the same second power line VSS. This arrangement can reduce the number of first power lines VDD and second power lines VSS, thereby reducing the structural complexity of the chip and facilitating chip fabrication.

[0102] Referring to Figures 6, 8, and 11, in this scenario, when reading data, the current on the second power line VSS is large, and the second power line VSS itself has a certain resistance. Therefore, as the length of the second power line VSS increases, the voltage drop on the second power line VSS is more significant. Accordingly, the fourth metal layer M4 may also include an auxiliary power line PVSS. The second power line VSS corresponding to every certain number of memory cells can be connected to the auxiliary power line PVSS. By providing the auxiliary power line PVSS, the voltage drop on the second power line VSS can be reduced, thereby improving the performance of the chip. It is understood that, as shown in Figures 6 and 8, the auxiliary power line PVSS can be connected to the corresponding second power line VSS through the conductive via 429.

[0103] In this scenario, the first pull-up tube PU1 and the second pull-up tube PU2 can be silicon field-effect transistors, and accordingly, the first gate tube PG1, the second gate tube PG2, the first pull-down tube PD1 and the second pull-down tube PD2 can all be oxide semiconductor (Oxide Semiconductor, referred to as OS) field-effect transistors; that is, the active areas AA of the first gate tube PG1, the second gate tube PG2, the first pull-down tube PD1 and the second pull-down tube PD2 all include oxide semiconductor channels. Exemplarily, the first pull-up tube PU1 and the second pull-up tube PU2 can both be fin field effect transistors (Fin Field Effect Transistor for short Fin FET) to increase the gate control capability of the gate 43; accordingly, the first gate tube PG1, the second gate tube PG2, the first pull-down tube PD1 and the second pull-down tube PD2 can be planar channel structures (as shown in Figure 1). Of course, the first gate tube PG1, the second gate tube PG2, the first pull-down tube PD1 and the second pull-down tube PD2 can also be fin field effect transistors or other transistor structures, and the embodiments of the present application are not limited to this.

[0104] In an implementation in which the first gate transistor PG1, the second gate transistor PG2, the first pull-down transistor PD1, and the second pull-down transistor PD2 are all oxide semiconductor field-effect transistors, the gate 43 of the first gate transistor PG1 may include a gate metal, an electrode layer covering the gate metal, and a high dielectric constant layer (high k) covering the electrode layer, the high dielectric constant layer being in contact with the channel. Exemplarily, the material of the gate metal may include tungsten, the material of the electrode layer may include titanium nitride, tantalum nitride, molybdenum nitride, a TiAl-based alloy, etc., and the material of the high dielectric constant layer may include hafnium dioxide. The gate 43 of the second gate transistor PG2, the gate 43 of the first pull-down transistor PD1, and the gate 43 of the second pull-down transistor PD2 may have substantially the same structure as the gate 43 of the first gate transistor PG1, and will not be described in detail here. Through the above-mentioned arrangement, the electrode layer can prevent the gate 43 metal from diffusing outward, thereby avoiding the performance degradation of the oxide semiconductor field-effect transistor; in addition, the electrode layer can also have a work function.

[0105] Continuing with FIG. 1 , in some embodiments, the metal interconnect layer 40 may include multiple stacked first metal interconnect layers 41 and multiple stacked second metal interconnect layers 42. The multiple first metal interconnect layers 41 are located between the second metal interconnect layers 42 and the device layer 30. Each first metal interconnect layer 41 includes a first pull-down transistor PD1 and a second pull-down transistor PD2 (as shown in FIG. 7 ). The first pull-down transistors PD1 in each first metal interconnect layer 41 are connected in parallel, and the second pull-down transistors PD2 in each first metal interconnect layer 41 are connected in parallel. Similarly, each second metal interconnect layer 42 includes a first gate transistor PG1 and a second gate transistor PG2 (as shown in FIG. 9 ). The first gate transistors PG1 in each second metal interconnect layer 42 are connected in parallel, and the second gate transistors PG2 in each second metal interconnect layer 42 are connected in parallel. This parallel connection increases the equivalent current of the pull-down transistors and the gate transistors, thereby improving chip performance.

[0106] Continuing with reference to FIG1 , it can be understood that the static random access memory may include a core region 10 and a peripheral region 20 located at the edge of the core region 10. The 6T cell array of the static random access memory is arranged in the core region 10, that is, the core region 10 is mainly used for data storage. Each metal layer can also form an auxiliary circuit. The first power line VDD, the second power line VSS, the word line WL, the bit line BL, and the anti-bit line BLB can be led to the peripheral region 20 through the auxiliary circuit. The auxiliary line wheel can be connected to the device layer 30 through the conductive vias V1, V2, V3, and the corresponding part of the metal layer. Accordingly, the auxiliary circuit can be arranged in the peripheral region 20 to avoid the auxiliary circuit occupying the space of the core region 10. In addition, since the auxiliary circuit is arranged in the peripheral region 20, there is no need to add an additional metal layer to set the auxiliary circuit, which can avoid increasing the number of metal layers and reduce manufacturing costs.

[0107] In some embodiments, the third contact structure 408 and the fourth contact structure 409 can be fabricated simultaneously in the same process step and using the same material as the conductive via V1 connecting the second metal layer M2 and the first metal layer M1 in the peripheral region 20, thereby reducing the complexity of chip manufacturing. Similarly, the sixth contact structure 411 and the seventh contact structure 412 can be fabricated simultaneously in the same process step and using the same material as the conductive via V2 connecting the second metal layer M2 and the third metal layer M3 in the peripheral region 20, further reducing the complexity of chip manufacturing.

[0108] In this scenario, the conductive holes can be formed into through holes on the corresponding film layers, and then the conductors are filled in the through holes to achieve electrical connection between the two sides of the film layers. For example, the material of each metal layer can include metals such as copper and tungsten, and the material of the conductor, each contact structure, and each conductive structure can all include copper, tungsten, etc. In some embodiments, a conductive barrier layer is provided on the periphery of each metal layer, the periphery of the conductor, the periphery of each contact structure, and the periphery of each conductive structure. The material of the conductive barrier layer can include titanium nitride, tantalum nitride, ruthenium, cobalt, etc. The conductive barrier layer can prevent the internal conductive material from diffusing outward.

[0109] Scene 2

[0110] Referring to Figures 12-14 , this scenario differs from Scenario 1 in that each memory cell includes eight transistors (8T SRAM). For example, the memory cell may include: a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first gate transistor PG1, a second gate transistor PG2, a first read transistor R1, and a second read transistor R2. Accordingly, the metal interconnect layer 40 may include a first metal interconnect layer 41, a second metal interconnect layer 42, and a third metal interconnect layer, arranged in a stacked manner. The second metal interconnect layer 42 may be located between the first metal interconnect layer 41 and the third metal interconnect layer, and the first metal interconnect layer 41 may be located near the device layer 30. The first pull-up tube PU1 and the second pull-up tube PU2 can be arranged in the device layer 30, and the structures and connection methods of the first pull-up tube PU1 and the second pull-up tube PU2 can be the same as those in scenario 1 (as shown in FIG4 ); the first pull-down tube PD1 and the second pull-down tube PD2 are arranged in the first metal interconnection layer 41, and the structures and connection methods of the first pull-down tube PD1 and the second pull-down tube PD2 can be the same as those in scenario 1 (as shown in FIG7 ); as shown in FIG12 , the first read tube R1 and the second read tube R2 can be arranged in the second metal interconnection layer 42, the gate 43 of the first read tube R1 is connected to the first word line RWL, one electrode of the first read tube R1 is connected to one electrode of the second read tube R2, the other electrode of the first read tube R1 can be connected to the first bit line RBL through the fourth conductive structure 415, the gate 43 of the second read tube R2 can be connected to the third contact structure 408 through the eighth contact structure 413, and the second read tube R 2 is connected to the second power supply line VSS through another fourth conductive structure 415; the first gate transistor PG1 and the second gate transistor PG2 can be arranged in the third metal interconnection layer, and the structures of the first gate transistor PG1 and the second gate transistor PG2 can be substantially the same as those in scenario 1. The gate 43 of the first gate transistor PG1 and the gate 43 of the second gate transistor PG2 can both be connected to the second word line WWL. One electrode of the first gate transistor PG1 is connected to the ninth contact structure 414 in the second metal interconnection layer 42 through the sixth contact structure 411, and the ninth contact structure 414 is connected to the fourth contact structure 409. The other electrode of the first gate transistor PG1 is connected to the third bit line WBL through the third conductive structure 410. One electrode of the second gate transistor PG2 is connected to the eighth contact structure 413 through the seventh contact structure 412. The other electrode of the second gate transistor PG2 is connected to the second bit line WBLB through another third conductive structure 410.

[0111] In the above implementation, a first metal layer M1 may be provided in the device layer 30, and the first power line VDD may be located in the first metal layer M1; a second metal layer M2 may be provided in the first metal interconnection layer 41, and the second power line VSS may be provided in the second metal layer M2; a third metal layer M3, a fourth metal layer M4 and a fifth metal layer may be provided in the second metal interconnection layer 42, and the first word line RWL and the first bit line RBL may be provided in any one or more of the third metal layer M3, the fourth metal layer M4 and the fifth metal layer; a sixth metal layer and a seventh metal layer may be provided in the third metal interconnection layer, and the second bit line WBLB, the second word line WWL and the third bit line WBL may be provided in the sixth metal layer and / or the seventh metal layer.

[0112] It is understandable that the first power line VDD, the second power line VSS, the first word line RWL, the first bit line RBL, the second bit line WBLB, the second word line WWL and the third bit line WBL can also be separately wired through other metal layers of the chip, which is not limited in this scenario.

[0113] Scene 3

[0114] Referring to Figures 15 to 18, this scenario differs from Scenario 1 in that the connection structure of the gate 43 of the first gate transistor PG1 and the gate 43 of the second gate transistor PG2 is different. In this scenario, the gate 43 of the first gate transistor PG1 and the gate 43 of the second gate transistor PG2 are arranged in parallel and spaced apart in the second metal interconnect layer 42 (as shown in Figure 1). A first connecting portion 404 is also provided in the second metal interconnect layer 42. An end of the gate 43 of the first gate transistor PG1 close to the second gate transistor PG2 and an end of the gate 43 of the second gate transistor PG2 close to the first gate transistor PG1 are connected via the first connecting portion 404. The first connecting portion 404 can be provided between the first gate transistor PG1 and the second gate transistor PG2. The first connecting portion 404 is connected to the word line WL. With this arrangement, the gate 43 of the first gate transistor PG1 and the gate 43 of the second gate transistor PG2 in each memory cell are connected to the word line WL through the corresponding first connection portion 404. Compared with a case where the gate 43 of the first gate transistor PG1 and the gate 43 of the second gate transistor PG2 in multiple memory cells are connected to the word line WL through the same fifth contact structure, the parasitic resistance of the word line WL can be reduced and the signal transmission response speed of the word line WL can be improved.

[0115] It can be understood that the first connection portion 404 can be provided on the side of the gate 43 of the first gate transistor PG1 and the gate 43 of the second gate transistor PG2 away from the device layer, and the first connection portion 404 is located on the side of the third metal layer M3 close to the device layer, so that the gate 43 corresponding to the first connection portion 404 is connected to the word line WL.

[0116] 16 and 17 , in this scenario, the first connecting portion 404 is located between the first gate transistor PG1 and the second gate transistor PG2. This configuration allows the gate 43 of the first gate transistor PG1 to extend only toward the second gate transistor PG2 to the first connecting portion 404. This reduces the extension length of the gate 43 of the first gate transistor PG1, thereby allowing the seventh contact structure 412 to extend toward the gate 43 of the first gate transistor PG1 in a direction perpendicular to the gate 43 of the first gate transistor PG1. This increases the volume of the seventh contact structure 412, thereby facilitating connection between the seventh contact structure 412 and the third contact structure 408. Furthermore, this increases the contact area between the seventh contact structure 412 and the third contact structure 408, thereby reducing the connection resistance between the seventh contact structure 412 and the third contact structure 408. Similarly, the gate 43 of the second gate transistor PG2 only extends toward the first gate transistor PG1 to the first connecting portion 404, which can reduce the extension length of the gate 43 of the second gate transistor PG2. As a result, the sixth contact structure 411 can be extended toward the gate 43 of the second gate transistor PG2 in a direction perpendicular to the gate 43 of the first gate transistor PG1, thereby increasing the volume of the sixth contact structure 411 to facilitate the connection between the sixth contact structure 411 and the fourth contact structure 409. In addition, the contact area between the sixth contact structure 411 and the fourth contact structure 409 can also be increased, thereby reducing the connection resistance between the sixth contact structure 411 and the fourth contact structure 409.

[0117] Exemplarily, the gate 43 of the first gate tube PG1 and the gate 43 of the second gate tube PG2 extend along the first direction (vertical direction in Figure 16), and the distance L20 between the active area AA of the first gate tube PG1 and the first connecting portion 404 along the first direction is 5nm-50nm (such as 5nm, 30nm, 50nm, etc.), and the distance L20 between the active area AA of the second gate tube PG2 and the first connecting portion along the first direction is 5nm-50nm (such as 5nm, 30nm, 50nm, etc.).

[0118] As shown in Figures 15 and 19, in this scenario, the fourth metal layer M4 may also include an auxiliary power line PVSS. The second power line VSS corresponding to every certain number of memory cells may be connected to the auxiliary power line PVSS. By providing the auxiliary power line PVSS, the voltage drop on the second power line VSS can be reduced, thereby improving chip performance. It is understood that the auxiliary power line PVSS can be connected to the corresponding second power line VSS through a conductive via 429.

[0119] Scene 4

[0120] Referring to Figures 20 and 21 , this scenario differs from Scenario 1 in that, within the same memory cell, the gate 43 of the first gate transistor PG1 and the gate 43 of the second gate transistor PG2 are integrated. That is, the gates 43 of the first gate transistor PG1 and the gates 43 of the second gate transistor PG2 are short-circuited in their extending direction. A second connecting portion 416 is also provided within the second metal interconnect layer 42. This second connecting portion 416 is located between the first gate transistor PG1 and the second gate transistor PG2, connected to the gate 43 of the first gate transistor PG1, and connected to the word line WL. This integrated structure of the gates 43 of the first gate transistor PG1 and the second gate transistor PG2 simplifies the structure of the SRAM and facilitates chip fabrication. Furthermore, the gates 43 of the first gate transistor PG1 and the gate 43 of the second gate transistor PG2 in each memory cell are connected to the word line WL via a single second connecting portion 416, reducing parasitic resistance.

[0121] In the above implementation, the gate 43 of the first gate transistor PG1 and the gate 43 of the second gate transistor PG2 extend along the same straight line. This arrangement can reduce the width of the first gate transistor PG1 and the second gate transistor PG2 in a direction perpendicular to the straight line, thereby reducing the size occupied by the first gate transistor PG1 and the second gate transistor PG2 in the direction perpendicular to the straight line, thereby improving the compactness of the chip structure. In addition, the seventh contact structure 412 can be extended in a direction perpendicular to the gate 43 of the second gate transistor PG2, away from the gate 43 of the second gate transistor PG2, to increase the volume of the seventh contact structure 412, thereby facilitating connection between the seventh contact structure 412 and the third contact structure 408 (as shown in FIG. 7 ). Furthermore, this can also increase the contact area between the seventh contact structure 412 and the third contact structure 408, thereby reducing the connection resistance between the seventh contact structure 412 and the third contact structure 408. Similarly, the sixth contact structure 411 can be extended away from the first gate transistor PG1 in a direction perpendicular to the gate electrode 43 of the first gate transistor PG1 to increase the volume of the sixth contact structure 411, thereby facilitating the connection between the sixth contact structure 411 and the fourth contact structure 409 (as shown in FIG. 7 ). In addition, the contact area between the sixth contact structure 411 and the fourth contact structure 409 can also be increased, thereby reducing the connection resistance between the sixth contact structure 411 and the fourth contact structure 409.

[0122] In this scenario, the projection of the word line WL on the second metal interconnect layer 42 can cover the corresponding gates 43 of the first gate transistor PG1 and the second gate transistor PG2. Accordingly, the second connecting portion 416 can be located between the first gate transistor PG1 and the second gate transistor PG2, and approximately in the middle position between the first gate transistor PG1 and the second gate transistor PG2, so that the current paths between the first gate transistor PG1 and the second gate transistor PG2 and the word line WL are the same, thereby ensuring that the voltages of the gates 43 of the first gate transistor PG1 and the second gate transistor PG2 are approximately equal.

[0123] Scene 5

[0124] 22 to 24 , the difference between this scenario and scenario one is that the first gate tube PG1 and the first pull-down tube PD1 are located in the first metal interconnection layer 41, and correspondingly, the second gate tube PG2 and the second pull-down tube PD2 are located in the second metal interconnection layer 42; alternatively, the first gate tube PG1 and the first pull-down tube PD1 are located in the second metal interconnection layer 42, and correspondingly, the second gate tube PG2 and the second pull-down tube PD2 are located in the first metal interconnection layer 41.

[0125] In an implementation mode in which the first gate tube PG1 and the first pull-down tube PD1 are located in the first metal interconnect layer 41, and the second gate tube PG2 and the second pull-down tube PD2 are located in the second metal interconnect layer 42, one electrode of the first pull-up tube PU1 and the second pull-up tube PU2 are both connected to the first power line VDD (as shown in FIG25 ), the other electrode of the first pull-up tube PU1 is connected to the gate 43 of the second pull-up tube PU2, and the other electrode of the second pull-up tube PU2 is connected to the gate 43 of the first pull-up tube PU1; the gate 43 of the first pull-up tube PU1 is also connected to one electrode of the second pull-down tube PD2, the other electrode of the second pull-down tube PD2 is connected to a second power line VSS, and the gate 43 of the second pull-down tube PD2 is connected to the second pull-up tube PU1. PU2, one electrode of the first pull-down transistor PD1 is connected to the gate 43 of the second pull-up transistor PU2, the other electrode of the first pull-down transistor PD1 is connected to another second power supply line VSS, the gate 43 of the first pull-down transistor PD1 is connected to the gate 43 of the first pull-up transistor PU1, one electrode of the first gate transistor PG1 is connected to the gate 43 of the second pull-down transistor PD2, the other electrode of the first gate transistor PG1 is connected to the bit line BL, the gate 43 of the first gate transistor PG1 is connected to a word line WL, one electrode of the second gate transistor PG2 is connected to the gate 43 of the first pull-down transistor PD1, the other electrode of the second gate transistor PG2 is connected to the bar bit line BLB, and the gate 43 of the second gate transistor PG2 is connected to another word line WL. The six transistors of the first gate transistor PG1, the second gate transistor PG2, the first pull-up transistor PU1, the second pull-up transistor PU2, the first pull-down transistor PD1, and the second pull-down transistor PD2 constitute a storage unit for data storage.

[0126] In the above implementation, one electrode of the first gate tube PG1, one electrode of the first pull-down tube PD1, the gate 43 of the second pull-down tube PD2, and the gate 43 of the second pull-up tube PU2 are connected to form a first storage node Q; one electrode of the second gate tube PG2, one electrode of the second pull-down tube PD2, the gate 43 of the first pull-down tube PD1, and the gate 43 of the first pull-up tube PU1 are connected to form a second storage node QB.

[0127] As shown in Figures 22 and 24 , the first gate transistor PG1 and the first pull-down transistor PD1 are located within the first metal interconnect layer 41, and one electrode of the first gate transistor PG1 is connected to one electrode of the first pull-down transistor PD1. Accordingly, the electrodes of the first gate transistor PG1 and the first pull-down transistor PD1 that are adjacent to each other can be configured as an integrated structure. This configuration eliminates the need for additional structures for connecting one electrode of the first gate transistor PG1 to one electrode of the first pull-down transistor PD1, simplifying the chip structure. Furthermore, since one electrode of the first gate transistor PG1 and one electrode of the first pull-down transistor PD1 are integrated, they can be formed simultaneously using the same process, thereby reducing the difficulty of chip manufacturing. It is understood that one electrode of the first gate transistor PG1 and one electrode of the first pull-down transistor PD1 can be connected to the second contact structure 308 shown in FIG. 4 via the tenth contact structure 417. The other electrode of the first gate transistor PG1 is connected to the bit line via the sixth conductive structure 419. The other electrode of the first pull-down transistor PD1 is connected to the second source line VSS via the fifth conductive structure 418. The gate 43 of the first pull-down transistor PD1 is connected to the first contact structure 307 shown in FIG. 4 via the eleventh contact structure 420. The gate 43 of the first gate transistor PG1 is connected to the word line WL. Exemplarily, the second power line VSS is located within the second metal layer M2 to reduce the distance between the second power line VSS and the first gate transistor PG1 and the first pull-down transistor PD1, thereby facilitating connection.

[0128] In some embodiments, the active areas AA of the first gate transistor PG1 and the first pull-down transistor PD1 may also be an integrated structure, that is, the active areas AA of the first gate transistor PG1 and the active areas AA of the second gate transistor PG2 may be formed simultaneously using the same process to further reduce the difficulty of chip manufacturing.

[0129] Referring to Figures 23 and 24 , similarly, the second gate transistor PG2 and the second pull-down transistor PD2 are located within the second metal interconnect layer 42, and one electrode of the second gate transistor PG2 is connected to one electrode of the second pull-down transistor PD2. Accordingly, the electrodes of the second gate transistor PG2 and the second pull-down transistor PD2 that are adjacent to each other can be configured as an integrated structure. This configuration eliminates the need for additional structures for connecting one electrode of the second gate transistor PG2 to one electrode of the second pull-down transistor PD2, thereby simplifying the chip structure. Furthermore, since one electrode of the second gate transistor PG2 and one electrode of the second pull-down transistor PD2 are an integrated structure, one electrode of the second gate transistor PG2 and one electrode of the second pull-down transistor PD2 can be formed simultaneously using the same process, thereby reducing the difficulty of chip manufacturing. It can be understood that one electrode of the second gate transistor PG2 and one electrode of the second pull-down transistor PD2 are connected to the eleventh contact structure 420 via the thirteenth contact structure 423, the gate electrode 43 of the second gate transistor PG2 is connected to the word line, and the other electrode of the second gate transistor PG2 is connected to the bar bit line BLB via the eighth conductive structure 424. The gate electrode 43 of the second pull-down transistor PD2 can be connected to the tenth contact structure 417 via the twelfth contact structure 421, and the other electrode of the second pull-down transistor PD2 can be connected to the second power line VSS via the seventh conductive structure 422. Exemplarily, the second power line VSS is located within the fourth metal layer M4 to reduce the distance between the second power line VSS and the second gate transistor PG2 and the second pull-down transistor PD2, thereby facilitating connection.

[0130] In some embodiments, the active area AA of the second gate tube PG2 and the second pull-down tube PD2 can also be an integrated structure, that is, the active area AA of the second gate tube PG2 and the active area AA of the second pull-down tube PD2 can be formed simultaneously using the same process to further reduce the difficulty of chip manufacturing.

[0131] In this scenario, the gate 43 of the first gate transistor PG1 is connected to a word line WL. Exemplarily, the word line WL may be located within the third metal layer M3. This configuration reduces the distance between the word line WL and the gate 43 of the first gate transistor PG1, facilitating connection. The gate 43 of the second gate transistor PG2 is connected to another word line WL. The word line WL may be located within the fourth metal layer M4. This reduces the distance between the word line WL and the gate 43 of the second gate transistor PG2, facilitating connection.

[0132] The present invention also provides a chip manufacturing method, including:

[0133] S101: a device layer and a pull-up tube located in the device layer are manufactured on a substrate using a front-end process, wherein the device layer includes a logic circuit.

[0134] As shown in FIG1 , for example, a pull-up tube PU and a logic circuit can be manufactured on a substrate 1 using a front-end process, and then a third dielectric layer 305 is formed on the substrate 1 . The third dielectric layer 305 covers the substrate 1 and the logic circuit and the pull-up tube PU located on the substrate 1 .

[0135] In some embodiments, after forming the third dielectric layer 305, a fourth dielectric layer 306 may be formed on the third dielectric layer 305, and a first metal layer M1 may be formed on the fourth dielectric layer 306. For example, the first metal layer M1 and the first power line VDD may be formed by processes such as patterning, etching, and deposition.

[0136] In the above implementation, before forming the first metal layer M1, a first hole can be formed in the third dielectric layer 305 by etching, and a second hole can be formed in the fourth dielectric layer 306. The first hole contacts one electrode of the pull-up transistor PU, and the second hole is connected to the first hole. Thereafter, a first conductive portion 303 is formed in the first hole, and a second conductive portion 304 is formed in the second hole. The first conductive portion 303 contacts one electrode of the pull-up transistor PU, and the first conductive portion 303 also contacts the second conductive portion 304. After forming the first power line VDD, the first power line VDD covers at least a portion of the second conductive portion 304, thereby establishing a connection between the first power line VDD and one electrode of the pull-up transistor PU via the first conductive portion 303 and the second conductive portion 304.

[0137] In the embodiment of the present application, after forming the device layer 30, the following steps are further included:

[0138] S102: forming a metal interconnection layer and a gate tube and a pull-down tube located in the metal interconnection layer in a stacked manner on the device layer by adopting a back-end process.

[0139] It is understood that the metal interconnect layer 40 and the gate transistor and pull-down transistor PD located within the metal interconnect layer 40 are formed using a back-end process. Accordingly, in the static random access memory including the gate transistor, the pull-up transistor PU, and the pull-down transistor PD, the pull-up transistor PU is located in the device layer 30, and the gate transistor and the pull-down transistor PD are located within the metal interconnect layer 40, so that the static random access memory is located inside the chip.

[0140] In some embodiments, the pull-up tube PU is a P-type transistor, the gate tube and the pull-down tube PD are N-type transistors. The oxide semiconductor transistors produced in the back-end process are more easily made into N-type transistors. The gate tube PG and the pull-down tube PD produced in the back-end process are N-type transistors, which can facilitate the production of the gate tube PG and the pull-down tube PD.

[0141] In some embodiments, the substrate 1 may be made of silicon. In other words, the substrate 1 is a silicon substrate. Accordingly, the pull-up transistor PU may be a silicon field-effect transistor, meaning that the active region of the pull-up transistor PU may be made of single-crystal silicon. This configuration further facilitates the fabrication of the pull-up transistor PU.

[0142] In the above implementation, the metal interconnection layer 40 and the gate transistor PG and the pull-down transistor PD located in the metal interconnection layer 40 are formed on the device layer 30 by using a back-end process, including:

[0143] A first metal interconnect layer 41 and a second metal interconnect layer 42 are stacked on the device layer 30 using a back-end process. The first metal interconnect layer 41 is located between the second metal interconnect layer 42 and the device layer 30. The gate transistor PG and the pull-down transistor PD are disposed within the first and second metal interconnect layers 41, 42. This arrangement reduces the area of ​​the static random access memory (SRAM) and the chip, compared to disposing both the gate transistor PG and the pull-down transistor PD in either the first or second metal interconnect layer 41, 42.

[0144] In an implementation in which a storage unit of a static random access memory includes 6 transistors, correspondingly, the gate tube PG includes a first gate tube PG1 and a second gate tube PG2, the pull-up tube PU includes a first pull-up tube PU1 and a second pull-up tube PU2, and the pull-down tube PD includes a first pull-down tube PD1 and a second pull-down tube PD2.

[0145] In some embodiments, forming the first metal interconnect layer 41 and the second metal interconnect layer 42 in a stacked manner on the device layer 30 using a back-end process includes: forming the first metal interconnect layer 41 and the first and second pull-down transistors PD1 and PD2 in a stacked manner on the device layer 30 using a back-end process. Subsequently, forming the second metal interconnect layer 42 and the first and second gate transistors PG1 and PG2 in a stacked manner on the first metal interconnect layer 41 using a back-end process. In other words, the first and second gate transistors PG1 and PG2 are both disposed in the second metal interconnect layer 42, and the first and second pull-down transistors PD1 and PD2 are both disposed in the first metal interconnect layer 41. This arrangement ensures that the number of transistors in the first and second metal interconnect layers 41 and 42 is not excessive, thereby preventing overly complex structures in the first and second metal interconnect layers 41 and 42.

[0146] In other embodiments, forming the first metal interconnect layer 41 and the second metal interconnect layer 42 in a stacked manner on the device layer 30 using a back-end process includes: forming the first metal interconnect layer 41, and the first pull-down transistor PD1 and the first gate transistor PG1 located within the first metal interconnect layer 41, in a stacked manner on the device layer 30 using a back-end process. Subsequently, forming the second metal interconnect layer 42, and the second pull-down transistor PD2 and the second gate transistor PG2 located within the second metal interconnect layer 42, in a stacked manner on the first metal interconnect layer 41 using a back-end process. This arrangement ensures that the number of transistors within each of the first and second metal interconnect layers 41, 42, is not excessive, thereby preventing the structures of the first and second metal interconnect layers 41, 42 from becoming overly complex.

[0147] In the chip fabricated using the chip fabrication method provided in the embodiments of the present application, the device layer 30 includes logic circuits and is fabricated using a front-end process. A metal interconnect layer 40 is stacked and disposed on the side of the device layer 30 facing away from the substrate 1 and is fabricated using a back-end process. The static random access memory includes a gate transistor PG, a pull-up transistor PU, and a pull-down transistor PD. The pull-up transistor PU is disposed within the device layer 30, while the gate transistor PG and the pull-down transistor PD are disposed within the metal interconnect layer 40. This arrangement reduces the number of devices fabricated using the front-end process, reduces the area of ​​the device layer, and thus reduces the area of ​​the chip.

[0148] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0149] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip, characterized in that: include: substrate; A device layer, the device layer is disposed on the substrate, the device layer includes a logic circuit, and the device layer is configured to be manufactured in a front-end process; A metal interconnection layer, the metal interconnection layer is stacked and arranged on a side of the device layer away from the substrate, and the metal interconnection layer is configured to be manufactured in a back-end process; A static random access memory comprises: a gate tube, a pull-up tube and a pull-down tube, wherein the pull-up tube is arranged in the device layer, and the gate tube and the pull-down tube are arranged in the metal interconnection layer.

2. The chip according to claim 1, characterized in that: The metal interconnection layer includes a first metal interconnection layer and a second metal interconnection layer which are stacked, wherein the first metal interconnection layer is located between the second metal interconnection layer and the device layer; the gate tube and the pull-down tube are arranged in the first metal interconnection layer and the second metal interconnection layer.

3. The chip according to claim 2, characterized in that: The gate tube includes a first gate tube and a second gate tube, the pull-up tube includes a first pull-up tube and a second pull-up tube, and the pull-down tube includes a first pull-down tube and a second pull-down tube; the static random access memory includes a storage unit, the storage unit is used to store data, the storage unit is a 6T storage unit, and the storage unit includes: the first gate tube, the second gate tube, the first pull-up tube, the second pull-up tube, the first pull-down tube and the second pull-down tube.

4. The chip according to claim 3, characterized in that: The first gate tube and the second gate tube are located in the second metal interconnection layer, and the first pull-down tube and the second pull-down tube are located in the first metal interconnection layer.

5. The chip according to claim 4, characterized in that: In the same storage unit, the gate of the first pull-up tube and the gate of the second pull-up tube are arranged in parallel and spaced apart, the gate of the first pull-up tube extends toward the second pull-up tube, and the gate of the first pull-up tube is connected to the electrode of the second pull-up tube through a first contact structure; the gate of the second pull-up tube extends toward the first pull-up tube, and the gate of the second pull-up tube is connected to the electrode of the first pull-up tube through a second contact structure.

6. The chip according to claim 5, characterized in that: The gate of the first pull-down tube and the gate of the second pull-down tube are arranged in parallel and at intervals, the gate of the first pull-down tube is connected to the electrode of the second pull-down tube at one end close to the second pull-down tube through a third contact structure, and the gate of the second pull-down tube is connected to the electrode of the second pull-down tube at one end close to the first pull-down tube through a fourth contact structure.

7. The chip according to claim 6, characterized in that: The electrode of the first gate tube is connected to the fourth contact structure through a sixth contact structure, and the fourth contact structure is also connected to the second contact structure. The first storage node includes: the sixth contact structure, the fourth contact structure and the second contact structure; the electrode of the second gate tube is connected to the third contact structure through a seventh contact structure, and the third contact structure is also connected to the first contact structure. The second storage node includes: the seventh contact structure, the third contact structure and the first contact structure.

8. The chip according to claim 4, characterized in that: The gates of the first gate tubes in the plurality of storage cells are an integrated structure, the gates of the second gate tubes in the plurality of storage cells are an integrated structure, the gate of at least one of the first gate tubes in the plurality of storage cells is connected to the gate of at least one of the second gate tubes, and is connected to the word line.

9. The chip according to claim 4, characterized in that: In the same storage unit, the gates of the first gate tube and the second gate tube are arranged in parallel and at intervals, and a first connecting portion is also arranged in the second metal interconnection layer, and an end of the gate of the first gate tube close to the second gate tube is connected to an end of the gate of the second gate tube close to the first gate tube through the first connecting portion, and the first connecting portion is connected to the word line.

10. The chip according to claim 4, characterized in that: In the same storage unit, the gate of the first gate tube and the gate of the second gate tube are an integrated structure, and a second connecting portion is also provided in the second metal interconnection layer, the second connecting portion is located between the first gate tube and the second gate tube, the second connecting portion is connected to the gate of the first gate tube, and the second connecting portion is connected to the word line.

11. The chip according to any one of claims 8 to 10, characterized in that: The word line is arranged on a side of the second metal interconnection layer away from the substrate.

12. The chip according to claim 3, characterized in that: The first gate tube and the first pull-down tube are located in the first metal interconnection layer, and the second gate tube and the second pull-down tube are located in the second metal interconnection layer.

13. The chip according to claim 12, characterized in that: The electrodes of the first gate tube and the first pull-down tube close to each other are an integral structure, and the electrodes of the second gate tube and the second pull-down tube close to each other are an integral structure.

14. The chip according to any one of claims 3 to 13, characterized in that: One electrode of the first pull-up tube and the second pull-up tube are both connected to the first power line, the other electrode of the first pull-up tube is connected to the gate of the second pull-up tube, and the other electrode of the second pull-up tube is connected to the gate of the first pull-up tube; the gate of the first pull-up tube is also connected to one electrode of the second pull-down tube, the other electrode of the second pull-down tube is connected to the second power line, the gate of the second pull-down tube is also connected to the gate of the second pull-up tube, one electrode of the first pull-down tube is connected to the gate of the second pull-up tube, the other electrode of the first pull-down tube is connected to the second power line, and the gate of the first pull-down tube is connected to the gate of the first pull-up tube; the gate of the first pull-down tube is also connected to one electrode of the second selection tube, the other electrode of the second selection tube is connected to the anti-bit line, and the gate of the second selection tube is connected to the word line; one electrode of the first selection tube is connected to the gate of the second pull-down tube, the other electrode of the first selection tube is connected to the bit line, and the gate of the first selection tube is also connected to the word line.

15. The chip according to any one of claims 1 to 14, characterized in that: The metal interconnection layer includes a plurality of first dielectric layers and a plurality of second dielectric layers which are alternately stacked, and the dielectric constant of the first dielectric layer is smaller than the dielectric constant of the second dielectric layer.

16. The chip according to any one of claims 1 to 15, characterized in that: The pull-up tube includes a P-type transistor, and the gate tube and the pull-down tube include N-type transistors.

17. The chip according to any one of claims 1 to 16, characterized in that: The material of the substrate includes silicon, and the pull-up tube includes a silicon field effect transistor.

18. An electronic device, characterized in that: include: A mainboard and a chip as described in any one of claims 1 to 17, wherein the chip is arranged on the mainboard.

19. A chip manufacturing method, characterized in that: include: A device layer and a pull-up tube located in the device layer are manufactured on a substrate by using a front-end process, wherein the device layer includes a logic circuit; A metal interconnection layer and a gate tube and a pull-down tube located in the metal interconnection layer are stacked on the device layer by adopting a back-end process; the static random access memory includes the gate tube, the pull-up tube and the pull-down tube.

20. The chip manufacturing method according to claim 19, characterized in that: The metal interconnection layer and the gate tube and the pull-down tube located in the metal interconnection layer are formed on the device layer by stacking by adopting the back-end process, including: A first metal interconnection layer and a second metal interconnection layer are stacked on the device layer by a back-end process, wherein the first metal interconnection layer is located between the second metal interconnection layer and the device layer; the gate tube and the pull-down tube are arranged in the first metal interconnection layer and the second metal interconnection layer.

21. The chip manufacturing method according to claim 20, characterized in that: The gate tube includes a first gate tube and a second gate tube, the pull-up tube includes a first pull-up tube and a second pull-up tube, and the pull-down tube includes a first pull-down tube and a second pull-down tube; the static random access memory includes a storage unit, the storage unit is used to store data, the storage unit is a 6T storage unit, and the storage unit includes: the first gate tube, the second gate tube, the first pull-up tube, the second pull-up tube, the first pull-down tube and the second pull-down tube; Forming a first metal interconnection layer and a second metal interconnection layer in a stacked manner on the device layer by a back-end process includes: Forming a first metal interconnect layer and the first pull-down tube and the second pull-down tube located in the first metal interconnect layer in a stacked manner on the device layer by a back-end process; A second metal interconnection layer and the first gate tube and the second gate tube located in the second metal interconnection layer are stacked on the first metal interconnection layer by adopting a back-end process.

22. The chip manufacturing method according to claim 20, characterized in that: The gate tube includes a first gate tube and a second gate tube, the pull-up tube includes a first pull-up tube and a second pull-up tube, and the pull-down tube includes a first pull-down tube and a second pull-down tube; the static random access memory includes a storage unit, the storage unit is used to store data, the storage unit is a 6T storage unit, and the storage unit includes: the first gate tube, the second gate tube, the first pull-up tube, the second pull-up tube, the first pull-down tube and the second pull-down tube; Forming a first metal interconnection layer and a second metal interconnection layer in a stacked manner on the device layer by a back-end process includes: Forming a first metal interconnection layer and the first pull-down tube and the first gating tube located in the first metal interconnection layer in a stacked manner on the device layer by adopting a back-end process; A second metal interconnection layer and the second pull-down tube and the second gate tube located in the second metal interconnection layer are stacked on the first metal interconnection layer by adopting a back-end process.

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