Semiconductor device and electronic equipment

Abstract

The present invention provides a highly integrated semiconductor device with high data retention capacity and data readout reliability. This semiconductor device has a transistor with a back gate, a first capacitive element, and a second capacitive element, wherein the first capacitive element has: as one electrode, a conductive layer formed by the same process as a first gate electrode; as a dielectric layer, a first gate insulating layer; and as the other electrode, the source electrode or the drain electrode of the transistor. The second capacitive element has: as one electrode, a conductive layer formed by the same process as a second gate electrode; as a dielectric layer, a second gate insulating layer; and as the other electrode, the source electrode or the drain electrode of the transistor.

Description

Semiconductor devices and electronic devices

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, power storage devices, memory devices, imaging devices, and driving methods thereof or manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0004] While silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, oxide semiconductors have also attracted attention as other materials. Transistors using oxide semiconductors are known to have extremely low current flow in the non-conducting (off) state.

[0005] For example, Patent Document 1 discloses a memory device that can retain stored data for a long period of time by utilizing the characteristic that a transistor including an oxide semiconductor has a small off-state current.

[0006] JP 2011-151383 A

[0007] A memory cell, which is an element of a memory device, often has a structure including a capacitor, which can improve the data retention capability and the reliability of data reading.

[0008] To increase the integration density of memory cells, it is desirable to reduce the area occupied by each cell, but because the capacitance of a capacitor is proportional to the electrode area, it is necessary to devise a layout for the capacitor. For example, a structure in which a trench-type capacitor is placed on top of a transistor is known, but this increases the difficulty of the manufacturing process, so a simpler structure is desired.

[0009] Therefore, an object of one embodiment of the present invention is to provide a semiconductor device with high data retention capability. Another object is to provide a semiconductor device with high data read reliability. Another object is to provide a semiconductor device with high integration. Another object is to provide a semiconductor device with high reliability. Another object is to provide a semiconductor device with high productivity. Another object is to provide a novel semiconductor device.

[0010] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc.

[0011] One embodiment of the present invention relates to a highly integrated semiconductor device with high data retention capability and high data read reliability.

[0012] One embodiment of the present invention includes a first transistor, a first capacitor, and a second capacitor. The first transistor includes a first conductive layer, a first insulating layer provided over the first conductive layer, a semiconductor layer provided over the first insulating layer, a second insulating layer provided over the first insulating layer and the semiconductor layer, a second conductive layer provided over the second insulating layer, a third conductive layer provided in contact with the semiconductor layer, and a fourth conductive layer provided in contact with the semiconductor layer. The first conductive layer, the first insulating layer, the semiconductor layer, the second insulating layer, and the second conductive layer overlap each other. the first capacitance element has a fifth conductive layer, a first insulating layer provided on the fifth conductive layer, and a third conductive layer provided on the first insulating layer; the second capacitance element has a semiconductor layer provided on the first insulating layer, a third conductive layer provided on the first insulating layer and on the semiconductor layer, a second insulating layer provided on the third conductive layer, and a sixth conductive layer provided on the second insulating layer; and the fifth conductive layer, the first insulating layer, the semiconductor layer, the third conductive layer, the second insulating layer, and the sixth conductive layer have regions that overlap each other.

[0013] The first conductive layer functions as a first gate electrode, the second conductive layer functions as a second gate electrode, the third conductive layer functions as one of a source electrode or a drain electrode and the other electrode of the first and second capacitor elements, the fourth conductive layer functions as the other of a source electrode or a drain electrode, the fifth conductive layer functions as one electrode of the first capacitor element, the sixth conductive layer functions as one electrode of the second capacitor element, the first insulating layer functions as a first gate insulating layer and a dielectric layer of the first capacitor element, the second insulating layer functions as a second gate insulating layer, and the third insulating layer functions as a dielectric layer of the second capacitor element.

[0014] The semiconductor device also includes a first transistor, a first capacitor, and a second capacitor, and includes a first insulating layer, a second insulating layer, a third insulating layer, a semiconductor layer, a first conductive layer, a second conductive layer, a second conductive layer, a fourth conductive layer, and a fifth conductive layer, the first conductive layer and the fourth conductive layer being provided on the same plane, the first insulating layer being provided on the first conductive layer and the fourth conductive layer, the semiconductor layer being provided on the first insulating layer, a second insulating layer being provided on the first conductive layer and the semiconductor layer, and a region where the second conductive layer is provided on the second insulating layer, and a region where the fourth conductive layer is provided on the fourth conductive layer. a third conductive layer is provided on a first insulating layer and a semiconductor layer, a third insulating layer is provided on the third conductive layer, and a sixth conductive layer is provided on a second insulating layer; a first transistor has the first conductive layer as a first gate electrode, the second conductive layer as a second gate electrode, and the third conductive layer as one of a source electrode and a drain electrode; a first capacitor has the fifth conductive layer as one electrode, the first insulating layer as a dielectric layer, and the third conductive layer as the other electrode; and a second capacitor has the sixth conductive layer as one electrode, the third insulating layer as a dielectric layer, and the third conductive layer as the other electrode.

[0015] The semiconductor layer is preferably provided along the sides of a substantially rectangular shape in top view, and the height of the semiconductor layer is preferably greater than the maximum width of the semiconductor layer in a cross-sectional view in the channel width direction.

[0016] In addition, the number of semiconductor layers in a cross section in the channel width direction is preferably two or more in a region overlapping with the second conductive layer.

[0017] The semiconductor device may include a second transistor, and the gate of the second transistor may be electrically connected to the third conductive layer.

[0018] The semiconductor layer preferably comprises a metal oxide, and the metal oxide preferably comprises In, Zn, and M (wherein M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf).

[0019] An electronic device including the above semiconductor device and a display portion is also one embodiment of the present invention.

[0020] By using one embodiment of the present invention, a semiconductor device with high data retention capability can be provided. Alternatively, a semiconductor device with high data read reliability can be provided. Alternatively, a semiconductor device with high integration density can be provided. Alternatively, a semiconductor device with high reliability can be provided. Alternatively, a semiconductor device with high productivity can be provided. Alternatively, a novel semiconductor device can be provided.

[0021] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0022] FIG. 1 is a perspective view illustrating a memory cell. FIG. 2A is a top view illustrating a memory cell. FIG. 2B is a circuit diagram illustrating a memory cell. FIG. 3 is a timing chart illustrating the operation of a memory cell. FIGS. 4A and 4B are cross-sectional views illustrating a transistor and a capacitor. FIGS. 5A and 5B are cross-sectional views illustrating a transistor. FIG. 5C is a cross-sectional view illustrating a capacitor. FIGS. 6A and 6B are cross-sectional views illustrating a transistor. FIGS. 7A and 7B are perspective views illustrating a semiconductor layer. FIGS. 8A to 8D are diagrams illustrating a method for manufacturing a transistor and a capacitor. FIGS. 9A to 9D are diagrams illustrating a method for manufacturing a transistor and a capacitor. FIGS. 10A to 10D are diagrams illustrating a method for manufacturing a transistor and a capacitor. FIGS. 11A to 11D are diagrams illustrating a method for manufacturing a transistor and a capacitor. FIGS. 12A to 12D are diagrams illustrating a method for manufacturing a transistor and a capacitor. FIGS. 13A to 13D are diagrams illustrating a method for manufacturing a transistor and a capacitor. FIGS. 14A to 14D are diagrams illustrating a method for manufacturing a transistor and a capacitor. FIGS. 15A to 15D are diagrams illustrating a method for manufacturing a transistor and a capacitor. FIGS. 16A to 16D are diagrams illustrating a method for manufacturing a transistor and a capacitor. FIGS. 17A to 17D are diagrams illustrating a method for manufacturing a transistor and a capacitor. FIGS. 18A to 18D are diagrams illustrating a method for manufacturing a transistor and a capacitor. FIG. 19A is a perspective view illustrating a transistor and a capacitor. FIG. 19B is a top view illustrating a transistor and a capacitor. FIG. 20 is a block diagram illustrating a configuration example of a semiconductor device. FIGS. 21A to 21H are diagrams illustrating a circuit configuration example of a memory cell. FIGS. 22A and 22B are perspective views illustrating a configuration example of a semiconductor device. FIG. 23 is a block diagram illustrating a CPU. FIG. 24 is a block diagram illustrating a CPU. FIGS. 25A and 25B are perspective views of a semiconductor device. FIGS. 26A and 26B are perspective views of a semiconductor device. 27A and 27B are diagrams illustrating the hierarchy of memory devices in a semiconductor device.Fig. 28A and Fig. 28B are diagrams showing an example of electronic equipment, and Fig. 28C to Fig. 28E are diagrams showing an example of a mainframe computer. Fig. 29 is a diagram showing an example of space equipment. Fig. 30 is a diagram showing an example of a storage system applicable to a data center.

[0023] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0024] In the drawings, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations may be omitted. In addition, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0025] In this specification and the like, an oxynitride is a material whose composition contains more oxygen than nitrogen. Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, and hafnium oxynitride. Examples of nitride oxides are silicon nitride oxide, aluminum nitride oxide, and hafnium nitride oxide.

[0026] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0027] Furthermore, in this specification, "parallel" refers to a state in which two lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases where the angle is -5 degrees or more and 5 degrees or less. "Approximately parallel" refers to a state in which two lines are arranged at an angle of -30 degrees or more and 30 degrees or less. "Perpendicular" refers to a state in which two lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less. "Approximately perpendicular" refers to a state in which two lines are arranged at an angle of 60 degrees or more and 120 degrees or less. "Orthogonal" refers to a state in which two lines intersect or connect at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less. "Approximately perpendicular" or "approximately perpendicular" refers to a state in which two lines intersect or connect at an angle of 60 degrees or more and 120 degrees or less.

[0028] In addition, in drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. Note that in this specification, the "X direction" refers to the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. More specifically, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification, one of the X direction, Y direction, and Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0029] Furthermore, in this specification, terms indicating position, such as "above" and "below," are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0030] In this embodiment, a semiconductor device that can be used for a memory device or the like according to one embodiment of the present invention will be described. A memory cell included in the semiconductor device includes a transistor having a back gate, and first and second capacitors each having a metal-insulator-metal (MIM) type.

[0031] The transistor has a first gate insulating layer and a first gate electrode provided under a semiconductor layer, and a second gate insulating layer and a second gate electrode provided over the semiconductor layer, with either the first gate electrode or the second gate electrode functioning as a back gate electrode.

[0032] The first capacitor element has a conductive layer formed in the same process and using the same material as the first gate electrode as one electrode, the first gate insulating layer as a dielectric layer, and a source or drain electrode of a transistor as the other electrode. The second capacitor element has a conductive layer formed in the same process and using the same material as the second gate electrode as one electrode, the second gate insulating layer as a dielectric layer, and a source or drain electrode of a transistor as the other electrode.

[0033] That is, the first capacitor and the second capacitor can be manufactured using the same process as the transistor, thereby improving productivity. In addition, the first capacitor and the second capacitor are connected in parallel, which increases the capacitance of the memory cell, thereby improving the data retention characteristics and the reliability of data reading.

[0034] The semiconductor layer is provided in a shape that follows the sides of a substantially rectangular shape when viewed from above. In other words, the outer periphery of the semiconductor layer is substantially rectangular when viewed from above, and the semiconductor layer has a hollow shape. By adopting this shape, the semiconductor layer can be said to be substantially fin-shaped, and the channel width can be increased. Furthermore, a multi-channel transistor having multiple semiconductor layers can be formed.

[0035] Therefore, the on-state current of the transistor can be increased, and the speed of writing and reading data can be increased. In addition, since the structure of the semiconductor layer can be the same in the second capacitor portion, the electrode area can be increased, and the capacitance can be increased.

[0036] 1 is a perspective view illustrating a schematic configuration of a memory cell 150 included in a semiconductor device of one embodiment of the present invention. FIG. 2A is a top view of the memory cell 150, and FIG. 2B is a circuit diagram illustrating the memory cell 150.

[0037] In Fig. 1, for clarity, some insulating layers are omitted or shown with dotted lines. Also, in the transistor, some elements are shown with dashed lines to partially visualize them. Also, a perspective cross-sectional view of the capacitance element is also shown. Also, Figs. 2A and 2B show wiring that is not shown in Fig. 1.

[0038] The memory cell 150 includes a transistor 110, a transistor 120, a capacitor 131, and a capacitor 132. The transistor 110 has a function of writing data. The transistor 120 has a function of reading data. The capacitors 131 and 132 have a function of retaining data.

[0039] The memory cell 150 has two transistors and two capacitance elements (2Tr2C), but the two capacitance elements are connected in parallel and can be considered as one capacitance element, so it can also be said to have a structure having two transistors and one capacitance element (2Tr1C). Note that the transistors and capacitance elements that can be used in the memory cell 150 can also be applied to 1Tr1C type memory cells such as DRAMs, and other memory cells.

[0040] The transistor 110 has a conductive layer 116 that functions as a first gate electrode and a conductive layer 114 that functions as a second gate electrode, and the conductive layer 116 is electrically connected to a wiring 141, and the conductive layer 114 is electrically connected to a wiring 113.

[0041] The transistor 120 has a conductive layer 129 that functions as a first gate electrode and a conductive layer 126 that functions as a second gate electrode, and the conductive layer 129 is electrically connected to a wiring 143, and the conductive layer 126 is electrically connected to one of the source and drain of the transistor 110 via a connection wiring 140.

[0042] The conductive layer 114, the conductive layer 116, the conductive layer 126, and the conductive layer 129 may be part of the wiring connected to each other.

[0043] In the transistor 110 and the transistor 120, the conductive layers 116 and 129, which are the first gate electrodes, function as back gates. For example, by supplying a constant potential lower than the source potential of the transistor to the back gate, the threshold voltage can be shifted in the positive direction, thereby reducing the off-state current. Note that the conductive layers 114 and 126 may also function as back gates. Note that a structure in which the conductive layers 116 and 129, which are the first gate electrodes, are not provided is also possible.

[0044] The conductive layer 133 functioning as one electrode of the capacitor 131 is electrically connected to a wiring 138. The conductive layer 134 functioning as one electrode of the capacitor 132 is electrically connected to a wiring 142. Note that the conductive layer 133 and the conductive layer 134 may be part of the wirings connected to each other.

[0045] Here, the conductive layer 112b functioning as one of the source electrode and the drain electrode of the transistor 110 is used as the other electrode of the capacitor 131 and the capacitor 132. That is, the capacitor 131 and the capacitor 132 have a stacked structure, but are connected in parallel because the conductive layer 112b is shared as the other electrode. Therefore, the area can be reduced and the capacitance can be increased.

[0046] The wiring 138 and the wiring 142 are constant potential lines, and may be low potential power supply lines or GND lines, for example. The wiring 138 and the wiring 142 may be electrically connected to each other.

[0047] One of the source electrode or drain electrode of the transistor 110 is electrically connected to the other electrode of the capacitor 131, the other electrode of the capacitor 132, and the second gate electrode of the transistor 120. Note that an electrode or a wiring for connecting these can be regarded as a component of the node SN shown in FIG. 2B . Note that one of the source electrode or drain electrode of the transistor 110 can be electrically connected to the second gate electrode of the transistor 120 through a connection wiring 140.

[0048] The wiring 113 connected to the conductive layer 114, which is the second gate electrode of the transistor 110, is a wiring that supplies a write word signal to the memory cell 150 and is also referred to as a write word line (WWL). The write word signal is a signal that controls the timing of writing data to the memory cell 150.

[0049] The wiring 117 connected to the conductive layer 112a, which is the other of the source electrode and the drain electrode of the transistor 110, is a wiring that applies a potential corresponding to a data signal (data) to the memory cell 150 and is also referred to as a write bit line (WBL). Ｈ ) or low level ("0" or V Ｌ It is a signal expressed as a binary value (also called a sine wave).

[0050] The wiring 127 connected to one of the source electrode and the drain electrode of the transistor 120 is a wiring that supplies a read word signal to the memory cell 150 and is also referred to as a read word line (RWL). The read word signal is a signal that controls the timing of reading data from the memory cell 150.

[0051] The wiring 128 connected to the other of the source electrode and the drain electrode of the transistor 120 is a wiring for reading out a potential corresponding to a data signal (data) held in the memory cell 150, and is also referred to as a read bit line (RBL). A current flows through the transistor 120 according to the data ("1" or "0") written to the memory cell 150, changing the potential of the precharged wiring 128. The potential can be input to a sense amplifier or the like to read out the data.

[0052] Next, the operation of the memory cell 150 will be described with reference to Fig. 3. Here, an ideal operation in which the influence of parasitic capacitance is eliminated will be described. Fig. 3 is a timing chart for explaining an example of the operation of the memory cell 150 shown in Fig. 2B.

[0053] 3 shows potentials applied to the wiring 113 (WWL), the wiring 117 (WBL), and the wiring 127 (RWL), a potential read to the wiring 128 (RBL), and a potential of the node SN. Note that in FIG. 3, the standby state of the wiring 117 (WBL) is set to a low level (V Ｌ )

[0054] The period T1 is a standby period. The period T2 is a write period. The period T3 is a standby period. The periods T4 and T5 are read periods. The period T6 is a standby period. Note that FIG. 3 illustrates data "1" or "0" written to the memory cell 150 (node ​​SN) via the wiring 117 (WBL). The data written to the memory cell 150 is data "1" when it is at a high level and data "0" when it is at a low level.

[0055] 3 illustrates data "1" or "0" read from the memory cell 150 via the wiring 128 (RBL). The wiring 128 (RBL) is set to a high-level potential (for example, V ＤＤ The data is read out to an external read circuit connected to the wiring 128 (RBL) according to a change in the precharged potential.

[0056] When the data stored in the memory cell 150 (node ​​SN) is data "1", the current flowing through the transistor 120 is large, and therefore the potential of the wiring 128 (RBL) decreases. When the data stored in the memory cell 150 (node ​​SN) is data "0", the current flowing through the transistor 120 is small, and therefore the fluctuation in the potential of the wiring 128 (RBL) is small. In other words, when the data stored in the memory cell 150 (node ​​SN) is data "1", the potential of the wiring 128 (RBL) becomes low. On the other hand, when the data stored in the memory cell 150 (node ​​SN) is data "0", the potential of the wiring 128 (RBL) becomes high (precharged potential).

[0057] In the period T1, the wiring 113 (WWL) is at a low level, and the wiring 117 (WBL) is at a low level (V Ｌ ), the wiring 127 (RWL) is at a high level, and the wiring 128 (RBL) is at a high level. At this time, the transistor 110 is in a non-conducting state. Furthermore, the transistor 120 has the same potential between the source and drain terminals, so no current flows. Note that the potential of the gate (node ​​SN) of the transistor 120 is the potential V written in the previous writing period. Ｈ or V Ｌ is.

[0058] During the period T2, the wiring 113 (WWL) is at a high level, and the wiring 117 (WBL) is at a signal (V Ｈ or V Ｌ ), the wiring 127 (RWL) is at a high level, and the wiring 128 (RBL) is at a high level. At this time, the transistor 110 is turned on, and the potential of the gate (node ​​SN) of the transistor 120 becomes a potential corresponding to the data. Since the source and drain terminals of the transistor 120 have the same potential, no current flows regardless of the gate potential.

[0059] In the period T3, the wiring 113 (WWL) is at a low level, and the wiring 117 (WBL) is at a low level (V Ｌ), the wiring 127 (RWL) is at a high level, and the wiring 128 (RBL) is at a high level. At this time, both the transistors 110 and 120 are off. In period T3, the potential written to the gate (node ​​SN) of the transistor 120 is held. Since the source and drain terminals of the transistor 120 have the same potential, no current flows regardless of the gate potential.

[0060] In the period T4, the wiring 113 (WWL) is at a low level, and the wiring 117 (WBL) is at a low level (V Ｌ ), the wiring 127 (RWL) is at a high level. The wiring 128 (RBL) is at a high level (precharge potential V ＰＲＥ At this time, the transistor 110 is in a non-conductive state. ＰＲＥ For example, V ＤＤ , which is the same potential as the high level of the wiring 128 (RBL). Since the source and drain terminals of the transistor 120 have the same potential, no current flows regardless of the potential of the gate (node ​​SN). That is, the potential of the wiring 128 does not change.

[0061] During the period T5, the wiring 113 (WWL) is at a low level, and the wiring 117 (WBL) is at a low level (V Ｌ ), and the wiring 127 (RWL) is at a low level. At this time, the transistor 110 is off. Furthermore, in the period T5, the wiring 128 (RBL) is in an electrically floating state. That is, the potential of the wiring 128 changes depending on the current flowing through the transistor 120 of the memory cell 150.

[0062] During the period T5, a potential difference occurs between the source and drain terminals of the transistor 120, causing a current to flow according to the potential of the gate (node ​​SN) of the transistor 120. When the data stored in the memory cell 150 is data "1," a large current flows through the transistor 120, causing the potential of the wiring 128 (RBL) to drop to a low level. This change in the potential of the wiring 128 (RBL) activates a sense amplifier connected to the wiring 128 (RBL), allowing data of the selected memory cell 150 to be read out to the outside.

[0063] Furthermore, when the data stored in the memory cell 150 is data "0", the current flowing through the transistor 120 is small, and therefore the potential of the wiring 128 (RBL) hardly changes from the high level (precharged potential).

[0064] In the period T5, in the memory cells 150 in the unselected rows, the wiring 127 (RWL) is at high level, and the source and drain terminals of the transistor 120 are at the same potential; therefore, no current flows regardless of the gate potential.

[0065] In the period T6, the wiring 113 (WWL) is at a low level, and the wiring 117 (WBL) is at a low level (V Ｌ ), the wiring 127 (RWL) is at a high level, and the wiring 128 (RBL) is at a high level. At this time, the transistor 110 is in a non-conducting state. Since the source and drain terminals of the transistor 120 have the same potential, no current flows regardless of the gate potential.

[0066] By the above operation, data can be read from the memory cells 150 in the selected row.

[0067] Next, the structures of the transistor and the capacitor will be described in detail. Note that although the transistor 110 will be described here, the transistor 120 also has the same basic structure.

[0068] Fig. 4A is a diagram illustrating a cross section of the transistor 110 in the channel length direction, taken along the line A1-A2 in Fig. 2A . Fig. 4B is a diagram illustrating a cross section of a region parallel to Fig. 4A , taken along the line A3-A4 in Fig. 2A .

[0069] 5A is a diagram illustrating a cross section of the transistor 110 in the channel width direction, showing the cross section between B1 and B2 shown in FIG. 2A. FIG. 5B is a diagram illustrating a cross section of one of the source region or drain region of the transistor 110, showing the cross section between B3 and B4 shown in FIG. 2A. FIG. 5C is a diagram illustrating a cross section of the capacitance elements 131 and 132, showing the cross section between B5 and B6 shown in FIGS. 1 and 2A.

[0070] 4A , 4B , and 5A to 5C , the insulating layer 215 is shown as the bottom layer. However, a substrate (not shown) is provided below the insulating layer 215. For example, an insulating substrate such as a glass substrate or a ceramic substrate, or a semiconductor substrate can be used as the substrate. The semiconductor substrate may be provided with a circuit connected to the semiconductor device of one embodiment of the present invention. Furthermore, a single layer or multiple layers including a wiring, a circuit, or the like may be provided between the substrate and the insulating layer 215.

[0071] The conductive layer 116 and the conductive layer 134 embedded in the insulating layer 216 are provided over the insulating layer 215. As described above, the conductive layer 116 functions as the first gate electrode of the transistor 110, and the conductive layer 134 functions as one electrode of the capacitor 132.

[0072] Note that the conductive layer 116 is not limited to a single layer and may be formed of multiple layers. For example, as in a modified example of the configuration of FIG. 4A shown in FIG. 6A , the conductive layer 116 may have a conductive layer 116a provided along the opening of the insulating layer 216 and a conductive layer 116b filling the opening. Similarly, the conductive layer 134 may have a conductive layer 134a and a conductive layer 134b.

[0073] The conductive layer 116a and the conductive layer 134a are made of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc., or a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0074] By using a conductive material capable of reducing hydrogen diffusion for the conductive layers 116a and 134a, impurities such as hydrogen contained in the conductive layers 116b and 134b can be prevented from diffusing into the semiconductor layer 111 via the insulating layer 216 or the like. Furthermore, by using a conductive material capable of suppressing oxygen diffusion for the conductive layers 116a and 134a, it is possible to prevent the conductive layers 116b and 134b from being oxidized and their conductivity from decreasing. Examples of conductive materials capable of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layers 116a and 134a can have a single-layer structure or a stacked-layer structure of the above conductive materials. For example, the conductive layers 116a and 134a preferably contain titanium nitride.

[0075] The conductive layers 116b and 134b are preferably made of a material that contains tungsten, copper, or aluminum as a main component and has lower conductivity than the conductive layers 116a and 134a. For example, the conductive layers 116b and 134b preferably contain tungsten.

[0076] When the conductive layer 116 and the conductive layer 134 are formed as a single layer, they are preferably formed using a material that can be used for the conductive layer 116b and the conductive layer 134b.

[0077] In addition, since the insulating layer 216 functions as an interlayer film, it is preferable that the insulating layer 216 be formed of a material with a relatively low dielectric constant. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between wirings can be reduced.

[0078] For example, the insulating layer 216 preferably includes one or more of silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies.

[0079] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. Furthermore, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0080] An insulating layer 137 is provided over the insulating layer 216, the conductive layer 116, and the conductive layer 134. The insulating layer 137 functions as a first gate insulating film in the transistor 110 and as a dielectric layer in the capacitor 132.

[0081] The insulating layer 137 is preferably a stack of insulating layers 137a and 137b. One or both of the insulating layers 137a and 137b may contain hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (e.g., copper atoms ...

[0082] Examples of the insulating material that can be used include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, silicon nitride, and silicon nitride oxide. For example, the insulating layer 137a is preferably made of silicon nitride, which has high hydrogen barrier properties. For example, the insulating layer 137b is preferably made of hafnium oxide, which is a high-dielectric-constant (high-k) material with high hydrogen capture or fixation capabilities.

[0083] The insulating layer 137a and the insulating layer 137b can also have a stacked-layer structure of any of the above materials and silicon oxide or silicon oxynitride. The insulating layer 137 may be formed as a single layer of either the insulating layer 137a or the insulating layer 137b.

[0084] With this structure, impurities such as water and hydrogen can be prevented from diffusing from an interlayer insulating film disposed below the insulating layer 137a to the transistor 110. Furthermore, providing the insulating layer 137b and the insulating layer 137a can prevent oxygen contained in the semiconductor layer 111 from diffusing below the transistor 110. Therefore, excessive oxygen and hydrogen can be prevented from diffusing into the oxide semiconductor. This can improve the electrical characteristics and reliability of the semiconductor device.

[0085] A semiconductor layer 111 is provided on the insulating layer 137. As shown in the top view of FIG. 2A and the perspective view of FIG. 7A, the semiconductor layer 111 is preferably hollow and provided along the sides of a roughly rectangular shape in top view. The semiconductor layer 111 has a high aspect ratio in a cross section in the channel width direction, with the height being large relative to the width (thickness in the film growth direction). In other words, the semiconductor layer 111 can be said to have a configuration in which multiple plate-shaped semiconductor layers are combined. In this specification and the like, this plate-shaped semiconductor layer is referred to as a fin-type semiconductor layer, or simply as a fin.

[0086] When a fin-type semiconductor layer with a high aspect ratio is formed alone, it may tilt during the manufacturing process, but the hollow semiconductor layer 111 has a structure in which multiple fin-type semiconductor layers support each other, so tilting can be prevented. Furthermore, by making the semiconductor layer 111 hollow, the contact area between the conductive layer functioning as a source electrode or a drain electrode and the semiconductor layer 111 can be increased, so that contact resistance can be reduced.

[0087] Here, the aspect ratio of the semiconductor layer 111 in the cross section in the channel width direction is, as shown in FIG. 5A, the width W of the semiconductor layer 111 in the B1-B2 direction. Ｓ and a height H in a direction perpendicular to the surface on which the semiconductor layer 111 is formed. Ｓ The width W of the semiconductor layer 111 in the B1-B2 direction is Ｓ is preferably constant in the height direction, but may not necessarily be constant. In that case, the maximum width of the semiconductor layer 111 in the height direction is set to the width W Ｓ Let's say.

[0088] Height H of the semiconductor layer 111 Ｓ is the width W of the semiconductor layer 111 within a range that does not affect the process. Ｓ It is preferable to make the height H Ｓ The larger the width W, the larger the channel width of the transistor. Ｓ is too small or the height H Ｓ If the distance is too large, the process becomes more difficult and defects such as the semiconductor layer collapsing or deforming may occur.

[0089] For example, the height H of the semiconductor layer 111 Ｓ is the width W Ｓ The thickness T is, for example, from 5 nm to 100 nm, preferably from 5 nm to 50 nm, more preferably from 10 nm to 30 nm, more preferably from 10 nm to 30 nm, more preferably from 2 nm to 100 nm, more preferably from 5 nm to 50 nm, more preferably from 10 nm to 30 nm.

[0090] As shown in FIG. 7B, a plurality of semiconductor layers 111 may be provided. FIG. 7B shows two semiconductor layers 111. In this case, the transistor has a structure in which channel formation regions are formed in four fin-type semiconductor layers, and the number of channels can be increased. In addition, an increase in the number of channels has the same effect as an increase in the channel width. Therefore, the on-current of the transistor can be increased. In addition, a structure in which three or more semiconductor layers 111 are provided may also be used.

[0091] An oxide semiconductor is preferably used for the semiconductor layer 111. In this specification and the like, a transistor having an oxide semiconductor in a channel formation region is referred to as an OS transistor. Since an OS transistor can be formed using a thin film, stacking is easy. Furthermore, an OS transistor has higher mobility than a transistor using amorphous silicon, does not require a crystallization process required in the manufacturing process of a polycrystalline silicon (LTPS) transistor, and has excellent uniformity in electrical characteristics. Details of the oxide semiconductor will be described later. Note that in this embodiment, an example in which an oxide semiconductor is used for the semiconductor layer 111 will be described.

[0092] A conductive layer 112 (conductive layers 112a and 112b) is provided over the semiconductor layer 111. The conductive layer 112b functions as one of the source and the drain of the transistor 110 (see FIG. 5B). The conductive layer 112a functions as the other of the source and the drain of the transistor 110. The conductive layer 112b functions as the other electrode of the capacitor 132 (see FIG. 5C).

[0093] The capacitance element 132 is configured with the conductive layer 134 as one electrode, the insulating layer 137 as a dielectric layer, and the conductive layer 112b as the other electrode. On the conductive layer 134, the conductive layer 112b is formed so as to cover the semiconductor layer 111, and is also formed so as to be in contact with the insulating layer 137 outside the semiconductor layer 111 and between the two semiconductor layers 111. The region of the conductive layer 112b in contact with the insulating layer 137 mainly functions as the other electrode of the capacitance element 132.

[0094] When an oxide semiconductor is used for the semiconductor layer 111, oxygen vacancies occur in the oxide semiconductor due to contact between the oxide semiconductor and the conductive layer 112, and the oxide semiconductor is likely to become n-type. That is, the resistance of the semiconductor layer 111 is reduced. Therefore, it can be said that the semiconductor layer 111 can also function as one electrode of the capacitor 132.

[0095] The conductive layer 112 (conductive layers 112a and 112b) is preferably formed using a conductive material that is not easily oxidized or a conductive material that has a function of suppressing oxygen diffusion. This can suppress a decrease in the conductivity of the conductive layer 112. Furthermore, when an oxide semiconductor is used for the semiconductor layer 111, oxygen can be suppressed from being extracted from the semiconductor layer 111, which can suppress the formation of an excessive amount of oxygen vacancy. Furthermore, it is preferable to use a material that easily absorbs (extracts) hydrogen for the conductive layer 112 because the hydrogen concentration in the oxide semiconductor can be reduced.

[0096] For the conductive layer 112, it is preferable to use a metal nitride, such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Alternatively, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when they absorb oxygen.

[0097] 6A , the conductive layer 112 may be formed of a plurality of layers, instead of a single layer. For example, the conductive layer 112a may be a stack of a conductive layer 112a_1 and a conductive layer 112a_2 from the semiconductor layer 111 side, and the conductive layer 112b may be a stack of a conductive layer 112b_1 and a conductive layer 112b_2 from the semiconductor layer 111 side.

[0098] In this case, the above-described conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion is preferably used for the layers in contact with the semiconductor layer 111 (the conductive layer 112a_1 and the conductive layer 112b_1). This can suppress a decrease in the conductivity of the conductive layer 112a and the conductive layer 112b. Furthermore, when an oxide semiconductor is used for the semiconductor layer 111, oxygen can be suppressed from being extracted from the oxide semiconductor, which can suppress the formation of an excessive amount of oxygen vacancy. Furthermore, using a material that easily absorbs (extracts) hydrogen is preferable because the hydrogen concentration in the oxide semiconductor can be reduced.

[0099] The conductive layers 112a_2 and 112b_2 preferably have higher conductivity than the conductive layers 112a_1 and 112b_1. Such a structure can reduce the resistance of the conductive layers 112a and 112b. This can increase the on-state current of the transistor 110, thereby improving the operating speed of the semiconductor device according to this embodiment.

[0100] For example, the conductive layers 112a_1 and 112b_1 can be made of tantalum nitride or titanium nitride, and the conductive layers 112a_2 and 112b_2 can be made of tungsten.

[0101] As shown in FIG. 6A, a structure may be employed in which the distance between the conductive layer 112a_1 and the conductive layer 112b_1 is shorter than the distance between the conductive layer 112a_2 and the conductive layer 112b_2.

[0102] Although the details of the configuration of the gate region will be described later, shortening the channel length in the configuration shown in FIG. 4A requires narrowly spaced openings in the insulating layer 280, the insulating layer 275, and the conductive film that will become the conductive layers 112a and 112b. In other words, the aspect ratio of the openings increases, which can make their formation more difficult. Even if it were possible to form openings with a high aspect ratio, design problems could arise, such as increased difficulty in the process of filling the openings with gate insulating films and gate electrodes, and limitations on the channel length due to the thickness of the gate insulating film.

[0103] 6A , first openings are provided in the insulating layer 280, the insulating layer 275, and the conductive film that will be the source of the conductive layer 112a_2 and the conductive layer 112b_2, and second openings are provided in the conductive film that will be the source of the conductive layer 112a_1 and the conductive layer 112b_1. Therefore, when it is desired to shorten the channel length, the second openings can be formed at narrow intervals in a thin conductive film, which can reduce the difficulty of the process.

[0104] An insulating layer 275 is provided over the insulating layer 137, the conductive layer 112a, and the conductive layer 112b, and an insulating layer 280 is provided over the insulating layer 275. The insulating layer 280 functions as an interlayer film and is therefore preferably formed of a material with a relatively low dielectric constant. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between wirings can be reduced. The insulating layer 280 can be formed of the material that can be used for the insulating layer 216 described above.

[0105] The insulating layer 275 preferably has a barrier property against oxygen. By providing the insulating layer 275, it is possible to prevent oxygen contained in the insulating layer 280 from diffusing into the conductive layers 112a and 112b. Therefore, it is possible to prevent the conductive layers 112a and 112b from being oxidized by the oxygen contained in the insulating layer 280 and thereby prevent an increase in resistivity. It is preferable that the insulating layer 275 be at least less permeable to oxygen than the insulating layer 280.

[0106] The insulating layer 275 preferably has a barrier property against hydrogen. In an oxide semiconductor, defects in which hydrogen is introduced into oxygen vacancies (hereinafter referred to as V Ｏ When the insulating layer 275 is formed, electrons that serve as carriers are generated, and the conductivity type becomes n-type. By providing the insulating layer 275, hydrogen in the source region and the drain region of the semiconductor layer 111 can be prevented from diffusing to the outside, and an increase in resistance can be suppressed.

[0107] For example, silicon nitride is an example of a barrier insulator against oxygen. Also, oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride are examples of barrier insulators against hydrogen. Therefore, it is preferable to use a single silicon nitride layer or a stack of silicon nitride and one or more of the above oxides for the insulating layer 275.

[0108] An opening 118 reaching the semiconductor layer 111 is provided in the insulating layer 280, the insulating layer 275, and the conductive layer 112 which is the source of the conductive layer 112a and the conductive layer 112b, in a region overlapping with the conductive layer .

[0109] The conductive layers 112a and 112b are formed by providing the opening 118. An insulating layer 115 functioning as a second gate insulating film is provided in the opening 118, and a conductive layer 114 functioning as a second gate electrode is further provided so as to fill the opening 118.

[0110] 5A , in a region overlapping with the conductive layer 114 functioning as the second gate electrode, the insulating layer 115 functioning as the second gate insulating layer is provided so as to cover the surface of the semiconductor layer 111. The conductive layer 114 is also provided on the insulating layer 115 so as to fill the opening 118. Therefore, the surface of the fin-shaped semiconductor layer 111 is configured to face the conductive layer 114 across the insulating layer 115 over almost the entire surface.

[0111] In other words, in this region, the surface of the fin-shaped semiconductor layer 111 becomes a channel formation region over almost the entire surface, which can increase the channel width, thereby increasing the on-state current of the transistor and enabling the circuit to operate at high speed.

[0112] In addition, the insulating layer 280 and the insulating layer 275 have openings 119 that reach the conductive layer 112b in regions overlapping with the conductive layer 134.

[0113] An insulating layer 136 functioning as a dielectric layer of the capacitor 132 is provided in the opening 119, and a conductive layer 133 functioning as one electrode of the capacitor 132 is further provided so as to fill the opening 119. The insulating layer 136 is an insulating layer formed in the same process as the insulating layer 115.

[0114] 5C , insulating layer 136, which functions as a dielectric layer, is provided so as to cover the surface of conductive layer 112b. Conductive layer 133, which functions as the other electrode, is a conductive layer formed in the same process as conductive layer 114, and is provided on insulating layer 136 so as to fill opening 119. Therefore, the surface of conductive layer 112b, which covers fin-shaped semiconductor layer 111, is configured to face conductive layer 133 across insulating layer 115 over almost the entire surface.

[0115] That is, the surface of the conductive layer 112b covering the fin-shaped semiconductor layer 111 and the surface of the opposing conductive layer 133 both have large areas, which can increase the capacitance of the capacitor 132. Therefore, in the memory device, the data retention characteristics can be improved, and the reliability of data reading can be increased.

[0116] The insulating layer 115 and the insulating layer 136 are not limited to a single layer, and may be a stack of multiple layers. Note that although the structure of the insulating layer 115 will be described here, the insulating layer 136 can also have a similar structure.

[0117] The insulating layer 115 preferably has a function of capturing or fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the oxide semiconductor. Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0118] 6B , the insulating layer 115 preferably has a stacked structure of an insulating layer 115a in contact with the semiconductor layer 111, an insulating layer 115b on the insulating layer 115a, an insulating layer 115c on the insulating layer 115b, and an insulating layer 115d on the insulating layer 115c. In this case, the insulating layer 115a and the insulating layer 115c preferably have a function of capturing or fixing hydrogen.

[0119] Examples of insulators capable of capturing or fixing hydrogen include metal oxides having an amorphous structure. For the insulating layer 115a and the insulating layer 115c, it is preferable to use a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium. In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. In other words, metal oxides having an amorphous structure can be said to have a high ability to capture or fix hydrogen.

[0120] Furthermore, it is preferable to use a high-dielectric constant (high-k) material for the insulating layer 115a and the insulating layer 115c. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. Using a high-k material for the insulating layer 115a and the insulating layer 115c makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. Furthermore, it makes it possible to reduce the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator.

[0121] For the insulating layer 115a and the insulating layer 115c, an oxide containing one or both of aluminum and hafnium is preferably used, and an oxide having an amorphous structure and containing one or both of aluminum and hafnium is more preferably used.

[0122] In this embodiment, an aluminum oxide film is used as the insulating layer 115a. The aluminum oxide preferably has an amorphous structure. By providing the insulating layer 115a in contact with the semiconductor layer 111, hydrogen contained in the semiconductor layer 111 and the like can be more effectively captured and fixed.

[0123] In this embodiment, hafnium oxide is used as the insulating layer 115c. Here, by providing the insulating layer 115c between the insulating layer 115b and the insulating layer 115d, hydrogen contained in the insulating layer 115b and the like can be more effectively captured and fixed.

[0124] The insulating layer 115b is preferably made of a thermally stable insulator such as silicon oxide or silicon oxynitride. In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0125] In order to suppress oxidation of the conductive layer 112a, the conductive layer 112b, and the conductive layer 114 (second gate electrode), it is preferable to provide a barrier insulator against oxygen near each of the conductive layer 112a, the conductive layer 112b, and the conductive layer 114.

[0126] Examples of insulators having barrier properties against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). For example, the insulating layer 115a, the insulating layer 115c, and the insulating layer 115d each preferably have a single-layer structure or a multilayer structure of the above-mentioned oxygen barrier insulators.

[0127] The insulating layer 115a preferably has a barrier property against oxygen. The insulating layer 115a is preferably at least less permeable to oxygen than the insulating layer 280. The insulating layer 115a has a region in contact with the side surface of the conductive layer 112a and the side surface of the conductive layer 112b. The insulating layer 115a having a barrier property against oxygen can prevent the side surfaces of the conductive layer 112a and the conductive layer 112b from being oxidized and oxide films from being formed on the side surfaces. This can prevent a decrease in on-state current or a decrease in field-effect mobility of the transistor 110.

[0128] The insulating layer 115a is provided in contact with the top surface and side surfaces of the semiconductor layer 111 and the top surface of the insulating layer 137b. The insulating layer 115a has a barrier property against oxygen, which can prevent oxygen from being released from the channel formation region of the semiconductor layer 111 during heat treatment or the like. Therefore, oxygen vacancies can be reduced in the semiconductor layer 111.

[0129] Furthermore, by providing the insulating layer 115a, an excessive amount of oxygen can be prevented from being supplied from the insulating layer 280 to the semiconductor layer 111, and an appropriate amount of oxygen can be supplied to the semiconductor layer 111. Therefore, a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 110 due to excessive oxidation of the source and drain regions can be prevented.

[0130] An oxide containing one or both of aluminum and hafnium has a barrier property against oxygen and can therefore be suitably used for the insulating layer 115a.

[0131] The insulating layer 115d also preferably has a barrier property against oxygen. The insulating layer 115d is provided between the channel formation region of the semiconductor layer 111 and the conductive layer 114, and between the insulating layer 280 and the conductive layer 114. This structure can prevent oxygen contained in the channel formation region of the semiconductor layer 111 from diffusing to the conductive layer 114 and forming oxygen vacancies in the channel formation region of the semiconductor layer 111. Furthermore, it can prevent oxygen contained in the semiconductor layer 111 and oxygen contained in the insulating layer 280 from diffusing to the conductive layer 114 and oxidizing the conductive layer 114. The insulating layer 115d is preferably at least less permeable to oxygen than the insulating layer 280. For example, a silicon nitride film is preferably used as the insulating layer 115d.

[0132] The insulating layer 115d preferably has a barrier property against hydrogen, which can prevent impurities such as hydrogen contained in the conductive layer 114 from diffusing into the semiconductor layer 111.

[0133] Although the insulating layer 115 has been described above as having a four-layer structure of insulating layers 115 to 115, the present invention is not limited to this. The insulating layer 115 can have a structure including at least one of the insulating layers 115a to 115d. By forming the insulating layer 115 using one, two, or three of the insulating layers 115a to 115d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0134] 6A and 6B, the conductive layer 114 may have a structure including a conductive layer 114a and a conductive layer 114b disposed over the conductive layer 114a. Note that although the structure of the conductive layer 114 will be described here, the conductive layer 133 may also have a similar structure.

[0135] For example, the conductive layer 114a is preferably disposed so as to be in contact with the bottom surface and side surfaces of the conductive layer 114b. In this case, the conductive layer 114a is preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion.

[0136] The conductive layer 114a is preferably made of a conductive material that has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms, or a conductive material that has a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0137] Furthermore, since the conductive layer 114a has a function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductive layer 114b caused by oxygen contained in the insulating layer 280, etc. As a conductive material having a function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0138] The conductive layer 114b is preferably formed using a material with high conductivity. For example, the conductive layer 114b can be formed using a conductive material containing tungsten, copper, or aluminum as a main component. The conductive layer 114b may have a stacked structure, for example, a stacked structure of titanium or titanium nitride and the above-mentioned conductive material. When the conductive layer 114 is a single layer, it is preferably formed using a material that can be used for the conductive layer 114b.

[0139] An insulating layer 282 and an insulating layer 285 are provided over the insulating layer 280 , the conductive layer 114 , the conductive layer 133 , the insulating layer 115 , and the insulating layer 136 .

[0140] The insulating layer 282 is preferably a stack of insulating layers 282a and 282b. One or both of the insulating layers 282a and 282b may contain hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (for example, copper atoms ...

[0141] With this structure, impurities such as water and hydrogen can be prevented from diffusing from an interlayer insulating film disposed above the insulating layer 282b to the transistor 110. Furthermore, providing the insulating layers 282a and 282b can prevent oxygen contained in the semiconductor layer 111 from diffusing above the transistor 110. Therefore, excessive oxygen and hydrogen can be prevented from diffusing into the oxide semiconductor. This can improve the electrical characteristics and reliability of the semiconductor device.

[0142] Since the insulating layer 285 functions as an interlayer film, it is preferable that the insulating layer 285 be formed of a material with a relatively low dielectric constant. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between wirings can be reduced. The insulating layer 285 can be formed of the material that can be used for the insulating layer 216 described above.

[0143] The insulating layer 285, the insulating layer 282, and the insulating layer 280 are provided with an opening 243a that reaches the conductive layer 112a that is one of the source and drain electrodes of the transistor 110, and an opening 243b that reaches the conductive layer 133 that is one electrode of the capacitor 131. An insulating layer 241 is provided on inner walls of the two openings, a conductive layer 240a is provided to fill the opening 243a, and a conductive layer 240b is provided to fill the opening 243b.

[0144] The insulating layer 241 can be a barrier insulating film that can be used for the insulating layer 275, etc. By providing the insulating layer 241, impurities such as water and hydrogen contained in the insulating layer 280, etc. can be prevented from being mixed into the oxide semiconductor 230 through the conductive layer 240a. Furthermore, oxygen contained in the insulating layer 280 can be prevented from being absorbed by the conductive layers 240a and 240b.

[0145] The conductive layers 240a and 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductive layers 240a and 240b may also have a two-layer structure in which a first conductor is provided in contact with the side surface of the insulating layer 241 and a second conductor is provided further inside. In this case, the above-described conductive material can be used as the second conductor.

[0146] Furthermore, when the conductive layers 240a and 240b have a two-layer structure, the first conductor is preferably made of a conductive material that has a function of suppressing the permeation of impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. With such a structure, impurities such as water and hydrogen contained in layers above the insulating layer 282 can be prevented from being mixed into the semiconductor layer 111 through the conductive layers 240a and 240b.

[0147] 4B and 5B , a fin-shaped semiconductor layer 111 having a large surface area is provided in the opening 243a, and a conductive layer 112a which is one of the source electrode and the drain electrode of the transistor 110 is provided so as to cover the semiconductor layer 111. Therefore, by filling the opening 243a with the conductive layer 240a, the contact area between the conductive layer 112a and the conductive layer 240a can be increased, and the contact resistance can be reduced.

[0148] A wiring 117 electrically connected to the conductive layer 240a and a wiring 138 electrically connected to the conductive layer 240b are provided over the insulating layer 285. The wiring 117 and the wiring 138 can be formed using a material similar to that of the conductive layers 240a and 240b.

[0149] Next, an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described with reference to Figures 8A to 18D. Here, the case of manufacturing the semiconductor device illustrated in Figures 4A to 5C will be described as an example.

[0150] (A) in each figure is a cross-sectional view at the same position as in Fig. 4A, corresponding to the section A1-A2 in Fig. 2A. (B) in each figure is a cross-sectional view at the same position as in Fig. 5A, corresponding to the section B1-B2 in Fig. 2A. (C) in each figure is a cross-sectional view at the same position as in Fig. 5B, corresponding to the section B3-B4 in Fig. 2A. (D) in each figure is a cross-sectional view at the same position as in Fig. 5C, corresponding to the section B5-B6 in Fig. 2A.

[0151] In the following, an insulating film for forming an insulating layer, a conductive film for forming a conductive layer, or a semiconductor film for forming a semiconductor layer can be formed by appropriately using a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0152] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0153] CVD methods can be classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, and photo-CVD (photo-CVD) methods that utilize light. CVD methods can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0154] The plasma CVD method can produce high-quality films at relatively low temperatures. However, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the semiconductor device may be destroyed by the accumulated electric charge. The thermal CVD method is a film formation method that does not use plasma and can reduce plasma damage to the surface to be formed, resulting in films with fewer defects. Since the thermal CVD method does not cause plasma damage, it can increase the yield of semiconductor devices.

[0155] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0156] The CVD method and the ALD method are film formation methods with good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a fast film formation rate.

[0157] First, an insulating layer 215 is formed on a substrate (not shown). An insulating layer 216 is formed on the insulating layer 215 (see FIGS. 8A to 8D ). The insulating layers 215 and 216 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method, and preferably, a sputtering method is used. Since a sputtering method does not require the use of a gas containing hydrogen as a deposition gas, the hydrogen concentration in the insulating layers 215 and 216 can be reduced.

[0158] Two openings reaching the insulating layer 215 are formed in the insulating layer 216, and the conductive layer 116 is formed in one opening and the conductive layer 134 is formed in the other opening. The conductive layer 116 and the conductive layer 134 can be formed by depositing a conductive layer so as to fill the two openings and removing part of the conductive layer by CMP treatment.

[0159] Next, the insulating layer 137a and the insulating layer 137b are formed over the insulating layer 216, the conductive layer 116, and the conductive layer 134. The insulating layer 137a and the insulating layer 137b can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0160] For example, silicon nitride is formed as the insulating layer 137a by PEALD, and hafnium oxide is formed as the insulating layer 137b by thermal ALD. By using silicon nitride, which has the function of suppressing hydrogen diffusion, for the insulating layer 137a, hydrogen diffusion from the lower layer of the transistor can be suppressed. Furthermore, by using hafnium oxide, which has the function of capturing or fixing hydrogen, for the insulating layer 137b, hydrogen contained in the semiconductor layer 111 can be captured or fixed to the insulating layer 137b. This reduces the hydrogen concentration in the semiconductor layer 111 and its vicinity.

[0161] Next, an insulating film is formed over the insulating layer 137b and etched to form an insulating layer 223. The insulating layer 223 functions as a support for forming the semiconductor layer 111 (oxide semiconductor). The insulating layer 223 may be formed using, for example, an insulator that can be used for the insulating layer 216.

[0162] The insulating layer 223 is processed into an island shape by lithography. Dry etching or wet etching can be used for this processing. Note that a plurality of insulating layers 223 may be formed. Note that the side surfaces of the insulating layer 223 are preferably perpendicular or approximately perpendicular to the top surface of the insulating layer 137b. This structure facilitates the formation of the semiconductor layer 111 in a later step.

[0163] Next, a semiconductor film 111f to be the semiconductor layer 111 is formed so as to cover the insulating layer 223 (see FIGS. 9A to 9D). The semiconductor film 111f can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0164] The semiconductor film 111f is preferably formed to have a uniform thickness along the surface of the insulating layer 223. Therefore, the semiconductor film 111f is preferably formed by an ALD method or the like, which has good coverage.

[0165] Furthermore, when the semiconductor film 111f has a three-layer structure using oxide semiconductor, for example, it is preferable to deposit the first and third layers by the ALD method and the second layer sandwiched between the first and third layers by the sputtering method.

[0166] The semiconductor film 111f is preferably subjected to heat treatment. The heat treatment is preferably performed within a temperature range in which the semiconductor film 111f does not become polycrystallized. The heat treatment can be performed using a furnace capable of controlling the atmosphere, for example, at 450° C. for one hour with a flow ratio of nitrogen gas to oxygen gas of 4:1.

[0167] By forming an oxide semiconductor film and performing heat treatment using the above method, crystal growth progresses from the second layer to other layers, and the crystallinity of the semiconductor film 111f in the film thickness direction can be increased. This improves the on-state current, S value, field-effect mobility, and frequency characteristics of the transistor, thereby providing a semiconductor device with good electrical characteristics. In addition, a highly reliable semiconductor device can be provided.

[0168] Next, a portion of the semiconductor film 111f is removed by anisotropic etching, and then the insulating layer 223 is removed (see FIGS. 10A to 10D). Since the semiconductor film 111f is etched mainly in the portion parallel to the substrate surface, a sidewall-shaped semiconductor layer 111 is formed in contact with the side surface of the insulating layer 223. Then, the insulating layer 223 is removed to form a fin-shaped semiconductor layer 111.

[0169] The anisotropic etching of the semiconductor film 111f is preferably performed by dry etching, and the insulating layer 223 can be removed by dry etching or wet etching.

[0170] Next, a conductive film 112f is formed over the insulating layer 137 and the semiconductor layer 111 (see FIGS. 11A to 11D). The conductive film 112f can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0171] Next, the conductive film 112f is processed into an island shape by lithography to form the conductive layer 112A (see FIGS. 12A to 12D). This processing can be performed by dry etching or wet etching. At this point, the basic structure of the capacitor 132 is completed.

[0172] Next, an insulating layer 275 is formed to cover the conductive layer 112A, and an insulating layer 280 is further formed on the insulating layer 275 (see FIGS. 13A to 13D ). The insulating layers 275 and 280 can each be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. As the insulating layer 280, it is preferable to form an insulating film that will become the insulating layer 280 and then perform CMP treatment on the insulating film to form an insulator with a flat upper surface.

[0173] Next, the conductive layer 112A, the insulating layer 275, and the insulating layer 280 are processed using lithography to form the opening 118A and the opening 119 that reach the conductive layer 112A (see FIGS. 14A to 14D).

[0174] Subsequently, the conductive layer 112A is processed by lithography to form openings 118 that reach the semiconductor layer 111 (see FIGS. 15A to 15D). Here, the conductive layer 112A is divided into conductive layers 112a and 112b.

[0175] As described above, since the transistor portion and the capacitor portion have different configurations, the openings 118 and 119 are separately formed. The above processing is preferably performed by dry etching, which allows anisotropic etching and is suitable for forming openings with a high aspect ratio.

[0176] 15A shows an example in which the widths of the openings 118 formed in the conductive layer 112A, the insulating layer 275, and the insulating layer 280 are the same, but when the channel length is to be made shorter, it is preferable to make the width of the openings formed in the conductive layer 112A narrower than the width of the openings formed in the insulating layer 275 and the insulating layer 280 so as to have a shape similar to that shown in FIG. 6A . This configuration makes it easier to form the openings 118 and to fill the openings 118 with a gate insulating film and a gate electrode.

[0177] It is preferable to perform a heat treatment after the etching. The temperature of the heat treatment is 100°C or higher and 650°C or lower, preferably 250°C or higher and 600°C or lower, more preferably 300°C or higher and 550°C or lower, and even more preferably 350°C or higher and 400°C or lower. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. The heat treatment is preferably performed in an atmosphere containing oxygen. For example, it is preferable to perform the treatment at a temperature of 350°C for 1 hour with a flow rate ratio of nitrogen gas to oxygen gas of 4:1.

[0178] As a result, oxygen can be supplied to the semiconductor layer 111 (oxide semiconductor), and oxygen vacancies can be reduced. In addition, by performing such heat treatment, the crystallinity of the oxide semiconductor can be improved. Furthermore, the supplied oxygen reacts with hydrogen remaining in the oxide semiconductor, converting the hydrogen into H ２ Therefore, hydrogen remaining in the oxide semiconductor 230 is recombined with the oxygen vacancies to form V. Ｏ The formation of H can be suppressed. Therefore, the electrical characteristics of the transistor including the oxide semiconductor 230 can be improved, and the reliability can be improved.

[0179] Next, an insulating film 115f that will become the insulating layer 115 and the insulating layer 136 is formed so as to cover the inner walls and bottoms of the openings 118 and 119 formed in the insulating layer 280 or the like (see FIGS. 16A to 16D ). Here, the insulating film 115f is in contact with the insulating layer 280, the insulating layer 275, the conductive layer 112a, the conductive layer 112b, the insulating layer 137b, and the semiconductor layer 111.

[0180] The insulating film 115f can be formed by sputtering, CVD, MBE, PLD, or ALD.

[0181] After the insulating film 115f is formed, microwave plasma treatment is preferably performed in an atmosphere containing oxygen. The frequency of the microwave plasma treatment apparatus is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, for example, 2.45 GHz. High-density plasma using microwaves can generate high-density oxygen radicals.

[0182] The microwave plasma treatment is preferably carried out under reduced pressure, with the pressure preferably being 10 Pa or more and 1000 Pa or less, and more preferably being 300 Pa or more and 700 Pa or less. The treatment temperature is preferably 750°C or less, more preferably 500°C or less, and can be, for example, about 250°C. After the oxygen plasma treatment, a heat treatment may be carried out without exposure to the outside air. The heat treatment temperature is, for example, preferably 100°C or more and 750°C or less, and more preferably 300°C or more and 500°C or less.

[0183] The microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. Here, the oxygen flow ratio (O ２ / (O ２ The oxygen flow rate ratio (O + Ar) is greater than 0% and less than or equal to 100%. ２ / (O ２ The oxygen flow rate ratio (O ２ / (O ２ The oxygen flow rate ratio (O ２ / (O ２+Ar)) is set to 10% or more and 30% or less.

[0184] By performing microwave plasma treatment in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to the channel formation region of the oxide semiconductor. Ｏ The H can be split into oxygen vacancies and hydrogen, and the hydrogen can be removed from the region. Also, oxygen radicals generated by the oxygen plasma can be supplied to the oxygen vacancies formed in the channel formation region.

[0185] Therefore, the carrier concentration in the oxide semiconductor can be reduced in the channel formation region, making the channel formation region i-type or substantially i-type, thereby suppressing fluctuations in the electrical characteristics of the transistor and suppressing variations in the electrical characteristics of the transistor within the substrate surface.

[0186] Next, a conductive film 114f to be the conductive layer 114 and the conductive layer 133 is formed on the insulating film 115f (see FIGS. 17A to 17D). The conductive film 114f can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, a plating method, or an ALD method.

[0187] Next, the insulating film 115f and the conductive film 114f are polished by CMP until the insulating layer 280 is exposed (see FIGS. 18A to 18D ). As a result, the insulating layer 115 and the conductive layer 114 are formed in the opening 118, and the insulating layer 136 and the conductive layer 133 are formed in the opening 119.

[0188] Through the above steps, the transistor 110, the capacitor 131, and the capacitor 132 can be formed.

[0189] Furthermore, after forming the insulating layer 282 and the insulating layer 285, two openings are formed therein, and conductive layers 240a, 240b, wiring 117, and wiring 138 are provided, whereby the semiconductor device configuration shown in Figures 4A to 5C can be manufactured.

[0190] If it is desired to further increase the capacitance of the capacitance elements 131 and 132, a configuration may be used in which the semiconductor layer 111 shown in FIG. 7A is extended into a substantially L-shape in top view, as shown in FIGS. 19A and 19B.

[0191] 19A is a perspective view including a cross section of a transistor 110L having an L-shaped semiconductor layer 111 and capacitors 131L and 132L, and FIG. 19B is a top view. Note that the cross section taken along C1-C2 in FIG. 19B is shown in the perspective view of FIG. 19A. A conductive layer 112a or a conductive layer 112b is provided on the L-shaped semiconductor layer 111 except for the channel formation region of the transistor 110L.

[0192] With this structure, the surface area of ​​the conductive layer 112b used as the electrode of the capacitors 131 and 132 can be increased, and accordingly, the area of ​​the conductive layer 133 and the conductive layer 134 overlapping with the conductive layer 112b can be increased, thereby increasing the capacitance. Note that the shape of the semiconductor layer 111 in top view is not limited to an L-shape and may be a T-shape, a U-shape, an S-shape, or the like.

[0193] This embodiment mode can be combined as appropriate with the descriptions of other embodiment modes or examples.

[0194] Embodiment 2 In this embodiment, an oxide semiconductor that can be used for the semiconductor layer 111 included in the transistor and the capacitor described in Embodiment 1 will be described.

[0195] The crystallinity of the semiconductor material used for the oxide semiconductor layer is not particularly limited, and any of an amorphous semiconductor, a single-crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. The use of a single-crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics. Note that the oxide semiconductor layer may have a stacked structure of two or more layers.

[0196] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of a transistor can be reduced. Because the off-state current of an OS transistor is low, the power consumption of a semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0197] The oxide semiconductor layer preferably includes a crystalline metal oxide. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0198] The oxide semiconductor layer preferably includes a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and are connected without being oriented in the a-b plane. Furthermore, when a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, an oxide semiconductor layer having a CAAC structure can also be said to have a structure having layered crystal parts.

[0199] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0200] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0201] Examples of metal oxides contained in the oxide semiconductor layer of one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide. The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, e.g., a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may also include metalloid elements.

[0202] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and indium aluminum oxide. Examples of usable materials include indium zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Other examples include indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0203] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-current and high frequency characteristics.

[0204] Instead of indium, the metal oxide may contain one or more metal elements with higher periodic numbers in the periodic table. Alternatively, the metal oxide may contain, in addition to indium, one or more metal elements with higher periodic numbers in the periodic table. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element with a higher periodic number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements with higher periodic numbers in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0205] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0206] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0207] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0208] In the present embodiment, an In—Ga—Zn oxide may be used as an example of the metal oxide.

[0209] For example, the oxide semiconductor layer can have a stacked structure of two or more metal oxide layers with different crystallinity. In this case, the two or more metal oxide layers may have different compositions or may have the same or approximately the same composition. For example, when a metal oxide has a two-layer structure, the surface on which the second metal oxide layer is formed is the surface of the first metal oxide layer, so that the crystallinity of the second metal oxide layer can be increased in some cases. Furthermore, by performing heat treatment (also referred to as crystallization treatment) after forming the second metal oxide layer, the crystallinity of the first layer can be increased.

[0210] For example, a first metal oxide layer is formed using an ALD method, and a second metal oxide layer is formed using a sputtering method to have a higher crystallinity than the first layer. Heat treatment can then be performed to improve the crystallinity of the first and second metal oxide layers. In this case, the crystals in the second layer grow continuously vertically toward the first layer, and the boundary between the first and second layers may become indistinguishable from cross-sectional observation.

[0211] Alternatively, a three-layer structure may be formed by depositing a third metal oxide layer on the second metal oxide layer using an ALD method. After the deposition of the third metal oxide layer, heat treatment can be performed to improve the crystallinity of the first to third metal oxide layers. In this case, the crystals contained in the second layer grow continuously vertically toward the first and third layers and then laterally, which may result in the boundary between the first and second layers and the boundary between the second and third layers becoming indistinguishable from cross-sectional observation.

[0212] In this way, by stacking a metal oxide layer with low crystallinity and a metal oxide layer with high crystallinity, continuous crystal growth occurs between them in the film thickness direction, and a semiconductor layer with high crystallinity can be formed throughout the entire film thickness. Alternatively, by stacking a metal oxide layer with low crystallinity and a metal oxide layer with high crystallinity and then performing heat treatment, continuous crystal growth occurs between them in the film thickness direction, and a semiconductor layer with high crystallinity can be formed throughout the entire film thickness. This makes it possible to realize a highly reliable transistor.

[0213] For example, in a three-layer structure in which a first metal oxide layer is formed by ALD, a second metal oxide layer is formed by sputtering to have a CAAC structure, and a third metal oxide layer is formed by ALD, the second CAAC structure can be used as a nucleus or seed to enhance the crystallinity of the upper and lower metal oxide layers. A metal oxide layer with enhanced crystallinity can be called an axial growth CAAC (AG CAAC).

[0214] The heat treatment is carried out at a temperature of 100° C. to 800° C., preferably 250° C. to 650° C., and more preferably 350° C. to 550° C. The treatment time is preferably, for example, 1 minute to 1 hour, or 10 minutes to 30 minutes, at a temperature of 350° C. to 550° C.

[0215] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA device may be used.

[0216] Examples of RTA devices that can be used include LRTA (Lamp Rapid Thermal Anneal) devices and GRTA (Gas Rapid Thermal Anneal) devices. LRTA devices are devices that heat workpieces by radiating light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. GRTA devices are devices that perform heat treatment using high-temperature gas.

[0217] Increasing the atomic ratio of zinc in the composition of an oxide semiconductor can improve the crystallinity of the oxide semiconductor. In particular, when the oxide semiconductor has a stacked structure of two or more metal oxide layers as described above, it is preferable that the first metal oxide layer contains zinc. For example, when the first metal oxide layer is formed by an ALD method and the second metal oxide layer is formed by a sputtering method, zinc contained in the first metal oxide layer may diffuse into the second metal oxide layer. This diffusion may occur during sputtering or subsequent heat treatment. The diffusion of zinc from the first metal oxide layer to the second metal oxide layer is expected to improve crystallinity. Alternatively, the diffusion of zinc from the first metal oxide layer to the second metal oxide layer is expected to promote the lateral growth of crystal parts having c-axis orientation, thereby accelerating the formation of CAAC.

[0218] Note that it is preferable to perform a treatment for improving the crystallinity of the oxide semiconductor layer during or after the formation of the oxide semiconductor layer. Examples of the treatment for improving the crystallinity of the oxide semiconductor layer include heat treatment, plasma treatment, microwave (typically, 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. Note that a plurality of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

[0219] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0220] Furthermore, it is more preferable to perform the treatment for increasing the crystallinity of the oxide semiconductor layer multiple times during the formation of the oxide semiconductor layer. For example, when the oxide semiconductor layer is formed by an ALD method, it is preferable to perform microwave plasma treatment every time an atomic layer is formed. Alternatively, it is preferable to perform the treatment for increasing the crystallinity every time an oxide semiconductor layer having a thickness within a predetermined range is formed, in order to increase productivity. Specifically, it is preferable to form a first oxide semiconductor layer having a thickness of 1 nm to 10 nm, perform the first microwave plasma treatment, and then form a second oxide semiconductor layer having a thickness of 1 nm to 10 nm, and perform the second microwave plasma treatment. Note that the method for forming the first oxide semiconductor layer and the second oxide semiconductor layer is not particularly limited, and ALD or sputtering may be used, respectively. In particular, forming the first oxide semiconductor layer by an ALD method is preferable because it can prevent elements of the layers constituting the formation surface from being mixed (also referred to as mixing) into the first oxide semiconductor layer and the second oxide semiconductor layer. This is particularly suitable when the element contained in the layer constituting the formation surface inhibits crystallization of the oxide semiconductor (for example, when silicon, carbon, or the like is contained). The first oxide semiconductor layer and the second oxide semiconductor layer may have different compositions. Although a stacked structure of the first oxide semiconductor layer and the second oxide semiconductor layer is illustrated here, the present invention is not limited to this. The same treatment can be applied to a single oxide semiconductor layer or a stacked structure of three or more layers.

[0221] Treatment for increasing the crystallinity of the oxide semiconductor layer may be performed after the oxide semiconductor layer is formed. Specifically, the treatment may be performed directly on the formed oxide semiconductor layer, or may be performed through another film such as an insulating film formed on the oxide semiconductor layer. For example, microwave plasma treatment may be performed after the oxide semiconductor layer is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, or an aluminum oxide film) may be formed after the oxide semiconductor layer is formed, and then heat treatment or microwave plasma treatment may be performed on the oxide semiconductor layer through the insulating film.

[0222] Note that the treatment for increasing the crystallinity of the oxide semiconductor layer can also serve as treatment for removing impurities contained in the oxide semiconductor layer. For example, carbon, hydrogen, nitrogen, and the like contained in the oxide semiconductor layer can be preferably removed. Alternatively, by performing the treatment for increasing the crystallinity of the oxide semiconductor layer in an oxygen gas atmosphere, oxygen vacancies in the oxide semiconductor layer can be reduced.

[0223] When the treatment for increasing the crystallinity of the oxide semiconductor layer is performed, the temperature of the substrate is preferably set to room temperature (for example, 25° C.) or higher, 100° C. or higher and 600° C. or lower, or 300° C. or higher and 450° C. The temperature of the heat treatment is preferably set to 100° C. or higher and 700° C. or lower, or 300° C. or higher and 450° C.

[0224] By increasing the crystallinity of the oxide semiconductor layer, a highly reliable transistor can be realized.

[0225] It is preferable that the amount of hydrogen in the oxide semiconductor layer be reduced as much as possible. Hydrogen in the oxide semiconductor layer is generated by oxygen vacancies (V Ｏ ) and V Ｏ Defects with hydrogen in the Ｏ H), which may deteriorate transistor characteristics (for example, the Id-Vg characteristics of the initial transistor or the Id-Vg characteristics in a long-term reliability test).

[0226] Therefore, a material that releases little hydrogen is preferably used as a material surrounding the oxide semiconductor layer, for example, as a material used for an insulator in contact with the oxide semiconductor layer, such as silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide.

[0227] This can prevent hydrogen from entering the oxide semiconductor layer. In particular, using silicon nitride for at least one of the insulators in contact with the oxide semiconductor layer can improve the reliability of the transistor. Note that a material that releases little hydrogen may have a function of capturing or fixing (also known as gettering) hydrogen inside the insulator.

[0228] The semiconductor device of this embodiment may also be applied to a transistor using another semiconductor material in the channel formation region. Examples of such another semiconductor material include semiconductors made of simple elements or compound semiconductors. Examples of semiconductors made of simple elements include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned oxide semiconductor is also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0229] Silicon that can be used as a semiconductor material for transistors includes single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low temperature polysilicon (LTPS).

[0230] This embodiment mode can be combined as appropriate with the descriptions of other embodiment modes or examples.

[0231] Embodiment 3 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0232] Fig. 20 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 20 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 20 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0233] The transistor, the capacitor, or the like described in Embodiment 1 can be applied to the memory cell 950. By using the transistor, the capacitor, or the like, the operation speed of the memory device can be improved. Furthermore, miniaturization and high integration of the memory device can be achieved. Furthermore, the capacitance per area of ​​the memory device can be increased.

[0234] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0235] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0236] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0237] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0238] The voltage generating circuit 928 has a function of generating a voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a voltage.

[0239] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0240] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0241] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0242] The PSW 931 is a V ＤＤ The PSW 932 has the function of controlling the supply of V to the row driver 923. ＨＭ Here, the high power supply voltage of the semiconductor device 900 is V ＤＤ and the low power supply voltage is GND (ground potential). ＨＭ is the high power supply voltage used to drive the word line high, and V ＤＤ 20, in the peripheral circuit 915, V ＤＤ Although the number of power domains to which power is supplied is set to one, it is also possible to set it to a plurality of power domains. In this case, a power switch may be provided for each power domain.

[0243] 21A to 21H, examples of other memory cell configurations that can be applied to the memory cell 950 will be described.

[0244] 21A shows an example of a circuit configuration of a DRAM memory cell. In this specification and the like, a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0245] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring that supplies a constant potential or a signal, or the front gate and the back gate may be connected to each other.

[0246] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0247] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0248] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and connecting the wiring BIL and the first terminal of the capacitor CA.

[0249] Furthermore, the memory cell that can be used for the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 952 shown in FIG. 21B may have a configuration. The memory cell 952 is an example in which the memory cell 952 does not include a capacitor CA and a wiring CAL. The first terminal of the transistor M1 is in an electrically floating state.

[0250] In the memory cell 952, the potential written through the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0251] Note that the transistor M1 is preferably the OS transistor described in Embodiment 1. For example, the transistor M1 and the capacitor CA of the memory cell 951 can have the structures of the transistor 110 and the capacitors 131 and 132 shown in FIGS.

[0252] By using the OS transistor described in Embodiment 1, the operation speed of the memory device can be improved. Furthermore, the area occupied by the memory cell can be reduced. Furthermore, the OS transistor has a characteristic of extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be significantly reduced. That is, written data can be held by the transistor M1 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, because the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 951 and the memory cell 952.

[0253] 21C shows an example circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a storage device having a gain cell type memory cell using an OS transistor as the transistor M2 is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0254] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0255] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0256] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and connecting the wiring WBL to the first terminal of the capacitance element CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitance element CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitance element CB and the potential of the gate of the transistor M3.

[0257] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0258] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in FIG. 21D. The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0259] 21E is an example in which the capacitance element CB and the wiring CAL in the memory cell 953 are omitted. Also, the memory cell 956 in Fig. 21F is an example in which the capacitance element CB and the wiring CAL in the memory cell 954 are omitted. With such a configuration, the integration degree of the memory cells can be increased.

[0260] Note that at least the transistor M2 is preferably the OS transistor described in Embodiment 1. For example, the transistor M2, the transistor M3, and the capacitor CB of the memory cell 953 and the memory cell 954 can have the structures of the transistor 110 and the capacitors 131 and 132 shown in FIGS. 4A to 5C . By using the OS transistor described in Embodiment 1, the operation speed of the memory device can be improved. Furthermore, the area occupied by the memory cell can be reduced.

[0261] Since the OS transistor has an extremely low off-state current, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956.

[0262] The memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956, in which an OS transistor is used as the transistor M2, are one embodiment of an NOSRAM.

[0263] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0264] When an OS transistor is used as the transistor M3, the memory cell can be configured as a unipolar circuit.

[0265] 21G shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 has transistors M4 to M6 and a capacitor CC.

[0266] The first terminal of the transistor M4 is connected to the first terminal of the capacitor CC, the second terminal of the transistor M4 is connected to the wiring BIL, and the gate of the transistor M4 is connected to the wiring WOL. The second terminal of the capacitor CC is electrically connected to the first terminal of the transistor M5 and the wiring GNDL. The second terminal of the transistor M5 is connected to the first terminal of the transistor M6, and the gate of the transistor M5 is connected to the first terminal of the capacitor CC. The second terminal of the transistor M6 is connected to the wiring BIL, and the gate of the transistor M6 is connected to the wiring RWL.

[0267] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0268] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and connecting the wiring BIL to the first terminal of the capacitor CC. Specifically, when the transistor M4 is turned on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0269] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0270] Note that at least the transistor M4 is preferably the OS transistor described in Embodiment 1. By using the OS transistor described in Embodiment 1, the area occupied by the memory cell can be reduced.

[0271] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0272] When OS transistors are used as the transistors M5 and M6, the memory cell can be configured as a unipolar circuit.

[0273] 21H shows an example of an SRAM (Static Random Access Memory) using an OS transistor. In this specification and the like, an SRAM using an OS transistor is referred to as an OS-SRAM (Oxide Semiconductor-SRAM). Note that a memory cell 958 shown in FIG. 21H is a memory cell of an SRAM capable of backing up data.

[0274] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that the transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

[0275] A first terminal of transistor M7 is connected to wiring BIL, and a second terminal of transistor M7 is connected to a first terminal of transistor MS1, a first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and a first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. A first terminal of transistor M8 is connected to wiring BILB, and a second terminal of transistor M8 is connected to a first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and a first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0276] A second terminal of the transistor MS1 is electrically connected to the wiring VDL. A second terminal of the transistor MS2 is electrically connected to the wiring VDL. A second terminal of the transistor MS3 is electrically connected to the wiring GNDL. A second terminal of the transistor MS4 is electrically connected to the wiring GNDL.

[0277] A second terminal of the transistor M9 is connected to a first terminal of the capacitor CD1, and a gate of the transistor M9 is connected to the wiring BRL. A second terminal of the transistor M10 is connected to a first terminal of the capacitor CD2, and a gate of the transistor M10 is connected to the wiring BRL.

[0278] A second terminal of the capacitance element CD1 is connected to the wiring GNDL, and a second terminal of the capacitance element CD2 is connected to the wiring GNDL.

[0279] The wirings BIL and BILB function as bit lines, the wiring WOL functions as a word line, and the wiring BRL is a wiring that controls the conductive state and non-conductive state of the transistors M9 and M10.

[0280] The wiring VDL is a wiring that applies a high-level potential, and the wiring GNDL is a wiring that applies a low-level potential.

[0281] Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is in a conductive state, a potential corresponding to information to be recorded is applied to the wiring BIL, and the potential is written to the second terminal of the transistor M10.

[0282] Since the memory cell 958 includes an inverter loop formed by the transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Because the transistor M8 is conductive, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Furthermore, because the transistors M9 and M10 are conductive, the potentials of the second terminals of the transistors M7 and M8 are held in the first terminals of the capacitors CD2 and CD1, respectively. Subsequently, a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL to turn off the transistors M7 to M10, thereby holding the potentials of the first terminals of the capacitors CD1 and CD2.

[0283] Data is read by precharging the wirings BIL and BILB to a predetermined potential in advance, and then applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL, so that the potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB. Also, the potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL. In the wirings BIL and BILB, the potentials of the first terminal of the capacitor CD2 and the first terminal of the capacitor CD1 change from the precharged potentials, respectively, so that the potential held in the memory cell can be read from the potential of the wiring BIL or the wiring BILB.

[0284] Note that OS transistors are preferably used as the transistors M7 to M10. This allows written data to be held by the transistors M7 to M10 for a long time, thereby reducing the frequency of refreshing the memory cells. Alternatively, refreshing the memory cells can be eliminated. Furthermore, by using the OS transistors described in Embodiment 1 as the transistors M7 to M10, the operating speed of the memory device can be improved. Furthermore, the area occupied by the memory cells can be reduced.

[0285] Note that Si transistors may be used as the transistors MS1 to MS4.

[0286] The driver circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in FIG. 22A, the driver circuit 910 and memory array 920 may be provided overlapping each other. By providing the driver circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 22B, the memory array 920 may be provided in multiple layers on the driver circuit 910.

[0287] In the above-described memory array 920, a plurality of memory arrays can be stacked. The memory density of the memory cells 951 can be improved by arranging the plurality of memory arrays in the memory array 920 in the vertical direction of the substrate surface on which the driver circuit 910 is provided. Furthermore, the memory array 920 can be fabricated using the same manufacturing process repeatedly in the vertical direction. The semiconductor device 900 can reduce the manufacturing cost of the memory array 920.

[0288] Next, an example of a processing unit that can include a semiconductor device such as the memory device will be described.

[0289] 23 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in FIG. 23 can be applied to, for example, a CPU (Central Processing Unit). The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0290] The arithmetic device 960 shown in FIG. 23 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be provided on separate chips.

[0291] The cache 999 is connected to a main memory provided on a separate chip via a cache interface 989. The cache interface 989 has a function of supplying part of the data held in the main memory to the cache 999. The cache interface 989 also has a function of outputting part of the data held in the cache 999 to the ALU 991, register 996, etc. via the bus interface 998.

[0292] As will be described later, a memory array 920 can be provided by stacking it on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 989 may have a function of supplying data held in the memory array 920 to the cache 999. In this case, it is preferable that a drive circuit 910 be included as part of the cache interface 989.

[0293] It is also possible to use only the memory array 920 as a cache without providing the cache 999 .

[0294] The arithmetic device 960 shown in FIG. 23 is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 23 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle via its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0295] An instruction input to the arithmetic unit 960 via the bus interface 998 is input to the instruction decoder 993, decoded, and then input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0296] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals for controlling the operation of the ALU 991. Furthermore, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 997 generates an address for a register 996 and reads or writes data from or to the register 996 depending on the state of the arithmetic unit 960.

[0297] Furthermore, the timing controller 995 generates signals that control the timing of the operations of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997. For example, the timing controller 995 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0298] 23, the register controller 997 selects the holding operation of the register 996 in accordance with an instruction from the ALU 991. That is, it selects whether the memory cells of the register 996 will hold data using flip-flops or using capacitance elements. If holding data using flip-flops is selected, a power supply voltage is supplied to the memory cells in the register 996. If holding data using capacitance elements is selected, the data is rewritten to the capacitance elements, and the supply of power supply voltage to the memory cells in the register 996 can be stopped.

[0299] FIG. 24 shows an example in which a substrate 990 is provided with not only the arithmetic unit 960 but also a storage device 962, an interface circuit 964, an input / output unit 966, and the like.

[0300] The memory device 962 can be used as a cache lower in level than the cache 999, or as a main memory. The memory device 962 is connected to a cache interface 989 in the arithmetic device 960 via an interface circuit 964. The memory device 962 is also connected to a main memory provided on a separate chip via the interface circuit 964 and an input / output unit 966.

[0301] The semiconductor device 900 having the memory array 920 can be applied to the memory device 962 .

[0302] Various interface circuits and bus lines are provided in the interface circuit 964. The interface circuit 964 may also include a power supply circuit, a clock generation circuit, and the like.

[0303] The interface circuit 964 may include, for example, an I2C (Inter Integrated Circuit), an SPI (Serial Peripheral Interface), or a GPIO (General Purpose Input / Output).

[0304] The input / output portion 966 has an input portion to which a signal, a potential, etc. is input from the outside, and an output portion to which a signal is output to the outside. The input / output portion 966 is provided with a plurality of connection terminals, which are connected to a substrate different from the substrate 990 by connection wiring. The input / output portion 966 may also be provided with a buffer circuit, a protection circuit, etc.

[0305] Methods for connecting the substrate 990 to another substrate include wire bonding using gold or copper wiring, flip-chip bonding using bumps, and direct bonding (hybrid bonding) using a direct bonding technique such as Cu-Cu bonding. Alternatively, a bonding method without using a substrate may be used in which two or more layers are bonded together with insulating films and then through-electrodes are formed to connect electrodes provided on each layer. In particular, using direct bonding or a method using through-electrodes is preferable because it allows the pitch of the connection electrodes to be extremely narrow, making it possible to arrange a large number of connection electrodes at a high density and increasing the amount of data transmitted between layers.

[0306] The memory array 920 and the arithmetic unit 960 can be provided overlapping each other. Perspective views of a semiconductor device 970A are shown in Figures 25A and 25B. The semiconductor device 970A has a layer 930 on which memory arrays are provided above the arithmetic unit 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic unit 960 and the layer 930 are shown separately in Figure 25B.

[0307] By stacking the layer 930 having the memory array and the arithmetic unit 960, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

[0308] As a method for stacking the layer 930 having a memory array and the arithmetic device 960, a method (also called monolithic stacking) in which the layer 930 having a memory array is stacked directly on the arithmetic device 960 may be used, or a method in which the arithmetic device 960 and the layer 930 are formed on different substrates, the two substrates are bonded together, and the two substrates are electrically connected using a through-via or a conductive film bonding technique (such as Cu-Cu bonding) may be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce the manufacturing cost.

[0309] Here, the arithmetic unit 960 does not have a cache 999, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory array 920L1 can be used as an L1 cache (also called a level 1 cache), the memory array 920L2 can be used as an L2 cache (also called a level 2 cache), and the memory array 920L3 can be used as an L3 cache (also called a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, the memory array 920L1 has the smallest capacity and the highest access frequency.

[0310] When the cache 999 provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0311] 25B, a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.

[0312] Although the number of memory arrays functioning as caches is three in this example, the number may be one or two, or four or more.

[0313] When the memory array 920L1 is used as a cache, the driver circuit 910L1 may function as part of the cache interface 989, or may be configured to be connected to the cache interface 989. Similarly, the driver circuits 910L2 and 910L3 may also function as part of the cache interface 989, or may be configured to be connected thereto.

[0314] Whether the memory array 920 is made to function as a cache or as a main memory is determined by a control circuit 912 included in each drive circuit 910. The control circuit 912 can cause some of the memory cells 950 included in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.

[0315] The semiconductor device 900 can cause some of the memory cells 950 to function as a cache and the other memory cells to function as a main memory. That is, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one embodiment of the present invention can function as, for example, a universal memory.

[0316] Furthermore, a layer 930 having one memory array 920 may be provided over the arithmetic device 960. Figure 26A shows a perspective view of a semiconductor device 970B.

[0317] In the semiconductor device 970B, one memory array 920 can be divided into multiple areas, each of which can be used for a different function. Fig. 26A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0318] Furthermore, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​the area L1. This configuration can improve the efficiency of calculation processing and increase the processing speed.

[0319] Also, multiple memory arrays may be stacked. Figure 26B shows a perspective view of a semiconductor device 970C.

[0320] The semiconductor device 970C includes a layer 930L1 having a memory array 920L1, a layer 930L2 having a memory array 920L2 on top of that, and a layer 930L3 having a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, which is farthest, can be used as a lower-level cache or main memory. This configuration allows the capacity of each memory array to be increased, thereby further improving processing power.

[0321] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0322] Embodiment 4 In this embodiment, an application example of a memory device according to one embodiment of the present invention will be described.

[0323] First, the hierarchy of a memory device applied to a semiconductor device will be described. Figure 27A shows the hierarchy of a conventional memory device.

[0324] In Figure 27A, the closer to the processor (CPU / GPU), the higher the access frequency, and the longer the base of the triangle, the larger the data capacity. The closer the storage device is to the processor, the faster the operating speed is required, while the farther away the storage device, the larger the storage capacity and recording density are required. Figure 27A shows a register as a memory integrated into a processor such as a CPU or GPU, and shows an example in which SRAM is used as cache memory, DRAM is used as main memory, and NAND memory and HDD (Hard Disk Drive) are used as storage.

[0325] The memory embedded in processors such as CPUs and GPUs is used for temporary storage of calculation results, and is therefore frequently accessed by the arithmetic processing unit. Therefore, faster operating speed is required rather than storage capacity. Registers also have the function of storing setting information for the arithmetic processing unit.

[0326] A cache has the function of duplicating and storing a portion of the data stored in main memory. By duplicating frequently used data and storing it in the cache, the access speed to the data can be increased. The storage capacity required for a cache is smaller than that of main memory, but it is required to operate at a faster speed than main memory. In addition, data rewritten in the cache is duplicated and supplied to the main memory.

[0327] The main memory has a function of holding programs, data, etc. read from storage.

[0328] Storage has the function of storing data that requires long-term storage, various programs used by processing units, etc. Therefore, storage requires a large memory capacity and a high recording density rather than an operating speed. For example, NAND memory such as 3D NAND, high-capacity non-volatile storage devices such as HDDs can be used.

[0329] In one embodiment of the present invention, among various memory devices shown in FIG. 27A , at least the DRAM used as the main memory is replaced with a memory device using an oxide semiconductor (OS memory). In particular, the DRAM requires a refresh operation and is a destructive readout memory device, and therefore consumes significantly more power than other memory devices. Therefore, power consumption can be significantly reduced by not using the DRAM. Note that in FIG. 27A , the range of various memory devices that is targeted for replacement with the OS memory is indicated by a dashed line. That is, not only the DRAM used as the main memory, but also part of the SRAM used as the cache and the NAND memory used for storage can be replaced with the OS memory.

[0330] 27B illustrates an example of a semiconductor device according to one embodiment of the present invention, and is a schematic diagram illustrating various memory devices used in the semiconductor device, layer by layer.

[0331] In FIG. 27B, a plurality of caches (L1 cache, L2 cache) and a Last Level cache (LLC) are shown as caches.

[0332] Multiple caches are provided in the order of L1 cache and L2 cache from the highest to lowest. The higher the cache, the more frequently it is accessed by the processor, so high-speed operation is required. Since the operating speed can also be increased by reducing the data capacity, it is preferable to reduce the data capacity of the higher-level cache. The higher-level cache is preferably physically closer to the processor and has shorter wiring length, so it is preferable to provide it in a form integrated with the layer where the processor is provided. The lower-level cache may be provided in a layer different from the processor.

[0333] The lowest level cache can be called an LLC. While LLCs are not required to operate faster than higher-level caches, they desirably have a large storage capacity. The OS memory of one embodiment of the present invention, which will be described below, has high operating speed and is capable of retaining data for a long period of time, and is therefore suitable for use as an LLC. Note that the OS memory of one embodiment of the present invention can also be applied to a final level cache (FLC).

[0334] SRAM can be used for various caches. OS memory can be used for LLC and main memory. This storage device has high operating speed and can retain data for a long period of time.

[0335] The configuration exemplified here does not use DRAM, which has been conventionally used as a main memory, etc. Instead, the DRAM is replaced with an OS memory according to one embodiment of the present invention. This configuration allows for a dramatic reduction in power consumption (for example, to one hundredth or one thousandth or less). Therefore, it is expected that the worldwide deployment of information processing devices, including computers, servers, and the like, to which this configuration is applied, will contribute significantly to the prevention of global warming.

[0336] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0337] In this embodiment, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)) that can use the semiconductor device described in the above embodiment will be described. The electronic devices, mainframes, space equipment, and data centers that use the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0338] [Electronic Device] Next, a perspective view of an electronic device 6500 is shown in FIG. 28A . The electronic device 6500 shown in FIG. 28A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.

[0339] 28B is an information terminal that can be used as a laptop personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, a control device 6616, and the like. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6615, the control device 6616, and the like. Note that the use of the semiconductor device of one embodiment of the present invention in the control device 6509 and the control device 6616 is preferable because power consumption can be reduced.

[0340] [Mainframe] Next, Fig. 28C shows a perspective view of a mainframe 5600. The mainframe 5600 shown in Fig. 28C has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe 5600 may also be called a supercomputer.

[0341] The computer 5620 can have the configuration shown in the perspective view in Fig. 28D, for example. In Fig. 28D, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0342] PC card 5621 shown in Figure 28E is an example of a processing board equipped with a CPU, GPU, storage device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that Figure 28E illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for those semiconductor devices, please refer to the descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 described below.

[0343] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0344] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. They can also be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB, SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of standards for the respective terminals include HDMI (registered trademark).

[0345] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0346] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU.

[0347] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. The semiconductor device 5628 is, for example, a memory device.

[0348] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0349] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as equipment for processing and storing information.

[0350] The semiconductor device of one embodiment of the present invention can include an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space.

[0351] Fig. 29 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 29, a planet 6804 is shown in outer space. Note that outer space refers to an altitude of 100 km or higher, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0352] 29 , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0353] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0354] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0355] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0356] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the semiconductor device of one embodiment of the present invention is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0357] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0358] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0359] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0360] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. To manage long-term data, the building must be large enough to install storage and servers for storing a huge amount of data, to ensure a stable power supply for maintaining the data, or to ensure cooling equipment required for maintaining the data.

[0361] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0362] Furthermore, the semiconductor device of one embodiment of the present invention consumes less power, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0363] Fig. 30 shows a storage system applicable to a data center. The storage system 6900 shown in Fig. 30 has a plurality of servers 6901sb as hosts 6901 (illustrated as Host computers). It also has a plurality of storage devices 6903md as storage 6903 (illustrated as Storage). The host 6901 and storage 6903 are shown connected via a storage area network 6904 (illustrated as SAN: Storage Area Network) and a storage control circuit 6902 (illustrated as Storage Controller).

[0364] The host 6901 corresponds to a computer that accesses data stored in the storage 6903. The hosts 6901 may be connected to each other via a network.

[0365] Although the storage 6903 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 6903, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0366] The above-mentioned cache memory is used in the storage control circuit 6902 and the storage 6903. Data exchanged between the host 6901 and the storage 6903 is stored in the cache memory in the storage control circuit 6902 and the storage 6903, and then output to the host 6901 or the storage 6903.

[0367] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0368] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0369] This embodiment mode can be combined as appropriate with the descriptions of other embodiment modes or examples.

[0370] 110L: transistor, 110: transistor, 111f: semiconductor film, 111: semiconductor layer, 112A: conductive layer, 112a: conductive layer, 112a_1: conductive layer, 112a_2: conductive layer, 112b: conductive layer, 112b_1: conductive layer, 112b_2: conductive layer, 112f: conductive film, 112: conductive layer, 113: wiring, 114a: conductive layer, 114b: conductive layer, 114f: conductive film, 114: conductive layer, 115a: insulating layer, 115b: insulating layer, 115c: insulating layer, 115d: insulating layer, 115f: insulating film, 115: insulating layer, 116a: conductive layer, 116b: conductive layer, 116: conductive layer, 117: wiring, 118A: opening, 118: opening, 119: opening, 120: transistor, 126: conductive layer, 127: wiring, 128: wiring, 129: conductive layer, 131L: capacitor, 131: capacitor, 132L: capacitor, 132: capacitor, 133: conductive layer, 134a: conductive layer, 134b: conductive layer, 134: conductive layer, 136: insulating layer, 137a: insulating layer, 137b: insulating layer, 137: insulating layer, 138: wiring, 140: connection wiring, 141: wiring, 142: wiring, 143: wiring, 150: memory cell, 215: insulating layer, 216: insulating layer, 223: insulating layer, 230: oxide semiconductor, 240a: conductive layer, 240b: conductive layer, 241: insulating layer, 243a: opening, 243b: opening, 275: insulating layer, 280: insulating layer, 282a: insulating layer, 282b: insulating layer, 282: insulating layer, 285: insulating layer, 900: semiconductor device, 910: driver circuit, 911: peripheral circuit, 912: control circuit, 915: peripheral circuit, 920: memory array, 923: row driver, 924: column driver, 925: input circuit, 926: output circuit, 927: sense amplifier, 928: voltage generation circuit, 930: layer, 931: PSW, 932: PSW, 941: row decoder, 942: column decoder, 950: memory cell, 951: memory cell, 952: memory cell, 953: memory cell, 954: memory cell, 955: memory cell, 956: memory cell, 957: memory cell, 958: memory cell, 960: arithmetic unit, 962: memory device, 964: interface circuit, 966: input / output unit, 970A: semiconductor device, 970B: semiconductor device, 970C: semiconductor device, 989: cache interface, 990: substrate, 991: ALU, 992: ALU controller, 993: instruction decoder,994: Interrupt controller, 995: Timing controller, 996: Register, 997: Register controller, 998: Bus interface, 999: Cache, 5600: Mainframe computer, 5610: Rack, 5620: Computer, 5621: PC card, 5622: Board, 5623: Connection terminal, 5624: Connection terminal, 5625: Connection terminal, 5626: Semiconductor device, 5627: Semiconductor device, 5628: Semiconductor device, 5629: Connection terminal, 5630: Motherboard, 5631: Slot, 6500: Electronic device, 6501: Housing, 6502: Display unit, 6503: Power button, 6504: Button, 6505: speaker, 6506: microphone, 6507: camera, 6508: light source, 6509: control device, 6600: electronic device, 6611: housing, 6612: keyboard, 6613: pointing device, 6614: external connection port, 6615: display unit, 6616: control device, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 6900: storage system, 6901sb: server, 6901: host, 6902: storage control circuit, 6903md: storage device, 6903: storage,

Claims

a first transistor, a first capacitance element, and a second capacitance element; The first transistor is A first conductive layer; and a first insulating layer provided on the first conductive layer; a semiconductor layer provided on the first insulating layer; a second insulating layer provided on the first insulating layer and the semiconductor layer; a second conductive layer provided on the second insulating layer; a third conductive layer provided in contact with the semiconductor layer; a fourth conductive layer provided in contact with the semiconductor layer; having the first conductive layer, the first insulating layer, the semiconductor layer, the second insulating layer, and the second conductive layer each have an overlapping region; The first capacitive element is A fifth conductive layer; and the first insulating layer provided on the fifth conductive layer; the third conductive layer provided on the first insulating layer; having The second capacitive element is The semiconductor layer provided on the first insulating layer; the third conductive layer provided on the first insulating layer and the semiconductor layer; a third insulating layer provided on the third conductive layer; a sixth conductive layer provided on the second insulating layer; having The fifth conductive layer, the first insulating layer, the semiconductor layer, the third conductive layer, the third insulating layer, and the sixth conductive layer each have an overlapping region. 　 In claim 1, the first conductive layer functions as a first gate electrode; the second conductive layer functions as a second gate electrode; the third conductive layer functions as one of a source electrode or a drain electrode and the other electrode of the first and second capacitance elements; the fourth conductive layer functions as the other of the source electrode and the drain electrode; the fifth conductive layer functions as one electrode of the first capacitor element; the sixth conductive layer functions as one electrode of the second capacitor element; the first insulating layer functions as a first gate insulating film and a dielectric layer of the first capacitive element; the second insulating layer functions as a second gate insulating film; The third insulating layer functions as a dielectric layer for the second capacitive element. 　 a first transistor, a first capacitance element, and a second capacitance element; a first insulating layer, a second insulating layer, a third insulating layer, a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer; the first conductive layer and the fourth conductive layer are provided on the same surface; the first insulating layer is provided on the first conductive layer and on the fourth conductive layer; The semiconductor layer is provided on the first insulating layer, on the first conductive layer, the second insulating layer is provided on the first insulating layer and the semiconductor layer, and the second conductive layer is provided on the second insulating layer; on the fourth conductive layer, a region in which the third conductive layer is provided on the first insulating layer and the semiconductor layer, the third insulating layer is provided on the third conductive layer, and the fifth conductive layer is provided on the third insulating layer; The first transistor is the first conductive layer serves as a first gate electrode, the second conductive layer serves as a second gate electrode, and the third conductive layer serves as one of a source electrode and a drain electrode; The first capacitive element is the fourth conductive layer is one electrode, the first insulating layer is a dielectric layer, and the third conductive layer is the other electrode; The second capacitive element is A semiconductor device in which the fifth conductive layer serves as one electrode, the third insulating layer serves as a dielectric layer, and the third conductive layer serves as the other electrode. 　 In any one of claims 1 to 3, The semiconductor layer is provided along a side of a substantially rectangular shape in a top view, A semiconductor device in which the height of the semiconductor layer is greater than the maximum width of the semiconductor layer in a cross-sectional view in a channel width direction. 　 In claim 4, In a region where the semiconductor layer overlaps with the second conductive layer, The semiconductor device has two or more semiconductor layers in a cross section in the channel width direction. 　 In any one of claims 1 to 3, A second transistor is provided. a gate of the second transistor is electrically connected to the third conductive layer. 　 In any one of claims 1 to 3, The semiconductor layer has a metal oxide, and the metal oxide has In, Zn, and M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf).

4. An electronic device comprising: the semiconductor device according to claim 1; and a display portion.

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