Solid-state imaging element, electronic device, and method for controlling solid-state imaging element

Abstract

The present invention improves data quality in solid-state imaging elements that detect address events.　A current / voltage conversion unit converts a photocurrent into a logarithmic voltage. A p-channel metal oxide semiconductor (pMOS) source follower circuit includes a pMOS source follower transistor that outputs, from the source as a negative-side output voltage, a voltage corresponding to a logarithmic voltage which was input to the gate. An n-channel MOS (nMOS) source follower circuit includes an nMOS source follower transistor that outputs, from the source as a positive-side output voltage, a voltage corresponding to a logarithmic voltage which was input to the gate.

Description

Solid-state imaging device, electronic device, and method for controlling solid-state imaging device

[0001] The present technology relates to a solid-state imaging device, and more particularly to a solid-state imaging device that detects that a change in luminance has exceeded a threshold, an electronic device, and a method for controlling the solid-state imaging device.

[0002] In recent years, in various fields such as transportation and robotics, there has been progress in the development and research of sensors that detect, for each pixel, an address event when a change in luminance exceeds a threshold. Such sensors are called dynamic vision sensors (DVS) or event-based vision sensors (EVS). Here, an address event includes at least one of an on-event indicating that the change in luminance exceeds an upper threshold and an off-event indicating that the change falls below a lower threshold. For example, a sensor has been proposed in which a p-channel metal oxide semiconductor (pMOS) source follower circuit is inserted between a current-to-voltage converter and a subtractor for each pixel (see, for example, Patent Document 1).

[0003] Special Publication No. 2015-501936

[0004] The above-mentioned conventional technology uses a pMOS source follower circuit, which has poor responsiveness to increases in the input voltage to the pMOS source follower circuit, potentially resulting in false detection of an off event. Furthermore, the difference between the pMOS source follower circuit's responsiveness to an increase in the input voltage and its responsiveness to a decrease in the input voltage can result in a large event time difference, which is the difference between the response time of an on event and the response time of an off event. These false detections and event time differences can result in a degradation of the data quality of the sensor's output data.

[0005] The present technology was developed in light of these circumstances, and aims to improve data quality in a solid-state imaging device that detects address events.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a solid-state imaging device including: a current-voltage converter that converts a photocurrent into a logarithmic voltage; a pMOS source follower circuit including a pMOS source follower transistor that outputs from its source a voltage corresponding to the logarithmic voltage input to its gate as a negative output voltage; and an nMOS source follower circuit including an nMOS source follower transistor that outputs from its source a voltage corresponding to the logarithmic voltage input to its gate as a positive output voltage, and a control method thereof, thereby providing an effect of improving data quality.

[0007] In addition, in the first aspect, the power supply voltage regulator may further include a negative-side subtractor that generates, by subtraction, a negative-side differential signal that indicates a change amount of the negative-side output voltage, and a positive-side subtractor that generates, by subtraction, a positive-side differential signal that indicates a change amount of the positive-side output voltage, thereby producing the effect of generating a differential signal.

[0008] In addition, in the first aspect, the circuit may further include a negative comparator that compares the negative differential signal with a negative threshold, and a positive comparator that compares the positive differential signal with a positive threshold, thereby providing the effect of detecting an address event from the comparison result between the differential signal and the threshold.

[0009] In this first aspect, the pMOS source follower circuit may include the pMOS source follower transistor and a pMOS current source transistor inserted between a power supply voltage and the pMOS source follower transistor, and the nMOS source follower circuit may include the nMOS source follower transistor and an nMOS current source transistor inserted between the nMOS source follower transistor and a reference voltage, thereby providing an effect that a current corresponding to the gate voltage of the current source transistor flows in the source follower circuit.

[0010] In addition, in this first aspect, a negative-side enable switch may be provided which selects either a power supply voltage or a first negative-side bias voltage lower than the power supply voltage and supplies the selected voltage to the gate of the pMOS current source transistor, thereby providing an effect that only an on-event is detected.

[0011] In addition, in the first aspect, a negative threshold supply unit may be further provided that supplies either a reference voltage or a second negative bias voltage higher than the reference voltage to the negative comparator as the negative threshold, thereby providing an effect that only on-events are detected.

[0012] In addition, in this first aspect, a positive-side enable switch may be provided which selects either a reference voltage or a first positive-side bias voltage higher than the reference voltage and supplies the selected voltage to the gate of the nMOS current source transistor, thereby providing an effect that only an OFF event is detected.

[0013] In addition, in the first aspect, the present invention may further include a positive-side threshold supply unit that supplies either a reference voltage or a second positive-side bias voltage higher than the reference voltage to the positive-side comparator as the positive-side threshold, thereby providing an effect that only off-events are detected.

[0014] A second aspect of the present technology is an electronic device including: a current-voltage converter that converts a photocurrent into a logarithmic voltage; a pMOS source follower circuit including a pMOS source follower transistor that outputs from a source a voltage corresponding to the logarithmic voltage input to a gate as a negative output voltage; an nMOS source follower circuit including an nMOS source follower transistor that outputs from a source a voltage corresponding to the logarithmic voltage input to the gate as a positive output voltage; and an arbiter that arbitrates requests from a plurality of pixels each including the pMOS source follower circuit and the nMOS source follower circuit. This brings about an effect of improving data quality in the electronic device.

[0015] 1 is a block diagram showing an example configuration of an electronic device according to a first embodiment of the present technology. FIG. 2 is a block diagram showing an example configuration of a solid-state imaging element according to the first embodiment of the present technology. FIG. 3 is a block diagram showing an example configuration of a pixel according to the first embodiment of the present technology. FIG. 4 is a circuit diagram showing an example configuration of a current-voltage conversion unit according to the first embodiment of the present technology. FIG. 5 is a circuit diagram showing an example configuration of a current-voltage conversion unit in the case of a stacked structure according to the first embodiment of the present technology. FIG. 6 is a circuit diagram showing an example configuration of a source follower circuit according to the first embodiment of the present technology. FIG. 7 is a circuit diagram showing an example configuration of a subtractor and a comparison unit according to the first embodiment of the present technology. FIG. 8 is a circuit diagram showing an example configuration of a pixel according to a comparative example. FIG. 9 is a graph showing an example of pixel characteristics according to the comparative example. FIG. 10 is a graph showing an example of pixel characteristics according to the first embodiment of the present technology. FIG. 11 is a diagram showing an example of image data according to the first embodiment of the present technology and a comparative example with a large event time difference. FIG. 12 is a diagram showing an example of image data according to the first embodiment of the present technology and a comparative example with a large number of false events. FIG. 13 is a graph showing an example of a simulation result of the first embodiment of the present technology and the comparative example. FIG. 14 is a diagram showing an example of data obtained by simulation of the first embodiment of the present technology and the comparative example. Fig. 1 is a circuit diagram showing an example configuration of a comparison unit in a first modified example of a second embodiment of the present technology. Fig. 2 is a circuit diagram showing an example configuration of a source follower circuit and a comparison unit in a second modified example of the second embodiment of the present technology. Fig. 3 is a circuit diagram showing an example configuration of a source follower circuit in a third embodiment of the present technology. Fig. 4 is a circuit diagram showing an example configuration of a comparison unit in a first modified example of the third embodiment of the present technology. Fig. 5 is a circuit diagram showing an example configuration of a source follower circuit and a comparison unit in a second modified example of the third embodiment of the present technology. Fig. 6 is a block diagram showing a schematic example configuration of a vehicle control system. Fig. 7 is an explanatory diagram showing an example of an installation position of an imaging unit.

[0016] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order: 1. First embodiment (an example using an nMOS source follower circuit and a pMOS source follower circuit) 2. Second embodiment (an example in which the nMOS source follower circuit of an nMOS source follower circuit and a pMOS source follower circuit is disabled) 3. Third embodiment (an example in which the pMOS source follower circuit of an nMOS source follower circuit and a pMOS source follower circuit is disabled) 4. Example of application to a mobile object

[0017] 1 is a block diagram showing an example of the configuration of an electronic device 100 according to a first embodiment of the present technology. The electronic device 100 includes an imaging lens 110, a solid-state imaging element 200, a recording unit 120, and a control unit 130. The electronic device 100 is assumed to be a camera mounted on an industrial robot, an in-vehicle camera, or the like.

[0018] The imaging lens 110 focuses incident light and guides it to the solid-state imaging element 200. The solid-state imaging element 200 detects, as an address event, that a change in luminance at each pixel address exceeds a predetermined threshold. The solid-state imaging element 200 processes the detection results for each pixel and outputs the processed data to the recording unit 120 via a signal line 209.

[0019] The recording section 120 records data from the solid-state imaging device 200. The control section 130 controls the solid-state imaging device 200 to detect an address event.

[0020] 2 is a block diagram showing an example of the configuration of a solid-state imaging device 200 according to the first embodiment of the present technology. The solid-state imaging device 200 includes a system control unit 210, an output unit 220, a pixel array unit 230, an X arbiter 240, and a Y arbiter 250. These circuits are provided on a single semiconductor chip, for example.

[0021] The system control unit 210 performs various controls such as adjusting a threshold value when detecting an address event.

[0022] The pixel array unit 230 has a plurality of pixels 300 arranged in a two-dimensional grid. When an address event occurs, each of the pixels 300 transmits a request to the X arbiter 240 or the Y arbiter 250. Then, upon receiving a response to the request, the pixel 300 supplies a detection signal indicating the detection result of the address event to the output unit 220. This detection signal includes, for example, at least one of one bit indicating the detection result of an on-event and one bit indicating the detection result of an off-event.

[0023] The Y arbiter 250 arbitrates requests from each row in the pixel array unit 230 and returns a response based on the arbitration result. The X arbiter 240 arbitrates requests from each column in the pixel array unit 230 and returns a response based on the arbitration result.

[0024] The output unit 220 performs various processes such as image recognition processing on image data in which detection signals for each pixel are arranged, and outputs the processing results to the recording unit 120 .

[0025] As described above, the method of asynchronously outputting an address event detection signal through arbitration by an arbiter is called the arbiter method. Note that the solid-state imaging device 200 can also use a scan method in which the solid-state imaging device 200 scans each row and outputs a detection signal each row instead of the arbiter method.

[0026] 3 is a block diagram showing an example of the configuration of a pixel 300 according to the first embodiment of the present technology. The pixel 300 includes a current-voltage conversion unit 310, a source follower circuit 320, a subtractor 350, a comparison unit 380, and a transfer unit 410.

[0027] The current-voltage converter 310 converts the photocurrent into a logarithmic voltage Vpr. The source follower circuit 320 outputs an output voltage Vfo corresponding to the logarithmic voltage Vpr to the subtractor 350. The source follower circuit 320 is also used for impedance conversion between the input side and the output side.

[0028] The subtractor 350 performs subtraction to obtain a differential signal V ｄｉｆｆThe comparison section 380 generates the differential signal V ｄｉｆｆ The comparison result COMP is supplied to the transfer unit 410 .

[0029] When an address event occurs, the transfer unit 410 performs a handshake with the X arbiter 240 and the Y arbiter 250 based on the comparison result. Then, when a response is received in the handshake, the transfer unit 410 initializes the subtractor 350 and supplies a detection signal to the output unit 220.

[0030] 4 is a circuit diagram showing an example of the configuration of the current-voltage converter 310 according to the first embodiment of the present technology. The current-voltage converter 310 includes log transistors 311 and 312, a photoelectric conversion element 313, a current source transistor 314, and TIAs (TransImpedance Amplifiers) 315 and 316. For example, a pMOS transistor is used as the current source transistor 314. Furthermore, for example, an nMOS (n-channel MOS) transistor is used as the transistor other than the current source transistor 314.

[0031] The log transistors 311 and 312 are inserted in series between the power supply voltage VDD and the photoelectric conversion element 313. The current source transistor 314, the TIA 315, and the TIA 316 are connected in series between the power supply voltage VDD and a reference voltage (such as a ground voltage).

[0032] The gate of log transistor 312 is connected to the connection node of TIAs 315 and 316, and the gate of TIA 316 is connected to the connection node of log transistor 312 and photoelectric conversion element 313. The gate of log transistor 311 is connected to the connection node of current source transistor 314 and TIA 315, and the gate of TIA 315 is connected to the connection node of log transistors 311 and 312. The connection node of current source transistor 314 and TIA 315 is connected to source follower circuit 320. A predetermined bias voltage V ｂｌｏｇ is applied.

[0033] With the above-described circuit configuration, the photocurrent generated in the photoelectric conversion element 313 is converted into a logarithmic voltage Vpr.

[0034] Although the loop circuit made up of the log transistor and the TIA is configured as two stages, it may be configured as one stage or three or more stages.

[0035] Furthermore, the circuits in the solid-state imaging device 200 can be distributed and arranged on a plurality of stacked semiconductor chips.

[0036] 5, in the case of a stacked structure, the current source transistor 314 and the circuits subsequent to the source follower circuit 320 are arranged on a circuit chip, and the other elements (such as the photoelectric conversion element 313) are arranged on a pixel chip. Alternatively, only the photoelectric conversion element 313 is arranged on the pixel chip, and the rest are arranged on the circuit chip.

[0037] 6 is a circuit diagram showing an example of the configuration of the source follower circuit 320 according to the first embodiment of the present technology. The source follower circuit 320 includes a pMOS source follower circuit 330 and an nMOS source follower circuit 340. The pMOS source follower circuit 330 includes a pMOS current source transistor 331 and a pMOS source follower transistor 332. The nMOS source follower circuit 340 includes an nMOS current source transistor 341 and an nMOS source follower transistor 342.

[0038] The subsequent subtractor 350 includes a negative subtractor 360 and a positive subtractor 370 , and the comparison section 380 includes a negative comparison section 390 and a positive comparison section 400 .

[0039] In the pMOS source follower circuit 330, a pMOS current source transistor 331 and a pMOS source follower transistor 332 are connected in series between a power supply voltage VDD and a reference voltage, with the pMOS current source transistor 331 acting as the power supply side. A predetermined negative bias voltage V ｂａｉｓ＿ｐis applied to the gate of the pMOS source follower transistor 332, and the logarithmic voltage Vpr is input to the gate of the pMOS source follower transistor 332. The source of the pMOS source follower transistor 332 is connected to the negative side subtractor 360.

[0040] In the nMOS source follower circuit 340, the nMOS current source transistor 341 and the nMOS source follower transistor 342 are connected in series between the power supply voltage VDD and the reference voltage, with the nMOS source follower transistor 342 on the power supply side. A predetermined positive bias voltage V higher than the reference voltage (ground voltage, etc.) is applied to the gate of the nMOS current source transistor 341. ｂａｉｓ＿ｎ is applied to the gate of the nMOS source follower transistor 342, and the logarithmic voltage Vpr is input to the gate of the nMOS source follower transistor 342. The source of the nMOS source follower transistor 342 is connected to the positive side subtractor 370.

[0041] With the above-described circuit configuration, the pMOS source follower transistor 332 outputs an output voltage Vfo_p corresponding to the logarithmic voltage Vpr input to its gate from its source to the negative-side subtractor 360. Furthermore, the nMOS source follower transistor 342 outputs an output voltage Vfo_n corresponding to the logarithmic voltage Vpr input to its gate from its source to the positive-side subtractor 370.

[0042] As shown in the figure, two circuits are arranged in the source follower circuit 320 and the subtractor 350. The effect of arranging two circuits will be described later.

[0043] 7 is a circuit diagram showing an example of the configuration of the subtractor and the comparator according to the first embodiment of the present technology. The negative subtractor 360 includes capacitors 361 and 363, an inverter 362, and a short-circuit switch 364. The positive subtractor 370 includes capacitors 371 and 373, an inverter 372, and a short-circuit switch 374. The negative comparator 390 includes a negative comparator 391 and a negative threshold supply unit 392. The positive comparator 400 includes a positive comparator 401 and a positive threshold supply unit 402.

[0044] In the negative-side subtractor 360, a capacitor 361 is inserted between the pMOS source follower circuit 330 and the input terminal of an inverter 362. The output terminal of the inverter 362 is connected to the non-inverting input terminal (+) of the negative-side comparator 391. A capacitor 363 is inserted between the input terminal and output terminal of the inverter 362. The short-circuit switch 364 shorts the input terminal and output terminal of the inverter 362 in accordance with a reset signal RST from the transfer unit 410.

[0045] In the positive-side subtractor 370, a capacitor 371 is inserted between the nMOS source follower circuit 340 and the input terminal of an inverter 372. The output terminal of the inverter 372 is connected to the non-inverting input terminal (+) of the positive-side comparator 401. A capacitor 373 is inserted between the input terminal and output terminal of the inverter 372. The short-circuit switch 374 shorts the input terminal and output terminal of the inverter 372 in accordance with a reset signal RST from the transfer unit 410.

[0046] With the above circuit configuration, the negative side subtractor 360 outputs a differential signal V ｄｉｆｆ＿ｎ and supplies it to the negative comparator 391. The positive subtractor 370 generates a differential signal V ｄｉｆｆ＿ｐ is generated and supplied to the positive side comparator 401.

[0047] In the negative comparison unit 390, a negative threshold supply unit 392 supplies a negative bias voltage V ＴＨｎｅｇ and supplies it to the inverting input terminal (-) of the negative comparator 391. The negative threshold is adjusted by the system control unit 210 and held in a register or the like. The negative comparator 391 generates a negative bias voltage V ＴＨｎｅｇ (negative threshold) and the negative differential signal V ｄｉｆｆ＿ｎ The differential signal V is compared with the differential signal V and the comparison result COMP− is supplied to the transfer unit 410. This comparison result COMP− indicates the detection result of an OFF event. ｄｉｆｆ＿ｎ An off-event is detected when the negative threshold is exceeded.

[0048] In the positive comparison unit 400, a positive threshold supply unit 402 supplies a positive bias voltage V ＴＨｐоｓand supplies it to the inverting input terminal (-) of the positive-side comparator 401. The positive-side threshold is adjusted by the system control unit 210 and held in a register or the like. The positive-side comparator 401 generates a positive-side bias voltage V ＴＨｐоｓ (positive threshold) and the positive differential signal V ｄｉｆｆ＿ｐ The differential signal V is compared with the differential signal V and the comparison result COMP+ is supplied to the transfer unit 410. This comparison result COMP+ indicates the result of detecting an ON event. ｄｉｆｆ＿ｐ An ON event is detected when the positive threshold is exceeded.

[0049] Here, a general configuration without the nMOS source follower circuit 340 and the positive side subtractor 370 is assumed as a comparative example.

[0050] 8 is a circuit diagram showing an example of the configuration of a pixel in a comparative example. In the comparative example, only one system of a pMOS source follower circuit 330 is arranged between a current-voltage conversion unit 310 and a subtractor 350. This pMOS source follower circuit 330 outputs an output voltage Vf0.

[0051] The subtractor 350 includes only one circuit system consisting of capacitors 361 and 363, an inverter 362, and a short-circuit switch 364. The differential signal V ｄｉｆｆ is input to both the negative comparator 391 and the positive comparator 401 .

[0052] 9 is a graph showing an example of pixel characteristics in a comparative example. A graph a in the figure shows an example of changes in the luminance of light incident on a pixel. The vertical axis of graph a in the figure represents luminance, and the horizontal axis represents time. For example, assume that the luminance increases at time T1 and decreases at time T2.

[0053] 1B shows an example of the fluctuation of the logarithmic voltage Vpr. The vertical axis of FIG. 1B represents the logarithmic voltage Vpr, and the horizontal axis represents time. As shown in FIG. 1B, the logarithmic voltage Vpr increases in response to an increase in luminance at time T1, and decreases in response to a decrease in luminance at time T2.

[0054] 10C shows an example of fluctuations in the output voltage Vfo of the pMOS source follower circuit 330. The vertical axis of FIG. 10C represents the output voltage Vfo, and the horizontal axis represents time. As shown in FIG. 10C, after time T1, the output voltage Vfo rises gradually in response to an increase in the input voltage (i.e., the logarithmic voltage Vpr). Then, after time T2, the output voltage Vfo drops sharply in response to a drop in the input voltage.

[0055] 10(d) shows an example of the pixel comparison result COMP. The upward arrow in d in the figure indicates the timing when an ON event is detected by the comparison result COMP+. The downward arrow indicates the timing when an OFF event is detected by the comparison result COMP-.

[0056] As shown in the example shown in d in the figure, at time T2, immediately after time T1, an ON event is detected in response to an increase in the output voltage Vfo_p. Two more ON events are then detected immediately after that. Since the brightness remains unchanged, these two ON events are false events that have been erroneously detected. The thin arrows indicate false events.

[0057] Then, at time T4 immediately after time T3, an OFF event is detected in response to a drop in output voltage Vfo_p. Immediately thereafter, another OFF event is detected. At this time, the luminance has not changed, so this OFF event is a false event that has been erroneously detected.

[0058] The period from time T1 to time T2 indicates the response time for an ON event, and the period from time T3 to time T4 indicates the response time for an OFF event. The difference between these response times is referred to as the "event time difference."

[0059] As shown in FIG. 1C, the pMOS source follower circuit 330 has low responsiveness to an increase in input voltage and high responsiveness to a decrease in input voltage. Therefore, as shown in FIG. 1D, there are many false detections of ON events. Furthermore, because the response time of ON events is longer than the response time of OFF events, an event time difference occurs. Due to these false detections and event time differences, the data quality of the output data from the pixel array unit 230 may be reduced in the comparative example.

[0060] In the comparative example, false detection of on-events can be reduced by replacing the pMOS source follower circuit 330 with the nMOS source follower circuit 340. However, in this case, false detection of off-events increases instead, and the event time difference cannot be suppressed.

[0061] 10 is a graph showing an example of the characteristics of the pixel 300 according to the first embodiment of the present technology. A graph a in the figure shows an example of a change in the luminance of light incident on the pixel. The vertical axis of graph a in the figure represents luminance, and the horizontal axis represents time. As in the comparative example, the luminance increases at time T1 and decreases at time T2.

[0062] 1B shows an example of fluctuations in the logarithmic voltage Vpr. The vertical axis of FIG. 1B represents the logarithmic voltage Vpr, and the horizontal axis represents time. As shown in FIG. 1B, the logarithmic voltage Vpr increases at time T1 and decreases at time T2.

[0063] 10C shows an example of fluctuations in the output voltage Vfo_p of the pMOS source follower circuit 330. The vertical axis of FIG. 10C represents the output voltage Vfo_p, and the horizontal axis represents time. As shown in FIG. 10C, after time T1, the output voltage Vfo_p gradually increases in response to an increase in the input voltage (logarithmic voltage Vpr). Then, after time T2, the output voltage Vfo_p suddenly decreases in response to a decrease in the input voltage.

[0064] 10(d) is a diagram showing an example of fluctuations in the output voltage Vfo_n of the nMOS source follower circuit 340. The vertical axis of FIG. 10(d) represents the output voltage Vfo_n, and the horizontal axis represents time. As shown in FIG. 10(d), after time T1, the output voltage Vfo_n rises sharply in response to an increase in the input voltage (logarithmic voltage Vpr). Then, after time T2, the output voltage Vfo_n gradually drops in response to a drop in the input voltage.

[0065] In the figure, e shows an example of the pixel comparison result COMP. The upward arrow in e in the figure indicates the timing when an ON event is detected based on the comparison result COMP+. The downward arrow indicates the timing when an OFF event is detected based on the comparison result COMP-. As shown in the example in e in the figure, the first ON event is detected at T2' immediately after time T1. The response time of the ON event from time T1 to time T2' is close to the response time of the OFF event from time T3 to time T4, and the time difference between these events is smaller than in the comparative example.

[0066] As shown in "c" in the figure, the pMOS source follower circuit 330 has a low responsiveness to an increase in the input voltage and a high responsiveness to a decrease in the input voltage. Conversely, as shown in "d" in the figure, the nMOS source follower circuit 340 has a high responsiveness to an increase in the input voltage and a low responsiveness to a decrease in the input voltage. Taking these characteristics into consideration, as described above, the output voltage of the pMOS source follower circuit 330 with a higher input voltage responsiveness is used to detect an off-event, and the output voltage of the nMOS source follower circuit 340 with a higher input voltage responsiveness is used to detect an on-event.

[0067] Therefore, as shown by e in the figure, the number of false detections of on-events is smaller than in the comparative example, and the event time difference is smaller than in the comparative example, thereby improving the data quality compared to the comparative example.

[0068] 11 is a diagram illustrating an example of image data in the first embodiment of the present technology and a comparative example with a large event time difference. In the same figure, a shows an example of an address event detection target. For example, it is assumed that an address event is detected for a black ball moving to the right.

[0069] In the figure, b shows an example of image data in which detection signals for each pixel of the solid-state imaging device 200 according to the first embodiment are arranged. The semicircle on the left side of b in the figure indicates a group of pixels in which an ON event is detected, and the semicircle on the right side indicates a group of pixels in which an OFF event is detected.

[0070] 10(c) shows an example of image data in which detection signals for each pixel are arranged in a comparative example. In this comparative example, the event time difference is larger than in the first embodiment. As shown in FIG. 10(c), when the event time difference is large, the shape of the pixel group in which ON events and OFF events are detected becomes distorted, resulting in a decrease in data quality.

[0071] In contrast, in the first embodiment, the event time difference is small, so the shape drawn by the pixel group where the ON event and OFF event are detected is semicircular, as shown in b in the same figure, and data quality is improved.

[0072] 12 is a diagram illustrating an example of image data in the first embodiment of the present technology and a comparative example with a large number of false events. In the same figure, a shows an example of an address event detection target. For example, it is assumed that an address event is detected for a black ball moving to the right.

[0073] In the figure, b shows an example of image data in which detection signals for each pixel of the solid-state imaging device 200 according to the first embodiment are arranged. The semicircle on the left side of b in the figure indicates a group of pixels in which an ON event is detected, and the semicircle on the right side indicates a group of pixels in which an OFF event is detected.

[0074] 10(c) shows an example of image data in which detection signals for each pixel are arranged in a comparative example. This comparative example has a larger number of false events than the first embodiment. As shown in FIG. 10(c), if the number of false events is large, the false events cause the semicircles drawn by the pixel groups in which ON events and OFF events are detected to create tails, resulting in a decrease in data quality.

[0075] In contrast, in the first embodiment, the event time difference is small, so as shown in b in the same figure, the semicircles drawn by the pixel groups where ON events and OFF events are detected do not leave any tails, and data quality is improved.

[0076] However, it should be noted that the first embodiment has a larger number of transistors than the comparative example, and therefore the circuit area and power consumption increase slightly.

[0077] Next, the results of a comparison of the response and the number of false events between the comparative example and the first embodiment through simulation are shown in FIGS. 13 and 14. FIG.

[0078] 13 is a graph showing an example of a simulation result of the first embodiment of the present technology and a comparative example. In the figure, a shows an example of a change in luminance of light incident on a pixel. The vertical axis of a in the figure represents luminance, and the horizontal axis represents time. It is assumed that the luminance decreases at time T10 and increases at time T20.

[0079] 10(b) is a diagram showing an example of fluctuations in the output voltage Vfo of the pMOS source follower circuit 330 in the comparative example. The vertical axis of FIG. 10(b) represents the output voltage Vfo, and the horizontal axis represents time. As shown in FIG. 10(b), an OFF event is detected at time T10, and an ON event is detected at time T20. However, false OFF events are erroneously detected at times T11 and T12, and false ON events are erroneously detected at times T21, T22, and T23. The number of false ON events is particularly high.

[0080] 10(c) shows an example of fluctuations in the output voltage Vfo_p of the pMOS source follower circuit 330 according to the first embodiment. The vertical axis of FIG. 10(c) represents the output voltage Vfo_p, and the horizontal axis represents time. As shown in FIG. 10(c), an OFF event is detected at time T10. Furthermore, false OFF events are erroneously detected at times T11 and T20, but the number of false events is smaller than in the comparative example.

[0081] 10(d) is a diagram showing an example of fluctuations in the output voltage Vfo_n of the nMOS source follower circuit 340 according to the first embodiment. The vertical axis of FIG. 10(d) represents the output voltage Vfo_n, and the horizontal axis represents time. As shown in FIG. 10(d), an ON event is detected at time T20. Although false ON events are erroneously detected at times T10 and T11, the number of false events is smaller than in the comparative example.

[0082] 14 is a diagram showing an example of data obtained by a simulation of the first embodiment of the present technology and the comparative example. The line a in the figure shows the event time difference between the first embodiment of the present technology and the comparative example, which was obtained by simulation. This event time difference was obtained taking into account the parasitic capacitance of the transistor. As shown in line a in the figure, the event time difference of the first embodiment is significantly smaller than that of the comparative example, resulting in a significant improvement.

[0083] The graph a in the figure shows the number of false events obtained by simulation for the first embodiment of the present technology and the comparative example. This number of false events represents the total number of false ON events and the number of false OFF events. In this simulation, extraction of the parasitic capacitance of the transistor is not performed. As shown in the graph b, the number of false events in the first embodiment is significantly reduced compared to the comparative example, which is a significant improvement.

[0084] By improving the event time difference and the number of false events, the data quality of the image data can be improved.

[0085] As described above, according to the first embodiment of the present technology, the logarithmic voltage of the current-voltage conversion unit 310 is input to the pMOS source follower circuit 330 and the nMOS source follower circuit 340, so that the event time difference and the number of false events can be reduced more than in the comparative example, thereby improving the data quality of the image data.

[0086] 2. Second Embodiment In the first embodiment described above, the solid-state imaging device 200 detects both ON events and OFF events for each pixel, but it is also possible to detect only one of them. The solid-state imaging device 200 in this second embodiment differs from the first embodiment in that it detects only ON events for each pixel.

[0087] 15 is a circuit diagram showing a configuration example of a source follower circuit 320 according to the second embodiment of the present technology. The source follower circuit 320 according to the second embodiment differs from the first embodiment in that a bias voltage supply unit 333, a power supply voltage supply unit 334, and a negative-side enable switch 335 are further provided in the pMOS source follower circuit 330.

[0088] The bias voltage supply unit 333 supplies a negative bias voltage V ｂａｉｓ＿ｐ to the negative-side enable switch 335. The power supply voltage supply unit 334 supplies the power supply voltage VDD to the negative-side enable switch 335.

[0089] The negative-side enable switch 335 is configured to supply the negative-side bias voltage V ｂａｉｓ＿ｐ and the power supply voltage VDD, and supplies it to the gate of the pMOS current source transistor 331. When the enable signal indicates enable, the negative bias voltage V ｂａｉｓ＿ｐ is selected, and the power supply voltage VDD is selected when the enable signal indicates disable.

[0090] As shown in the figure, the negative-side enable switch 335 allows the system control unit 210 to disable the pMOS source follower circuit 330 and stop detecting off events. This reduces power consumption. The system control unit 210 controls the pMOS source follower circuits 330 of all pixels to be enabled or disabled as needed.

[0091] As described above, according to the second embodiment of the present technology, the negative-side enable switch 335 is provided, so that the pMOS source follower circuit 330 can be disabled and only an on-event can be detected.

[0092] [First Modification] In the second embodiment described above, the pMOS source follower circuit 330 is disabled to detect only on-events, but it is also possible to detect only on-events by control other than the pMOS source follower circuit 330. The solid-state imaging device 200 in this first modification of the second embodiment differs from the second embodiment in that the threshold value of the negative-side comparator 391 is controlled.

[0093] 16 is a circuit diagram showing an example of a configuration of the comparison unit 380 in the first modified example of the second embodiment of the present technology. In this first modified example of the second embodiment, the system control unit 210 controls the negative side threshold supply unit 392 to calculate the negative side bias voltage V ＴＨｎｅｇ and the reference voltage GND are supplied to the negative comparator 391 as the negative threshold. By setting the negative threshold to the reference voltage GND, it is possible to stop the detection of an OFF event. The system control unit 210 sets the negative thresholds of all pixels to the negative bias voltage V ＴＨｎｅｇ Alternatively, the positive threshold voltage is controlled to the reference voltage GND. On the other hand, the positive threshold voltage is fixed to a constant value.

[0094] In the first modification of the second embodiment, the negative-side enable switch 335 is not provided.

[0095] As described above, according to the first modification of the second embodiment of the present technology, the negative threshold supply unit 392 supplies the reference voltage GND as the negative threshold, so that only an ON event can be detected.

[0096] [Second Modification] In the first modification of the second embodiment described above, the negative threshold value is controlled without providing the negative enable switch 335, but this configuration is not limiting. The solid-state imaging device 200 in this second modification of the second embodiment differs from the first modification of the second embodiment in that the negative enable switch 335 is further provided.

[0097] 17 is a circuit diagram showing a configuration example of a source follower circuit 320 and a comparison unit 380 in a second modified example of the second embodiment of the present technology. The pMOS source follower circuit 330 in the second modified example of the second embodiment differs from the first modified example of the second embodiment in that it further includes a bias voltage supply unit 333, a power supply voltage supply unit 334, and a negative-side enable switch 335.

[0098] As shown in the figure, by controlling both the pMOS source follower circuit 330 and the negative threshold, it is possible to reliably stop the detection of an off event.

[0099] As described above, according to the second modification of the second embodiment of the present technology, the system control unit 210 controls both the pMOS source follower circuit 330 and the negative threshold value, and therefore, only an on-event can be detected.

[0100] 3. Third Embodiment In the first embodiment described above, the solid-state imaging device 200 detects both ON events and OFF events for each pixel, but it is also possible to detect only one of them. The solid-state imaging device 200 in this third embodiment differs from the first embodiment in that it detects only OFF events for each pixel.

[0101] 18 is a circuit diagram showing a configuration example of a source follower circuit 320 according to the third embodiment of the present technology. The source follower circuit 320 according to the third embodiment differs from the first embodiment in that a bias voltage supply unit 343, a reference voltage supply unit 344, and a positive-side enable switch 345 are further provided in the nMOS source follower circuit 340.

[0102] The bias voltage supply unit 343 supplies a positive bias voltage V ｂａｉｓ＿ｎ to the positive side enable switch 345. The reference voltage supply unit 344 supplies the reference voltage GND to the positive side enable switch 345.

[0103] The positive side enable switch 345 is configured to supply the positive side bias voltage V ｂａｉｓ＿ｎ and the reference voltage GND, and supplies it to the gate of the nMOS current source transistor 341. When the enable signal indicates enable, the positive side bias voltage V ｂａｉｓ＿ｎ is selected, and when the enable signal indicates disable, the reference voltage GND is selected.

[0104] As shown in the figure, the provision of the positive-side enable switch 345 allows the system control unit 210 to disable the nMOS source follower circuit 340 and stop detecting on-events. This reduces power consumption. The system control unit 210 controls the nMOS source follower circuits 340 of all pixels to be enabled or disabled as necessary.

[0105] The third embodiment can be applied to the second embodiment.

[0106] As described above, according to the third embodiment of the present technology, since the positive-side enable switch 345 is provided, it is possible to disable the nMOS source follower circuit 340 and detect only the off event.

[0107] [First Modification] In the third embodiment described above, the nMOS source follower circuit 340 is disabled to detect only off events, but it is also possible to detect only off events by controlling something other than the nMOS source follower circuit 340. The solid-state imaging device 200 in this first modification of the third embodiment differs from the second embodiment in that the threshold value of the positive-side comparator 401 is controlled.

[0108] 19 is a circuit diagram showing an example of a configuration of the comparison unit 380 in the first modified example of the third embodiment of the present technology. In this first modified example of the third embodiment, the system control unit 210 controls the positive-side threshold supply unit 402 to supply a positive-side bias voltage V ＴＨｐоｓ and the reference voltage GND are supplied to the positive comparator 401 as the positive threshold. By setting the positive threshold to GND, it is possible to stop the detection of an ON event. The system control unit 210 sets the positive threshold of all pixels to the positive bias voltage V ＴＨｐоｓ Alternatively, the negative threshold is controlled to GND. On the other hand, the negative threshold is fixed to a constant value.

[0109] In the first modified example of the third embodiment, the positive side enable switch 345 is not provided.

[0110] Moreover, the first modified example of the third embodiment can be applied to the first modified example of the second embodiment.

[0111] As described above, according to the first modification of the third embodiment of the present technology, the positive-side threshold supplying unit 402 supplies GND as the positive-side threshold, so that only an OFF event can be detected.

[0112] [Second Modification] In the first modification of the third embodiment described above, the positive-side threshold value is controlled without providing the positive-side enable switch 345. However, this is not limiting. The solid-state imaging device 200 in the second modification of the third embodiment differs from the first modification of the third embodiment in that a positive-side enable switch 345 is further provided.

[0113] 20 is a circuit diagram showing a configuration example of a source follower circuit 320 and a comparison unit 380 in a second modified example of the third embodiment of the present technology. The nMOS source follower circuit 340 in the second modified example of the third embodiment differs from the first modified example of the second embodiment in that it further includes a bias voltage supply unit 343, a reference voltage supply unit 344, and a positive-side enable switch 345.

[0114] As shown in the figure, by controlling both the nMOS source follower circuit 340 and the positive threshold, it is possible to reliably stop the detection of an on-event.

[0115] The second modified example of the third embodiment can be applied to the second modified example of the second embodiment.

[0116] As described above, according to the second modification of the third embodiment of the present technology, the system control unit 210 controls both the nMOS source follower circuit 340 and the positive threshold value, and therefore, only an off event can be detected.

[0117] 4. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0118] FIG. 21 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0119] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 21 , the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0120] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0121] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0122] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0123] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0124] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0125] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0126] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0127] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0128] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 21, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0129] FIG. 22 is a diagram showing an example of the installation position of the imaging unit 12031.

[0130] In FIG. 22, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0131] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0132] 22 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0133] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0134] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0135] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0136] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0137] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the image capturing unit 12031 of the above-described configuration. Specifically, the electronic device 100 in FIG. 1 can be applied to the image capturing unit 12031. Applying the technology according to the present disclosure to the image capturing unit 12031 improves the data quality of image data, thereby improving the accuracy of object detection.

[0138] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist thereof.

[0139] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0140] The present technology may also be configured as follows: (1) A solid-state imaging device comprising: a current-voltage converter that converts a photocurrent into a logarithmic voltage; a pMOS source follower circuit having a pMOS source follower transistor that outputs from its source, as a negative output voltage, a voltage corresponding to the logarithmic voltage input to its gate; and an nMOS source follower circuit having an nMOS source follower transistor that outputs from its source, as a positive output voltage, a voltage corresponding to the logarithmic voltage input to its gate. (2) The solid-state imaging device according to (1), further comprising: a negative subtractor that generates, by subtraction, a negative differential signal indicating a change in the negative output voltage; and a positive subtractor that generates, by subtraction, a positive differential signal indicating a change in the positive output voltage. (3) The solid-state imaging device according to (2), further comprising: a negative comparator that compares the negative differential signal with a negative threshold; and a positive comparator that compares the positive differential signal with a positive threshold. (4) The solid-state imaging device according to (3), wherein the pMOS source follower circuit comprises the pMOS source follower transistor and a pMOS current source transistor inserted between a power supply voltage and the pMOS source follower transistor, and the nMOS source follower circuit comprises the nMOS source follower transistor and an nMOS current source transistor inserted between the nMOS source follower transistor and a reference voltage. (5) The solid-state imaging device according to (4), further comprising a negative-side enable switch that selects either a power supply voltage or a first negative-side bias voltage lower than the power supply voltage and supplies the selected voltage to a gate of the pMOS current source transistor. (6) The solid-state imaging device according to (4) or (5), further comprising a negative-side threshold supply unit that supplies either a reference voltage or a second negative-side bias voltage higher than the reference voltage to the negative comparator as the negative-side threshold. (7) The solid-state imaging device according to any one of (4) to (6), further comprising a positive-side enable switch that selects either a reference voltage or a first positive-side bias voltage higher than the reference voltage and supplies the selected voltage to the gate of the nMOS current source transistor.(8) The solid-state imaging element according to any one of (4) to (7), further comprising a positive-side threshold supply unit that supplies either a reference voltage or a second positive-side bias voltage higher than the reference voltage to the positive-side comparator as the positive-side threshold. (9) An electronic device comprising: a current-voltage converter that converts a photocurrent into a logarithmic voltage; a pMOS source follower circuit including a pMOS source follower transistor that outputs from its source a voltage corresponding to the logarithmic voltage input to its gate as a negative-side output voltage; an nMOS source follower circuit including an nMOS source follower transistor that outputs from its source a voltage corresponding to the logarithmic voltage input to its gate as a positive-side output voltage; and an arbiter that arbitrates requests from a plurality of pixels each including the pMOS source follower circuit and the nMOS source follower circuit. (10) A method for controlling a solid-state imaging device, comprising: a current-voltage conversion step of converting a photocurrent into a logarithmic voltage; a step of controlling a pMOS source follower circuit, including a pMOS source follower transistor, which outputs a voltage corresponding to the logarithmic voltage input to its gate from its source as a negative output voltage, to output the negative output voltage; and a step of controlling a pMOS source follower circuit, including a pMOS source follower transistor, which outputs a voltage corresponding to the logarithmic voltage input to its gate from its source as a negative output voltage, to output the negative output voltage.

[0141] 100 Electronic device 110 Imaging lens 120 Recording unit 130 Control unit 200 Solid-state imaging element 210 System control unit 220 Output unit 230 Pixel array unit 240 X arbiter 250 Y arbiter 300 Pixel 310 Current-voltage conversion unit 311, 312 Log transistor 313 Photoelectric conversion element 314 Current source transistor 315, 316 TIA 320 Source follower circuit 330 pMOS source follower circuit 331 pMOS current source transistor 332 pMOS source follower transistor 333, 343 Bias voltage supply unit 334 Power supply voltage supply unit 335 Negative side enable switch 340 nMOS source follower circuit 341 nMOS current source transistor 342 nMOS source follower transistor 344 Reference voltage supply unit 345 Positive side enable switch 350 Subtractor 360 Negative side subtractor 361, 363, 371, 373 Capacitor 362, 372 Inverter 364, 374 Short-circuit switch 370 Positive side subtractor 380 Comparator 390 Negative side comparator 391 Negative side comparator 392 Negative side threshold supply unit 400 Positive side comparator 401 Positive side comparator 402 Positive side threshold supply unit 410 Transfer unit 12031 Imaging unit

Claims

1. A solid-state imaging device comprising: a current-voltage converter that converts a photocurrent into a logarithmic voltage; a pMOS (p-channel Metal Oxide Semiconductor) source follower circuit having a pMOS (p-channel Metal Oxide Semiconductor) source follower transistor that outputs from its source a voltage corresponding to the logarithmic voltage input to its gate as a negative output voltage; and an nMOS (n-channel MOS) source follower circuit having an nMOS (n-channel MOS) source follower transistor that outputs from its source a voltage corresponding to the logarithmic voltage input to its gate as a positive output voltage.

2. A solid-state imaging device as described in claim 1, further comprising: a negative side subtractor that generates, by subtraction, a negative side differential signal indicating the amount of change in the negative side output voltage; and a positive side subtractor that generates, by subtraction, a positive side differential signal indicating the amount of change in the positive side output voltage.

3. A solid-state imaging device according to claim 2, further comprising: a negative comparator for comparing said negative differential signal with a negative threshold; and a positive comparator for comparing said positive differential signal with a positive threshold.

4. A solid-state imaging device according to claim 3, wherein said pMOS source follower circuit comprises: said pMOS source follower transistor; and a pMOS current source transistor inserted between a power supply voltage and said pMOS source follower transistor; and said nMOS source follower circuit comprises: said nMOS source follower transistor; and an nMOS current source transistor inserted between said nMOS source follower transistor and a reference voltage.

5. The solid-state imaging device according to claim 4, further comprising a negative-side enable switch which selects either a power supply voltage or a first negative-side bias voltage lower than said power supply voltage and supplies the selected voltage to the gate of said pMOS current source transistor.

6. The solid-state imaging device according to claim 4, further comprising a negative threshold supply section which supplies either a reference voltage or a second negative bias voltage higher than the reference voltage to the negative comparator as the negative threshold.

7. The solid-state imaging device according to claim 4, further comprising a positive-side enable switch which selects either a reference voltage or a first positive-side bias voltage higher than the reference voltage and supplies the selected voltage to the gate of the nMOS current source transistor.

8. The solid-state imaging device according to claim 4, further comprising a positive threshold supply section which supplies either a reference voltage or a second positive bias voltage higher than the reference voltage to the positive comparator as the positive threshold.

9. An electronic device comprising: a current-voltage converter that converts a photocurrent into a logarithmic voltage; a pMOS source follower circuit having a pMOS source follower transistor that outputs from its source a voltage corresponding to the logarithmic voltage input to its gate as a negative output voltage; an nMOS source follower circuit having an nMOS source follower transistor that outputs from its source a voltage corresponding to the logarithmic voltage input to its gate as a positive output voltage; and an arbiter that arbitrates requests from a plurality of pixels each including the pMOS source follower circuit and the nMOS source follower circuit.

10. A method for controlling a solid-state imaging device comprising: a current-voltage conversion step of converting a photocurrent into a logarithmic voltage; a step of controlling a pMOS source follower circuit having a pMOS source follower transistor that outputs a voltage corresponding to the logarithmic voltage input to its gate from its source as a negative output voltage to output the negative output voltage; and a step of controlling a pMOS source follower circuit having a pMOS source follower transistor that outputs a voltage corresponding to the logarithmic voltage input to its gate from its source as a negative output voltage to output the negative output voltage.

Images