Semiconductor device, method for manufacturing semiconductor device, and communication device

Abstract

Provided is a semiconductor device comprising: a ternary or quaternary compound semiconductor layer; a first insulating layer that is laminated on the compound semiconductor layer and has a first opening which exposes a first region on the upper surface of the compound semiconductor layer; a second insulating layer that is laminated on the first insulating layer and inside the first opening and has a second opening which has an opening narrower than the first opening and exposes a second region that is a portion of the first region of the compound semiconductor layer exposed by the first opening; and a gate electrode that is laminated on the upper surface of the second insulating layer and inside the second opening and is in direct contact with the second region on the upper surface of the compound semiconductor layer.

Description

Semiconductor device, semiconductor device manufacturing method, and communication device

[0001] The present disclosure relates to a semiconductor device, a method for manufacturing a semiconductor device, and a communication device.

[0002] HEMT (High Electron Mobility Transistor) devices, which are heterogeneous field-effect transistors (FETs) made of gallium nitride (GaN)-based wide-gap semiconductor materials, are capable of low resistance, high-speed, and high-voltage operation, and are therefore expected to be applied to RF (Radio Frequency) devices such as power devices and switches in 5G high-speed communication systems.

[0003] JP 2021-125575 A JP 2020-13883 A

[0004] However, in conventional HEMT devices, it is difficult to suppress degradation of on-state characteristics while reducing the off-state current determined by gate leakage. Even if it is possible to suppress degradation of on-state characteristics while reducing the off-state current, it is difficult to avoid extremely complicated manufacturing processes, and it is also difficult to avoid damage to the semiconductor surface.

[0005] Therefore, the present disclosure proposes a semiconductor device, a method for manufacturing the semiconductor device, and a communication device equipped with the reaction device, which can be manufactured using a simple and damage-free method, and which can reduce the current when off while suppressing deterioration of characteristics when on.

[0006] According to the present disclosure, there is provided a semiconductor device comprising: a ternary or quaternary compound semiconductor layer; a first insulating layer stacked on the compound semiconductor layer and having a first opening exposing a first region on an upper surface of the compound semiconductor layer; a second insulating layer stacked on the first insulating layer and in the first opening and having a second opening exposing a second region that is a part of the first region of the compound semiconductor layer exposed by the first opening and having an opening narrower than the first opening; and a gate electrode stacked on the upper surface of the second insulating layer and in the second opening and in direct contact with the second region on the upper surface of the compound semiconductor layer.

[0007] Furthermore, according to the present disclosure, there is provided a method for manufacturing a semiconductor device, including: depositing a first insulating layer on a ternary or quaternary compound semiconductor layer, the first insulating layer having a first opening exposing a first region on an upper surface of the compound semiconductor layer; performing a reduction treatment on the first region; depositing a second insulating layer on the first insulating layer and in the first opening, the second insulating layer having a second opening narrower than the first opening, exposing a second region that is a part of the first region of the compound semiconductor layer exposed by the first opening; and forming a gate electrode on the upper surface of the second insulating layer and in the second opening, the gate electrode being in direct contact with the second region on the upper surface of the compound semiconductor layer.

[0008] Furthermore, according to the present disclosure, there is provided a communication device equipped with a semiconductor device, the semiconductor device comprising: a ternary or quaternary compound semiconductor layer; a first insulating layer stacked on the compound semiconductor layer and having a first opening exposing a first region on an upper surface of the compound semiconductor layer; a second insulating layer stacked on the first insulating layer and in the first opening and having a second opening exposing a second region that is a part of the first region of the compound semiconductor layer exposed by the first opening, the second opening having an opening narrower than the first opening; and a gate electrode stacked on the upper surface of the second insulating layer and in the second opening and in direct contact with the second region on the upper surface of the compound semiconductor layer.

[0009] 13A is an explanatory diagram illustrating an overview of a HEMT device having an MIS gate structure. FIG. 13B is an explanatory diagram illustrating an overview of a HEMT device having a Schottky gate structure. FIG. 13C is an explanatory diagram (1) illustrating details of the study conducted by the present inventors. FIG. 13D is an explanatory diagram (2) illustrating details of the study conducted by the present inventors. FIG. 13E is an explanatory diagram (3) illustrating details of the study conducted by the present inventors. FIG. 13F is an explanatory diagram (5) illustrating details of the study conducted by the present inventors. FIG. 13G is an explanatory diagram (6) illustrating details of the study conducted by the present inventors. FIG. 13H is an explanatory diagram (7) illustrating details of the study conducted by the present inventors. FIG. 13I is an explanatory diagram (8) illustrating details of the study conducted by the present inventors. FIG. 13J is an explanatory diagram (9) illustrating details of the study conducted by the present inventors. FIG. 13J is an explanatory diagram (10) illustrating details of the study conducted by the present inventors. FIG. 13A is an enlarged cross-sectional view of a region B shown in FIG. 13A. FIG. 13B is a cross-sectional view (1) illustrating a method for manufacturing a HEMT device according to a first embodiment of the present disclosure. 15A . FIG. 15B is a cross-sectional view (part 2) illustrating a method for manufacturing a HEMT device according to a first embodiment of the present disclosure. FIG. 15C is a cross-sectional view (part 3) illustrating a method for manufacturing a HEMT device according to a first embodiment of the present disclosure. FIG. 15D is a cross-sectional view (part 4) illustrating a method for manufacturing a HEMT device according to a first embodiment of the present disclosure. FIG. 15E is a cross-sectional view (part 5) illustrating a method for manufacturing a HEMT device according to a first embodiment of the present disclosure. FIG. 15F is a cross-sectional view (part 6) illustrating a method for manufacturing a HEMT device according to a first embodiment of the present disclosure. FIG. 15G is a cross-sectional view (part 7) illustrating a method for manufacturing a HEMT device according to a first embodiment of the present disclosure. FIG. 15H is a cross-sectional view of a structure of a HEMT device according to a second embodiment of the present disclosure. FIG. 15H is an enlarged cross-sectional view of a region C shown in FIG. 15A . FIG. 15H is a cross-sectional view (part 1) illustrating a method for manufacturing a HEMT device according to a second embodiment of the present disclosure. FIG. 15I is a cross-sectional view (part 2) illustrating a method for manufacturing a HEMT device according to a second embodiment of the present disclosure. FIG. 17I is a cross-sectional view (part 3) illustrating a method for manufacturing a HEMT device according to a second embodiment of the present disclosure. FIG. 17I is a cross-sectional view of a structure of a HEMT device according to a third embodiment of the present disclosure. FIG. 17I is an enlarged cross-sectional view of a region D shown in FIG.10A to 10C are cross-sectional views (part 1) illustrating a method for manufacturing a HEMT device according to a third embodiment of the present disclosure; FIG. 10B are cross-sectional views (part 2) illustrating a method for manufacturing a HEMT device according to a third embodiment of the present disclosure; and FIG. 10C are explanatory views illustrating application examples of the HEMT device according to each embodiment of the present disclosure.

[0010] Preferred embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description will be omitted. Furthermore, in this specification and the drawings, multiple components having substantially the same or similar functional configurations may be distinguished by adding different letters after the same reference numeral. However, when there is no particular need to distinguish between multiple components having substantially the same or similar functional configurations, only the same reference numerals will be used.

[0011] The drawings referred to in the following description are for explaining and facilitating understanding of one embodiment of the present disclosure, and for the sake of clarity, the shapes, dimensions, ratios, etc. shown in the drawings may differ from the actual ones. Furthermore, the design of the devices shown in the drawings can be modified as appropriate, taking into consideration the following description and known technologies.

[0012] The description will be given in the following order: 1. Background 2. Consideration of embodiments of the present disclosure 3. First embodiment 3.1 Detailed configuration 3.2 Manufacturing method 4. Second embodiment 4.1 Detailed configuration 4.2 Manufacturing method 5. Third embodiment 5.1 Detailed configuration 5.2 Manufacturing method 6. Summary 7. Application example 8. Supplementary information

[0013] <<1. Background>> First, the background that led the inventors to create the embodiments of the present disclosure will be described with reference to Figures 1 and 2. Figure 1 is an explanatory diagram illustrating an overview of a HEMT device 10b with an MIS gate structure, and Figure 2 is an explanatory diagram illustrating an overview of a HEMT device 10a with a Schottky gate structure.

[0014] GaN, a wide-gap semiconductor material, has characteristics such as a high breakdown voltage, high-temperature operation, and a high saturated drift velocity. Furthermore, the two-dimensional electron gas (2DEG) layer generated at GaN-based heterojunctions has high mobility and a high sheet electron density. Due to these characteristics, GaN HEMTs, which are one type of GaN-based heterojunction FET, are capable of low resistance, high-speed, and high-voltage operation, and are therefore expected to be applied to RF devices such as power devices and switches in 5G high-speed communication systems. GaN HEMTs are particularly expected to be applied to power amplifiers (hereinafter referred to as PAs), where characteristics such as power density, power-added efficiency, and output power (Pout) are important in the millimeter-wave band, where spatial attenuation is large.

[0015] The 2DEG layer is a layer in which electrons are distributed two-dimensionally. Specifically, polarization within the crystal, which is one of the characteristics of Group III nitrides, results in a sheet-like electron distribution at the heterojunction interface. This sheet-like layer resulting from the electron distribution is called the 2DEG layer, and the 2DEG layer functions as the channel of the HEMT device.

[0016] First, referring to FIG. 1 , the configuration of a HEMT device 10b with a typical MIS (Metal-Insulator-Semiconductor) gate structure will be described. As shown in the upper part of FIG. 1 , the HEMT device 10b with the MIS structure has a GaN buffer layer 110 on a substrate 100 and a GaN channel layer 112 that forms a 2DEG layer 114 on the GaN buffer layer 110. In the MIS structure, a layer made of AlGaN, AlInN, or the like is heterojunctionally bonded to the GaN channel layer 112 as a barrier layer 120. Furthermore, in the MIS structure, a gate insulating film 140 and a gate electrode 152 sandwiched between the source 160a and the drain 160b are formed on the barrier layer 120 to control the current flowing between the source 160a and the drain 160b.

[0017] In the HEMT device 10b having such an MIS gate structure, when stress such as voltage or temperature is applied, electrons are captured in or released from traps present at the interface between the gate insulating film 140 and the semiconductor layer (specifically, the barrier layer 120). Therefore, as shown in the lower part of FIG. 1 , the measured value of the threshold voltage Vth of the HEMT device 10b is likely to fluctuate toward the positive or negative side compared to the theoretical value. If such fluctuations in the threshold voltage Vth occur during operation, device control becomes difficult, raising concerns about the reliability of the HEMT device 10b having the MIS gate structure over long-term use.

[0018] Due to these concerns, HEMT devices 10a with a Schottky gate structure are preferred for application to RF devices and the like in 5G high-speed communication systems, rather than MIS gate structures. Specifically, as shown in the upper part of FIG. 2 , the HEMT device 10a with a Schottky gate structure also includes a GaN buffer layer 110 on a substrate 100 and a GaN channel layer 112 that forms a 2DEG layer 114 on the GaN buffer layer 110. In addition, in the Schottky gate structure, a barrier layer 120 is heterojunctioned on the GaN channel layer 112. Furthermore, in the Schottky gate structure, a gate electrode 152 is formed on the barrier layer 120. As described above, the Schottky gate structure does not include a gate insulating film 140, resulting in fewer trap sources than the MIS gate structure, and therefore less fluctuation in threshold voltage Vth.

[0019] However, as shown in the lower part of FIG. 2, the HEMT device 10a having the Schottky gate structure does not have the gate insulating film 140, and therefore the current in the off state determined by gate leakage is higher than that of the MIS gate structure. Furthermore, the electric field strength is also high at the gate end of the gate electrode 152, and therefore the leakage current is likely to become noticeable.

[0020] The off-state current determined by gate leakage is the current that flows between the gate electrode 152 and the 2DEG layer 114, and an effective way to improve this is to alleviate the electric field concentration at the gate edge of the gate electrode 152. Therefore, it is conceivable to alleviate the electric field by utilizing the field plate effect (FP effect) by devising the shape of the gate electrode 152, but there is a limit to the improvement that can be achieved by such devising the shape.

[0021] Another approach to improving gate leakage is to make the depletion layer 170 (see FIG. 9 ), which occurs in the semiconductor layer (specifically, the barrier layer 120) from directly below the gate electrode 152 to the drain 160b side when a voltage is applied, more easily extend (spread). To achieve this, it is conceivable to lower the channel electron concentration Ns by changing the composition of the barrier layer 120 (e.g., by increasing the In concentration in the barrier layer 120 made of AlInN) or by thinning the barrier layer 120. However, such a measure would result in a uniform decrease in the electron concentration Ns throughout the entire region of the HEMT device 10a, which would increase resistance, particularly on the source 160a side, and thus potentially degrade the on-state characteristics, such as an increase in the on-state resistance (Ron) and a decrease in the on-state current (Id) of the HEMT device 10a. This would also result in a decrease in the power density of the HEMT device 10a.

[0022] In addition, it is possible to address the above problem by partially changing the composition of the barrier layer 120 or thinning the barrier layer 120, but such an approach would extremely complicate the manufacturing process and would also make the semiconductor surface more susceptible to damage.

[0023] Therefore, in view of these circumstances, the present inventors have repeatedly sought to obtain a structure that can be manufactured using a simple and damage-free method, and that can suppress degradation of on-state characteristics while reducing the off-state current determined by gate leakage. Through this search, the present inventors have come up with an embodiment of the present disclosure that can be manufactured using a simple and damage-free method, and that can suppress degradation of on-state characteristics while reducing the off-state current.

[0024] <<2. Considerations of Embodiments of the Present Disclosure>> First, details of the considerations conducted by the present inventors in creating the embodiments of the present disclosure will be described with reference to Figures 3 to 12. Figures 3 to 12 are explanatory diagrams for explaining the details of the considerations conducted by the present inventors.

[0025] The present inventors have investigated a method for making the depletion layer more easily extendable (spreadable) using TCAD Sim (Technology Computer-Aided Design Simulation) in order to obtain a structure that can be manufactured using a simple and damage-free method and that can reduce the off-state current determined by gate leakage while suppressing degradation of on-state characteristics. Specifically, the present inventors investigated a method for making the depletion layer 170 (see FIG. 9 ) more easily extendable by negatively charging the fixed charge state on the surface of the barrier layer 120 (semiconductor layer). During this investigation, the present inventors focused on the surface of the barrier layer 120 (semiconductor layer) located around the gate electrode 152. It was also found that the depletion layer 170 extends toward the drain 160b as the positive fixed charge decreases or the negative fixed charge increases on the surface of the barrier layer 120 located around the gate electrode 152, thereby easing the electric field at the gate end of the gate electrode 152 and reducing the off-state current determined by gate leakage.

[0026] Specifically, as shown in FIG. 3, the inventors have determined that the fixed charge density in a region A on the surface of the barrier layer 120, which is located around the gate electrode 152 and is sandwiched between the gate electrode 152 and the drain electrode 154 (and the source electrode), is 5.0e12 / cm ２ (positive fixed charge), none, -5.0e12 / cm ２ TCAD Sim was performed under the condition of (negative fixed charge). Then, Vg (gate voltage) - Id (drain current) characteristics were calculated under each condition (Vd (drain voltage) = 5 V applied). As a result, it was found that in region A, the off-state current determined by gate leakage decreases as the positive fixed charge decreases or as the negative fixed charge increases.

[0027] Furthermore, the inventors used TCAD Sim to divide the surface of the barrier layer 120 (semiconductor layer) located around the gate electrode 152 into a plurality of regions, and studied how the off-state current determined by gate leakage changes by changing the surface fixed charge density of each region.

[0028] 4, the surface of the barrier layer 120 of the HEMT device 10a with a Schottky gate structure was divided into three regions: between the gate electrode 152 and the source 160a (GS) (region a), directly below the gate electrode 152 (region b), and between the gate electrode 152 and the drain 160b (GD) (region b). Furthermore, the fixed charge density of each region was set to 5.0e12 / cm ２ (positive fixed charge), none, -5.0e12 / cm ２ (negative fixed charge). Then, the Vg-Id characteristics were calculated under each condition (Vd=5 V applied).

[0029] 5 shows the results of changing the fixed charge density in all of the regions a, b, and c. In this case, the off-state current determined by gate leakage decreased as the positive fixed charge decreased or the negative fixed charge increased in the regions a, b, and c. Furthermore, the on-state current (Id) in the on-state (linear scale on the vertical axis) also decreased as the positive fixed charge decreased or the negative fixed charge increased in the regions a, b, and c, raising concerns about a decrease in the power density of the HEMT device 10a.

[0030] 6 shows the results of changing the fixed charge density in regions a and c, i.e., in the regions outside the gate electrode 152. In this case, the results for both the off-current and the on-current were similar to those when the fixed charge density was changed in all of regions a, b, and c in FIG. 5. This result suggests that the influence of the change in fixed charge density on the off-current and on-current is predominantly due to the change in fixed charge density in the region outside the gate electrode 152.

[0031] Next, Figure 7 shows the results of changing the fixed charge density in region a, i.e., the region between G and S. In this case, the off-state current does not change (there is no sensitivity). Furthermore, in region a, the on-state current (Id) (vertical axis linear scale) decreases as the positive fixed charge decreases or the negative fixed charge increases. This is because when the fixed charge density in region a is changed, the extension of the depletion layer 170 toward the drain 160b does not change, and only the source resistance increases. This state is the most undesirable state in terms of device characteristics.

[0032] Next, Figure 8 shows the results of changing the fixed charge density in region c, i.e., the region between G and D. In region c, the fewer the positive fixed charges or the more the negative fixed charges, the smaller the off-state current determined by gate leakage. Furthermore, even when the fixed charge density in region c is changed, no significant change is observed in the on-state current (Id). This result suggests that changing the fixed charge density in region c in the negative direction results in a small extension of the depletion layer 170 toward the drain 160b and a small increase in source resistance. This state is the most favorable state in terms of device characteristics.

[0033] Through such original investigations by the inventors, it was found that if the fixed charge density can be changed in the negative direction in region c, i.e., in the region between G and D, it is possible to reduce the off-state current determined by gate leakage while suppressing deterioration of the on-state characteristics.

[0034] Therefore, the present inventors investigated in what range of region between G and D the fixed charge density must be changed in the negative direction in order to reduce the off-state current determined by gate leakage.

[0035] 9, in order to define the range of the region where the fixed charge density between G and D is changed in the negative direction, the distance from the end face on the drain 160b side of the part of the gate electrode 152 that is in direct contact with the surface of the barrier layer 120 to the end of the region where the fixed charge density is changed in the negative direction on the drain 160b side is defined as Ld. The fixed charge density in the surface region is then set to −5.0e12 / cm２ The Vg-Id characteristics were calculated (Vd=5 V applied) when the distance Ld was changed assuming a negative fixed charge (Vg=-5 V), and the results are shown in Figure 10. Figure 11 shows the current when off when Vg=-5 V is plotted against the distance Ld.

[0036] 11, when the distance Ld was 5 nm or more, the off-state current was rapidly reduced. Furthermore, as the distance Ld was increased, the effect of reducing the off-state current gradually saturated, and the effect became less apparent at around 100 nm. In other words, in order to reduce the off-state current determined by the gate leakage, it is considered effective to set the range of the region where the fixed charge density is changed in the negative direction to a position 5 nm or more but 100 nm or less away from the end face of the part of the gate electrode 152 on the drain 160b side that is in direct contact with the surface of the barrier layer 120.

[0037] Furthermore, the inventors have investigated to what extent the expansion of the region between G and S where the fixed charge density changes in the negative direction needs to be suppressed in order to suppress the deterioration of the characteristics when on.

[0038] 9, in order to define the range of the region where the fixed charge density between G and S is changed in the negative direction, the distance from the end face on the source 160a side of the part of the gate electrode 152 that is in direct contact with the surface of the barrier layer 120 to the end of the region where the fixed charge density is changed in the negative direction on the source 160a side is defined as Ls. Then, the fixed charge density in the surface region is set to −5.0e12 / cm ２ (negative fixed charge), the Vg-Id characteristics were calculated (Vd=5 V applied) when the distance Ls was changed, and the drain current value when Vg=0 V was plotted against the distance Ls, as shown in FIG. 12.

[0039] 12, as the distance Ls increases, the on-current (Id) decreases accordingly. That is, in order to suppress the decrease in the on-current, it is considered effective to prevent the region between G and S from extending as far as possible toward the source 160a, where the fixed charge density is changed in the negative direction.

[0040] Based on the results of the previous studies, the present inventors have created the following structure of the HEMT device 10. Specifically, in the HEMT device 10 (see FIG. 13A ) according to an embodiment of the present disclosure created by the present inventors, when forming the gate electrode 152, the gate opening on the surface of the barrier layer 120 is wider on the drain 160b side than on the source 160a side, and the surface of the barrier layer 120 exposed by the opening is subjected to a reduction treatment to change the fixed charge density on the surface in a negative direction. Furthermore, in an embodiment of the present disclosure, after the reduction treatment, the gate electrode 152 is formed closer to the source 160a side than the center of the gate opening. This allows the surface of a specific semiconductor layer (specifically, the barrier layer 120) located between the gate electrode 152 and the drain 160b to be selectively negatively charged. As a result, according to the embodiment of the present disclosure, it is possible to suppress a decrease in on-current and reduce the off-state current determined by gate leakage.

[0041] Hereinafter, the details of the structure of the HEMT device 10 according to each embodiment of the present disclosure, which has been created by the inventor and enables the surface of such a specific semiconductor layer (specifically, the barrier layer 120) to be selectively negatively charged, will be sequentially described.

[0042] <<3. First Embodiment>> <3.1 Detailed Configuration> First, a detailed structure of the HEMT device 10 according to the first embodiment of the present disclosure will be described with reference to Fig. 13A and Fig. 13B. Fig. 13A is a cross-sectional view of the structure of the HEMT device 10 according to this embodiment, and Fig. 13B is an enlarged cross-sectional view of region B shown in Fig. 13A. Note that in all figures referred to in the following description, the reduction treatment surface 122 is indicated by a thick line.

[0043] As shown in FIG. 13A , the HEMT device 10 according to this embodiment includes a buffer layer 110 on a substrate 100 and a channel layer 112 on the buffer layer 110, the channel layer 112 forming a 2DEG layer 114. In this embodiment, a barrier layer 120 is formed on the channel layer 112 at a heterojunction. Furthermore, in this embodiment, a source 160 a and a drain 160 b are formed on either side of the barrier layer 120. The thickness of the barrier layer 120 located below an insulating layer 132 (described later) is the same as the thickness of the barrier layer 120 located below a gate electrode 152 (described later). That is, the barrier layer 120 is a continuous layer with a uniform thickness. In the following description, the stack from the substrate 100 to the barrier layer 120 is also referred to as a compound semiconductor layer.

[0044] Furthermore, in this embodiment, an insulating layer (first insulating layer) 132 having an opening (first opening) 132a exposing a reduced surface (first region) 122 that is a portion of the upper surface of the barrier layer 120 is stacked on the barrier layer 120. An insulating layer (second insulating layer) 130 is stacked on the insulating layer 132 and within the opening 132a. The insulating layer 130 has an opening (second opening) 130a that exposes a portion (second region) of the reduced surface 122 of the upper surface of the barrier layer 120 exposed by the opening 132a and is narrower than the opening 132a.

[0045] Specifically, the center of opening 130a is located closer to source 160a than the center of opening 132a. Also, the inner surface of opening 132a on the source 160a side is located closer to source 160a than the inner surface of opening 130a on the source 160a side. Furthermore, the inner surface of opening 132a on the drain 160b side is located closer to drain 160b than the inner surface of opening 130a on the drain 160b side.

[0046] Furthermore, in this embodiment, a gate electrode 152 is formed on the insulating layer 130 located between the source 160a and the drain 160b and in the opening 130a, so as to be in direct contact with the upper surface (second region) of the barrier layer 120 exposed by the opening 130a.

[0047] In this embodiment, by adopting such a structure, a specific surface region of the semiconductor layer located between the gate electrode 152 and the drain 160b is subjected to a reduction treatment and selectively made negatively charged.

[0048] In this embodiment, as shown in FIG. 13B , the reduced surface 122 is a region d (first region) that is a part of the upper surface of the barrier layer 120 between the source 160a and the drain 160b. Specifically, the reduced surface 122 includes a region c (third region) that is located closer to the drain 160b than a region b (second region) where the gate electrode 152 and the barrier layer 120 are in direct contact with each other. The reduced surface 122 also includes a region b where the gate electrode 152 and the barrier layer 120 are in direct contact with each other. Furthermore, the reduced surface 122 includes a region a (fourth region) that is located closer to the source 160a than region b. In this embodiment, region c is wider than region a.

[0049] Furthermore, in this embodiment, it is preferable that the distance Ld between the end of region c on the drain 160b side and the end face of the gate electrode 152 on the drain 160b side that is in direct contact with region b is 5 nm or more and 100 nm or less. Also, in this embodiment, it is preferable that the distance Ls between the end of region a on the source 160a side and the end face of the gate electrode 152 on the source 160a side that is in direct contact with region b is as short as possible.

[0050] In this embodiment, the reduced surface 122 (region d) that is in direct contact with the gate electrode 152 and the insulating layer 130 has been subjected to a reduction treatment, and therefore has a smaller amount of positive fixed charge or a larger amount of negative fixed charge than the upper surface of the barrier layer 120 other than region d, specifically, the upper surface of the barrier layer 120 that is in direct contact with the insulating layer 132. In this embodiment, by doing so, the channel electron concentration Ns of the reduced surface 122 can be lowered compared to the upper surface of the barrier layer 120 other than region d, specifically, the upper surface of the barrier layer 120 that is in direct contact with the insulating layer 132. For example, the reduced surface 122 may have a smaller amount of oxygen or a larger amount of hydrogen than the upper surface of the barrier layer 120 other than region d. The amounts of oxygen and hydrogen can be analyzed using, for example, SIMS (Secondary Ion Mass Spectrometry) or the like.

[0051] In this embodiment, the gate electrode 152 is in direct contact with the barrier layer 120. Furthermore, in this embodiment, the gate electrode 152 has a structure in which it protrudes onto the insulating layer 130 in a part of the region c shown in FIG. 13B . In this embodiment, the thickness t1 of the insulating layer 130 is made thin (for example, 5 nm to 50 nm) to narrow the gap between the gate electrode 152 and the barrier layer 120 (reduced surface 122) in the region c. In this embodiment, by doing so, a field plate effect due to the shape of the gate electrode 152 appears, and the electric field at the gate end of the gate electrode 152 can be alleviated.

[0052] Further details of each layer will be explained in turn.

[0053] The substrate 100 is made of a semiconductor material and can be formed from a ternary or quaternary compound semiconductor material, such as a III-V group compound semiconductor material. More specifically, the substrate 100 can be made of, for example, a semi-insulating single-crystal GaN substrate. The substrate 100 may have a different lattice constant from that of the channel layer 112 by controlling the lattice constant with a buffer layer 110, which will be described later. Specifically, silicon carbide (SiC), sapphire, silicon (Si) substrates, etc. can be used as the substrate 100. The use of a Si substrate has the advantage that it is inexpensive and can be large-diameter.

[0054] The buffer layer 110 is composed of, for example, a compound semiconductor epitaxially grown on the substrate 100. When the lattice constants of the substrate 100 and the channel layer 112 are different, controlling the lattice constant with the buffer layer 110 can improve the crystalline state of the channel layer 112 and control the warpage of the entire compound semiconductor layer. For example, when the substrate 100 is made of single-crystal silicon and the channel layer 112 is made of GaN, the buffer layer 110 can be made of, for example, aluminum nitride (AlN), AlGaN, GaN, or the like. Furthermore, the buffer layer 110 does not necessarily have to be a single layer, but may be a stack of different layers. Furthermore, when the buffer layer 110 is made of a ternary or quaternary compound semiconductor, the buffer layer 110 may have a composition that gradually changes along its thickness.

[0055] The channel layer 112 is a region where carriers accumulate due to polarization with the barrier layer 120, which will be described later. Such a channel layer 112 is made of a compound semiconductor in which carriers are likely to accumulate due to polarization. An example of the channel layer 112 is a GaN epitaxial growth layer. The channel layer 112 may also be a u (undoped)-GaN layer to which no impurities have been added. This suppresses impurity scattering of carriers in the channel layer 112, thereby enabling carrier movement with high mobility. In this embodiment, the film thickness of the channel layer 112 is preferably, for example, 50 nm to 300 nm.

[0056] The barrier layer 120 is made of a compound semiconductor in which a two-dimensional electron gas is generated in the channel layer 112 (heterojunction interface) due to polarization with the channel layer 112, and carriers are accumulated. Such a barrier layer 120 is made of a group III nitride containing at least one of indium (In), gallium (Ga), and aluminum (Al), for example, and specifically, Al １－ｘ－ｙ Ga ｘ In ｙ The barrier layer 120 can be an epitaxially grown layer of u-Al (0≦x<1, 0≦y<1). １－ｘ－ｙ Ga ｘ In ｙ N. This suppresses impurity scattering of carriers in the channel layer 112, enabling high-mobility carrier movement. The barrier layer 120 does not necessarily have to be a single layer, and may be a stack of different layers. For example, Al １－ｘ－ｙ Ga ｘ In ｙ The barrier layer 120 may be an N layer, and may be a stack of layers with different compositions. Alternatively, the barrier layer 120 may have a composition that gradually changes along the thickness. In this embodiment, the thickness of the barrier layer 120 is preferably, for example, 3 nm to 20 nm. Furthermore, a cap layer (not shown) may be provided on the upper surface of the barrier layer 120 to protect it from oxidation processes and thermal processes. For example, the cap layer may be a 0.2 nm to 5 nm thick GaN or silicon nitride (Si ｘ N ｙ )

[0057] In this embodiment, a back barrier layer (not shown) may be provided between the channel layer 112 and the buffer layer 110. The back barrier layer is made of a semiconductor having a wider energy gap than the channel layer 112. An example of the back barrier layer is Al １－ｘ－ｙ Ga ｘ In ｙ N (0≦x<1, 0≦y<1), u-Al １－ｘ－ｙ Ga ｘ In ｙAn epitaxially grown layer of N can be used. The back barrier layer does not necessarily have to be a single layer, but may be a laminate of different layers. For example, １－ｘ－ｙ Ga ｘ In ｙ The N layer may be a stack of layers with different compositions, or the back barrier layer may have a composition that gradually changes along the thickness.

[0058] Furthermore, both the insulating layer 132 and the insulating layer 130 are stacked on the source 160a and the drain 160b, and although not shown, a source electrode 150 and a drain electrode 154 electrically connected to the source 160a and the drain 160b may be provided on the source 160a and the drain 160b. Furthermore, it is preferable that the insulating layer 132 is made of a material that is insulating with respect to the barrier layer 120, has a property of not deteriorating the device characteristics by forming a good interface with the barrier layer 120, and can be etched by wet etching. Specifically, the insulating layer 132 is made of an oxide, for example, aluminum oxide (Al ２ O ３ ), hafnium oxide (HfO ２ ) or silicon oxide (SiO ２ ), or a laminate thereof. Furthermore, it is preferable to use a material for the insulating layer 130 that is insulating with respect to the insulating layer 132 and that has the property of not deteriorating the device characteristics by forming a good interface with the barrier layer 120 since the insulating layer 130 is in direct contact with the barrier layer 120 in the opening 132a. In addition, it is preferable to use a material for the insulating layer 130 that can be etched by dry etching. Specifically, the insulating layer 132 is made of a nitride, for example, Si ３ N ４ It consists of:

[0059] The gate electrode 152 may have a laminated structure in which, for example, nickel (Ni) and gold (Au) are laminated. Furthermore, in order to reduce gate impedance, the gate electrode 152 generally has a T-gate shape. To suppress metal diffusion, a barrier metal (not shown) such as titanium (Ti) may be formed to cover the surface of the gate electrode 152.

[0060] As described above, in this embodiment, by adopting such a structure, it is possible to selectively reduce and negatively charge a specific surface region of the semiconductor layer located between the gate electrode 152 and the drain 160b. Specifically, in this embodiment, by selectively negatively charging the surface of the barrier layer 120 located between the gate electrode 152 and the drain 160b, the electron concentration of the channel on the drain 160b side is reduced, making it easier for the depletion layer 170 to extend toward the drain 160b side. As a result, this embodiment reduces the electric field at the gate end of the gate electrode 152, thereby reducing the off-state current determined by gate leakage. Furthermore, this embodiment makes it possible to suppress degradation of on-state characteristics by making the negatively charged region located on the source 160a side narrower than the negatively charged region located on the drain 160b side.

[0061] In this embodiment, the structure of the HEMT device 10 is not limited to the structure shown in FIGS. 13A and 13B, but can be modified into various other structures.

[0062] 14A to 14G, a method for manufacturing the HEMT device 10 according to this embodiment will be described. Figures 14A to 14G are cross-sectional views illustrating the method for manufacturing the HEMT device according to this embodiment, and more specifically, each figure is a cross-sectional view at each manufacturing stage corresponding to Figure 13A.

[0063] First, a GaN buffer layer 110 is formed on a GaN substrate 100, and a GaN channel layer 112 and a barrier layer 120 are sequentially stacked on the GaN buffer layer 110. Next, a high-concentration N-type (N+) region is formed in the region that will become the source 160a and the drain 160b. Specifically, the source 160a and the drain 160b are formed by, for example, forming ohmic electrodes (not shown) on both sides of the region where the gate electrode 152 will be formed, followed by annealing or the like. A high-concentration N-type region is formed on the substrate side by, for example, selective ion implantation. This can reduce contact resistance (both the source 160a and the drain 160b are electrically connected to the above-mentioned 2DEG layer 114). Alternatively, instead of ion implantation, the source 160a and the drain 160b may be formed by selective crystal regrowth on the substrate. In this case, the regrown layer may be, for example, n (N-type)-In. １－ｘ Ga ｘ In this embodiment, the high concentration N-type regions that become the source 160a and the drain 160b do not necessarily have to be a single layer, but may be a stack of different layers. For example, １－ｘ Ga ｘ The N (0≦x<1) layer may be a stack of layers with different compositions. Alternatively, the high concentration N-type region may have a composition that gradually changes along the film thickness. Furthermore, Si, germanium (Ge), etc. can be used as the N-type dopant (impurity), and the impurity concentration may be, for example, 1×10 １８ cm －３ It is preferable that the ohmic electrodes are those that cover the high-concentration N-type regions and are connected to each other with low resistance. For example, such ohmic electrodes can have a structure in which titanium (Ti), aluminum (Al), nickel (Ni), and gold (Au) are stacked in this order from the substrate side.

[0064] Furthermore, an isolation region (not shown) that separates the HEMT device 10 is formed on the substrate side. The isolation region can be formed by, for example, forming a high-resistance inactive region by ion implantation of boron (B). In this manner, the configuration shown in FIG. 14A can be obtained. Although the source 160 a and drain 160 b are described as being formed first, this is not limiting, and the source 160 a and drain 160 b may be formed after the formation of the gate electrode 152, which will be described later.

[0065] 14B, an insulating layer (first insulating layer) 132 is formed on the barrier layer 120 (semiconductor layer). The insulating layer 132 is preferably made of a material that is insulating with respect to the barrier layer 120, that forms a good interface with the barrier layer 120, and that does not deteriorate the device characteristics, and that can be etched by wet etching. Therefore, the insulating layer 132 is preferably made of, for example, aluminum oxide (Al ) having a thickness of about 1 nm to 50 nm, which is formed by the atomic layer deposition (ALD) method. ２ O ３ ) and hafnium oxide (HfO ２ Alternatively, the insulating layer 132 may be, for example, a SiO film formed by a CVD (Chemical Vapor Deposition) method. ２ may be.

[0066] Next, as shown in FIG. 14C , isotropic wet etching is performed on the insulating layer 132 until a portion of the surface of the barrier layer 120 is exposed, forming an opening (first opening) 132a. For wet etching, for example, buffered hydrofluoric acid (BHF) or diluted tetramethylammonium hydroxide (TMAH) can be used. By performing such wet etching, damage to the surface of the barrier layer 120 and the like can be reduced. At this time, the opening 132a is formed so as to open wider toward the drain 160b than the actual gate length. Specifically, the opening 132a is formed so as to open in a range of 5 nm to 200 nm starting from the gate end on the drain 160b side.

[0067] 14D , a reduction treatment is performed on the surface (first region) of the barrier layer 120 exposed from the opening 132a, forming a reduced surface 122. By performing such treatment, the amount of positive fixed charges can be reduced and the amount of negative fixed charges can be increased on the surface of the barrier layer 120 exposed from the opening 132a. For example, the reduction treatment may be a treatment using a gas or treatment liquid containing fluorine (F), chlorine (Cl), hydrogen (H), or the like. For example, the reduced surface 122 can be formed by performing a hydrogen plasma treatment for approximately 0.3 to 3 minutes.

[0068] As described above, in this embodiment, the surface region of a specific semiconductor layer (more specifically, the barrier layer 120) located between the gate electrode 152 and the drain 160b is selectively reduced rather than by ion implantation or the like, thereby preventing damage to the interior of the barrier layer 120, etc.

[0069] Next, as shown in FIG. 14E, an insulating layer (second insulating layer) 130 is formed on the insulating layer 132 and in the opening 132a. The insulating layer 130 is preferably made of a material that is insulating with respect to the insulating layer 132 and that does not deteriorate the device characteristics by forming a good interface with the barrier layer 120 because it is in direct contact with the barrier layer 120 in the opening 132a. In addition, the insulating layer 130 is preferably made of a material that can be etched by dry etching. Therefore, the insulating layer 130 can be made of, for example, p (P-type)-SiN with a film thickness of about 5 nm to 200 nm, formed by plasma CVD. Specifically, the insulating layer 130 can be made of, for example, silane gas (SiH ４ ) and ammonia gas (NH ３ ) to generate a silicon nitride film and hydrogen, which are then deposited on the substrate.

[0070] Next, as shown in FIG. 14F , dry etching is performed on the insulating layer 130 using a fluorocarbon (CF)-based gas to form an opening (second opening) 130a having a narrow opening 132a. The opening width of the opening 130a corresponds to the gate length and is preferably set to, for example, 0.1 μm to 1.0 μm. As a result, the insulating layer 130 protrudes into the opening 132a of the insulating layer 132 so as to be in direct contact with the barrier layer 120 (reduced surface 122), with the amount of protrusion being greater on the drain 160b side than on the source 160a side.

[0071] Next, as shown in FIG. 14G, a gate electrode 152 is formed on the insulating layer 130 and in the opening 130a. The gate electrode 152 can be formed, for example, by depositing Ni and Au from the substrate side using mask vapor deposition. As described above, the gate electrode 152 is generally formed in a T-gate shape to reduce gate impedance. Furthermore, to suppress diffusion of the upper metal Au, a barrier metal such as Ti (not shown) may be formed between the upper metal Au and the lower metal Ni.

[0072] In this manner, the HEMT device 10 according to this embodiment can be fabricated. As described above, in this embodiment, the HEMT device 10 according to this embodiment can be fabricated by a simple and damage-free method without significantly changing the conventional manufacturing process. That is, according to this embodiment, it is possible to obtain a HEMT device 10 that can be fabricated by a simple and damage-free method and that can reduce the current when it is off while suppressing deterioration of its characteristics when it is on.

[0073] <<4. Second Embodiment>> <4.1 Detailed Configuration> First, a detailed structure of a HEMT device 10 according to a second embodiment of the present disclosure will be described with reference to Figures 15A and 15B. Figure 15A is a cross-sectional view of the structure of the HEMT device 10 according to this embodiment, and Figure 15B is an enlarged cross-sectional view of region C shown in Figure 15A. This embodiment differs from the first embodiment in that the film thickness t1 of the insulating layer 130 is thicker than in the first embodiment.

[0074] 15A, in the same manner as in the first embodiment, the HEMT device 10 according to the present embodiment has a buffer layer 110, a channel layer 112, and a barrier layer 120 on a substrate 100. Furthermore, in the present embodiment as well, a source 160a and a drain 160b are formed so as to sandwich the barrier layer 120 therebetween.

[0075] Furthermore, in this embodiment, an insulating layer 132 having an opening 132a exposing a portion of the reduced surface 122 on the upper surface of the barrier layer 120 is stacked on the barrier layer 120. Also, in this embodiment, an insulating layer 130 is stacked on the insulating layer 132 and within the opening 132a. The insulating layer 130 has an opening 130a that exposes a portion of the reduced surface 122 on the upper surface of the barrier layer 120 exposed by the opening 132a and is narrower than the opening 132a. Also, in this embodiment, the center of the opening 130a is located closer to the source 160a than the center of the opening 132a. Also, in this embodiment, the inner surface of the opening 132a on the source 160a side is located closer to the source 160a than the inner surface of the opening 130a on the source 160a side. Also, in this embodiment, the inner surface of the opening 132a on the drain 160b side is located closer to the drain 160b than the inner surface of the opening 130a on the drain 160b side.

[0076] Furthermore, in this embodiment, a gate electrode 152 is formed on the insulating layer 130 located between the source 160a and the drain 160b and within the opening 130a, so as to be in direct contact with the upper surface of the barrier layer 120 exposed by the opening 130a.

[0077] In this embodiment, too, the reduced surface 122 is a region d, which is a portion of the upper surface of the barrier layer 120 sandwiched between the source 160a and the drain 160b, as shown in FIG. 15B . Specifically, the reduced surface 122 includes a region b where the gate electrode 152 and the barrier layer 120 are in direct contact, a region c located on the drain 160b side of region b, and a region a located on the source 160a side of region b. Also in this embodiment, region c is wider than region a. Specifically, also in this embodiment, the distance Ld between the end of region c on the drain 160b side and the end face of the gate electrode 152 on the drain 160b side that is in direct contact with region b is preferably 5 nm or more and 100 nm or less. Also in this embodiment, the distance Ls between the end of region a on the source 160a side and the end face of the gate electrode 152 on the source 160a side that is in direct contact with region b is preferably as short as possible.

[0078] In this embodiment, the reduced surface 122 that is in direct contact with the gate electrode 152 and the insulating layer 130 has also been subjected to a reduction treatment, and therefore has a smaller amount of positive fixed charges or a larger amount of negative fixed charges than the upper surface of the barrier layer 120 other than the region d, specifically, the upper surface of the barrier layer 120 that is in direct contact with the insulating layer 132. In this manner, in this embodiment, the channel electron concentration Ns of the reduced surface 122 can be reduced compared to the upper surface of the barrier layer 120 that is in direct contact with the insulating layer 132.

[0079] Furthermore, in this embodiment, the gate electrode 152 also has a structure in which it protrudes above the insulating layer 130 in a portion of region c shown in FIG. 15B . In this embodiment, the thickness t1 of the insulating layer 130 is thicker (e.g., 50 nm to 200 nm) than in the first embodiment described above. This increases the distance between the gate electrode 152 and the barrier layer 120 (reduced surface 122), thereby reducing the capacitance Cgd between the gate electrode 152 and the drain 160b. As a result, this embodiment improves the gain characteristics of the HEMT device 10. Thus, in each embodiment of the present disclosure, it is preferable to adjust the thickness t1 of the insulating layer 130 depending on the required characteristics.

[0080] As described above, in this embodiment, by adopting such a structure, it is possible to selectively reduce and negatively charge a specific surface region of the semiconductor layer located between the gate electrode 152 and the drain 160b. Specifically, in this embodiment, by selectively negatively charging the surface of the barrier layer 120 located between the gate electrode 152 and the drain 160b, the electron concentration of the channel on the drain 160b side is reduced, making it easier for the depletion layer 170 to extend toward the drain 160b side. As a result, this embodiment reduces the electric field at the gate end of the gate electrode 152, thereby reducing the off-state current determined by gate leakage. Furthermore, this embodiment makes it possible to suppress degradation of on-state characteristics by making the negatively charged region located on the source 160a side narrower than the negatively charged region located on the drain 160b side.

[0081] In this embodiment, the structure of the HEMT device 10 is not limited to the structure shown in FIGS. 15A and 15B, but can be modified into various other structures.

[0082] 16A to 16C, a method for manufacturing the HEMT device 10 according to this embodiment will be described. Figures 16A to 16C are cross-sectional views illustrating the method for manufacturing the HEMT device according to this embodiment, and more specifically, each figure is a cross-sectional view at each manufacturing stage corresponding to Figure 15A.

[0083] First, similarly to the method for manufacturing the HEMT device 10 according to the first embodiment described with reference to Figures 14A to 14E, layers are stacked up to the insulating layer 130, thereby obtaining the configuration shown in Figure 16A. Note that this embodiment differs from the first embodiment in that the insulating layer 130 has a thicker film thickness.

[0084] Next, as shown in FIG. 16B, similarly to the first embodiment, dry etching is performed on the insulating layer 130 to form an opening 130a having an opening narrower than the opening 132a.

[0085] Next, as shown in FIG. 16C, a gate electrode 152 is formed on the insulating layer 130 and in the opening 130a, similarly to the first embodiment.

[0086] In this manner, the HEMT device 10 according to this embodiment can be fabricated. As described above, in this embodiment, the HEMT device 10 according to this embodiment can be fabricated by a simple and damage-free method without significantly changing the conventional manufacturing process. That is, according to this embodiment, it is possible to obtain a HEMT device 10 that can be fabricated by a simple and damage-free method and that can reduce the current when it is off while suppressing deterioration of its characteristics when it is on.

[0087] 17A and 17B , a detailed structure of the HEMT device 10 according to a third embodiment of the present disclosure will be described. Fig. 17A is a cross-sectional view of the structure of the HEMT device 10 according to this embodiment, and Fig. 17B is an enlarged cross-sectional view of region D shown in Fig. 17A . This embodiment differs from the first and second embodiments in that the reduced treatment surface 122 is provided only on the drain 160 b side of the gate electrode 152, and is not provided on the source 160 a side of the gate electrode 152.

[0088] 17A, the HEMT device 10 according to this embodiment has a buffer layer 110, a channel layer 112, and a barrier layer 120 on a substrate 100. Furthermore, in this embodiment as well, a source 160a and a drain 160b are formed so as to sandwich the barrier layer 120 therebetween.

[0089] Furthermore, in this embodiment, an insulating layer 132 having an opening 132a exposing a reduced surface 122, which is a portion of the upper surface of the barrier layer 120, is stacked on the barrier layer 120. An insulating layer 130 is stacked on the insulating layer 132 and within the opening 132a. The insulating layer 130 has an opening 130a that exposes the upper surface of the barrier layer 120 exposed by the opening 132a and is narrower than the opening 132a. Unlike the previously described embodiments, in this embodiment, the opening 130a does not expose the reduced surface 122. Also, in this embodiment, the center of the opening 130a is located closer to the source 160a than the center of the opening 132a. Furthermore, in this embodiment, unlike the previously described embodiments, the inner surface of the opening 132a on the source 160a side is flush with the inner surface of the opening 130a on the source 160a side. However, in this embodiment, the inner surface of the opening 132a on the source 160a side is not limited to being flush with the inner surface of the opening 130a on the source 160a side, and the inner wall of the opening 132a on the source 160a side may be closer to the source 160a than the inner surface of the opening 130a on the source 160a side. Furthermore, in this embodiment as well, the inner surface of the opening 132a on the drain 160b side is located closer to the drain 160b than the inner surface of the opening 130a on the drain 160b side.

[0090] Furthermore, in this embodiment as well, a gate electrode 152 is formed on the insulating layer 130 located between the source 160 a and the drain 160 b and in the opening 130 a, so as to be in direct contact with the upper surface of the barrier layer 120 exposed by the opening 130 a. In this embodiment, unlike the embodiments described so far, the gate electrode 152 is not in direct contact with the reduced treatment surface 122.

[0091] 17B , the reduction treatment surface 122 in this embodiment differs from the embodiments described so far in that it includes only a region c located on the drain 160b side relative to a region b where the gate electrode 152 is in direct contact with the barrier layer 120. Furthermore, in this embodiment, the distance Ld between the end of region c on the drain 160b side and the end face of the gate electrode 152 on the drain 160b side that is in direct contact with region b is preferably 5 nm or more and 100 nm or less.

[0092] In this embodiment as well, the reduced surface 122 in direct contact with the insulating layer 130 has been subjected to a reduction treatment, and therefore has a smaller amount of positive fixed charge or a larger amount of negative fixed charge than the upper surface of the barrier layer 120 in direct contact with the gate electrode 152 and the insulating layer 132. In this embodiment as well, by doing so, the channel electron concentration Ns of the reduced surface 122 can be made lower than that of the upper surface of the barrier layer 120 in direct contact with the gate electrode 152 and the insulating layer 132.

[0093] Furthermore, in this embodiment, the gate electrode 152 also has a structure in which it protrudes above the insulating layer 130 in a portion of region c shown in FIG. 17B . In this embodiment, if the thickness t1 of the insulating layer 130 is increased, the gap between the gate electrode 152 and the barrier layer 120 (reduced surface 122) increases, thereby reducing the capacitance Cgd between the gate electrode 152 and the drain 160b. As a result, the gain characteristics of the HEMT device 10 can be improved. Furthermore, in this embodiment, if the thickness t1 of the insulating layer 130 is decreased, the gap between the gate electrode 152 and the barrier layer 120 (reduced surface 122) in region c decreases, resulting in a field plate effect due to the shape of the gate electrode 152, which can alleviate the electric field at the gate end of the gate electrode 152. Thus, in this embodiment, it is preferable to adjust the thickness t1 of the insulating layer 130 according to the required characteristics.

[0094] As described above, in this embodiment, by adopting such a structure, it is possible to selectively reduce and negatively charge a specific surface region of the semiconductor layer located between the gate electrode 152 and the drain 160b. Specifically, in this embodiment, by selectively negatively charging the surface of the barrier layer 120 located between the gate electrode 152 and the drain 160b, the electron concentration of the channel on the drain 160b side is reduced, making it easier for the depletion layer 170 to extend toward the drain 160b. As a result, this embodiment reduces the electric field at the gate end of the gate electrode 152, thereby reducing the off-state current determined by gate leakage. Furthermore, in this embodiment, since the reduced surface 122 is not provided on the source 160a side of the gate electrode 152, there is no increase in resistance on the source 160a side, and deterioration of the on-state characteristics can be further suppressed. Furthermore, in this embodiment, since the upper surface (region b) of the barrier layer 120 directly below the gate electrode 152 is not reduced, fluctuations in the characteristics of the HEMT device 10 can be suppressed.

[0095] In this embodiment, the structure of the HEMT device 10 is not limited to the structure shown in FIGS. 17A and 17B, but can be modified into various other structures.

[0096] 18A and 18B, a method for manufacturing the HEMT device 10 according to this embodiment will be described. Figures 18A and 18B are cross-sectional views illustrating the method for manufacturing the HEMT device according to this embodiment, and more specifically, each figure is a cross-sectional view at a manufacturing stage corresponding to Figure 18A.

[0097] First, similarly to the manufacturing method of the HEMT device 10 according to the first embodiment described with reference to FIGS. 14A to 14E and the manufacturing method of the HEMT device 10 according to the second embodiment described with reference to FIG. 16A, layers are stacked up to the insulating layer 130. Furthermore, in this embodiment, as shown in FIG. 16A, dry etching is performed on the insulating layer 130 to form an opening 130a on the source 160a side, the opening 130a being narrower than the opening 132a. At this time, it is preferable that the edge of the reduced surface 122 on the source 160a side and the inner surface of the opening 130a on the drain 160b side are flush with each other. However, this embodiment is not limited to this configuration, and a portion of the reduced surface 122 may be present within the opening of the opening 130a. Furthermore, in this embodiment, it is preferable that the inner surface of the opening 132a on the source 160a side be flush with the inner surface of the opening 130a on the source 160a side.

[0098] Next, as shown in FIG. 18B, a gate electrode 152 is formed on the insulating layer 130 and in the opening 130a, similarly to the first embodiment.

[0099] In this manner, the HEMT device 10 according to this embodiment can be fabricated. As described above, in this embodiment, the HEMT device 10 can be fabricated by a simple and damage-free method without significantly changing the conventional manufacturing process. That is, according to this embodiment, it is possible to obtain a HEMT device 10 that can be fabricated by a simple and damage-free method and that can reduce the current in the off state while suppressing deterioration of the on state characteristics.

[0100] <<6. Summary>> As described above, in each embodiment of the present disclosure, a specific surface region of a semiconductor layer located between the gate electrode 152 and the drain 160b can be selectively reduced to negatively charge it. Specifically, in this embodiment, by selectively negatively charging the surface of the barrier layer 120 located between the gate electrode 152 and the drain 160b, the electron concentration of the channel on the drain 160b side is reduced, making it easier for the depletion layer 170 to extend toward the drain 160b side. As a result, according to this embodiment, the electric field at the gate end of the gate electrode 152 is alleviated, thereby reducing the off-state current determined by gate leakage. Furthermore, according to each embodiment of the present disclosure, by narrowing the negatively charged region located on the source 160a side compared to the negatively charged region located on the drain 160b side, or by not providing a negatively charged region on the source 160a side, degradation of on-state characteristics can be suppressed.

[0101] Furthermore, in each embodiment of the present disclosure, a surface region of a specific semiconductor layer (specifically, the barrier layer 120) located between the gate electrode 152 and the drain 160b is selectively reduced rather than by ion implantation or the like, thereby preventing damage to the interior of the barrier layer 120, etc. Furthermore, according to each embodiment of the present disclosure, the HEMT device 10 can be manufactured by a simple method without significantly changing the conventional manufacturing process. That is, according to each embodiment of the present disclosure, it is possible to provide a HEMT device 10 that can be manufactured by a damage-free method and that can reduce the off-state current while suppressing deterioration of the on-state characteristics.

[0102] Although the HEMT device 10 according to each embodiment of the present disclosure is a GaN-based compound semiconductor, the present disclosure is not limited to this and may be, for example, a compound semiconductor such as GaAs, or a semiconductor using a Si substrate, etc.

[0103] Furthermore, the materials, film thicknesses, film formation methods, and film formation conditions of each layer in the above-described embodiments are not limited to those described above and can be changed as appropriate. That is, in this embodiment, the semiconductor device can be manufactured using techniques, devices, and conditions that are commonly used in the manufacture of semiconductor devices.

[0104] Examples of the above-mentioned techniques include physical vapor deposition (PVD), CVD, and ALD. Examples of PVD include vacuum deposition, electron beam (EB) deposition, various sputtering methods (magnetron sputtering, RF (radio frequency)-direct current (DC) combined bias sputtering, electron cyclotron resonance (ECR) sputtering, facing target sputtering, and high frequency sputtering), ion plating, laser ablation, molecular beam epitaxy (MBE), and laser transfer. Examples of CVD methods include plasma CVD, thermal CVD, metal organic (MO) CVD, and photo-CVD. Other methods include electroplating, electroless plating, spin coating, dipping, casting, microcontact printing, drop casting, various printing methods such as screen printing, inkjet printing, offset printing, gravure printing, and flexographic printing, stamping, spraying, and various coating methods such as air doctor coater, blade coater, rod coater, knife coater, squeeze coater, reverse roll coater, transfer roll coater, gravure coater, kiss coater, cast coater, spray coater, slit orifice coater, and calendar coater. Examples of patterning methods include chemical etching such as shadow masking, laser transfer, and photolithography, and physical etching using ultraviolet light or lasers. Additionally, examples of planarization techniques include CMP (Chemical Mechanical Polishing), laser planarization, and reflow.

[0105] <<7. Application Examples>> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be applied to a communication device. Therefore, as an example of application of the technology according to the present disclosure, a wireless communication device (communication device) 500 will be described with reference to FIG. 19 . FIG. 19 is an explanatory diagram illustrating an application example of the HEMT device 10 according to each embodiment of the present disclosure.

[0106] The wireless communication device 500 shown in FIG. 19 is a mobile phone system having multiple functions, such as voice and data communication and LAN (Local Area Network) connection. For example, the wireless communication device 500 includes an antenna (ANT) 510, an antenna switch circuit 520, a radio frequency integrated circuit (RFIC) 530, a baseband unit 540, a high power amplifier (HPA) 550, and an output unit 560 including an audio output unit (MIC), a data output unit (DT), and an interface (IF) unit. The interface (IF) unit can connect to a device that performs wireless communication, such as a wireless LAN or Bluetooth (registered trademark). The radio frequency integrated circuit RFIC 530 and the baseband unit 540 are connected via an internal bus.

[0107] During transmission, a transmission signal output from the baseband unit 540 is output to the antenna 510 via the radio frequency integrated circuit RFIC 530, the high power amplifier 550, and the antenna switch circuit 520. During reception, a received signal received by the antenna 510 is input to the baseband unit 540 via the antenna switch circuit 520 and the radio frequency integrated circuit RFIC 530. The baseband unit 540 processes the input signal and outputs it from the output unit 560 to an external device or the like.

[0108] For example, the technology of the present disclosure can be applied to an antenna switch circuit 520, a radio frequency integrated circuit (RFIC) 530, a high-power amplifier 550, and the like. The effects of the technology of the present disclosure are particularly pronounced in wireless communication devices whose communication frequencies are in the UHF (Ultra High Frequency) band or higher. That is, by using the HEMT device 10 according to each embodiment of the present disclosure, which has excellent high-frequency characteristics and high efficiency characteristics, as an antenna switch circuit 520, a radio frequency integrated circuit (RFIC) 530, a high-power amplifier 550, and the like, it is possible to achieve high-speed communication processing, high efficiency, and low power consumption in the wireless communication device 500. In particular, when the wireless communication device 500 is applied to a mobile communication terminal, the high-speed processing, high efficiency, and low power consumption enable longer battery life and improved portability.

[0109] The above describes an example configuration of the wireless communication device 500. Each of the above components may be configured using general-purpose components, or may be configured using hardware specialized for the function of each component. Such a configuration may be changed as appropriate depending on the technical level at the time of implementation.

[0110] <<8. Supplementary Information>> Although preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, the technical scope of the present disclosure is not limited to such examples. It is clear that a person skilled in the art of the present disclosure can conceive of various modified or altered examples within the scope of the technical idea described in the claims, and it is understood that these also naturally fall within the technical scope of the present disclosure.

[0111] Furthermore, the effects described herein are merely descriptive or exemplary and are not limiting. In other words, the technology according to the present disclosure may achieve other effects that will be apparent to those skilled in the art from the description of this specification, in addition to or in place of the above-described effects.

[0112] The present technology can also be configured as follows: (1) A semiconductor device comprising: a ternary or quaternary compound semiconductor layer; a first insulating layer stacked on the compound semiconductor layer and having a first opening exposing a first region on an upper surface of the compound semiconductor layer; a second insulating layer stacked on the first insulating layer and within the first opening and having a second opening exposing a second region that is a part of the first region of the compound semiconductor layer exposed by the first opening and having a narrower opening than the first opening; and a gate electrode stacked on the upper surface of the second insulating layer and within the second opening and in direct contact with the second region on the upper surface of the compound semiconductor layer. (2) The semiconductor device according to (1), wherein the first region includes a third region that is an upper surface of the compound semiconductor layer located on the drain side of the second region, and the third region is a reduced surface. (3) The semiconductor device according to (2) above, wherein the reduced surface has a larger amount of negative fixed charge than other regions on the top surface of the compound semiconductor layer. (4) The semiconductor device according to (2) above, wherein the reduced surface has a smaller amount of positive fixed charge than other regions on the top surface of the compound semiconductor layer. (5) The semiconductor device according to (2) above, wherein the reduced surface has a smaller amount of oxygen than other regions on the top surface of the compound semiconductor layer. (6) The semiconductor device according to any one of (2) to (5) above, wherein the reduced surface extends to a part of the top surface of the compound semiconductor layer located under the gate electrode. (7) The semiconductor device according to (6) above, wherein the reduced surface extends to the second region and a fourth region on the top surface of the compound semiconductor layer located on the source side of the second region, and the third region is larger than the fourth region. (8) The semiconductor device according to any one of (2) to (7) above, wherein a distance between an end face on the drain side of a part of the gate electrode that is in direct contact with the second region and an end face on the drain side of the third region is 5 nm or more. (9) The semiconductor device according to (8) above, wherein a distance between an end face on the drain side of a part of the gate electrode that is in direct contact with the second region and an end face on the drain side of the third region is 100 nm or less.(10) The semiconductor device according to any one of (2) to (6), wherein the center of the second opening is located closer to the source than the center of the first opening. (11) The semiconductor device according to (10), wherein the source-side inner surface of the first opening and the source-side inner surface of the second opening are flush with each other. (12) The semiconductor device according to (10), wherein the source-side inner surface of the first opening is located closer to the source than the source-side inner surface of the second opening. (13) The semiconductor device according to (12), wherein the drain-side inner surface of the first opening is located closer to the drain than the drain-side inner surface of the second opening. (14) The semiconductor device according to any one of (1) to (13), wherein the compound semiconductor layer includes a Group III nitride containing at least one of gallium, indium, and aluminum. (15) The semiconductor device according to any one of (1) to (14) above, wherein the first insulating layer is made of an oxide. (16) The semiconductor device according to (15) above, wherein the first insulating layer is made of aluminum oxide, hafnium oxide, silicon oxide, or a laminate of these. (17) The semiconductor device according to any one of (1) to (16) above, wherein the second insulating layer is made of a nitride. (18) The semiconductor device according to (17) above, wherein the second insulating layer is made of silicon nitride. (19) A method for manufacturing a semiconductor device, comprising: depositing a first insulating layer on a ternary or quaternary compound semiconductor layer, the first insulating layer having a first opening exposing a first region on an upper surface of the compound semiconductor layer; performing a reduction treatment on the first region; depositing a second insulating layer on the first insulating layer and in the first opening, the second insulating layer having a second opening narrower than the first opening, exposing a second region that is a part of the first region of the compound semiconductor layer exposed by the first opening; and forming a gate electrode on the upper surface of the second insulating layer and in the second opening, the gate electrode being in direct contact with the second region on the upper surface of the compound semiconductor layer.(20) A communication device equipped with a semiconductor device, the semiconductor device comprising: a ternary or quaternary compound semiconductor layer; a first insulating layer stacked on the compound semiconductor layer and having a first opening exposing a first region on an upper surface of the compound semiconductor layer; a second insulating layer stacked on the first insulating layer and in the first opening and having a second opening narrower than the first opening exposing a second region that is a part of the first region of the compound semiconductor layer exposed by the first opening; and a gate electrode stacked on the upper surface of the second insulating layer and in the second opening and in direct contact with the second region on the upper surface of the compound semiconductor layer.

[0113] 10, 10a, 10b HEMT device 100 substrate 110 buffer layer 112 channel layer 114 2DEG layer 120 barrier layer 122 reduced surface 130, 132 insulating layer 130a, 132a opening 140 gate insulating film 150 source electrode 152 gate electrode 154 drain electrode 160a source 160b drain 170 depletion layer 500 wireless communication device 510 antenna 520 antenna switch circuit 530 high frequency integrated circuit RFIC 540 baseband section 550 high power amplifier 560 output section

Claims

1. A semiconductor device comprising: a ternary or quaternary compound semiconductor layer; a first insulating layer stacked on the compound semiconductor layer and having a first opening exposing a first region on an upper surface of the compound semiconductor layer; a second insulating layer stacked on the first insulating layer and within the first opening, the second insulating layer having a second opening exposing a second region that is a part of the first region of the compound semiconductor layer exposed by the first opening and having an opening narrower than the first opening; and a gate electrode stacked on the upper surface of the second insulating layer and within the second opening, the gate electrode being in direct contact with the second region on the upper surface of the compound semiconductor layer.

2. The semiconductor device according to claim 1, wherein the first region includes a third region which is an upper surface of the compound semiconductor layer located on the drain side of the second region, and the third region is a reduced treatment surface.

3. The semiconductor device according to claim 2, wherein the reduction treated surface has a larger amount of negative fixed charges than other regions of the upper surface of the compound semiconductor layer.

4. The semiconductor device according to claim 2, wherein the reduction treated surface has a smaller amount of positive fixed charges than other regions of the upper surface of the compound semiconductor layer.

5. The semiconductor device according to claim 2, wherein the reduction treated surface has a smaller amount of oxygen than other regions of the upper surface of the compound semiconductor layer.

6. The semiconductor device according to claim 2, wherein the reduced surface extends to a portion of the upper surface of the compound semiconductor layer located under the gate electrode.

7. The semiconductor device according to claim 6, wherein the reduction treatment surface extends to the second region and a fourth region on the upper surface of the compound semiconductor layer located on the source side of the second region, and the third region is larger than the fourth region.

8. The semiconductor device according to claim 2, wherein the distance between an end surface on the drain side of a portion of said gate electrode that is in direct contact with said second region and an end portion on the drain side of said third region is 5 nm or more.

9. The semiconductor device according to claim 8, wherein the distance between an end surface on the drain side of a portion of said gate electrode that is in direct contact with said second region and an end portion on the drain side of said third region is 100 nm or less.

10. The semiconductor device according to claim 2, wherein the center of said second opening is located closer to the source side than the center of said first opening.

11. The semiconductor device according to claim 10, wherein an inner surface of said first opening on the source side and an inner surface of said second opening on the source side are flush with each other.

12. The semiconductor device according to claim 10, wherein an inner surface on the source side of said first opening is located on the source side with respect to an inner surface on the source side of said second opening.

13. The semiconductor device according to claim 12, wherein an inner surface on the drain side of said first opening is located on the drain side with respect to an inner surface on the drain side of said second opening.

14. The semiconductor device according to claim 1, wherein the compound semiconductor layer comprises a Group III nitride containing at least one of gallium, indium, and aluminum.

15. The semiconductor device according to claim 1, wherein the first insulating layer is made of an oxide.

16. The semiconductor device according to claim 15, wherein the first insulating layer is made of aluminum oxide, hafnium oxide, silicon oxide, or a laminate of these.

17. The semiconductor device according to claim 1, wherein the second insulating layer is made of a nitride.

18. The semiconductor device according to claim 17, wherein the second insulating layer is made of silicon nitride.

19. A method for manufacturing a semiconductor device, comprising: depositing a first insulating layer on a ternary or quaternary compound semiconductor layer, the first insulating layer having a first opening exposing a first region on an upper surface of the compound semiconductor layer; performing a reduction treatment on the first region; depositing a second insulating layer on the first insulating layer and within the first opening, the second insulating layer having a second opening narrower than the first opening and exposing a second region that is a part of the first region of the compound semiconductor layer exposed by the first opening; and forming a gate electrode on the upper surface of the second insulating layer and within the second opening, the gate electrode being in direct contact with the second region on the upper surface of the compound semiconductor layer.

20. A communication device equipped with a semiconductor device, the semiconductor device comprising: a ternary or quaternary compound semiconductor layer; a first insulating layer stacked on the compound semiconductor layer and having a first opening exposing a first region on an upper surface of the compound semiconductor layer; a second insulating layer stacked on the first insulating layer and within the first opening, exposing a second region that is a part of the first region of the compound semiconductor layer exposed by the first opening and having a second opening narrower than the first opening; and a gate electrode stacked on the upper surface of the second insulating layer and within the second opening, and in direct contact with the second region on the upper surface of the compound semiconductor layer.

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