Multilayered gallium nitride structure and method for producing multilayered gallium nitride structure

Abstract

Provided are: a multilayered gallium nitride structure which can have trenches formed therein in an increased density without forming cavities in structures filling the inside of the trenches; and a method for producing the multilayered gallium nitride structure. The multilayered gallium nitride structure is characterized by comprising: a base layer including gallium nitride; film deposition layers including gallium nitride deposited on one surface of the base layer; and trenches formed from one surface of the film deposition layers along the deposition direction to a depth not larger than the thickness of the film deposition layers. The multilayered gallium nitride structure is further characterized in that the trenches each have inner surfaces and a bottom surface and that the inner surfaces of the trench are inclined at an inclination angle with the deposition direction in the range of 5-10° so as to widen upward along the deposition direction, and are inclined surfaces in which the trench has a change in the inclination angle within ±1°.

Description

Gallium nitride laminated structure and method for manufacturing the same

[0001] The present invention relates to a gallium nitride stacked structure and a method for manufacturing the same. This application claims priority to Japanese Patent Application No. 2023-149425, filed on September 14, 2023, the contents of which are incorporated herein by reference.

[0002] For example, silicon has traditionally been widely used as a material for power semiconductor elements that have high breakdown voltages and control large currents. One example of a power semiconductor element using silicon is the metal-oxide-semiconductor field-effect transistor (MOSFET). While such MOSFETs can be used as high-breakdown-voltage and high-speed switching elements up to several MHz, they suffer from high losses.

[0003] In recent years, there has been a demand for MOSFETs that combine low loss and high-speed switching. To achieve such MOSFETs, gallium nitride (GaN) has been used as a MOSFET material.

[0004] Gallium nitride is a chemically very stable material with a wurtzite tetrahedron structure, and has the excellent characteristics of being extremely stable as a semiconductor even in high-temperature environments, with a wide band gap. Gallium nitride also has the excellent characteristic of being able to increase the dielectric breakdown voltage of semiconductor elements, as the maximum electric field strength that causes avalanche breakdown in a semiconductor substrate is greater than that of silicon.

[0005] An example of such a semiconductor element using gallium nitride is a trench-structured MOSFET (see, for example, Patent Document 1). Such a trench-structured MOSFET has a structure in which a gate electrode is formed inside a trench extending from a P-type semiconductor layer of gallium nitride to an N-type semiconductor layer via an insulating film.

[0006] Conventionally, such trench structures using gallium nitride are formed by forming a trench using dry etching or other methods, depositing an insulating film inside the trench, and then filling the space inside the insulating film with the material that makes up the gate electrode.

[0007] Japanese Patent Application Laid-Open No. 2008-053448

[0008] However, when manufacturing a trench structure using gallium nitride, if the trench has a large aspect ratio, it is difficult to fill the trench with the gate electrode material from the bottom to the upper opening edge without leaving any gaps, and voids are likely to form inside the gate electrode. When voids form inside the gate electrode, there is a problem in that the characteristics of the semiconductor device are degraded.

[0009] On the other hand, as in Patent Document 1, by increasing the width of the upper opening end of the trench and forming a trench with a V-shaped cross section and no bottom, it is possible to prevent the formation of cavities when filling the trench with the constituent material of the gate electrode. However, increasing the width of the upper opening end of the trench and lowering the aspect ratio of the trench results in a problem of a decrease in the formation density of the trench, which deteriorates the characteristics as a semiconductor element.

[0010] The present invention has been made in view of the above background, and aims to provide a gallium nitride laminate structure that is capable of increasing the trench formation density without creating voids inside the structure that fills the inside of the trench, and a method for manufacturing a gallium nitride laminate structure.

[0011] In order to solve the above problems, a gallium nitride stack structure according to one embodiment of the present invention proposes the following means: (1) A gallium nitride stack structure according to aspect 1 of the present invention comprises a base layer containing gallium nitride, a deposition layer containing gallium nitride stacked on one surface of the base layer, and a trench formed from one surface of the deposition layer along a stacking direction to a depth within the thickness of the deposition layer, the trench having an inner side surface and a bottom surface, the inner side surface of the trench being inclined so as to widen upward in the stacking direction at an inclination angle of 5° or more and 10° or less with respect to the stacking direction, and the inclination angle of the trench being an inclined surface with a change of ±1° or less.

[0012] (2) Aspect 2 of the present invention is characterized in that, in the gallium nitride stack structure of Aspect 1, the deposition layer has a first deposition layer of a first semiconductor type, a second deposition layer of a second semiconductor type containing gallium nitride stacked on the first deposition layer, and a source region of the first semiconductor type containing gallium nitride arranged so as to be in contact with the second deposition layer, and further comprises an insulating film formed from a dielectric material and covering the inner side surface of the trench, a gate electrode formed inside the insulating film so as to fill the trench, and a drain electrode arranged so as to be overlapped on the other surface of the base layer, and the trench is formed to a depth that reaches the first deposition layer along the stacking direction from one side of the source region.

[0013] (3) Aspect 3 of the present invention is characterized in that, in the gallium nitride stack structure of aspect 1 or 2, the bottom surface of the trench is a flat surface perpendicular to the stacking direction, or a curved surface whose center is recessed more than the peripheral edge.

[0014] (4) Aspect 4 of the present invention is characterized in that, in the gallium nitride stack structure of any one of aspects 1 to 3, the trench has an aspect ratio of 1 or more, which is the ratio of the depth along the stacking direction to the opening width perpendicular to the stacking direction on one surface of the deposition layer.

[0015] (5) A fifth aspect of the present invention is characterized in that, in the gallium nitride stack structure of any one of the first to fourth aspects, the depth direction of the trench is along the gallium nitride crystal orientation [1-100] or a crystal orientation equivalent thereto.

[0016] (6) A sixth aspect of the present invention is characterized in that, in the gallium nitride stacked structure of any one of the second to fifth aspects, the gate electrode has a solid structure with no voids inside.

[0017] (7) A seventh aspect of the present invention is characterized in that, in the gallium nitride stack structure of any one of the first to sixth aspects, the gallium nitride crystal plane orientation of the surface of the substrate layer is within an off-angle of 1.0° from {0001}.

[0018] (8) Aspect 8 of the present invention is characterized in that, in the gallium nitride stack structure of any one of aspects 1 to 7, an aspect ratio, which is the ratio of the depth along the stacking direction to the distance between trenches perpendicular to the stacking direction at the bottom of the trenches, is 1 or more.

[0019] (9) A manufacturing method of a gallium nitride laminate structure of aspect 9 of the present invention is a manufacturing method of a gallium nitride laminate structure of any one of aspects 1 to 8, characterized in that it comprises: a first trench processing step of forming, by dry etching, a processed groove having a processed surface along the stacking direction from one surface of a deposition layer along the stacking direction to a depth within the thickness of the deposition layer; and a second trench processing step of pouring an etching solution containing phosphoric acid into the processed groove and forming, by wet etching, the trench having the inner side surface consisting of the inclined surface.

[0020] (10) A tenth aspect of the present invention is the method for producing a gallium nitride laminated structure according to the ninth aspect, characterized in that the etching solution is an aqueous solution of phosphoric acid.

[0021] (11) Aspect 11 of the present invention is characterized in that, in the method for manufacturing a gallium nitride stack structure of aspect 9 or 10, the second trench processing step is performed by maintaining the liquid temperature of the etching solution in the range of 85°C or higher and 150°C or lower, and by setting the processing time in the range of 3 minutes or higher and 60 minutes or lower.

[0022] According to the present invention, it is possible to provide a gallium nitride stack structure that can increase the formation density of trenches without creating voids inside the structure that fills the inside of the trenches, and a method for manufacturing a gallium nitride stack structure.

[0023] FIG. 1 is a schematic cross-sectional view showing a gallium nitride stack structure according to one embodiment of the present invention. FIG. 2 is a flowchart showing, in stages, a method for manufacturing a gallium nitride stack structure according to one embodiment of the present invention. FIG. 3 is a schematic cross-sectional view showing, in stages, a method for manufacturing a gallium nitride stack structure according to one embodiment of the present invention. FIG. 4 is a schematic cross-sectional view and a cross-sectional SEM image of a trench portion of a sample used in Verification Example 1. FIG. 5 is a graph showing the CV characteristics of the sample used in Verification Example 1. FIG. 6 is a graph showing the interface defect state density of the sample used in Verification Example 1, estimated by the High-Low method. FIG. 7 is an SEM photograph showing a cross section along the thickness direction of the trench of an example of the present invention and a comparative example in Verification Example 2. FIG. 8 is a graph showing MOS channel mobility (field effect mobility) of an example of the present invention and a comparative example in Verification Example 2.

[0024] The present embodiment will be described in detail below with reference to the drawings as appropriate. The drawings used in the following description may show characteristic portions enlarged for the sake of clarity, and the dimensional ratios of each component may differ from the actual ones. The materials, dimensions, etc. exemplified in the following description are merely examples, and the present invention is not limited thereto. Appropriate changes can be made within the scope of the present invention.

[0025] 1 is a schematic cross-sectional view showing a gallium nitride stack structure according to one embodiment of the present invention. In this embodiment, a stacking direction S indicates the direction in which the layers constituting the gallium nitride stack structure are stacked, and this direction is along the

[0001] crystal plane orientation of gallium nitride.

[0026] The gallium nitride stack structure 10 of this embodiment constitutes, for example, a trench-structure power MOSFET (semiconductor device). The gallium nitride stack structure 10 includes a first film layer 12, a second film layer 13, and a film layer 18 having a source region 14, which are stacked in this order on one surface 11a of a substrate (base layer) 11, a source electrode 15, a trench 21 having an insulating film 16 and a gate electrode 17 formed therein, and a drain electrode 19 formed on the other surface 11b of the substrate 11.

[0027] The gallium nitride laminated structure 10 includes a substrate (base layer) 11 containing gallium nitride (GaN). The substrate 11 is a first semiconductor type N ＋ Any semiconductor of this type may be used.

[0028] A first deposition layer 12, which is an epitaxial film formed by epitaxially growing gallium nitride, constituting the deposition layer 18, is formed on one surface 11a of the substrate 11. The first deposition layer 12 is a first semiconductor type N doped with impurities such as silicon at a low concentration. － Any semiconductor of this type may be used.

[0029] A second deposition layer 13, which is an epitaxial film formed by epitaxially growing gallium nitride, and which constitutes a deposition layer 18, is formed on one surface 12a of the first deposition layer 12. The second deposition layer 13 is a P semiconductor layer of a second semiconductor type doped with a low concentration of impurities such as magnesium. － Any semiconductor of this type may be used.

[0030] A source region 14, which is an epitaxial film formed by epitaxially growing gallium nitride and constitutes a deposition layer 18, is formed on one surface 13a of the second deposition layer 13. The source region 14 is made of a first semiconductor type N ＋ Any semiconductor is acceptable.

[0031] In addition, such a source region 14 may be arranged so as to be in contact with the second film layer 13, and in addition to being formed by overlapping one surface 13a of the second film layer 13 as in this embodiment, it may also be formed so as to be embedded in a part of the second film layer 13 from the one surface 13a side of the second film layer 13 along the stacking direction S.

[0032] A source electrode 15 made of a conductive material is formed on one surface 14a of the source region 14. Such source electrode 15 is electrically connected to the source region 14. The source electrode 15 may be made of a conductor such as a Ni-Au alloy, a Ni-Ti-Au alloy, a Pd-Au alloy, a Pd-Ti-Au alloy, a Pd-Pt-Au alloy, Pt, Al, or Ti.

[0033] The gallium nitride stack structure 10 has one or more trenches 21 formed therein. The trenches 21 are formed from one surface of the deposition layer 18 along the stacking direction S to a depth within the thickness of the deposition layer 18. In this embodiment, the trenches 21 are elongated grooves formed from one surface 14a of the source region 14 downward in the stacking direction S to a depth reaching the first deposition layer 12. The trenches 21 have inner side surfaces 21a, 21a on both sides of the trench and a bottom surface 21b, and extend in the depth direction in FIG. 1 . The depth direction may be, for example, a direction along the [1-100] crystal orientation of gallium nitride or a crystal direction equivalent thereto.

[0034] The inner surface 21a of the trench 21 forms an inclined surface that is inclined so as to widen upward in the stacking direction S at an inclination angle θ in the range of 5° or more and 10° or less, preferably in the range of 6° or more and 8° or less, relative to the stacking direction S.

[0035] The inner side surface 21 a of the trench 21 is formed so that the change in the inclination angle θ is within ±1° over the entire inclined surface from the opening end on the side of the surface 14 a of the source region 14 to the bottom surface 21 b. In this embodiment, the inner side surface 21 a is an inclined surface made of a flat surface inclined at a uniform (constant) inclination angle θ.

[0036] In this embodiment, the inner surface 21a is an inclined surface inclined at an inclination angle θ of, for example, 7° with respect to the stacking direction S, and one inner surface 21a is, for example, a surface along the crystal plane orientation (33-61) of gallium nitride, and the other inner surface 21a is, for example, a surface along the crystal plane orientation (-3-361) of gallium nitride.

[0037] By making the inner surface 21a a slightly inclined surface with respect to the stacking direction S, it is possible to form trenches 21 at a high density while preventing cavities from occurring inside the gate electrode 17 when forming the gate electrode 17 described below.

[0038] Furthermore, by making the inner surface 21 a a slightly inclined surface with respect to the stacking direction S, the intersection angle between the inner surface 21 a and the bottom surface 21 b of the trench 21 becomes larger than 90°, and therefore, when the gallium nitride stack structure 10 of this embodiment is applied to a trench-structure type power MOSFET (semiconductor device), it is possible to suppress electric field breakdown from the bottom of this trench 21.

[0039] The bottom surface 21b of the trench 21 may be a flat surface perpendicular to the stacking direction S or a curved surface with the center recessed more than the peripheral edge. When the bottom surface 21b is a flat surface perpendicular to the stacking direction S, it is, for example, a surface along the (0001) crystal plane orientation of gallium nitride.

[0040] Such trenches 21 may have an aspect ratio (L2 / L1) of 1 or more, which is the ratio of the depth L2 along the stacking direction S to the opening width L1 perpendicular to the stacking direction S on one surface 14a of the source region 14. The gallium nitride stack structure 10 of this embodiment can prevent voids from being generated inside the trenches 21 when the gate electrode 17 is formed, even if the trenches 21 have an aspect ratio exceeding 1.

[0041] In addition, in FIG. 1 of this embodiment, the trapezoidal fin portion 25 formed between the adjacent trenches 21, 21 may have an aspect ratio (L2 / L3) of 1 or more, which is the ratio of the depth L2 along the stacking direction S to the distance L3 between the trenches 21, 21.

[0042] An insulating film 16 is formed in the trench 21 so as to cover the inner side surface 21a. The insulating film 16 may be made of any dielectric material, such as silicon oxide (SiO ２ The insulating film 16 is formed with a uniform thickness on the inner side surface 21 a of the trench 21, and the inner surface 16 a of the insulating film 16 is a surface parallel to the inner side surface 21 a of the trench 21, i.e., a surface slightly inclined with respect to the stacking direction S.

[0043] The insulating film 16 of this embodiment is formed to cover the inner side surface 21 a of the trench 21 and also the upper part of the gate electrode 17 described later, and is electrically isolated from the source electrode 15 .

[0044] The gate electrode 17 is formed inside the insulating film 16 so as to fill the trench 21. The gate electrode 17 may be made of a conductor such as W, Al, or polysilicon.

[0045] The gate electrode 17 is formed as a solid member that fills the trench 21, without creating any cavities or slits inside during formation, because the inner surface 21a of the trench 21 is a slightly inclined surface with respect to the stacking direction S.

[0046] On the other hand, a drain electrode 19 is formed on the other surface 11b of the substrate 11. The drain electrode 19 may be made of a conductor such as a Ni-Au alloy, a Ni-Ti-Au alloy, a Pd-Au alloy, a Pd-Ti-Au alloy, a Pd-Pt-Au alloy, Pt, or Al.

[0047] (Method for manufacturing a gallium nitride stack structure) Fig. 2 is a flowchart showing the steps of the method for manufacturing a gallium nitride stack structure of this embodiment. Also, Figs. 3 and 4 are schematic cross-sectional views showing the steps of the method for manufacturing a gallium nitride stack structure of this embodiment.

[0048] The method for manufacturing the gallium nitride stack structure of this embodiment includes a first film layer forming step S1, a second film layer forming step S2, a source region forming step S3, a trench forming step S4, an insulating film forming step S5, a gate electrode forming step S6, a source electrode forming step S7, and a drain electrode forming step S8.

[0049] In the first film layer forming step S1, for example, N ＋ A gallium nitride substrate 11 made of a type semiconductor is used. Gallium nitride doped with a low concentration of impurities such as silicon is epitaxially grown on one surface 11a of the substrate 11, and N － An epitaxial film that will become the first deposition layer 12, which is a type semiconductor, is formed (see FIG. 3(a)).

[0050] Next, in the second film layer forming step S2, gallium nitride doped with a low concentration of impurities such as magnesium is epitaxially grown on the one surface 12a side of the first film layer 12, thereby forming a P － An epitaxial film that will become the second film formation layer 13, which is a type semiconductor, is formed (see FIG. 3B).

[0051] Next, in the source region forming step S3, gallium nitride doped with a high concentration of impurities such as silicon is epitaxially grown on the surface 13a of the second film formation layer 13, and N ＋ An epitaxial film that will become the source region 14, which is a type semiconductor, is formed (see FIG. 3(c)).

[0052] Next, in the trench formation process S4, a first trench processing step S4-1 and a second trench processing step S4-2 are carried out in sequence. First, in the first trench processing step S4-1, an etching resist Q is formed that overlaps one surface 14a of the source region 14 and defines the shape of the upper opening end of the trench 21 to be formed (see Figure 3(d)).

[0053] Then, using this etching resist Q as an etching mask, a groove F having a uniform width and a vertical processed surface along the stacking direction S is formed by dry etching (see FIG. 3( e)). The groove F may be formed to a depth that reaches the first film formation layer 12 along the stacking direction S from one surface 14 a of the source region 14. Dry etching may be performed by reactive ion etching using a reactive gas such as chlorine or silicon tetrachloride, or physical etching such as ion milling.

[0054] Next, in the second trench processing step S4-2, an etching solution Rq containing phosphoric acid is poured into the inside of the trench F to perform wet etching (see FIG. 4A). As the etching solution Rq, for example, phosphoric acid (H ３ P.O. ４ ) can be used as an aqueous solution.

[0055] In this embodiment, the phosphoric acid aqueous solution is heated to 100°C to 110°C, and the laminate (processed intermediate body) including the processed groove F is immersed in the solution for about 30 minutes. The temperature of the etching solution in the second trench processing step S4-2 may be in the range of 85°C to 150°C, and the etching time (processing time) may be in the range of 3 minutes to 60 minutes.

[0056] When the inside of the groove F is wet-etched with an etching solution containing phosphoric acid, the etching is performed so that the surface is inclined at an angle of, for example, about 7° with respect to the

[0001] crystal plane orientation of gallium nitride.

[0057] This allows the formation of trench 21 having inner surface 21a consisting of an inclined surface that is inclined so as to widen upward in stacking direction S at an inclination angle θ in the range of 5° or more and 10° or less, preferably 6° or more and 8° or less, relative to stacking direction S.

[0058] Next, in the insulating film forming step S5, an insulating film 16 is formed by, for example, chemical vapor deposition so as to cover the inner side surface 21a and the bottom surface 21b of the trench 21 formed in the trench forming step S4 (see FIG. 4B). As the film forming material, for example, silicon dioxide (SiO ２ ) to form the insulating film 16 containing a silicon oxide film with a uniform thickness.

[0059] Next, in the gate electrode formation step S6, the gate electrode 17 is formed by, for example, sputtering inside the insulating film 16 formed in the insulating film formation step S5 so as to fill the trench 21 (see FIG. 4C). As the sputtering target, for example, a conductor such as a Ni—Au alloy, a Ni—Ti—Au alloy, a Pd—Au alloy, a Pd—Ti—Au alloy, a Pd—Pt—Au alloy, Pt, Al, or polysilicon may be used.

[0060] In the gate electrode formation process S6, the inner surface 21a of the trench 21 is inclined so as to widen upward in the stacking direction S at an inclination angle θ in the range of 5° or more and 10° or less, preferably 6° or more and 8° or less, relative to the stacking direction S. Therefore, during sputtering, the conductor is deposited evenly from the bottom to the top of the inside of the insulating film 16, and a solid gate electrode 17 can be formed without any cavities or slits inside.

[0061] Furthermore, the inner surface 21a of such trench 21 has a slight inclination angle of 5° or more and 10° or less with respect to the stacking direction S, and the opening end at the top of the trench does not become extremely large, such as having an aspect ratio of less than 1, so the formation density of trench 21 does not decrease.

[0062] Thereafter, an insulating film similar to the insulating film 16 is formed so as to cover the upper surface of the gate electrode 17, and then in a source electrode formation step S7, a source electrode 15 which is a conductor is formed so as to cover one surface 14a of the source region 14, and further in a drain electrode formation step S8, a drain electrode 19 which is a conductor is formed on the other surface 11b side of the substrate 11, whereby the gallium nitride stack structure 10 can be manufactured by the manufacturing method of the gallium nitride stack structure of this embodiment (see FIG. 4(d)).

[0063] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as defined in the claims.

[0064] The effects of the gallium nitride stack structure and the manufacturing method thereof of the present invention were verified. [Verification Example 1] The substrate was － Mold (1 x 10 １６ cm －３A Ga-face freestanding GaN substrate (G) was used. The freestanding GaN substrate had a crystal misorientation angle of 1° or less. A SiO film was formed on one surface of the substrate, which was shaped to match the opening shape of the trench to be formed. ２ After forming the etching mask, dry etching was performed to form a trench having a constant width along the stacking direction S and with side surfaces aligned along the crystal plane orientation (11-20) (first trench processing stage).

[0065] Next, a phosphoric acid aqueous solution (concentration: 85 wt %) heated to 105°C was poured into the processed groove to perform wet etching, etching the side surfaces of the processed groove and forming a trench having inner surfaces inclined at 7° with respect to the stacking direction S (second trench processing stage).

[0066] Then, SiO is deposited in the trench as a gate insulating film. ２ A 50-nm-thick oxide film containing TiN was formed by CVD. A conductor containing TiN was deposited inside the oxide film by sputtering to form a gate electrode. A conductive material containing AlTi was deposited on the other side of the substrate and annealed at 550°C for 10 minutes to form a drain electrode.

[0067] Figure 5 shows a schematic cross-sectional view of the trench portion of the sample formed as described above, and a cross-sectional SEM image (both of which show only half of the trench). As shown in Figure 5, wet etching with a phosphoric acid solution resulted in the inner side of the trench becoming an inclined surface equivalent to a surface tilted approximately 7° toward the Ga polarity side from the a-plane of the (11-20) crystal plane. The crystal plane index of this inclined surface is close to (33-61).

[0068] Typical CV characteristics of a MOS capacitor in which a gate electrode is formed in a trench having such an inclined surface are shown in Figure 6. As shown in Figure 6, it was confirmed that the specimen in the verification example had CV characteristics with small frequency dispersion. As shown in Figure 7, the interface defect state density roughly calculated by the High-Low method was 10 １１ cm －２ eV －１ It was confirmed that a MOS capacitor having excellent semiconductor characteristics and a small capacitance of less than 100 kJ / cm2 can be realized.

[0069] [Verification Example 2] In Verification Example 2, a Ga-face freestanding GaN substrate having an n+ type / p- type / n+ type stacked structure was fabricated. The trenches had side surfaces aligned along the crystal plane orientation (11-20) after the first trench processing step in Verification Example 1. The trenches were then fabricated using SiO 2 in the same manner as in Verification Example 1. ２ A gallium nitride stacked structure (MOS transistor) of the comparative example was fabricated by forming an oxide film containing AlTi on the front surface of the substrate and depositing a conductor containing TiN inside the oxide film by sputtering. A conductor containing AlTi was then deposited on the front surface of the substrate and annealed at 550°C for 10 minutes to form source and drain electrodes.

[0070] In addition to the comparative example described above, a second trench processing step was performed in accordance with Verification Example 1 to form a trench having an inner side surface inclined at 5° with respect to the stacking direction S, which was designated as an example of the present invention. SEM photographs of cross sections along the thickness direction of the trenches of the example of the present invention and the comparative example are shown in FIG.

[0071] Next, the MOS channel mobility (field effect mobility) was measured using the gallium nitride stacked structures (MOS transistors) of the invention example and the comparative example, and the results are shown in the graph of FIG.

[0072] 9, it was confirmed that the MOS transistor of the example of the present invention, which has an inner side surface inclined about 5° toward the Ga polarity side from the a-plane of the crystal plane (11-20), has an improved MOS channel mobility of about 10%, compared to the MOS transistor of the comparative example, which has an inner side surface inclined about 5° toward the Ga polarity side from the a-plane of the crystal plane (11-20). In the example of the present invention, the waveform distortion of the comparative example is eliminated, which confirms that the damaged portion caused by the plasma (dry etching) is removed by the etching in the second trench processing stage.

[0073] The gallium nitride stacked structure and the method for manufacturing the gallium nitride stacked structure of the present invention make it possible to realize a power MOSFET having excellent semiconductor characteristics without generating voids inside the gate electrode, and therefore have industrial applicability.

[0074] REFERENCE SIGNS LIST 10 Gallium nitride laminate structure 11 Substrate (base layer) 12 First deposition layer 13 Second deposition layer 14 Source region 15 Source electrode 16 Insulating film 17 Gate electrode 19 Drain electrode 21 Trench 21a Inner surface

Claims

1. A gallium nitride stacked structure comprising: a substrate layer containing gallium nitride; a deposition layer containing gallium nitride stacked on one surface of the substrate layer; and a trench formed from one surface of the deposition layer along a stacking direction to a depth within the thickness of the deposition layer, wherein the trench has an inner side and a bottom surface, the inner side of the trench is inclined so as to widen toward the upper side in the stacking direction at an inclination angle of 5° or more and 10° or less with respect to the stacking direction, and the inclination angle of the trench is an inclined surface that changes within ±1°.

2. The gallium nitride stack structure according to claim 1, characterized in that the deposition layer has a first deposition layer of a first semiconductor type, a second deposition layer of a second semiconductor type containing gallium nitride stacked on the first deposition layer, and a source region of the first semiconductor type containing gallium nitride arranged in contact with the second deposition layer, and further comprises an insulating film formed from a dielectric material and covering the inner side of the trench, a gate electrode formed inside the insulating film so as to fill the trench, and a drain electrode arranged to be overlapped on the other side of the base layer, the trench being formed to a depth reaching the first deposition layer along the stacking direction from one side of the source region.

3. A gallium nitride stacked structure as described in claim 1 or 2, characterized in that the bottom surface of the trench is a flat surface perpendicular to the stacking direction, or a curved surface whose center is recessed more than the peripheral edge.

4. A gallium nitride stacked structure as described in claim 1 or 2, characterized in that the trench has an aspect ratio, which is the ratio of the depth along the stacking direction to the opening width perpendicular to the stacking direction on one side of the deposition layer, of 1 or more.

5. A gallium nitride stacked structure according to claim 1 or 2, characterized in that the depth direction of the trench is along the gallium nitride crystal orientation [1-100] or a crystal orientation equivalent thereto.

6. The gallium nitride laminate structure according to claim 2, wherein the gate electrode has a solid structure with no voids therein.

7. A gallium nitride laminate structure according to claim 1 or 2, characterized in that the gallium nitride crystal plane orientation on the surface of the base layer is within an off angle of 1.0° from {0001}.

8. A gallium nitride stacked structure as described in claim 1 or 2, characterized in that the aspect ratio, which is the ratio of the depth along the stacking direction to the distance between the trenches perpendicular to the stacking direction at the bottom of the trenches, is 1 or more.

9. A method for producing a gallium nitride laminate structure as claimed in claim 1 or 2, comprising: a first trench processing step of forming a processed groove having a processed surface along the stacking direction by dry etching from one surface of a deposition layer along a stacking direction to a depth within the thickness of the deposition layer; and a second trench processing step of pouring an etching solution containing phosphoric acid into the processed groove and forming the trench having the inner side surface consisting of the inclined surface by wet etching.

10. The method for producing a gallium nitride laminate structure according to claim 9, wherein the etching solution is an aqueous solution of phosphoric acid.

11. The method for manufacturing a gallium nitride stack structure according to claim 9, wherein the second trench processing step is performed by maintaining the temperature of the etching solution in the range of 85°C or more and 150°C or less and for a processing time in the range of 3 minutes or more and 60 minutes or less.

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