Inductor performance enhancement using an outer, peripheral patterned ground shield
By integrating a patterned ground shield on the periphery of a multiturn inductor within RF front-end modules, the challenges of reduced form factor and performance degradation are addressed, resulting in improved inductor KPIs and device isolation.
WO2025058818A1PCT designated stage expired Publication Date: 2025-03-20QUALCOMM INC
Patent Information
- Application Number
- PCT/US2024/043484
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-09-15
- Filing Date
- 2024-08-22
- Publication Date
- 2025-03-20
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Figure US2024043484_20032025_PF_FP_ABST
Abstract
A device is described, in which the device includes a substrate. The device includes a multitum inductor (410) coupled to the substrate. The device also includes a patterned ground shield (420) on a periphery of the multiturn inductor and coupled to the substrate.
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Citation Information
Patent Citations
Shielded system
DE102013005984A1
Pgs and semiconductor device including the same
KR100759252B1
Planar inductive component and an integrated circuit comprising a planar inductive component
US20060049481A1
Circuits for and methods of implementing an inductor and a pattern ground shield in an integrated circuit
US20180190584A1
Semiconductor integrated circuit devices having high-Q wafer backside inductors and methods of fabricating same
US7531407B2