Semiconductor device and manufacturing method therefor, and an electronic device

The challenge of manufacturing devices with high density on limited substrates is solved by designing vertically stacked semiconductor devices and specific manufacturing methods, achieving high density and high performance semiconductor devices.

WO2025060315A1 Publication Date: 2025-03-27BEIJING SUPERSTRING ACAD OF MEMORY TECH
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Patent Information

Application Number
PCT/CN2024/071616
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2023-09-20
Filing Date
2024-01-10
Publication Date
2025-03-27

AI Technical Summary

Technical Problem

With the development of integrated circuit technology, the critical size of devices has reduced, resulting in small differences in process production that have a significant impact on device performance, while manufacturing as many device units as possible on a limited substrate is a challenge.

Method used

A semiconductor device is designed, which includes a plurality of vertically stacked transistors, gate electrodes and semiconductor layers, a bit line is connected to the semiconductor layer, a word line includes a gate electrode and a connection electrode, an alternately stacked insulating layer and sacrificial layer structure is formed by a specific manufacturing method, etching to form trenches and through holes, and deposition to form a gate electrode, an insulating layer and a semiconductor layer.

Benefits of technology

A high-density stacking of semiconductor devices on a finite substrate is achieved, reducing the coupling capacitance between the bit line and the gate electrode, and improving device density and performance.

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Abstract

A semiconductor device and a manufacturing method therefor, and an electronic device, which belong to the technical field of semiconductors. The semiconductor device comprises: a plurality of transistors, which are distributed at different layers and are stacked in the direction perpendicular to a substrate (1), wherein each transistor comprises a gate electrode (26) and a semiconductor layer (23); a bit line (30), which extends in the direction perpendicular to the substrate (1) and is connected to a plurality of semiconductor layers (23) of the plurality of transistors; and a word line (40), which extends in a first direction (X) parallel to the substrate (1), and comprises the gate electrodes (26) and connection electrodes (27) that are distributed in the first direction (X), wherein the connection electrodes (27) extend in the first direction (X) and are in contact with the gate electrodes (26). Side walls of the semiconductor layers extend in a second direction (Y) parallel to the substrate (1), the gate electrodes (26) are insulated from the semiconductor layers (23), and the first direction (X) intersects with the second direction (Y).
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