Piezoelectric unit and preparation method therefor, and electronic device

Abstract

A piezoelectric unit and a preparation method therefor, and an electronic device, which relate to the technical field of piezoelectric device preparation. The piezoelectric unit comprises a substrate, a monocrystalline dielectric oxide layer, a first electrode layer, a perovskite-type monocrystalline seed layer and a piezoelectric layer which are arranged in a stacked manner, wherein the lattice orientation ratio (100) / ((100)+(001)) of the piezoelectric layer is within the range of 0.7-0.8. The piezoelectric unit of the present application has a relatively high piezoelectric constant, such that the piezoelectric unit can better perform driving; moreover, the dielectric constant of the piezoelectric layer is controlled within a relatively low range, thereby reducing the electrical energy consumed and the heat emitted during driving.

Description

Piezoelectric unit, manufacturing method thereof, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on September 19, 2023, with application number 202311214532.0, and priority to the Chinese patent application entitled “Piezoelectric unit, preparation method thereof, and electronic device”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the technical field of piezoelectric device preparation, and in particular to a piezoelectric unit, a preparation method thereof, and an electronic device. Background Art

[0003] In recent years, piezoelectric cells made of piezoelectric materials such as lead zirconate titanate have been widely used in microelectromechanical systems (MEMS) devices, such as sensors and actuators. These piezoelectric cells, formed by forming thin films of these piezoelectric materials on substrates such as silicon and then fabricating them through MEMS processing, are expected to be used in a variety of MEMS devices, including piezoelectric thin film printheads, MEMS speakers, MEMS micromirrors, and gyroscopes.

[0004] As a piezoelectric thin film material, the elements such as lead, zirconium, titanium and oxygen in the piezoelectric thin film material form a perovskite crystal structure. The ideal perovskite structure is a cubic lattice, but it also includes tetragonal and orthorhombic crystals that are deformations of cubic crystals. In addition, the orientation of the crystal has a great influence on piezoelectric properties, especially piezoelectric properties such as electromechanical conversion efficiency, dielectric constant and dielectric loss. The higher the piezoelectric constant, the more efficient it can be driven. The larger the capacitance, the greater the power consumption during driving and the heat generated by the component itself. Currently, when preparing high-performance piezoelectric materials for use in MEMS components such as actuators, it is not possible to simultaneously meet the needs of increasing the piezoelectric constant and reducing the dielectric constant. As a result, the prepared piezoelectric thin film materials do not have a good working condition.

[0005] Summary of the Invention

[0006] The present application provides a piezoelectric unit, a preparation method thereof, and an electronic device. A single-crystal dielectric oxide layer, a first electrode layer, and a perovskite-type single-crystal seed layer, which are consistent with the lattice orientation of the single-crystal substrate, are sequentially grown on a single-crystal silicon substrate, and a piezoelectric film based on PZT with a certain thickness can be formed by a chemical solution deposition method. A piezoelectric unit with a higher piezoelectric constant and a lower dielectric constant can be prepared.

[0007] In a first aspect, the present application provides a piezoelectric unit comprising a stacked substrate, a single crystal dielectric oxide layer, a first electrode layer, a perovskite single crystal seed layer and a piezoelectric layer, wherein the lattice orientation ratio of the piezoelectric layer is (100) / ((100)+(001)) in the range of 0.7 to 0.8.

[0008] In this embodiment, a single crystal dielectric oxide layer, a first electrode layer, and a perovskite single crystal seed layer are sequentially grown on a single crystal silicon substrate, each of which has a lattice orientation consistent with that of the single crystal substrate. A piezoelectric film based on PZT having a certain thickness can be formed by chemical solution deposition. The lattice orientation of the prepared piezoelectric unit can be consistent with that of the single crystal silicon substrate. For example, when the lattice orientation of the single crystal silicon substrate is (100), the (100) orientation ratio ((100) / ((100)+(001))) of the prepared piezoelectric layer can be increased, thereby improving the piezoelectric constant of the piezoelectric layer and enabling the piezoelectric unit to be driven better. When the lattice orientation of the single crystal silicon substrate is (001), the (001) orientation ratio ((001) / ((100)+(001))) of the prepared piezoelectric layer can be increased to control the dielectric constant of the piezoelectric layer and reduce the power consumption and heat generated during driving.

[0009] In one possible implementation, the substrate includes a single crystal silicon substrate or a single crystal SOI substrate with a lattice orientation of (100), so as to grow a piezoelectric unit with a lattice orientation of (100) accounting for a major proportion, thereby improving the piezoelectric constant of the piezoelectric unit.

[0010] In one possible implementation, the lattice orientation ratio (100) / ((100)+(001)) of at least one of the single crystal dielectric oxide layer, the first electrode layer, and the perovskite single crystal seed layer is in the range of 0.7 to 0.8. In this embodiment, on a single crystal substrate with a lattice orientation of (100), a single crystal dielectric oxide layer, a first electrode layer, and a perovskite single crystal seed layer with a lattice orientation of (100) as the main proportion can be formed, so that the lattice orientation ratio (100) / ((100)+(001)) of the piezoelectric layer grown on the perovskite single crystal seed layer is in the range of 0.7 to 0.8, which can improve the piezoelectric constant of the piezoelectric layer so that the piezoelectric unit can be better driven; control the dielectric constant of the piezoelectric layer, and reduce the power consumed and the heat generated during driving.

[0011] In one possible implementation, the piezoelectric unit further includes a second electrode layer, the second electrode layer being located on a side of the piezoelectric layer facing away from the first electrode layer, and the piezoelectric layer being located between the first and second electrode layers. The first and second electrode layers are located on opposite sides of the piezoelectric layer and are capable of generating a certain potential difference to drive the piezoelectric layer to perform bending vibration.

[0012] In a possible implementation, the substrate is in a frame structure and is provided with first through holes that penetrate the substrate in a thickness direction;

[0013] The piezoelectric layer is located on one side of the substrate along the thickness direction, and includes at least one diaphragm. A second through hole is provided between the diaphragm and the substrate and / or between two adjacent diaphragms. At least a portion of an edge of the diaphragm is fixedly connected to the substrate to form a cantilever structure. The diaphragm covers a portion of the first through hole, and the second through hole is connected to the first through hole.

[0014] The piezoelectric unit further includes an organic film, and the organic film covers the diaphragm and the second through hole.

[0015] In this embodiment, a diaphragm actuation structure is provided so that the speaker unit has a cantilever structure. Since one end of the cantilever structure is suspended in the air, the actuation performance of the speaker unit is improved and the output power of the speaker unit can be increased.

[0016] In a second aspect, the present application provides an electronic device comprising a housing and a piezoelectric unit as described in any of the above items, wherein the housing encloses an inner cavity, and the piezoelectric unit is located in the inner cavity and fixed within the housing. The electronic device described in the present application has a piezoelectric unit with a high piezoelectric constant and a low dielectric constant, and the piezoelectric unit has a high driving capability and low driving heat generation.

[0017] In a possible implementation, the electronic device further includes a controller, which is electrically connected to the piezoelectric unit described above, and is configured to control the vibration of the piezoelectric unit.

[0018] In a third aspect, the present application provides a method for preparing a piezoelectric unit, comprising the following steps:

[0019] forming a single crystal dielectric oxide layer, a first electrode layer, and a perovskite type single crystal seed layer in sequence on a single crystal substrate, wherein the single crystal dielectric oxide layer is a single crystal oxide layer epitaxially grown on the single crystal substrate;

[0020] Applying a precursor liquid on the perovskite single crystal seed layer to form an intermediate, wherein the intermediate includes the single crystal substrate, the single crystal dielectric oxide layer, the first electrode layer, the perovskite single crystal seed layer, and the precursor liquid;

[0021] The intermediate is dried, calcined and cooled to allow the precursor liquid to crystallize and solidify to form a piezoelectric layer.

[0022] In one possible implementation, the single crystal substrate includes a single crystal silicon substrate or a single crystal SOI substrate. The thickness of the single crystal substrate can be in the range of 300 microns to 800 microns, and the lattice orientation of the single crystal substrate can be a silicon substrate with a (100) crystal plane index or a silicon substrate with a (001) crystal plane index, so as to achieve the desired lattice orientation for the piezoelectric layer to be grown in the piezoelectric unit fabricated in the present application.

[0023] In a possible implementation, the lattice orientations of the single crystal silicon substrate and the single crystal SOI substrate are (100), so as to grow a piezoelectric unit in which the lattice orientation is (100) and a major proportion, thereby improving the piezoelectric constant of the piezoelectric unit.

[0024] In a possible implementation, the first electrode layer includes at least one of a platinum electrode layer, a silver electrode layer, a copper electrode layer, and a gold electrode layer to form an electrode layer on one side of the piezoelectric layer in the piezoelectric unit.

[0025] In one possible implementation, the perovskite single crystal seed layer is made of at least one material selected from strontium ruthenate, lead lanthanum titanate, and disodium lanthanum oxide tetrahydrate to form a piezoelectric unit with a perovskite structure.

[0026] In one possible implementation, after the steps of drying, calcining and cooling the intermediate, the steps of coating the precursor liquid, drying, calcining and cooling are repeated on the formed piezoelectric layer until a piezoelectric layer of a preset thickness is formed. Through multiple coating, drying, calcining and cooling steps, a piezoelectric layer with a high density and a certain thickness can be formed.

[0027] In a possible implementation, the step of coating the precursor liquid on the perovskite single crystal seed layer includes:

[0028] The precursor liquid contains zirconium and titanium elements. By adjusting the ratio of zirconium and titanium elements in the precursor liquid, the orientation rate (100) / ((100)+(001)) in the piezoelectric layer formed after drying, calcining and cooling is determined to be in the range of 0.7 to 0.8. The prepared piezoelectric unit has a higher piezoelectric constant and a smaller dielectric constant.

[0029] In one possible implementation, the ratio of the molar amount of zirconium element to the molar amount of titanium element in the precursor liquid is in the range of 0.5 to 1, so that the orientation rate (100) / ((100)+(001)) in the prepared piezoelectric unit is in the range of 0.7 to 0.8, and the prepared piezoelectric unit has a higher piezoelectric constant and a smaller dielectric constant.

[0030] In one possible implementation, the step of calcining the precursor liquid includes heating the precursor liquid to a first predetermined temperature until the precursor liquid sintered and solidified; and then heating the precursor liquid to a second predetermined temperature to crystallize the precursor liquid. Pre-sintering is performed at the first predetermined temperature to allow the precursor liquid to sinter and solidify, and then calcining is performed at the second predetermined temperature to allow the solidified precursor to crystallize, forming a single-crystal piezoelectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIG1 is a schematic flow chart of a method for preparing a piezoelectric unit according to an embodiment of the present application;

[0032] FIG2 is a schematic diagram of XRD characterization of a piezoelectric unit provided in this application;

[0033] FIG3 is a schematic diagram showing the correspondence between voltage and strain provided in an embodiment of the present application;

[0034] FIG4 is a schematic diagram of strain of a (001) lattice orientation provided in an embodiment of the present application;

[0035] FIG5 is a schematic diagram of strain of a (100) lattice orientation provided by an embodiment of the present application;

[0036] FIG6 is a schematic diagram showing the correspondence between the piezoelectric constant d31 and the zirconium content provided in an embodiment of the present application;

[0037] FIG7 is a schematic diagram showing the correspondence between dielectric constant and zirconium content provided in an embodiment of the present application;

[0038] FIG8 is a schematic diagram of the structure of each layer of a piezoelectric unit provided in an embodiment of the present application;

[0039] FIG9 is a three-dimensional schematic diagram of a speaker unit provided in an embodiment of the present application;

[0040] FIG10 is an exploded view of the structure of the speaker unit in FIG9 provided by this application;

[0041] FIG11 is a partial cross-sectional schematic diagram of the structure of the speaker unit in FIG9 provided by the present application;

[0042] FIG12 is a three-dimensional schematic diagram of the diaphragm and substrate of the speaker unit in FIG9 provided by the present application;

[0043] FIG13 is a schematic structural diagram of a true wireless headset provided in an embodiment of the present application;

[0044] Figure 14 is a cross-sectional view of the true wireless headset in Figure 13 provided in this application. DETAILED DESCRIPTION

[0045] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0046] For ease of understanding, the English abbreviations and related technical terms involved in the embodiments of this application are explained and described below.

[0047] It should be clear that the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0048] The terms used in the embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0049] It should be understood that the term "and / or" as used herein is simply a term used to describe the existence of three possible relationships between related objects. For example, "A and / or B" can represent the existence of A alone, the existence of both A and B, and the existence of B alone. Furthermore, the character " / " in this document generally indicates that the related objects are in an "or" relationship.

[0050] The word "if," as used herein, may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to the determination" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)," depending on the context.

[0051] It should be understood that the terms “first”, “second”, etc. used in this application are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order.

[0052] In the description of this application, the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limiting this application.

[0053] When used in this application, "within the range of...", unless it is specifically stated that the end value is not included, it is assumed that both end values ​​of the range are included. For example, in the range of 1 to 5, the two values ​​1 and 5 are included.

[0054] Lattice orientation, also known as crystal orientation, generally refers to the directionality of a crystal. This refers to the tendency for covalent bonds to form in a particular direction. According to the quantum theory of covalent bonds, the strength of a covalent bond depends on the degree of electron cloud overlap. Due to the asymmetric distribution of partially filled electron shells, lattice growth always forms bonds in the direction of maximum electron cloud density.

[0055] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "install", "connect" and "connect" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, a conflicting connection or an integrated connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0056] The present application provides a method for preparing a piezoelectric unit, as shown in FIG1 , comprising the following steps:

[0057] Step S100, forming a single crystal dielectric oxide layer, a first electrode layer, and a perovskite single crystal seed layer having a certain thickness on a single crystal substrate in sequence, wherein the single crystal dielectric oxide layer is a single crystal oxide layer epitaxially grown on the single crystal substrate;

[0058] First, prepare a single crystal substrate. This can be a single-crystal silicon substrate or a silicon-on-insulator (SOI) substrate. SOI substrates incorporate a buried oxide layer between the top silicon layer and the backing substrate, enabling dielectric isolation of integrated circuit components and completely eliminating the parasitic latch-up effect in bulk silicon CMOS circuits. This application uses a single-crystal silicon substrate as an example.

[0059] The thickness of the single crystal silicon substrate can be in the range of 300 microns to 800 microns, and it can be a circular substrate. The radius of the circular substrate is related to the size of the piezoelectric unit to be formed, and this application does not make any specific restrictions. In addition, the lattice orientation of the single crystal silicon substrate can be a silicon substrate with a (100) crystal plane index or a silicon substrate with a (001) crystal plane index, which is used for the preparation of the piezoelectric unit of this application, so as to facilitate the lattice orientation required for the growth of the formed piezoelectric layer. It should be noted that when an SOI substrate is used, the SOI substrate can also use a single crystal substrate with a lattice orientation of (100) or (001).

[0060] In the present application, the single crystal substrate constitutes the substrate for preparing the piezoelectric unit, and the lattice orientations of the single crystal dielectric oxide layer, the first electrode layer, the perovskite single crystal seed layer and the piezoelectric layer grown thereon are all related to the single crystal substrate.

[0061] A single-crystalline dielectric oxide layer of a certain thickness is formed on a single-crystalline silicon substrate. The single-crystalline dielectric oxide layer can be made of at least one of zirconium oxide (ZrO2), yttrium-stabilized zirconium oxide (YSZ), and hafnium oxide (HfO2). The thickness can be in the range of 20 nanometers to 100 nanometers to form a buffer layer on the substrate. A single-crystalline dielectric oxide layer made of a material such as ZrO2 forms the buffer layer on the substrate (single-crystalline substrate). Specifically, the buffer layer can be formed on the substrate using a metal organic chemical vapor deposition (MOCVD) process, an electron beam evaporation process, a sputtering process, or other suitable processes.

[0062] In one embodiment, the single crystal substrate serves as the vibration layer, and the single crystal dielectric oxide layer formed on the single crystal silicon substrate serves as the buffer layer. The thickness of the buffer layer may be around 60 nanometers, for example, in the range of 55 nanometers to 65 nanometers.

[0063] In one embodiment, the formed buffer layer can also be used as a vibration plate for the piezoelectric unit. The stiffness of the vibration plate has a significant impact on its natural frequency and resonant frequency. Higher stiffness can increase the natural frequency of the vibration plate, thereby improving the frequency stability of the vibration plate. At the same time, when the piezoelectric unit is used in an actuator, the sensitivity of the vibration plate is an important indicator. Higher stiffness can make the piezoelectric unit more sensitive to external excitations, more likely to produce displacement or response, thereby improving the performance of the actuator. In addition, the thickness of the buffer layer in this embodiment can be controlled within the range of 200 nanometers to 8000 nanometers, so that the buffer layer 120 has a certain stiffness. In addition, the buffer layer needs to have a larger thickness. An increase in thickness also means that the lateral dimensions need to be increased, which also increases the lateral constraints on the buffer layer. Lateral constraints can make the buffer layer produce greater resistance when subjected to force. Therefore, the stiffness of the buffer layer is increased in combination with an increase in thickness.

[0064] Furthermore, the present application employs a single crystal silicon substrate, such as a single crystal silicon substrate with a (100) lattice orientation, on which a single crystal oxide layer can be epitaxially grown. In this case, the lattice orientation of the dielectric oxide layer can be consistent with that of the single crystal silicon substrate, thereby forming a dielectric oxide layer with a (100) lattice orientation. This dielectric oxide layer can then serve as a seed layer for the subsequent growth of an electrode layer, a perovskite single crystal seed layer, and a piezoelectric layer, thereby ensuring that the grown seed layer has a single crystal structure.

[0065] After forming the single-crystalline dielectric oxide layer, a first electrode layer is formed on the single-crystalline dielectric oxide layer. The first electrode layer can be made of at least one metal material, such as platinum (Pt), silver (Ag), copper (Cu), and gold (Au). In this application, the first electrode layer uses a Pt electrode as an example. A layer of electrode film can be formed on the first buffer layer by sputtering.

[0066] In this application, since silicon has a (100) lattice orientation, ZrO2 is grown on single crystal silicon (growing along the same orientation as silicon), and its lattice orientation is also (100). Furthermore, the electrode layer grown on the ZrO2 will also grow along the same orientation, and the Pt electrode layer will also grow along the lattice orientation (100).

[0067] After forming the Pt electrode layer, a perovskite single crystal seed layer is formed on the Pt electrode layer. Specifically, a single crystal seed layer having a perovskite structure can be formed on the Pt electrode layer by a sputtering method or other method using at least one material such as strontium ruthenate (SRO), lead lanthanum titanate (PLT), and disodium lanthanum oxide tetrahydrate (LNO). Specifically, the perovskite single crystal seed layer forms a film structure on the Pt electrode layer. Since the Pt electrode layer generally has a (100) lattice orientation, the perovskite single crystal seed layer grown thereon can also grow along the (100) lattice orientation.

[0068] Step S200 , coating a precursor liquid on the perovskite single crystal seed layer to form an intermediate, wherein the intermediate includes the single crystal substrate, the single crystal dielectric oxide layer, the first electrode layer, the perovskite single crystal seed layer and the precursor liquid.

[0069] The precursor liquid is an oxide containing elements such as lead, zirconium and titanium, which is used to form the piezoelectric layer material. For example, in this embodiment, the precursor liquid is Pb(Zr x Ti (1-x) )O3 as an example. The precursor liquid can be coated on the wafer (a wafer structure composed of a single crystal silicon substrate, a first electrode layer and a perovskite single crystal seed crystal layer) by a spin coater, and the precursor liquid can be in a sol state. And by controlling parameters such as the rotation speed of the spin coater, the spin coating time and the amount of spin coating liquid, the amount of the precursor liquid finally spin-coated on the wafer can be adjusted to achieve the preset designed piezoelectric layer thickness. Wherein, x is the ratio of zirconium element to the total content of zirconium and titanium elements, and 1-x is the ratio of titanium element to the total content of zirconium and titanium elements. This ratio can affect the ratio of lattice orientation in the prepared piezoelectric layer.

[0070] Step S300 , drying, calcining and cooling the intermediate, so that the precursor liquid is crystallized and solidified to form a piezoelectric layer.

[0071] After applying the precursor liquid, the precursor liquid can be heated and dried using a hot plate or electric furnace. The heating temperature can be in the range of 100°C to 150°C, and the heating time can be in the range of 10 minutes to 30 minutes. This heating step can remove substances such as organic solvents in the precursor liquid, thereby forming a denser piezoelectric layer.

[0072] After heating in the range of 100°C to 150°C for 10 to 30 minutes, the material can be further heated to the range of 600°C to 700°C for calcination using equipment such as a rapid annealing furnace (RTA), and heated in the range of 600°C to 700°C for 5 to 30 minutes. During the calcination process, gases such as oxygen are introduced to form a relatively dense seed layer after cooling.

[0073] In one embodiment, after the precursor liquid is dried, it can be heated to a temperature within a range of 200°C to 450°C and maintained at this temperature for a period of 10 to 30 minutes to pre-sinter the precursor liquid and solidify it. The solidified precursor is then heated to a temperature within a range of 600°C to 700°C and calcined to crystallize the solidified precursor and form a single-crystal oriented piezoelectric layer.

[0074] In this application, a PZT thin film with a preferred lattice orientation of (100) can be prepared on a Pt electrode layer through chemical solution deposition (CSD), so that the prepared piezoelectric layer can contain a certain amount of crystal structure with a lattice orientation of (100).

[0075] In this embodiment, a single crystal dielectric oxide layer, a first electrode layer, and a perovskite single crystal seed layer are sequentially grown on a single crystal silicon substrate, each of which has a lattice orientation consistent with that of the single crystal substrate. A piezoelectric film based on PZT having a certain thickness can be formed by chemical solution deposition. The lattice orientation of the prepared piezoelectric unit can be consistent with that of the single crystal silicon substrate. For example, when the lattice orientation of the single crystal silicon substrate is (100), the (100) orientation ratio ((100) / ((100)+(001))) of the prepared piezoelectric layer can be increased, thereby improving the piezoelectric constant of the piezoelectric layer and enabling the piezoelectric unit to be driven better. When the lattice orientation of the single crystal silicon substrate is (001), the (001) orientation ratio ((001) / ((100)+(001))) of the prepared piezoelectric layer can be increased, thereby reducing the dielectric constant of the piezoelectric layer and reducing the power consumed and the heat generated during driving.

[0076] In this example, a piezoelectric unit was fabricated using a single-crystal silicon substrate with a (100) lattice orientation. The reflection intensity of the fabricated piezoelectric unit was characterized by 2θ-Xφ scanning using X-ray diffraction measurements. As shown in Figure 2, the XRD pattern below shows peaks at (400) and (004), indicating that (100) and (400) are equivalent, and (001) and (004) are equivalent. For Zr:Ti ratios of 43:57 and 53:47, only the (400) peak is present at Zr:Ti ratios of 63:37 and 53:47, indicating that the (100) oriented lattice accounts for nearly 100%. Taking a Zr:Ti ratio of 43:57 as an example, the reflection intensity of the lattice orientation (100) influences the sum of the intensities of the lattice orientations (001) and (100) by approximately 80%. Taking a Zr:Ti ratio of 33:67 as an example, the reflection intensity of the lattice orientation (100) influences the sum of the intensities of the lattice orientations (001) and (100) by approximately 75%. The intensities of the peaks at 43:57 and 33:67 are calculated based on the intensity ratio of the two peaks. For example, at a ratio of 33:67, the (400) peak intensity is 724, and the (004) peak intensity is 242 (724 / (724+242)=75%). At a Zr:Ti ratio of 63:37, the (100) peak intensity is calculated to be approximately 75%. The Zr:Ti ratio is a molar ratio. By adjusting the ratio of Zr and Ti in the precursor solution, the proportion of lattice orientations (100) and (001) in the prepared piezoelectric unit can be adjusted to prepare a piezoelectric unit with a higher piezoelectric constant and dielectric constant.

[0077] In this embodiment, after the piezoelectric layer is formed, a second electrode layer and other structures are formed on the piezoelectric layer to form electrode layers on both the upper and lower sides of the piezoelectric layer, and the piezoelectric layer is located between the first electrode layer and the second electrode layer. Referring to FIG3 , electrode layers are formed on the upper and lower sides of the piezoelectric layer deposited on the piezoelectric unit to form a simple vibration structural element. By studying the deformation amount, the deformation amount of the lattice orientation film with a mixed existence of (100) and (001) proposed in this application is compared with the deformation amount of the piezoelectric film with a completely lattice orientation of (001). When a low voltage (in the range of 0 to 10V) is applied, the strain amount corresponding to the piezoelectric film with a completely lattice orientation of (001) is greater than that of the lattice orientation film with a mixed existence of (100) and (001) in this application. As the applied voltage increases, when the applied voltage reaches above 10V, the strain corresponding to the lattice orientation film of the present application in which (100) and (001) are mixed gradually becomes greater than the strain corresponding to the piezoelectric film whose lattice orientation is completely (001), so as to meet the requirements of more high-power devices for the vibration intensity of the piezoelectric unit.

[0078] As shown in Figure 4, when the lattice orientation is (001), the domain is parallel to the c-axis (the vertical upward direction in Figure 4, which is consistent with the direction of the voltage applied by the upper and lower electrode layers of the piezoelectric unit). Corresponding to the voltage applied extending in the c-axis direction, it can be observed that the lattice is deformed in the linear extension direction of the voltage.

[0079] As shown in Figure 5, when the lattice orientation is (100), the domains are oriented along the a-axis (horizontally to the right in Figure 4). When a voltage is applied along the c-axis, the domains rotate 90° from the a-axis toward the direction of the electric field (in this case, the c-axis), causing deformation. This strain is greater than typical piezoelectric strain. For example, the deformation H2 in Figure 5 is greater than the deformation H1 in Figure 4.

[0080] In addition, domain rotation requires a relatively large electric field. As shown in FIG3 , a threshold voltage that causes domain rotation may exist in the voltage range of 10 V to 14 V, so that when a voltage exceeding the threshold voltage is applied, the deformation of the (100) lattice along the c-axis under the action of the voltage in the c-axis direction is greater than the deformation of the (001) lattice in the c-axis direction.

[0081] Moreover, the lattice orientation of the piezoelectric film in the piezoelectric unit prepared in the present application is mainly (100), which can account for 70% to 80% of the sum of the (100) and (001) lattice orientations. Most of the lattice orientations in the piezoelectric film are consistent in direction. When a higher voltage (a voltage exceeding 10V) is applied, the degree of mutual cancellation of piezoelectric strains between adjacent crystals is reduced. In addition, the lattice with the (100) lattice orientation has a larger deformation amount than the lattice with the (001) lattice orientation, so that the prepared piezoelectric unit has higher piezoelectric properties.

[0082] In this embodiment, the dielectric constant can be measured using an impedance measuring instrument, such as the parallel plate method. The parallel plate method is also called the three-terminal method in the ASTM D150 standard. Its principle is to form a capacitor by inserting a material or liquid thin sheet between two electrodes, and then measure its capacitance and calculate the dielectric constant based on the measurement results. In the actual test device, the two electrodes are equipped on a test fixture that clamps the dielectric material. In this embodiment, the dielectric constant of the prepared single crystal oriented piezoelectric layer can be measured. When the orientation ratio of the lattice orientation (001) in the piezoelectric layer is close to 100%, the dielectric constant is about 500K, when the orientation ratio of the lattice orientation (100) in the piezoelectric layer is close to 100%, the dielectric constant is about 1000K, and when the piezoelectric layer is in an amorphous state, the dielectric constant is about 1800K. It can be seen that forming a single crystal piezoelectric layer can effectively reduce the dielectric constant of the piezoelectric unit, especially when the (001) crystal orientation ratio in the piezoelectric layer is high, the dielectric constant value is small. In this embodiment, the piezoelectric layer produced by using a single crystal (100) silicon substrate in the above embodiment can be controlled to have an orientation ratio (100) / ((100)+(001)) of the piezoelectric layer formed within the range of 0.7 to 0.8, thereby measuring the dielectric constant of the piezoelectric unit to be around 900K. Compared with the piezoelectric layer of an amorphous structure, the dielectric constant has been significantly reduced. In addition, the orientation ratio of the lattice orientation (100) is relatively high, and the corresponding lattice has a larger deformation, so that the prepared piezoelectric unit has higher piezoelectric properties.

[0083] In one embodiment, in step S200 and step S300, a piezoelectric layer of a predetermined thickness may be formed by multiple coating, drying, calcining, and cooling processes, wherein the thickness of the final piezoelectric layer may be within 5 microns.

[0084] After the precursor liquid is spin-coated on the seed layer and dried, calcined, and cooled to form a piezoelectric layer of a certain thickness, the precursor liquid is spin-coated again on the formed piezoelectric layer and dried, calcined, and cooled to form a piezoelectric layer of a certain thickness. After multiple (at least two) coating, drying, calcining, and cooling processes, a piezoelectric layer of a predetermined thickness is formed, for example, a predetermined thickness of 2 microns.

[0085] In a possible implementation, in step S300 , the step of calcining the precursor liquid includes: gradually heating the precursor liquid to a plurality of calcination temperature values, and maintaining each calcination temperature value for a certain period of time.

[0086] In this embodiment, the precursor liquid can be first heated to a first preset temperature and maintained at the first preset temperature for a certain period of time, and the precursor liquid is sintered and solidified; after the precursor liquid is solidified, it is heated to a second preset temperature, which is greater than the first preset temperature, and maintained at the second preset temperature for a certain period of time, and the solidified precursor is crystallized to form a piezoelectric layer with a single crystal orientation.

[0087] For example, after drying the precursor liquid, it can be heated to a temperature within a range of 200°C to 450°C and maintained at this temperature for 10 to 30 minutes to pre-sinter the precursor liquid and solidify it. The solidified precursor is then heated to a temperature within a range of 600°C to 700°C and calcined to crystallize the solidified precursor and form a single-crystal oriented piezoelectric layer.

[0088] In one embodiment, in step S200, the ratio of zirconium and titanium elements in the precursor liquid can be adjusted to ensure that the orientation ratio (100) / ((100)+(001)) of the piezoelectric layer formed after drying, calcination and cooling in step S300 is within the range of 0.7 to 0.8.

[0089] In this embodiment, the precursor liquid can be Pb(Zr x Ti (1-x) )O3 as an example, where x is the percentage of zirconium element in the precursor liquid to the sum of the total amount of zirconium element and titanium element.

[0090] FIG6 is a schematic diagram showing the ratio of the piezoelectric constant of the piezoelectric unit to the zirconium content in the precursor liquid, and FIG7 is a schematic diagram showing the ratio of the dielectric constant of the piezoelectric unit to the zirconium content in the precursor liquid.

[0091] As shown in Figures 6 and 7, the higher the proportion of zirconium in the precursor liquid, the higher the piezoelectric constant of the prepared piezoelectric layer and the greater the dielectric constant. Therefore, a piezoelectric layer with a higher piezoelectric constant can be formed by increasing the proportion of zirconium in the precursor liquid; and a piezoelectric layer with a lower dielectric constant can be formed by reducing the proportion of zirconium in the precursor liquid. In addition, according to the selection of the use scenario of the piezoelectric unit, and referring to the relationship between the piezoelectric constant and dielectric constant and the proportion of zirconium in the precursor liquid in Figures 6 and 7, it is possible to select a range of driving for high-performance actuators that takes into account both low dielectric constant and high piezoelectric constant.

[0092] In one embodiment, the ratio of the zirconium content to the sum of the zirconium and titanium content in the precursor liquid can be limited to be within the range of 0.35 to 0.5, and the ratio of the molar amount of the zirconium element to the molar amount of the titanium element in the precursor liquid can be limited to be within the range of 0.5 to 1. In this case, the piezoelectric constant of the prepared piezoelectric layer can be within the range of 200N / C to 250N / C, and the dielectric constant can be within the range of 700K to 1400K. For example, the precursor liquid is composed of Pb(Zr x Ti (1-x) )O3 as an example, the value of x can be in the range of 0.35 to 0.5, while maintaining a relatively large piezoelectric constant, a more suitable dielectric constant characteristic value below 1500 is obtained.

[0093] The present application also provides a piezoelectric unit, which can be made by the piezoelectric unit preparation method described in any of the above embodiments, as shown in Figure 8, including a stacked substrate and a piezoelectric layer, and the lattice orientation rate of the piezoelectric layer is (100) / ((100)+(001)) in the range of 0.7 to 0.8.

[0094] Among them, the piezoelectric unit includes a substrate 310, a single crystal dielectric oxide layer 320, a first electrode layer 330, a perovskite single crystal seed layer 340 and a piezoelectric layer 350 stacked in sequence. Each layer structure can be prepared by the preparation method of the above-mentioned embodiments and will not be repeated here.

[0095] The stacked substrate 310, single crystal dielectric oxide layer 320, first electrode layer 330, perovskite single crystal seed layer 340 and piezoelectric layer 350 can all be layered structures, and each layer structure has the same shape and the same size on the extended plane, so that the piezoelectric unit forms a multi-layer composite structure.

[0096] The lattice orientation ratio (100) / ((100)+(001)) of the piezoelectric layer is in the range of 0.7 to 0.8, and the lattice orientation ratio (100) / ((100)+(001)) of at least one of the single crystal dielectric oxide layer, the first electrode layer and the perovskite single crystal seed layer may also be in the range of 0.7 to 0.8.

[0097] In one embodiment, a second electrode layer 360 is further provided on the piezoelectric layer 350. The second electrode layer 360 is located on a side of the piezoelectric layer 350 facing away from the first electrode layer 330, and the piezoelectric layer 350 is located between the first electrode layer 330 and the second electrode layer 360. The first electrode layer and the second electrode layer are located on both sides of the piezoelectric layer and can generate a certain potential difference to drive the piezoelectric layer to perform bending vibration.

[0098] The piezoelectric unit described in the present application may be a piezoelectric device with certain functions, such as a micro-electro-mechanical system (MEMS) piezoelectric sensor and a speaker.

[0099] For example, the present application takes a piezoelectric speaker as an example and provides a speaker unit 10. Referring to Figures 9 to 12, the speaker unit 10 is composed of a multi-layer structure stacked in its thickness direction (Z direction in Figure 11), including a circuit substrate 110, a base layer 120, a diaphragm layer 130, and an organic film 140. The base layer 120, the diaphragm layer 130, and the organic film 140 can be grown and formed in sequence on the circuit substrate 110 to form the circuit substrate 110, the base layer 120, the diaphragm layer 130, and the organic film 140 stacked in sequence along the thickness direction. Among them, the base layer 120 can be the substrate 310 in each of the above embodiments, and the diaphragm layer 130 can be the piezoelectric layer 350 with a preferred lattice orientation of (100) on the electrode layer by chemical solution deposition (CSD). The lattice orientation ratio of the piezoelectric layer 350 is (100) / ((100)+(001)) in the range of 0.7 to 0.8.

[0100] Referring to Figure 11 , a base layer 120 is secured to a circuit substrate 110. Base layer 120 is provided with first through-holes 121 extending through the thickness of the base layer 120. First through-holes 121 are located in the middle of the base layer 120, forming a U-shaped structure. A frame structure surrounding first through-holes 121 is secured to the circuit substrate 110. Circuit substrate 110 is provided with fourth through-holes 111 extending through the thickness of the circuit substrate 110. Fourth through-holes 111 are located in the middle of the circuit substrate 110, forming a U-shaped structure.

[0101] The fourth through hole 111 and the first through hole 121 are connected in the thickness direction. The first outer wall surface 1211 of the first through hole 121 (the inner wall surface of the middle cavity of the base layer 120) and the second outer wall surface 1111 of the fourth through hole 111 (the inner wall surface of the middle cavity of the circuit substrate 110) can be flush with each other, and the first outer wall surface 1211 and the second outer wall surface 1111 can be coplanar along the Z direction. Alternatively, the first outer wall surface 1211 and the second outer wall surface 1111 can be non-coplanar along the Z direction, so that the base layer 120 and the circuit substrate 110 form a step structure at the connection. The width H1 of one side of the circuit substrate 110 along the X direction is greater than or equal to the width H2 of one side of the base layer 120 along the X direction, so that the circuit substrate 110 can better support the base layer 120, as well as support the diaphragm layer 130 and the organic film 140 set on the base layer 120.

[0102] In one embodiment, the width of the circuit substrate 110 along one side in the X direction is greater than or equal to the width of the base layer 120 along one side in the X direction. At the same time, the width of the circuit substrate 110 along the X direction is greater than or equal to the width of the base layer 120 along the X direction. Alternatively, the width of one of the two sides of the circuit substrate 110 along the X direction, both in the one side and in the opposite direction, is greater than or equal to the width of the base layer 120 along the X direction. This allows the circuit substrate 110 to provide better support for the base layer 120.

[0103] In one embodiment, the width of the side edge of the circuit substrate 110 along the Y direction is greater than or equal to the width of the side edge of the base layer 120 along the Y direction. At the same time, the width of the side edge of the circuit substrate 110 along the Y direction is greater than or equal to the width of the side edge of the base layer 120 along the Y direction. Alternatively, the width of one of the two sides of the circuit substrate 110 along the Y direction, on one side and on the other side, is greater than or equal to the width of the side edge of the base layer 120 on the same side, so that the circuit substrate 110 provides better support for the base layer 120.

[0104] It should be noted that the dotted lines in FIG. 11 are only used to illustrate the positions of the first through hole 121 and the fourth through hole 111 to better illustrate the structure of the circuit substrate 110 and the base layer 120 , and do not make any specific or special limitation on the structure of the speaker unit 10 .

[0105] Referring to Figures 10 and 12, a diaphragm layer 130 is provided on the base layer 120. The diaphragm layer 130 is provided on the base layer 120 of the "U"-shaped structure and is located on one side of the base layer 120 along the thickness direction. The diaphragm layer 130 includes a diaphragm 131. At least part of the edge of the diaphragm 131 is fixedly connected to the base layer 120 to form a cantilever structure 1311. The diaphragm 131 includes a fixed portion 131a and a suspended portion 131b. At least part of the edge of the fixed portion 131a of the diaphragm 131 is fixedly connected to the base layer 120, and the suspended portion 131b of the diaphragm 131 is suspended on the inner side of the base layer 120 and extends from the frame of the "U"-shaped structure of the base layer 120 toward one side of the second through hole 132, thereby forming a cantilever structure 1311. The diaphragm layer 130 includes at least one diaphragm 131. For example, the diaphragm layer 130 may include two diaphragms 131, namely a first diaphragm 1312 and a second diaphragm 1312 (FIG. 12). The diaphragm 131 partially covers the first through hole 121, that is, at least a portion of the diaphragm 131 is projected along the thickness direction and overlaps with the first through hole 121.

[0106] A second through hole 132 is provided between the diaphragm 131 and the base layer 120, as well as between adjacent diaphragms 131. The second through hole 132 and the first through hole 121 intersect each other, and the second through hole 132 is located on one side of the first through hole 121 along the positive direction of the Y direction. Referring to FIG12 , the diaphragm 131 includes a first diaphragm 1312 and a second diaphragm 1313 disposed oppositely on the base layer 120. The first diaphragm 1312 and the second diaphragm 1313 can both be isosceles trapezoids. The longer base sides of the isosceles trapezoids of the first diaphragm 1312 and the second diaphragm 1313 are fixedly connected to the frame structure of the base layer 120, and the shorter base sides of the isosceles trapezoids of the first diaphragm 1312 and the second diaphragm 1313 are parallel to and opposite each other. The first diaphragm 1312 has a first edge 1316 on a side close to the second diaphragm 1313 , and the second diaphragm 1313 has a second edge 1317 on a side close to the first diaphragm 1312 . The second through hole 132 is spaced between the first edge 1316 and the second edge 1317 .

[0107] In one embodiment, a second through hole 132 is provided between the diaphragm 131 and the base layer 120 . It is understandable that when the diaphragm layer 130 includes a diaphragm 131 , the second through hole 132 is formed by a portion of the edge of the diaphragm 131 and the base layer 120 .

[0108] The diaphragm layer 130 deforms under the influence of a driving voltage, and the cantilever structure 1311 of the diaphragm layer 130 drives the diaphragm 131 to vibrate, thereby producing sound. By providing a diaphragm actuation structure, the speaker unit 10 has a cantilever structure. Since one end of the cantilever structure 1311 is suspended in the air, it improves the actuation performance of the speaker unit 10 and can increase the output power of the speaker unit 10.

[0109] It should be noted that the shape of the diaphragm 131 in Figures 9 to 12 of the present application is only an example and does not specifically limit the shape of the diaphragm in the present application.

[0110] As shown in Figure 9, the organic film 140 is disposed on and covers the diaphragm layer 130. The organic film 140 is disposed along the thickness direction on one side of the diaphragm layer 130 along the Z direction and is fixedly connected to the diaphragm layer 130. The organic film 140 completely blocks the first through-hole 121. That is, the projection of the organic film 140 along the thickness direction completely covers the first through-hole 121. By providing the organic film 140 to completely block the first through-hole 121, a reduction in sound pressure can be prevented without affecting the actuation of the diaphragm 131.

[0111] The speaker unit 10 provided in this embodiment, on the one hand, has a cantilever structure by providing a diaphragm actuation structure, which can increase the output power of the speaker unit 10; on the other hand, by providing an organic film 140 that closes the first through hole 121, it prevents the sound pressure from decreasing without affecting the actuation of the diaphragm 131. Therefore, the above structural design is conducive to minimizing the size of the speaker unit 10 and maximizing the sound pressure within a limited space. Therefore, the speaker unit 10 of the present application can achieve both miniaturization and increased output power, and can meet the performance requirements of active noise reduction.

[0112] In addition, the present application also provides an electronic device comprising the piezoelectric unit described in any of the above embodiments, wherein the piezoelectric unit can be a speaker unit, etc., which uses the piezoelectric vibration characteristics as a drive to achieve functions such as sound generation and driving medium flow.

[0113] Specifically, the piezoelectric unit in this embodiment takes a speaker unit as an example. The speaker unit can be applied to electronic devices such as headphones and hearing aids.

[0114] Referring to Figures 13 and 14, Figure 13 is a schematic structural diagram of a true wireless headset 100 according to an embodiment of the present application, and Figure 14 is a cross-sectional view of the true wireless headset 100 shown in Figure 13. The true wireless headset 100 includes a speaker unit 10, a housing 20, and a controller (not shown in the figure). The housing 20 may include a first housing 210 and a second housing 220. The first housing 210 and the second housing 220 are arranged opposite to each other to form an inner cavity of the headset, and the speaker unit 10 is integrated into the inner cavity of the headset. The speaker unit 10 is arranged in the inner cavity of the headset and divides the inner cavity of the headset into a front cavity 230 and a rear cavity 240. The speaker unit 10 is provided with a front sound hole 250 and a rear sound hole 260, wherein the front sound hole 250 is connected to the front cavity 230, and the rear sound hole 260 is connected to the rear cavity 240, thereby forming the front sound channel and the rear sound channel of the true wireless headset 100. The speaker unit 10 is electrically connected to the controller. When the speaker unit 10 receives an electrical signal, the controller drives the speaker unit 10 to vibrate and converts the electrical signal into a sound signal, thereby playing the sound and transmitting the sound to the user's ears.

[0115] With the development of information and communication technology and electronic devices, electronic devices such as headphones are trending towards miniaturization and portability. The speaker unit 10 built into the electronic device must not only evolve towards miniaturization, but also ensure that the acoustic performance of the speaker unit 10, such as sound pressure level or wider bandwidth, meets user needs.

[0116] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A piezoelectric unit, characterized in that: The invention comprises a substrate, a single crystal dielectric oxide layer, a first electrode layer, a perovskite single crystal seed layer and a piezoelectric layer which are stacked, wherein the lattice orientation rate (100) / ((100)+(001)) of the piezoelectric layer is in the range of 0.7 to 0.

8.

2. The piezoelectric unit according to claim 1, characterized in that The substrate includes a single crystal silicon substrate or a single crystal SOI substrate having a lattice orientation of (100).

3. The piezoelectric unit according to claim 1 or 2, characterized in that: A lattice orientation ratio (100) / ((100)+(001)) of at least one of the single crystalline dielectric oxide layer, the first electrode layer, and the perovskite type single crystalline seed layer is in the range of 0.7 to 0.

8.

4. The piezoelectric unit according to any one of claims 1 to 3, characterized in that: The piezoelectric unit further includes a second electrode layer, which is located on a side of the piezoelectric layer away from the first electrode layer, and the piezoelectric layer is located between the first electrode layer and the second electrode layer.

5. The piezoelectric unit according to claim 4, characterized in that: The substrate is in a frame structure and is provided with first through holes that intersect each other in the thickness direction; The piezoelectric layer is located on one side of the substrate along the thickness direction, and includes at least one diaphragm, a second through hole is provided between the diaphragm and the substrate and / or between two adjacent diaphragms, at least a portion of the edge of the diaphragm is fixedly connected to the substrate to form a cantilever structure, the diaphragm covers a portion of the first through hole, and the second through hole is connected to the first through hole; The piezoelectric unit further includes an organic film, and the organic film covers the diaphragm and the second through hole.

6. An electronic device, characterized in that: It comprises a shell and the piezoelectric unit according to any one of claims 1 to 5, wherein the shell encloses an inner cavity, and the piezoelectric unit is located in the inner cavity and fixed in the shell.

7. The electronic device according to claim 6, characterized in that: The electronic device further includes a controller, which is electrically connected to the piezoelectric unit and is used to control the vibration of the piezoelectric unit.

8. A method for preparing a piezoelectric unit, for preparing the piezoelectric unit according to any one of claims 1 to 7, characterized in that: The steps include: forming a single crystal dielectric oxide layer, a first electrode layer and a perovskite type single crystal seed layer in sequence on a single crystal substrate, wherein the single crystal dielectric oxide layer is a single crystal oxide layer epitaxially grown on the single crystal substrate; Coating a precursor liquid on the perovskite type single crystal seed crystal layer to form an intermediate, wherein the intermediate includes the single crystal substrate, the single crystal dielectric oxide layer, the first electrode layer, the perovskite type single crystal seed crystal layer and the precursor liquid; The intermediate is dried, calcined and cooled to allow the precursor liquid to crystallize and solidify to form a piezoelectric layer.

9. The method for preparing a piezoelectric unit according to claim 8, characterized in that: The single crystal substrate has a lattice orientation of (100).

10. The method for preparing a piezoelectric unit according to claim 8 or 9, characterized in that: The step of coating a precursor liquid on the perovskite type single crystal seed layer comprises: The precursor liquid contains zirconium and titanium. The ratio of zirconium to titanium in the precursor liquid is adjusted to ensure that the orientation rate (100) / ((100)+(001)) of the piezoelectric layer formed after drying, calcining and cooling is within the range of 0.7 to 0.

8.

11. The method for preparing a piezoelectric unit according to claim 10, characterized in that: The ratio of the molar amount of zirconium element to the molar amount of titanium element in the precursor liquid is in the range of 0.5 to 1.

12. The method for preparing a piezoelectric unit according to any one of claims 8 to 11, characterized in that: The step of calcining the precursor liquid comprises: Heating to a first preset temperature until the precursor liquid is sintered and solidified; Continue heating to a second preset temperature to allow the precursor liquid to crystallize.

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