Random access memory and manufacturing method therefor

Abstract

Provided in the present disclosure are a random access memory and a manufacturing method therefor. The random access memory comprises: a substrate, which has a first conductive channel and a second conductive channel that are arranged spaced apart from each other, wherein both the first conductive channel and the second conductive channel extend from a first surface of the substrate into the substrate; a storage unit, which is located on the first surface and is in contact with the first conductive channel; a first insulating dielectric layer, which is located on the first surface and covers a side wall of the storage unit; a barrier layer, which is located on the side of the first insulating dielectric layer that is away from the storage unit; and a first metal layer, which is located on the side of the substrate that has the storage unit, wherein the first metal layer is in contact with the side of the storage unit that is away from the substrate. By means of the present disclosure, the manufacturing cost of a random access memory is reduced.

Description

Random access memory and manufacturing method thereof Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a random access memory and a manufacturing method thereof. Background Art

[0002] As a new type of memory, random access memory (RAM) offers significant advantages over traditional Flash memory in terms of read / write speed and device reliability. The current industry-wide integration solution generally involves first fabricating bottom vias and memory cells in the array area containing the memory cells, then fabricating bottom vias in the non-memory area (logic area), and finally fabricating a top metal layer common to both the memory area (array area) and the non-memory area (logic area). Consequently, conventional techniques require fabricating the bottom vias in the memory area (array area) and the bottom vias in the non-memory area (logic area) in two separate steps using a single photomask, increasing manufacturing costs. Furthermore, since magnetic random access memory (RAM) typically consists of a three-layer basic unit consisting of a ferromagnetic layer, an insulating tunneling layer, and a pinned layer, when the magnetic moments of the ferromagnetic layer and the pinned layer are in opposite directions, the memory device exhibits a high-resistance state (Rap). When the magnetic moments of the two layers are in the same direction, the memory device exhibits a low-resistance state (Rp), used for storing "1" and "0" information. Therefore, the information stored in this RAM can be disrupted by external magnetic fields.

[0003] Therefore, a new random access memory is urgently needed.

[0004] Summary of the Invention

[0005] The main purpose of the present disclosure is to provide a random access memory to solve the problem of high manufacturing cost of random access memory in the prior art.

[0006] To achieve the above objectives, according to one aspect of the present disclosure, a random access memory is provided, comprising: a substrate having a first conductive channel and a second conductive channel spaced apart, and both the first conductive channel and the second conductive channel extend from a first surface of the substrate into the substrate; a memory cell located on the first surface and in contact with the first conductive channel; a first insulating dielectric layer located on the first surface and covering a sidewall of the memory cell; a barrier layer located on a side of the first insulating dielectric layer away from the memory cell; and a first metal layer located on a side of the substrate having the memory cell, and the first metal layer in contact with a side of the memory cell away from the substrate.

[0007] Furthermore, the barrier layer is a metal layer or a metal oxide layer.

[0008] Furthermore, the material of the barrier layer at least includes magnetic material.

[0009] Furthermore, the random access memory further includes: a second insulating dielectric layer located on a side of the blocking layer away from the first insulating dielectric layer, so that the blocking layer is located between the first insulating dielectric layer and the second insulating dielectric layer.

[0010] Furthermore, the storage unit has a first projection on the first surface, the first insulating dielectric layer has a second projection on the first surface, the barrier layer has a third projection on the first surface, and the second projection is located between the first projection and the third projection.

[0011] Furthermore, the random access memory is any one of a magnetic random access memory, a phase change random access memory, a variable resistance memory and a ferroelectric memory.

[0012] According to another aspect of the present disclosure, a method for manufacturing a random access memory is provided, comprising: providing a substrate, the substrate having a first conductive channel and a second conductive channel spaced apart, and both the first conductive channel and the second conductive channel extending from a first surface of the substrate into the substrate; forming a memory cell on the first surface so that the memory cell contacts the first conductive channel; forming a first insulating dielectric layer on the first surface so that the first insulating dielectric layer covers a sidewall of the memory cell; forming a barrier layer on a side of the first insulating dielectric layer away from the memory cell; and forming a first metal layer on a side of the substrate having the memory cell so that the first metal layer contacts a side of the memory cell away from the substrate.

[0013] Furthermore, the steps of forming a first insulating dielectric layer and a barrier layer include: depositing a first insulating material layer on one side of a substrate having a first surface so that the first insulating material layer covers the first surface, the sidewalls of the storage unit and the second surface, the second surface being a surface of the side of the storage unit away from the first surface; depositing a barrier material layer on a side of the first insulating material layer away from the first surface so that the barrier material layer covers the first insulating material layer; removing a portion of the first insulating material layer outside the covered sidewalls and a portion of the barrier material layer outside the side of the first insulating material layer away from the storage unit so that the remaining first insulating material layer forms a first insulating dielectric layer, the remaining barrier material layer forms a barrier layer, and the first insulating dielectric layer is located between the storage unit and the barrier layer.

[0014] Furthermore, the steps of forming a first insulating dielectric layer and a barrier layer include: depositing a first insulating material layer on one side of a substrate having a first surface so that the first insulating material layer covers the first surface, the sidewalls of the storage unit and the second surface, where the second surface is a surface of the storage unit away from the first surface; removing at least a portion of the first insulating material layer other than the sidewalls so that the second surface and a portion of the first surface are exposed, and the remaining first insulating material layer forms a first insulating dielectric layer; depositing a barrier material layer on a side of the first insulating dielectric layer away from the first surface so that the barrier material layer covers the exposed second surface, the exposed first surface and the first insulating dielectric layer; and removing at least a portion of the barrier material layer other than the first insulating dielectric layer using an etching process so that the remaining barrier material layer forms a barrier layer.

[0015] Furthermore, before the step of forming the first metal layer, the manufacturing method further includes: forming a second insulating dielectric layer on a side of the barrier layer away from the first insulating dielectric layer, so that the barrier layer is located between the first insulating dielectric layer and the second insulating dielectric layer.

[0016] By applying the technical solution disclosed in the present invention, a random access memory is provided, comprising a substrate, a memory cell, a first insulating dielectric layer, a barrier layer and a first metal layer, wherein the substrate has a first conductive channel and a second conductive channel spaced apart, and both the first conductive channel and the second conductive channel extend from the first surface of the substrate into the substrate, so that the first conductive channel and the second conductive channel can be formed using the same mask and through a single etching process, and the memory cell serves as a core unit in the random access memory, and the first insulating dielectric layer and the barrier layer not only prevent the memory cell from being damaged, but also serve as an isolation layer between the first metal layer and the memory cell, so that the first metal layer does not contact the side wall of the memory cell, thereby further saving the top electrode mask required for forming the first metal layer, and further reducing the production cost of the random access memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which constitute part of the present disclosure, are intended to provide a further understanding of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are intended to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the accompanying drawings:

[0018] FIG1 shows a schematic cross-sectional structure diagram of an embodiment of a random access memory according to the present disclosure;

[0019] FIG2 shows a schematic cross-sectional structure diagram of a substrate provided in a method for manufacturing a random access memory according to an embodiment of the present disclosure;

[0020] FIG3 is a schematic cross-sectional view showing a structure in which a storage film is formed on the substrate shown in FIG2 ;

[0021] FIG4 shows a schematic cross-sectional structure diagram of a first insulating material layer formed after etching the memory thin film shown in FIG3 and forming a memory cell;

[0022] FIG5 is a schematic cross-sectional view showing a barrier material layer formed after etching the first insulating material layer shown in FIG4 ;

[0023] FIG6 shows a schematic cross-sectional structure diagram of a first protective layer formed after etching the barrier material layer shown in FIG5 ;

[0024] FIG7 shows a schematic cross-sectional structural diagram of a barrier material layer formed on the first insulating material layer shown in FIG4 ;

[0025] FIG8 is a schematic cross-sectional view showing a second protective layer formed after sequentially etching the barrier material layer and the first insulating material layer of the structure shown in FIG7 ;

[0026] FIG9 shows a schematic cross-sectional structure diagram of a second insulating material layer formed after sequentially etching the barrier material layer and the first insulating material layer of the structure shown in FIG7 ;

[0027] FIG10 shows a schematic cross-sectional structure diagram of a third protective layer formed after etching the second insulating material layer shown in FIG9 ;

[0028] FIG11 shows a schematic cross-sectional structural diagram of a dielectric thin film layer formed on the second protective layer shown in FIG8 ;

[0029] FIG12 is a schematic cross-sectional view showing a first metal layer formed after etching the dielectric film layer and the second protective layer of the structure shown in FIG11 .

[0030] The above drawings include the following reference numerals:

[0031] 10. Substrate; 101. First metal wiring layer; 102. Second metal wiring layer; 20. First conductive channel; 30. Second conductive channel; 40. Storage unit; 401. Storage film; 50. First insulating dielectric layer; 501. First insulating material layer; 60. Barrier layer; 601. Barrier material layer; 70. First protective layer; 80. Second protective layer; 90. Second insulating dielectric layer; 901. Second insulating material layer; 100. Third protective layer; 110. Dielectric film layer; 120. First metal layer. DETAILED DESCRIPTION

[0032] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0033] In order to enable those skilled in the art to better understand the solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present disclosure.

[0034] It should be noted that the terms "first," "second," and the like in the specification and claims of the present disclosure and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate for the embodiments of the present disclosure described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or inherent to these processes, methods, products, or apparatus.

[0035] As described in the background art, the bottom through holes of the storage area (array area) and the bottom through holes of the non-storage area (logic area) in the prior art need to be made in two steps using a single mask, thereby increasing the manufacturing cost. And since the magnetic random access memory is usually composed of three basic units consisting of a ferromagnetic layer, an insulating tunneling layer, and a fixed layer. When the magnetic moment directions of the ferromagnetic layer and the fixed layer are opposite, the memory device exhibits a high-resistance state Rap, and when the magnetic moment directions of the two layers are the same, it exhibits a low-resistance state Rp, which is used for storing information "1" and "0". It can be seen that the storage of information in the magnetic random access memory will be disturbed under the influence of an external magnetic field. In order to solve the above technical problems, the present disclosure provides a random access memory and a method for manufacturing the same.

[0036] According to one aspect of the present disclosure, a random access memory is provided, as shown in FIG1 , the random access memory comprising: a substrate 10 having a first conductive channel 20 and a second conductive channel 30 spaced apart, wherein the first conductive channel 20 and the second conductive channel 30 both extend from a first surface of the substrate 10 into the substrate 10; a memory cell 40 located on the first surface and in contact with the first conductive channel 20; a first insulating dielectric layer 50 located on the first surface and covering a sidewall of the memory cell 40; a barrier layer 60 located on a side of the first insulating dielectric layer 50 away from the memory cell 40; and a first metal layer 120 located on a side of the substrate 10 having the memory cell 40, wherein the first metal layer 120 is in contact with a side of the memory cell 40 away from the substrate 10.

[0037] Furthermore, the random access memory substrate 10 may further include multiple metal wiring layers. For example, the substrate 10 may include a first metal wiring layer 101 and a second metal wiring layer 102. The first metal wiring layer 101 and the second metal wiring layer 102 both extend from the back surface of the substrate 10 into the substrate 10. The first metal wiring layer 101 contacts the first conductive path 20, and the second metal wiring layer 102 contacts the second conductive path 30. The back surface is the surface opposite to the first surface. Optionally, the first metal wiring layer 101 and the second metal wiring layer 102 may be copper wiring layers.

[0038] Specifically, in a direction perpendicular to the first surface, as shown in FIG. 1 , the first conductive path 20 and the second conductive path 30 may have the same height in the substrate 10 .

[0039] Specifically, the first conductive channel 20 and the second conductive channel 30 may be metal channels. Optionally, the metal materials used as the first conductive channel 20 and the second conductive channel 30 may include but are not limited to a combination of one or more of tungsten (W), copper (Cu), tantalum nitride (TAN), and titanium nitride (TIN).

[0040] Specifically, the random access memory may include multiple memory cells 40. Furthermore, since the memory cells 40 in the random access memory are in contact with the first conductive channels 20, when the random access memory includes multiple memory cells 40, the random access memory also includes multiple first conductive channels 20, and the multiple first conductive channels 20 correspond one-to-one to the multiple memory cells 40. It is understood that the region corresponding to the multiple first conductive channels 20 and the multiple memory cells 40 in the random access memory is the array region, and the region corresponding to the second conductive channels 30 is the logic region, with the array region and the logic region being adjacently disposed.

[0041] Specifically, the material of the first insulating dielectric layer 50 and the material of the barrier layer 60 may include, but are not limited to, any one or more of silicon nitride, silicon oxide, silicon carbonitride, and aluminum oxide, etc. Alternatively, the barrier layer 60 may also be a metal oxide layer.

[0042] In which, when the blocking layer 60 is located on the side of the first insulating dielectric layer 50 away from the storage unit 40, the above-mentioned first insulating dielectric layer 50 in some optional embodiments can be entirely located between the blocking layer 60 and the storage unit 40, as shown in Figure 1; while in other optional embodiments, the above-mentioned first insulating dielectric layer 50, in addition to including the first part located between the blocking layer 60 and the storage unit 40, can also include a second part located between the blocking layer 60 and the substrate 10, and the above-mentioned first part and second part are connected as a whole.

[0043] In some optional embodiments, when the first metal layer 120 is located on the side of the substrate 10 having the storage unit 40 , the first metal layer 120 not only contacts the side of the storage unit 40 away from the substrate 10 , but also contacts the second conductive path 30 .

[0044] Specifically, the first metal layer 120 may be a metal layer. Exemplarily, the material of the first metal layer 120 may include, but is not limited to, one or a combination of multiple metal material layers such as copper, aluminum, tungsten and silver.

[0045] In the above embodiment, since the substrate 10 of the random access memory of the present invention has the first conductive channel 20 and the second conductive channel 30 arranged at intervals, and the first conductive channel 20 and the second conductive channel 30 both extend from the first surface of the substrate 10 into the substrate 10, the first conductive channel 20 and the second conductive channel 30 can be formed using the same mask and through one etching. The memory cell 40 serves as the core unit in the random access memory. The first insulating dielectric layer 50 and the barrier layer 60 not only prevent the memory cell 40 from being damaged, but also the first insulating dielectric layer 50 and the barrier layer 60 can also serve as an isolation layer between the first metal layer 120 and the memory cell 40, so that the first metal layer 120 will not contact the sidewalls of the memory cell 40, thereby further saving the top electrode mask required when forming the first metal layer 120, and further reducing the production cost of the random access memory.

[0046] In some optional embodiments, to improve the etching barrier effect of the barrier layer 60, the barrier layer 60 of the random access memory of the present disclosure may also be made of a metal material, that is, the barrier layer 60 may be a metal layer. For example, the material of the barrier layer 60 may include, but is not limited to, one or more metal materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and tungsten (W).

[0047] In some optional embodiments, when the barrier layer 60 is a metal layer, in order to enable the barrier layer 60 to also shield the external magnetic field, the material of the barrier layer 60 may also include a magnetic material. For example, the magnetic material may be a ferromagnetic material. Further, the ferromagnetic material may include, but is not limited to, one or more combinations of nickel-iron alloy (NiFe), cobalt-iron alloy (CoFe), and vanadium-iron alloy (FeV).

[0048] In addition, in some optional embodiments, in order to enable the barrier layer 60 to also shield the external magnetic field, the barrier layer 60 may be made of a soft magnetic material. Further, the soft magnetic material may include but is not limited to iron-silicon alloys and soft ferrites.

[0049] In some optional embodiments, the random access memory may further include a second insulating dielectric layer (not shown in the figure), which may be located on the side of the blocking layer 60 away from the first insulating dielectric layer 50, so that the blocking layer 60 is located between the first insulating dielectric layer 50 and the second insulating dielectric layer.

[0050] Specifically, the material of the second insulating dielectric layer may include, but is not limited to, silicon nitride and aluminum oxide. It is understood that when the barrier layer 60 of the random access memory is made of a ferromagnetic material, the second insulating dielectric layer is used to prevent the first metal layer 120 of the random access memory from weakening or offsetting the magnetic shielding effect of the ferromagnetic material, thereby preventing the magnetic shielding of the barrier layer 60 from failing.

[0051] In some optional embodiments, as shown in Figure 1, the above-mentioned storage unit 40 has a first projection on the above-mentioned first surface, the above-mentioned first insulating dielectric layer 50 has a second projection on the above-mentioned first surface, and the above-mentioned barrier layer 60 has a third projection on the above-mentioned first surface, and the above-mentioned second projection is located between the above-mentioned first projection and the above-mentioned third projection.

[0052] As can be seen from the above, the first insulating dielectric layer 50 is located only between the barrier layer 60 and the memory cell 40, and the first insulating dielectric layer 50 covers the sidewalls of the memory cell 40, while the barrier layer 60 covers the side of the first insulating dielectric layer 50 away from the memory cell 40. More specifically, in a direction perpendicular to the first surface, the height of the barrier layer 60 is equal to the vertical height between the first surface and the second surface, wherein the first surface is the side surface of the substrate 10 having the memory cell 40, and the second surface is the side surface of the memory cell 40 away from the substrate 10. For example, when the barrier layer 60 of the random access memory of the present disclosure is made of a ferromagnetic material, the barrier layer 60 can block the external magnetic field around the sidewalls of the memory cell 40, and thus the random access memory of this embodiment has a better magnetic shielding effect.

[0053] In some optional implementations, the random access memory is any one of a magnetic random access memory, a phase change random access memory, a variable resistance memory, and a ferroelectric memory.

[0054] Exemplarily, when the random access memory is a magnetic random access memory, the storage unit 40 of the random access memory may be a magnetic tunnel junction, wherein, in some optional embodiments, the magnetic tunnel junction may include a first ferromagnetic layer, a tunneling barrier layer, and a second ferromagnetic layer stacked in sequence, and the second ferromagnetic layer is in contact with the first metal layer 120, and the first ferromagnetic layer is in contact with the first conductive channel 20 in the substrate 10. Optionally, in other embodiments, when the random access memory is a magnetic random access memory, the magnetic tunnel junction in the random access memory may further include an upper electrode layer and a lower electrode layer, wherein the upper electrode layer is located on a side of the second ferromagnetic layer away from the tunneling barrier layer, and the lower electrode layer is located on a side of the first ferromagnetic layer away from the tunneling barrier layer. Furthermore, the materials of the upper electrode layer and the lower electrode layer may include, but are not limited to, one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and tungsten (W).

[0055] According to another aspect of the present disclosure, a method for manufacturing a random access memory is also provided, the manufacturing method comprising: providing a substrate 10, the substrate 10 having a first conductive channel 20 and a second conductive channel 30 spaced apart, and the first conductive channel 20 and the second conductive channel 30 both extending from the first surface of the substrate 10 into the substrate 10, as shown in FIG2 ; forming a memory cell on the first surface so that the memory cell contacts the first conductive channel 20; forming a first insulating dielectric layer on the first surface so that the first insulating dielectric layer covers the sidewalls of the memory cell; forming a barrier layer on a side of the first insulating dielectric layer away from the memory cell; and forming a first metal layer on a side of the substrate 10 having the memory cell so that the first metal layer contacts the side of the memory cell away from the substrate 10.

[0056] Specifically, the substrate 10 may further include a first metal wiring layer 101 and a second metal wiring layer 102 , wherein the first metal wiring layer 101 is connected to the first conductive path 20 , and the second metal wiring layer 102 is connected to the second conductive path 30 .

[0057] Among them, the step of forming the above-mentioned substrate 10 can include first providing a substrate, and then using a mask structure to form a first hole structure and a second hole structure in the substrate, wherein the above-mentioned mask structure has a first hollow area and a second hollow area, the above-mentioned first hollow area corresponds to the first hole structure, and the above-mentioned second hollow area corresponds to the second hole structure, so that the formed first hole structure and the second hole structure both extend from the same surface of the substrate into the substrate, and then the above-mentioned first hole structure and the second hole structure are filled with a conductive material, thereby forming a first conductive channel 20 corresponding to the first hole structure and a second conductive channel 30 corresponding to the second hole structure, and the substrate having the above-mentioned first conductive channel 20 and the second conductive channel 30 is used as the substrate 10 for forming the random access memory of the present disclosure.

[0058] When a random access memory is formed using the above-mentioned manufacturing method disclosed in the present invention, the first conductive channel 20 and the second conductive channel 30 in the substrate 10 only require one mask to be formed, thereby reducing the manufacturing cost. Furthermore, after the memory cell is formed on the first surface of the substrate 10, the first insulating dielectric layer and the barrier layer are sequentially formed on the sidewalls of the memory cell, thereby preventing the memory cell from being damaged. Moreover, the first insulating dielectric layer and the barrier layer can also serve as an isolation layer between the first metal layer and the memory cell, so that the first metal layer will not contact the sidewalls of the memory cell, thereby further saving the top electrode mask required when forming the first metal layer, and further reducing the manufacturing cost of the random access memory.

[0059] The following describes in more detail exemplary embodiments of the method for manufacturing a random access memory according to the present disclosure. However, these exemplary embodiments can be implemented in a variety of different forms and should not be construed as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of this disclosure thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art.

[0060] In some optional embodiments, the step of forming the memory cell 40 may include: first, depositing a multilayer memory film 401 on the first surface, as shown in FIG3 , and then removing the multilayer memory film 401 outside the first conductive channel 20 by photolithography and etching, so that a portion of the first surface and the second conductive channel 30 are exposed. The remaining multilayer memory film 401 covering the first conductive channel 20 forms the memory cell 40, as shown in FIG4 . In some optional embodiments, the corresponding film layers of the multilayer memory film 401 of the memory cell 40 may be a first ferromagnetic layer, a tunneling barrier layer, and a second ferromagnetic layer; in other optional embodiments, the corresponding film layers of the multilayer memory film 401 of the memory cell 40 may be a lower electrode layer, a first ferromagnetic layer, a tunneling barrier layer, a second ferromagnetic layer, and an upper electrode layer.

[0061] In some optional embodiments, the step of forming the memory cell 40 may further include depositing a hard mask layer on a side of the multilayer memory film 401 away from the substrate 10, wherein the hard mask layer covers the multilayer memory film 401. In the process of removing the multilayer memory film 401 outside the first conductive channel 20 by photolithography and etching, the hard mask layer serves as an etching sacrificial layer to prevent the portion of the multilayer memory film 401 in contact with the first conductive channel 20 from being etched. By removing the hard mask layer, the remaining multilayer memory film 401 forms the memory cell 40. Optionally, the material of the hard mask layer may include, but is not limited to, metal tantalum, tantalum nitride, titanium, titanium nitride, silicon oxide, silicon nitride, and combinations thereof.

[0062] In some optional embodiments, the step of forming the above-mentioned first insulating dielectric layer 50 and the above-mentioned barrier layer 60 may include: as shown in Figure 4, depositing a first insulating material layer 501 on one side of the above-mentioned substrate 10 having the above-mentioned first surface, so that the above-mentioned first insulating material layer 501 covers the above-mentioned first surface, the side wall of the above-mentioned storage unit 40 and the second surface, and the above-mentioned second surface is the side surface of the above-mentioned storage unit 40 away from the above-mentioned first surface; as shown in Figure 5, depositing a barrier material layer 601 on the side of the above-mentioned first insulating material layer 501 away from the above-mentioned first surface, so that the above-mentioned barrier material layer 601 covers the above-mentioned first insulating material layer 501; removing the portion of the above-mentioned first insulating material layer 501 located outside the covering side wall and the portion of the above-mentioned barrier material layer 601 located outside the side of the above-mentioned first insulating material layer 501 away from the above-mentioned storage unit 40, so that the remaining above-mentioned first insulating material layer 501 forms the above-mentioned first insulating dielectric layer 50, and the remaining above-mentioned barrier material layer 601 forms the above-mentioned barrier layer 60, and the above-mentioned first insulating dielectric layer 50 is located between the above-mentioned storage unit 40 and the above-mentioned barrier layer 60.

[0063] Among them, in other optional embodiments, in order to prevent the subsequent etching process from damaging the above-mentioned barrier layer 60, after the step of forming the above-mentioned first insulating dielectric layer 50 and the barrier layer 60, a first protective layer 70 can also be formed on the side of the substrate 10 having the first surface, as shown in Figure 6, so that the first protective layer 70 covers the exposed surface of the first surface, the exposed surface of the first insulating dielectric layer 50, the exposed surface of the barrier layer 60 and the second surface, and the second surface is the surface of the storage unit 40 away from the side of the substrate 10.

[0064] It will be appreciated that, since the first insulating material layer 501 and the barrier material layer 601 in this embodiment are deposited sequentially, the barrier material layer 601 covers the first insulating material layer 501. Therefore, when the same etching process is used to remove the portion of the first insulating material layer 501 outside the memory cell 40 and the portion of the barrier material layer 601 located outside the side of the first insulating material layer 501 away from the memory cell 40, in order to retain the portion of the barrier material layer 601 to form the barrier layer 60, the first insulating dielectric layer 50 after etching may include a first portion and a second portion, wherein the first portion is located between the barrier layer 60 and the memory cell 40, and the second portion is located between the barrier layer 60 and the substrate 10. It will be appreciated that, in a direction perpendicular to the first surface, the height of the barrier layer 60 in this embodiment is less than the vertical distance between the first surface and the second surface.

[0065] In other optional embodiments, the steps of forming the above-mentioned first insulating dielectric layer 50 and the above-mentioned barrier layer 60 may include: depositing a first insulating material layer 501 on the above-mentioned first surface, as shown in Figure 4, so that the above-mentioned first insulating material layer 501 covers the above-mentioned first surface, the side wall of the above-mentioned storage unit 40 and the second surface, and the above-mentioned second surface is the side surface of the above-mentioned storage unit 40 away from the above-mentioned first surface; removing at least a portion of the above-mentioned first insulating material layer 501 other than the above-mentioned side wall, so that the above-mentioned second surface and a portion of the above-mentioned first surface are exposed, and the remaining above-mentioned first insulating material layer 501 forms the above-mentioned first insulating dielectric layer 50; depositing a barrier material layer 601 on the side of the above-mentioned first insulating dielectric layer 50 away from the above-mentioned first surface, as shown in Figure 7, so that the above-mentioned barrier material layer 601 covers the exposed second surface, the exposed first surface and the above-mentioned first insulating dielectric layer 50; and using an etching process to remove at least a portion of the above-mentioned barrier material layer 601 other than the above-mentioned first insulating dielectric layer 50, so that the remaining above-mentioned barrier material layer 601 forms the above-mentioned barrier layer 60.

[0066] Among them, in other optional embodiments, in order to prevent the subsequent etching process from damaging the above-mentioned barrier layer 60, after the step of forming the above-mentioned barrier layer 60, a second protective layer 80 can also be formed on the side of the substrate 10 having the first surface, as shown in Figure 8, so that the second protective layer 80 covers the exposed surface of the first surface, the exposed surface of the first insulating dielectric layer 50, the exposed surface of the barrier layer 60 and the second surface, and the second surface is the surface of the storage unit 40 away from the side of the substrate 10.

[0067] It will be appreciated that, because the barrier material layer 601 in this embodiment is deposited after the first insulating dielectric layer 50 is etched to form, the barrier material layer 601 covers the exposed surface of the first surface and the side of the first insulating dielectric layer 50 away from the memory cell 40. Furthermore, after an etching process is used to remove the portion of the barrier material layer 601 located outside the side of the first insulating dielectric layer 50 away from the memory cell 40 and form the barrier layer 60, the first insulating dielectric layer 50 is located only between the memory cell 40 and the barrier layer 60. It will be appreciated that, in a direction perpendicular to the first surface, the height of the barrier layer 60 in this embodiment is equal to the vertical distance between the first surface and the second surface, where the second surface is the surface of the memory cell 40 away from the substrate 10.

[0068] Optionally, after the step of removing the first insulating material layer 501 and / or the blocking material layer 601 by an etching process, the present disclosure can use chemical mechanical polishing to remove excess first insulating material layer 501 and / or blocking material layer 601 located on the second surface to expose the second surface.

[0069] In some optional embodiments, before the step of forming the above-mentioned first metal layer 120, the above-mentioned manufacturing method also includes: forming a second insulating dielectric layer 90 on the side of the above-mentioned barrier layer 60 away from the above-mentioned first insulating dielectric layer 50, so that the above-mentioned barrier layer 60 is located between the above-mentioned first insulating dielectric layer 50 and the above-mentioned second insulating dielectric layer 90.

[0070] Specifically, a second insulating material layer 901 can be deposited on one side of the substrate 10 having a first surface, as shown in Figure 9, and then an etching process is used to remove the portion of the second insulating material layer 901 other than the covering barrier layer 60, so that the remaining portion of the second insulating material layer 901 forms a second insulating dielectric layer 90. At this time, the barrier layer 60 is located between the second insulating dielectric layer 90 and the first insulating dielectric layer 50, thereby avoiding the exposure of the barrier layer 60 located on the side of the first insulating dielectric layer 50 away from the storage unit 40.

[0071] Among them, in other optional embodiments, in order to prevent the subsequent etching process from damaging the above-mentioned second insulating dielectric layer 90, after the step of forming the above-mentioned second insulating dielectric layer 90, a third protective layer 100 can also be formed on the side of the substrate 10 having the first surface, as shown in Figure 10, so that the third protective layer 100 covers the exposed surface of the first surface, the exposed surface of the first insulating dielectric layer 50, the exposed surface of the barrier layer 60, the exposed surface of the second insulating dielectric layer 90 and the second surface, and the second surface is the surface of the storage unit 40 away from the side of the substrate 10.

[0072] Furthermore, after the step of forming the above-mentioned first protective layer 70, the second protective layer 80 or the third protective layer 100, a dielectric film layer 110 can be deposited on the side of the first protective layer 70, the second protective layer 80 or the third protective layer 100 away from the substrate 10, as shown in FIG11, so that the dielectric film layer 110 covers the above-mentioned first protective layer 70, the second protective layer 80 or the third protective layer 100, and then the above-mentioned dielectric film layer 110 and the first protective layer 70 can be removed by photolithography and etching processes to expose at least the second conductive path 30 and the second surface, and then a conductive material is deposited on the side of the substrate 10 having the storage unit 40 to form a first metal layer 120, as shown in FIG12, and the first metal layer 120 can connect the above-mentioned storage unit 40 and The second conductive channel 30; or the dielectric film layer 110 and the second protective layer 80 can be removed by photolithography and etching processes to expose at least the second conductive channel 30 and the second surface, and then a conductive material is deposited on one side of the substrate 10 having the storage unit 40 to form a first metal layer 120, which can connect the above-mentioned storage unit 40 and the second conductive channel 30; or the dielectric film layer 110 and the third protective layer 100 can be removed by photolithography and etching processes to expose at least the second conductive channel 30 and the second surface, and then a conductive material is deposited on one side of the substrate 10 having the storage unit 40 to form a first metal layer 120, which can connect the above-mentioned storage unit 40 and the second conductive channel 30.

[0073] Optionally, in the step of depositing a conductive material to form the first metal layer 120, chemical mechanical polishing may be used to planarize the side of the first metal layer 120 away from the substrate 10. Optionally, the materials of the first protective layer 70, the second protective layer 80, and the third protective layer 100 may include, but are not limited to, one or more of silicon nitride and aluminum oxide.

[0074] From the above description, it can be seen that the above embodiments of the present disclosure achieve the following technical effects:

[0075] A random access memory disclosed herein includes a substrate, a memory cell, a first insulating dielectric layer, a barrier layer, and a first metal layer, wherein the substrate has a first conductive channel and a second conductive channel spaced apart, and both the first conductive channel and the second conductive channel extend from the first surface of the substrate into the substrate. Therefore, the first conductive channel and the second conductive channel can be formed using the same mask and through a single etching process. The memory cell serves as a core unit in the random access memory. The first insulating dielectric layer and the barrier layer not only prevent the memory cell from being damaged, but also serve as an isolation layer between the first metal layer and the memory cell, so that the first metal layer does not contact the sidewalls of the memory cell, thereby further saving the top electrode mask required when forming the first metal layer and further reducing the production cost of the random access memory.

[0076] The foregoing description is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

1. A random access memory, comprising: A substrate having a first conductive channel and a second conductive channel spaced apart from each other, wherein both the first conductive channel and the second conductive channel extend from a first surface of the substrate into the substrate; a storage unit, located on the first surface and in contact with the first conductive path; A first insulating dielectric layer, located on the first surface and covering the sidewalls of the storage unit; A blocking layer, located on a side of the first insulating dielectric layer away from the storage unit; The first metal layer is located on a side of the substrate having the memory unit, and the first metal layer is in contact with a side of the memory unit away from the substrate.

2. The random access memory according to claim 1, wherein: The barrier layer is a metal layer or a metal oxide layer.

3. The random access memory according to claim 2, wherein: The material of the barrier layer at least includes magnetic material.

4. The random access memory according to claim 3, wherein: The random access memory further comprises: The second insulating dielectric layer is located on a side of the blocking layer away from the first insulating dielectric layer, so that the blocking layer is located between the first insulating dielectric layer and the second insulating dielectric layer.

5. The random access memory according to any one of claims 1 to 4, wherein: The storage unit has a first projection on the first surface, the first insulating medium layer has a second projection on the first surface, the barrier layer has a third projection on the first surface, and the second projection is located between the first projection and the third projection.

6. The random access memory according to claim 5, wherein: The random access memory is any one of a magnetic random access memory, a phase change random access memory, a variable resistance memory and a ferroelectric memory.

7. A method for manufacturing a random access memory, wherein: include: A substrate is provided, wherein the substrate has a first conductive path and a second conductive path arranged at intervals, and the The first conductive path and the second conductive path both extend from the first surface of the substrate into the substrate; forming a memory cell on the first surface so that the memory cell contacts the first conductive path; forming a first insulating dielectric layer on the first surface so that the first insulating dielectric layer covers the sidewalls of the memory cell; forming a blocking layer on a side of the first insulating dielectric layer away from the memory cell; A first metal layer is formed on a side of the substrate having the memory cell, so that the first metal layer is in contact with a side of the memory cell away from the substrate.

8. The method according to claim 7, wherein: The steps of forming the first insulating dielectric layer and the barrier layer include: Depositing a first insulating material layer on one side of the substrate having the first surface, so that the first insulating material layer covers the first surface, the sidewall of the storage unit and a second surface, wherein the second surface is a side surface of the storage unit away from the first surface; depositing a barrier material layer on a side of the first insulating material layer away from the first surface, so that the barrier material layer covers the first insulating material layer; The portion of the first insulating material layer outside the sidewall and the portion of the blocking material layer outside the first insulating material layer away from the storage unit are removed, so that the remaining first insulating material layer forms the first insulating dielectric layer, the remaining blocking material layer forms the blocking layer, and the first insulating dielectric layer is located between the storage unit and the blocking layer.

9. The method according to claim 7, wherein: The steps of forming the first insulating dielectric layer and the barrier layer include: Depositing a first insulating material layer on one side of the substrate having the first surface, so that the first insulating material layer covers the first surface, the sidewall of the storage unit and a second surface, wherein the second surface is a side surface of the storage unit away from the first surface; removing at least a portion of the first insulating material layer other than that covering the sidewall, so that the second surface and a portion of the first surface are exposed, and the remaining first insulating material layer forms the first insulating medium layer; Depositing a barrier material layer on a side of the first insulating dielectric layer away from the first surface, so that the barrier material layer covers the exposed second surface, the exposed first surface and the first insulating dielectric layer; An etching process is adopted to remove at least a portion of the barrier material layer covering the first insulating dielectric layer, so that the remaining barrier material layer forms the barrier layer.

10. The production method according to any one of claims 7 to 9, wherein: Before the step of forming the first metal layer, the manufacturing method further includes: A second insulating dielectric layer is formed on a side of the blocking layer away from the first insulating dielectric layer, so that the blocking layer is located between the first insulating dielectric layer and the second insulating dielectric layer.

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