Imaging device, comparator, and imaging method

Abstract

The present invention makes it possible to transfer a charge from a capacitor to a floating diffusion while suppressing a decrease in frame rate.　This imaging device comprises: pixels capable of respectively transferring and holding charges obtained through photoelectric conversion; and an analog-to-digital (AD) conversion unit capable of switching, in a time division manner, AD conversion of pixel signals read from pixels in the same column between different rows. Each pixel may comprise a photoelectric conversion part, a capacitor that holds a charge obtained through photoelectric conversion by the photoelectric conversion part, a first transfer transistor that transfers the charge obtained through the photoelectric conversion by the photoelectric conversion part to the capacitor, a second transfer transistor that transfers the charge held in the capacitor to a floating diffusion, an output transistor that outputs a pixel signal on the basis of the charge transferred to the floating diffusion, and a selection transistor that selects the output of the pixel signal.

Description

Image pickup device, comparator, and image pickup method

[0001] The present technology relates to an imaging device, a comparator, and an imaging method. More particularly, the present technology relates to an imaging device, a comparator, and an imaging method that are capable of transferring photoelectrically converted charges and holding them in pixels.

[0002] In a global shutter, a capacitor that holds the charge transferred from a photoelectric conversion unit is provided in each pixel. For example, an imaging device has been proposed that includes a pixel including a capacitor that holds the charge transferred from the photoelectric conversion unit and a floating diffusion to which the charge is transferred from the capacitor (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2020-21987

[0004] However, in the above-described conventional technology, AD conversion of pixel signals is put on hold for each row during the period in which charges are transferred from the capacitor to the floating diffusion, which may result in a decrease in frame rate.

[0005] This technology was developed in light of these circumstances, and aims to enable charge transfer from a capacitor to a floating diffusion while suppressing a decrease in frame rate.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is an imaging device including a pixel capable of transferring and holding photoelectrically converted electric charges, and an AD converter capable of time-divisionally switching AD (Analog to Digital) conversion of pixel signals read out from pixels in different rows in the same column, thereby achieving an effect of AD-converting pixel signals read out from each of the first pixel and the second pixel without providing a waiting period before AD conversion for the first pixel and the second pixel in the same column.

[0007] In addition, in the first aspect, the pixel may include a photoelectric conversion unit, a capacitor that holds charge photoelectrically converted by the photoelectric conversion unit, a first transfer transistor that transfers the charge photoelectrically converted by the photoelectric conversion unit to the capacitor, a second transfer transistor that transfers the charge held in the capacitor to a floating diffusion, an output transistor that outputs the pixel signal based on the charge transferred to the floating diffusion, and a selection transistor that selects the output of the pixel signal. This provides the effect of configuring a pixel that can transfer and hold charge photoelectrically converted.

[0008] In the first aspect, the AD conversion unit may perform AD conversion on a pixel signal read from a second pixel in a second row in the first column during an AD conversion period that overlaps with a transfer period in which charge held in a capacitor of a first pixel in a first row in a first column is transferred to a floating diffusion, thereby achieving an effect that a pixel signal read from a second pixel in the same column as the first pixel is AD converted during charge transfer in the first pixel.

[0009] In addition, in the first aspect, the pixel circuit may further include a vertical signal line that transmits the pixel signal in a column direction, a first comparator having an input connected to the vertical signal line, and a second comparator having an input connected to the vertical signal line, whereby the use of the two comparators results in an effect of subjecting pixel signals read out from pixels in different rows in the same column to AD conversion in a time-division manner.

[0010] Furthermore, in the first aspect, the first comparator may perform AD conversion of a P-phase of a pixel signal read out from the first pixel after an auto-zero operation of the first comparator, the second comparator may perform AD conversion of a P-phase of a pixel signal read out from the first pixel after the auto-zero operation of the second comparator, the second comparator may perform AD conversion of a P-phase of a pixel signal read out from the second pixel after the auto-zero operation of the second comparator, the first comparator may perform AD conversion of a D-phase of a pixel signal read out from the first pixel after the AD conversion of a P-phase of a pixel signal read out from the second pixel, and the second comparator may perform AD conversion of a D-phase of a pixel signal read out from the second pixel after the AD conversion of a D-phase of a pixel signal read out from the first pixel. This brings about an effect that AD conversions of the P-phase and D-phase of a pixel signal read out from the first pixel are performed after the auto-zero operation of the first comparator, and AD conversions of the P-phase and D-phase of a pixel signal read out from the second pixel are performed after the auto-zero operation of the second comparator.

[0011] In the first aspect, the AD conversion of the second comparator may be suspended during the AD conversion of the first comparator, and the AD conversion of the first comparator may be suspended during the AD conversion of the second comparator, thereby providing an effect that the comparator is activated according to its usage state.

[0012] In addition, in the first aspect, the pixel circuit may further include a vertical signal line that transmits the pixel signal in a column direction, a comparator having an input connected to the vertical signal line, a first switch connected between the input of the comparator and the vertical signal line, and a second switch connected between the input of the comparator and the vertical signal line, thereby achieving an effect that pixel signals read out from pixels in different rows in the same column are AD converted in a time-division manner based on a switching operation of the input of a single comparator.

[0013] In the first aspect, when the first switch is on and the second switch is off, AD conversion of the pixel signal read from the first pixel may be performed by the comparator, and when the first switch is off and the second switch is on, AD conversion of the pixel signal read from the second pixel may be performed by the comparator. This brings about an effect that AD conversion of the pixel signal read from the second pixel is performed during transfer of the charge held in the first pixel, and AD conversion of the pixel signal read from the first pixel is performed during transfer of the charge held in the second pixel.

[0014] In addition, according to a first aspect, the pixel circuit may include a vertical signal line that transmits the pixel signal in a column direction, and a comparator having a first input and a second input connected to the vertical signal line, the comparator including a first transistor, a second transistor, a third transistor that can form a differential pair with each of the first transistor and the second transistor, a fourth transistor that can form a differential pair with each of the first transistor and the second transistor, a first switch connected in series with the first transistor, a second switch connected in series with the second transistor, a third switch connected in series with the third transistor, and a fourth switch connected in series with the fourth transistor. This suppresses the effects of charge injection and feedthrough caused by switching the input of a single comparator, and enables pixel signals read from pixels in different rows in the same column to be AD converted in a time-division manner.

[0015] In addition, in the first aspect, the input / output amplifier may include a first capacitor connected in series to the gate of the first transistor, a second capacitor connected in series to the gate of the second transistor, a third capacitor connected in series to the gate of the third transistor, a fourth capacitor connected in series to the gate of the fourth transistor, a first auto-zero switch connected between the gate of the first transistor and the first switch, a second auto-zero switch connected between the gate of the second transistor and the second switch, a third auto-zero switch connected between the gate and drain of the third transistor, and a fourth auto-zero switch connected between the gate and drain of the fourth transistor. This provides the effect of realizing the auto-zero operation of the comparator while suppressing the effects of charge injection and feedthrough caused by the switching operation of the input of a single comparator from being transmitted to the capacitors.

[0016] Furthermore, in the first aspect, when the first switch and the third switch are on and the second switch and the fourth switch are off, the first auto-zero switch and the third auto-zero switch are on to perform an auto-zero operation, and then the comparator performs AD conversion of a P-phase of a pixel signal read out from the first pixel; when the first switch and the third switch are off and the second switch and the fourth switch are on, the second auto-zero switch and the fourth auto-zero switch are on to perform an auto-zero operation, and then the comparator performs AD conversion of a P-phase of a pixel signal read out from the second pixel; when the first switch and the third switch are on and the second switch and the fourth switch are off, the comparator performs AD conversion of a D-phase of a pixel signal read out from the first pixel; and when the first switch and the third switch are off and the second switch and the fourth switch are on, the comparator performs AD conversion of a D-phase of a pixel signal read out from the second pixel. This brings about the effect that pixel signals read out from pixels in different rows in the same column are AD converted in a time-division manner based on the input switching operation of a single comparator after the auto-zero operation.

[0017] In addition, in the first aspect, the pixel shift register may further include a first P-phase register that holds a P-phase AD conversion result of a pixel signal read from the first pixel, a second P-phase register that holds the P-phase AD conversion result of a pixel signal read from the second pixel, and a CDS processing unit that performs a first CDS (Correlated Double Sampling) process based on the P-phase AD conversion result of the pixel signal read from the first pixel held in the first P-phase register and the D-phase AD conversion result of the pixel signal read from the first pixel output from the AD conversion unit, and performs a second CDS process based on the P-phase AD conversion result of the pixel signal read from the second pixel held in the second P-phase register and the D-phase AD conversion result of the pixel signal read from the second pixel output from the AD conversion unit. This brings about an effect that, in a charge domain global shutter system, CDS processing is realized while AD converting pixel signals read from pixels in different rows in the same column in a time-division manner.

[0018] In the first aspect, the pixels may transfer and hold the photoelectrically converted charges based on a global shutter operation, thereby providing an effect that exposure is started simultaneously for all pixels.

[0019] A second aspect of the present invention is a comparator including a first transistor, a second transistor, a third transistor capable of forming a differential pair with each of the first transistor and the second transistor, a fourth transistor capable of forming a differential pair with each of the first transistor and the second transistor, a first switch connected in series with the first transistor, a second switch connected in series with the second transistor, a third switch connected in series with the third transistor, and a fourth switch connected in series with the fourth transistor, thereby achieving an effect of performing AD conversion on a plurality of signals in a time-division manner while suppressing the effects of charge injection and feedthrough caused by a switching operation of the input of a single comparator.

[0020] In a second aspect, a first capacitor may be connected in series to the gate of the first transistor, a second capacitor may be connected in series to the gate of the second transistor, a third capacitor may be connected in series to the gate of the third transistor, a fourth capacitor may be connected in series to the gate of the fourth transistor, a first auto-zero switch may be connected between the gate of the first transistor and the first switch, a second auto-zero switch may be connected between the gate of the second transistor and the second switch, a third auto-zero switch may be connected between the gate and drain of the third transistor, and a fourth auto-zero switch may be connected between the gate and drain of the fourth transistor. This provides the effect of suppressing the effects of charge injection and feedthrough caused by the switching operation of the input of a single comparator from being transmitted to the capacitors.

[0021] In the second aspect, when the first switch and the third switch are turned on, the second switch and the fourth switch may be turned off, and when the first switch and the third switch are turned off, the second switch and the fourth switch may be turned on. This brings about an effect that a plurality of signals are AD converted in a time-division manner based on a switching operation of the input of a single comparator.

[0022] In the second aspect, when the first switch and the third switch are on, the first auto-zero switch and the third auto-zero switch may be on, and when the second switch and the fourth switch are on, the second auto-zero switch and the fourth auto-zero switch may be on. This brings about an effect that a plurality of signals are AD converted in a time-division manner based on the input switching operation of a single comparator after the auto-zero operation.

[0023] In the second aspect, the gate of the first transistor and the gate of the second transistor may be connected to the same signal line, and the gate of the third transistor and the gate of the fourth transistor may receive the same reference signal, thereby achieving an effect of performing single-slope AD conversion on pixel signals read out from pixels in different rows in the same column in a time-division manner.

[0024] A third aspect of the present invention is an imaging method in which a first pixel in a first row and a first column transfers and holds a photoelectrically converted charge to a capacitor within the first pixel, and a second pixel in a second row and the first column transfers and holds a photoelectrically converted charge to a capacitor within the second pixel, and an AD conversion unit performs AD conversion on a pixel signal read out from the second pixel during an AD conversion period that overlaps with a transfer period in which the charge held in the capacitor of the first pixel is transferred to a floating diffusion. This brings about an effect that a pixel signal read out from a second pixel in the same column as the first pixel is AD converted during the charge transfer in the first pixel.

[0025] 1 is a block diagram showing a configuration example of an imaging device according to a first embodiment. FIG. 1 is a block diagram showing a configuration example of a solid-state imaging device according to the first embodiment. FIG. 2 is a diagram showing a circuit configuration example of a pixel of the solid-state imaging device according to the first embodiment. FIG. 3 is a block diagram showing a schematic configuration example of an AD conversion unit of the solid-state imaging device according to the first embodiment. FIG. 4 is a timing chart showing waveforms of each unit of a pixel during operation of the solid-state imaging device according to the first embodiment. FIG. 5 is a timing chart showing waveforms of vertical signal lines and each unit of a pixel during AD conversion of the solid-state imaging device according to the first embodiment. FIG. 6 is a block diagram showing a configuration example of an AD conversion unit for one column of the solid-state imaging device according to the first embodiment. FIG. 7 is a timing chart showing an operation example of the AD conversion unit for one column of the solid-state imaging device according to the first embodiment. FIG. 8 is a block diagram showing a configuration example of a column signal processing unit of the solid-state imaging device according to the first embodiment. FIG. 9 is a timing chart showing an operation of CDS processing of the solid-state imaging device according to the first embodiment. FIG. 10 is a block diagram showing a configuration example of an AD conversion unit for one column of the solid-state imaging device according to the second embodiment. FIG. 11 is a timing chart showing an operation example of the AD conversion unit for one column of the solid-state imaging device according to the second embodiment. FIG. 12 is a block diagram showing a configuration example of an AD conversion unit for one column of the solid-state imaging device according to the third embodiment. 10 is a timing chart showing an example of operation of an AD conversion unit for one column of a solid-state imaging device according to a third embodiment. FIG. 11 is a block diagram showing an example of the configuration of an AD conversion unit for one column of a solid-state imaging device according to a fourth embodiment. FIG. 12 is a diagram showing an example of the configuration of a comparator for one column of a solid-state imaging device according to a fifth embodiment. FIG. 13 is a diagram showing an example of the circuit configuration of a pixel of a solid-state imaging device according to a sixth embodiment. FIG. 14 is a diagram showing the order in which pixels of a solid-state imaging device according to the sixth embodiment are read out. FIG. 15 is a timing chart showing the operation of a solid-state imaging device according to a seventh embodiment. FIG. 16 is a timing chart showing the operation of a solid-state imaging device according to an eighth embodiment. FIG. 17 is a timing chart showing the operation of a solid-state imaging device according to a ninth embodiment. FIG. 18 is a timing chart showing the operation of a solid-state imaging device according to a tenth embodiment.12. A diagram showing the order of reading out pixels of a solid-state imaging device according to an eleventh embodiment. 13. A timing chart showing the operation of a solid-state imaging device according to an eleventh embodiment. 14. A timing chart showing an example of the operation of an AD conversion unit for one column of a solid-state imaging device according to an eleventh embodiment. 15. A timing chart showing the operation of CDS processing of a solid-state imaging device according to an eleventh embodiment. 16. A perspective view showing an example of stacking of a pixel array unit according to a twelfth embodiment. 17. A block diagram showing a schematic configuration example of a vehicle control system. 18. An explanatory diagram showing an example of the installation position of an imaging unit.

[0026] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described in the following order.1. First Embodiment (an example in which pixel signals read out from pixels in different rows in the same column are AD converted in a time-division manner based on the switching operation of two comparators) 2. Second Embodiment (an example in which pixel signals read out from pixels in different rows in the same column are AD converted in a time-division manner based on the switching operation of two comparators, and an unused comparator is put on standby) 3. Third Embodiment (an example in which pixel signals read out from pixels in different rows in the same column are AD converted in a time-division manner based on the switching operation of the input of a single comparator) 4. Fourth Embodiment (an example in which pixel signals read out from pixels in different rows in the same column are AD converted in a time-division manner based on the switching operation of the input of a single comparator, and a switch for switching the input is built into the comparator) 5. Fifth Embodiment (an example in which pixel signals read out from pixels in different rows in the same column are AD converted in a time-division manner based on the switching operation of the input of a single comparator, and a switch for switching the input is built into the comparator, and the auto-zero operation on the reference signal input side is omitted) 6. 6. Sixth Embodiment (an example in which a charge domain is applied to each pixel of a 4-pixel shared cell) 7. Seventh Embodiment (an example in which the reset period of a 4-pixel shared cell to which a charge domain is applied is made different from the transfer period of charge held in a capacitor) 8. Eighth Embodiment (an example in which the reset period of a 2-pixel shared cell to which a charge domain is applied is made different from the transfer period of charge held in a capacitor) 9. Ninth Embodiment (an example in which the reset period of a 4-pixel shared cell to which a charge domain is applied is made different from the transfer period of charge held in a capacitor and overlaps with the D-phase AD conversion period) 10. Tenth Embodiment (an example in which the reset period of a 2-pixel shared cell to which a charge domain is applied is made different from the transfer period of charge held in a capacitor and overlaps with the D-phase AD conversion period) 11. Eleventh Embodiment (an example in which it is possible to switch between a process of putting AD conversion on hold during the transfer period of charge held in a capacitor in a charge domain and a process of performing AD conversion overlapping with the transfer period of charge held in a capacitor in a charge domain) 12. Twelfth embodiment (an example in which semiconductor chips on which solid-state imaging devices are formed are stacked) 13. Example of application to a moving body.

[0027] 1. First Embodiment FIG. 1 is a block diagram showing an example of the configuration of an imaging device according to a first embodiment.

[0028] In the figure, the imaging device 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, the image processing unit 104, the storage unit 105, the display unit 106, and the operation unit 107 are connected to one another via a bus 108. The imaging device 100 may be used as a standalone device, or may be incorporated into a mobile terminal such as a smartphone, an authentication device, a monitoring device, a vehicle, or a drone.

[0029] The optical system 101 causes light from a subject to be incident on the solid-state imaging device 102, and forms an optical image on the light-receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0030] The solid-state imaging device 102 converts an optical image formed on the light-receiving surface into an electrical signal for each pixel, digitizes the electrical signal, and outputs it. The solid-state imaging device 102 can operate based on a charge domain global shutter system. The solid-state imaging device 102 is, for example, a complementary metal oxide semiconductor (CMOS) image sensor. The CMOS image sensor may be a back-illuminated image sensor or a front-illuminated image sensor. The light received by the solid-state imaging device 102 may be visible light, near infrared light (NIR), short wavelength infrared light (SWIR), ultraviolet light, X-rays, or the like.

[0031] The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on instructions from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, etc. of the solid-state imaging device 102.

[0032] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. The image processing includes, for example, gamma correction, white balance processing, sharpness processing, and tone conversion processing. The image processing unit 104 may include a processor that executes processing based on software.

[0033] The storage unit 105 stores images captured by the solid-state imaging device 102 and stores imaging parameters of the solid-state imaging device 102. The storage unit 105 can also store a program that operates the imaging device 100 based on software. The storage unit 105 may include a read-only memory (ROM), a random access memory (RAM), and a memory card.

[0034] The display unit 106 displays captured images and various information that supports the image capturing operation, etc. The display unit 106 may be a liquid crystal display or an organic EL (Electro Luminescence) display.

[0035] The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100. The operation unit 107 may be configured as a touch panel together with the display unit 106.

[0036] Depending on the configuration of the imaging device 100, some of the above functions may not be present, or conversely, the imaging device 100 may further include functions that are not disclosed.

[0037] FIG. 2 is a block diagram showing an example of the configuration of the solid-state imaging device according to the first embodiment.

[0038] In the figure, the solid-state imaging device 102 includes a pixel array section 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing section 114, a horizontal scanning circuit 115, and a control circuit 116.

[0039] The pixel array unit 111 includes a plurality of pixels PIX. The pixels PIX are arranged in a matrix along the row direction (also referred to as the horizontal direction) and the column direction (also referred to as the vertical direction). Each pixel PIX can transfer and hold photoelectrically converted charges based on a global shutter operation. Each pixel PIX can form a source follower for each column between itself and the column readout circuit 113 when reading out signals. Each pixel PIX is connected to a horizontal drive line HSL for each row and to a vertical signal line VSL for each column. The horizontal drive line HSL drives each pixel PIX for each row when reading out signals from the pixels PIX. The vertical signal line VSL transmits a potential based on a current flowing through the pixel PIX when reading out signals to the column signal processing unit 114 for each column.

[0040] The vertical scanning circuit 112 scans the pixels PIX to be read in the column direction. The vertical scanning circuit 112 may be configured using vertical registers.

[0041] When reading out a signal from each pixel PIX, the column readout circuit 113 can form a source follower for each column between the pixel PIX and the column readout circuit 113 via the vertical signal line VSL. At this time, the column readout circuit 113 can change the potential of the vertical signal line VSL based on the charge held in the pixel PIX.

[0042] The column signal processing unit 114 processes signals transmitted in the column direction from each pixel PIX. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on the signals transmitted in the column direction from each pixel PIX. The column signal processing unit 114 can also perform analog-to-digital (AD) conversion processing based on the signals transmitted in the column direction from each pixel PIX, and output an image pickup signal Gout.

[0043] The column signal processing unit 114 includes a column ADC unit 114A. The column ADC unit 114A can perform AD conversion processing in parallel for each column. At this time, the column ADC unit 114A can perform AD conversion for each column based on the comparison result between the pixel signal read from the pixel PIX and a reference signal. Here, the column ADC unit 114A can switch in a time-division manner between AD conversion of pixel signals read from pixels in different rows in the same column. Note that the column ADC unit 114A is an example of an AD conversion unit as defined in the claims.

[0044] The horizontal scanning circuit 115 scans the pixels PIX to be read in the row direction. The horizontal scanning circuit 115 may be configured using a horizontal register.

[0045] The control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 114.

[0046] 3 is a diagram showing an example of the circuit configuration of a pixel of the solid-state imaging device according to the first embodiment, which shows the configuration of two pixels in the same column but different rows.

[0047] In the figure, each pixel PIX1, PIX2 includes a photodiode PD1, PD2, a floating diffusion FD1, FD2, a capacitor CA1, CA2, and an overflow control transistor 122, 222. Furthermore, each pixel PIX1, PIX2 includes a transfer transistor 123, 124, 223, 224, a reset transistor 125, 225, an output transistor 126, 226, and a selection transistor 127, 227.

[0048] The overflow control transistors 122, 222, the transfer transistors 123, 124, 223, 224, the reset transistors 125, 225, the output transistors 126, 226, and the selection transistors 127, 227 may be MOS (Metal Oxide Semiconductor) transistors. The capacitors CA1, CA2 may be MIM (Metal Insulation Metal) capacitances or junction capacitances formed on a semiconductor substrate.

[0049] Each photodiode PD1, PD2 performs photoelectric conversion and accumulates the photoelectrically converted charge. Each photodiode PD1, PD2 is an example of a photoelectric conversion unit described in the claims. Each capacitor CA1, CA2 holds the charge transferred from each photodiode PD1, PD2. Charge transfer from each photodiode PD1, PD2 to each capacitor CA1, CA2 may be performed simultaneously for all pixels. Each overflow control transistor 122, 222 controls the overflow of charge from each photodiode PD1, PD2.

[0050] Each transfer transistor 123, 223 transfers the charge accumulated in each photodiode PD1, PD2 to each capacitor CA1, CA2. Each transfer transistor 124, 224 transfers the charge held in each capacitor CA1, CA2 to each floating diffusion FD1, FD2. Each reset transistor 125, 225 resets each floating diffusion FD1, FD2. Each output transistor 126, 226 outputs a signal corresponding to the potential of each floating diffusion FD1, FD2. Each selection transistor 127, 227 selects the output of each output transistor 126, 226.

[0051] In pixel PIX1, the output transistor 126 and the selection transistor 127 are connected in series. The cathode of the photodiode PD1 is connected to an overflow potential OFD via an overflow control transistor 122. The cathode of the photodiode PD1 is also connected to a capacitor CA1 via a transfer transistor 123. The capacitor CA1 is also connected to a floating diffusion FD1 via a transfer transistor 124. The floating diffusion FD1 is also connected to a reset voltage VRS via a reset transistor 125. The series circuit of the output transistor 126 and the selection transistor 127 is connected between a power supply voltage VDD and a vertical signal line VSL. The gate of the output transistor 126 is connected to the floating diffusion FD1.

[0052] In pixel PIX2, the output transistor 226 and the selection transistor 227 are connected in series. The cathode of the photodiode PD2 is connected to an overflow potential OFD via an overflow control transistor 222. The cathode of the photodiode PD2 is also connected to a capacitor CA2 via a transfer transistor 223. The capacitor CA2 is also connected to a floating diffusion FD2 via a transfer transistor 224. The floating diffusion FD2 is also connected to a reset voltage VRS via a reset transistor 225. The series circuit of the output transistor 226 and the selection transistor 227 is connected between a power supply voltage VDD and a vertical signal line VSL. The gate of the output transistor 226 is connected to the floating diffusion FD2.

[0053] Overflow control signals OFG1 and OFG2 are applied to the gates of the overflow control transistors 122 and 222. Transfer signals TRX1 and TRX2 are applied to the gates of the transfer transistors 123 and 223. Transfer signals TRG1 and TRG2 are applied to the gates of the transfer transistors 124 and 224. Reset signals RST1 and RST2 are applied to the gates of the reset transistors 125 and 225. Select signals SEL1 and SEL2 are applied to the gates of the select transistors 127 and 227. The overflow control signals OFG1 and OFG2, transfer signals TRX1, TRX2, TRG1 and TRG2, reset signals RST1 and RST2, and select signals SEL1 and SEL2 can be transmitted to the pixels PIX1 and PIX2 via the horizontal drive line HSL in FIG. 2 .

[0054] FIG. 4 is a block diagram showing an example of a schematic configuration of an AD conversion unit of the solid-state imaging device according to the first embodiment.

[0055] In the figure, the column ADC unit 114A of FIG. 2 includes comparators 131-1 to 131-3 and counters 132-1 to 132-3 for each column. Vertical signal lines VSL1 to VSL3 are provided for each column. Each comparator 131-1 to 131-3 compares pixel signals transmitted via the corresponding vertical signal lines VSL1 to VSL3 with a reference signal VRF and outputs the comparison results VO1 to VO3 to the counters 132-1 to 132-3. The reference signal VRF may include a ramp signal. Each comparator 131-1 to 131-3 is capable of switching, in a time-division manner, between AD conversion of pixel signals read from pixels in different rows in the same column. Each comparator 131-1 to 131-3 may include, for each column, a single or multiple comparators that switch between inputting pixel signals read from pixels in different rows in the same column in a time-division manner.

[0056] An auto-zero signal AZ is also input to each of the comparison units 131-1 to 131-3. The auto-zero signal AZ activates an auto-zero operation during an auto-zero period. In the auto-zero operation, a charge that balances the non-inverting input and the inverting input of each of the comparison units 131-1 to 131-3 can be stored in a DC blocking capacitor.

[0057] A clock signal CKL is input to each of the counters 132-1 to 132-3. At this time, each of the counters 132-1 to 132-3 performs a count operation based on the output timing of each of the comparison results VO1 to VO3 output from each of the comparators 131-1 to 131-3. Then, each of the counters 132-1 to 132-3 digitizes the pixel signals transmitted via each of the vertical signal lines VSL1 to VSL3 based on the count values ​​CN1 to CN3 resulting from the count operation.

[0058] 5 is a timing chart showing waveforms at various parts of a pixel during operation of the solid-state imaging device according to the first embodiment. The operation of pixel PIX1 in FIG. 3 is taken as an example in the diagram. Also, "a" in the diagram shows a waveform during charge transmission from photodiode PD1 to capacitor CA1. "b" in the diagram shows a waveform during shuttering of pixel PIX1. "c" in the diagram shows a waveform during readout of a pixel signal from pixel PIX1.

[0059] In the figure, at "a", when charge is transferred from the photodiode PD1 to the capacitor CA1, the selection signal SEL1 is set to a low level, turning off the selection transistor 127. Then, the transfer signal TRG1 and the reset signal RST1 rise (t1), turning on the transfer transistor 124 and the reset transistor 125, thereby resetting the capacitor CA1 and the floating diffusion FD1.

[0060] Next, the transfer signal TRG1 and the reset signal RST1 fall sequentially, and then the transfer signal TRX1 rises (t2). At this time, the transfer transistor 123 turns on while the transfer transistor 124 and the reset transistor 125 are off, and the charge accumulated in the photodiode PD1 is transferred to the capacitor CA1. Then, after the transfer signal TRX1 falls, the overflow control signal OFG1 rises (t3).

[0061] At b in the figure, during shuttering, the transfer signals TRX1, TRG1, reset signal RST1, and selection signal SEL1 are set to low level. Then, the overflow control signal OFG1 falls (t4), turning off the overflow control transistor 122. This shuttering operation can be performed simultaneously for all pixels, including pixel PIX1, and exposure can be started simultaneously for all pixels.

[0062] At c in the figure, in reading out pixel signals, the overflow control signal OFG1 is set to a high level, the transfer signal TRX1 is set to a low level, the overflow control transistor 122 is turned on, and the selection transistor 127 is turned off. Then, the reset signal RST1 and the selection signal SEL1 rise (t5), turning on the reset transistor 125 and the selection transistor 127. At this time, the floating diffusion FD1 is reset, and the P-phase level of the floating diffusion FD1 is transmitted via the vertical signal line VSL.

[0063] Next, the reset signal RST1 falls, and the transfer signal TRG1 rises while the reset transistor 125 is turned off, turning on the transfer transistor 124 (t6). At this time, the charge held in the capacitor CA1 is transferred to the floating diffusion FD1, and the D-phase level of the floating diffusion FD1 is transmitted via the vertical signal line VSL.

[0064] 6 is a timing chart showing waveforms of the vertical signal lines and the respective parts of the pixels during AD conversion in the solid-state imaging device according to the first embodiment. Note that the same figure shows waveforms of the respective parts of the pixels PIX1 and PIX2 in FIG. 3 and the waveform of the vertical signal line VSL during AD conversion.

[0065] In the figure, in this solid-state imaging device, a P-phase settling period PS2 and a P-phase AD conversion period PA2 of pixel PIX2 are set to overlap with a charge transfer period K1 from capacitor CA1 of pixel PIX1 to floating diffusion FD1. Also, a P-phase settling period PS1 and a P-phase AD conversion period PA1 of pixel PIX1 are set to overlap with a charge transfer period K2 from capacitor CA2 of pixel PIX2 to floating diffusion FD2.

[0066] Specifically, the transfer signals TRX1 and TRX2 are always set to a low level. After the selection signal SEL1 rises, the reset signal RST1 rises (t11), and the potential of the vertical signal line VSL is set according to the P-phase level of the floating diffusion FD1. After the reset signal RST1 falls and P-phase settling of the pixel PIX1 is performed (PS1), P-phase AD conversion is performed (PA1).

[0067] Next, the selection signal SEL1 falls and the selection signal SEL2 rises (t12).

[0068] Next, the reset signal RST2 rises (t13), and the potential of the vertical signal line VSL is set according to the P-phase level of the floating diffusion FD2. Then, the reset signal RST2 falls, and after P-phase settling of the pixel PIX2 is performed (PS2), P-phase AD conversion is performed (PA2).

[0069] Furthermore, the transfer signal TRG1 rises at the falling timing of the reset signal RST2, and after the charge accumulated in the photodiode PD1 is transferred to the capacitor CA1, the transfer signal TRG1 falls.

[0070] Next, the selection signal SEL1 rises and the selection signal SEL2 falls (t14), and the potential of the vertical signal line VSL is set according to the D-phase level of the floating diffusion FD1. After D-phase settling of the pixel PIX1 is performed (DS1), D-phase AD conversion is performed (DA1).

[0071] Next, the reset signal RST1 rises (t15), and the potential of the vertical signal line VSL is set according to the P-phase level of the floating diffusion FD1. Then, the reset signal RST1 falls, and P-phase settling of the pixel PIX1 is performed (PS1), and then P-phase AD conversion is performed (PA1).

[0072] Furthermore, the transfer signal TRG2 rises at the falling timing of the reset signal RST1, and after the charge accumulated in the photodiode PD2 is transferred to the capacitor CA2, the transfer signal TRG2 falls.

[0073] Next, the selection signal SEL1 falls and the selection signal SEL2 rises (t16), and the potential of the vertical signal line VSL is set according to the D-phase level of the floating diffusion FD2. After D-phase settling of the pixel PIX2 is performed (DS2), D-phase AD conversion is performed (DA2).

[0074] FIG. 7 is a block diagram showing an example of the configuration of an AD conversion unit for one column of the solid-state imaging device according to the first embodiment.

[0075] In the figure, the column ADC unit 114A includes comparators CM1 and CM2, a selector SEC, and a counter CNT. The inverting input terminals of the comparators CM1 and CM2 are connected to the vertical signal line VSL via capacitors C1A and C2A, respectively. The non-inverting input terminals of the comparators CM1 and CM2 receive a reference signal VRF via capacitors C1B and C2B, respectively. An auto-zero switch SW1A is connected between the gate and drain of the differential transistor on the inverting input side of the comparator CM1. An auto-zero switch SW1B is connected between the gate and drain of the differential transistor on the non-inverting input side of the comparator CM1. An auto-zero switch SW2A is connected between the gate and drain of the differential transistor on the inverting input side of the comparator CM2. An auto-zero switch SW2B is connected between the gate and drain of the differential transistor on the non-inverting input side of the comparator CM2. The outputs of the comparators CM1 and CM2 are input to a counter CNT. The vertical signal line VSL is grounded via a current source 151.

[0076] The selector SEC switches between the outputs of the comparators CM1 and CM2 and inputs them to the counter CNT. The counter CNT performs a counting operation based on the output timing of each comparison result output from the comparators CM1 and CM2. At this time, the counter CNT digitizes the pixel signal transmitted via the vertical signal line VSL based on the count value CN resulting from the counting operation.

[0077] FIG. 8 is a timing chart showing an example of the operation of the AD conversion unit for one column of the solid-state imaging device according to the first embodiment.

[0078] In the figure, the selector SEC switches the outputs of the comparators CM1 and CM2 in accordance with the readout timing of the pixels PIX1 and PIX2. Here, when the comparator CM1 is selected, the auto-zero switches SW1A and SW1B are turned on, thereby setting the auto-zero period AZ1 of the comparator CM1. At this time, the P-phase settling period PS1 is set during the auto-zero period AZ1. When the comparator CM2 is selected, the auto-zero switches SW2A and SW2B are turned on, thereby setting the auto-zero period AZ2 of the comparator CM2. At this time, the P-phase settling period PS2 is set during the auto-zero period AZ2.

[0079] The current P-phase AD conversion period PA1 and D-phase AD conversion period DA1 are set between the current auto-zero period AZ1 and the next auto-zero period AZ1. Comparator CM1 is in use during period AK1, from the current P-phase AD conversion period PA1 to the D-phase AD conversion period DA1. The current P-phase AD conversion period PA2 and D-phase AD conversion period DA2 are set between the current auto-zero period AZ2 and the next auto-zero period AZ2. Comparator CM2 is in use during period AK2, from the current P-phase AD conversion period PA2 to the D-phase AD conversion period DA2. For this reason, the period in which comparator CM1 is in use may overlap with the period in which comparator CM2 is in use.

[0080] FIG. 9 is a block diagram showing an example of the configuration of a column signal processing unit of the solid-state imaging device according to the first embodiment.

[0081] In the figure, the column signal processing unit 114 of FIG. 2 includes a counter unit CNB, P-phase registers 161 and 162, a CDS processing unit 163, and an output register 164.

[0082] The counter unit CNB includes a counter CNT for each column, as shown in Fig. 7. The comparison results VO of the comparators CM1 and CM2 are input to the counter unit CNB for each column.

[0083] The P-phase register 161 stores the P-phase AD conversion result PN1 of the pixel PIX1. The P-phase register 162 stores the P-phase AD conversion result PN2 of the pixel PIX2. Each of the P-phase registers 161 and 162 may be a line memory.

[0084] The CDS processing unit 163 reads the P-phase AD conversion result PN1 of pixel PIX1 from the P-phase register 161 based on the output timing of the D-phase AD conversion result DN1 of pixel PIX1 from the counter unit CNB. The CDS processing unit 163 then performs CDS processing based on the P-phase AD conversion result PN1 and the D-phase AD conversion result DN1. The CDS processing unit 163 also reads the P-phase AD conversion result PN2 of pixel PIX2 from the P-phase register 162 based on the output timing of the D-phase AD conversion result DN2 of pixel PIX2 from the counter unit CNB. The CDS processing unit 163 then performs CDS processing based on the P-phase AD conversion result PN2 and the D-phase AD conversion result DN2.

[0085] The output register 164 stores the CDS processing results CS1 and CS2 of the pixels PIX1 and PIX2 calculated by the CDS processing unit 163, and outputs them at a predetermined timing.

[0086] FIG. 10 is a timing chart showing the operation of the CDS process of the solid-state imaging device according to the first embodiment.

[0087] In the figure, a P-phase count period CT1 is provided during a P-phase AD conversion period PA1 of pixel PIX1. A P-phase count period CT2 is provided during a P-phase AD conversion period PA2 of pixel PIX2. A D-phase count period CT3 is provided during a D-phase AD conversion period DA1 of pixel PIX1. A D-phase count period CT4 is provided during a D-phase AD conversion period DA2 of pixel PIX2.

[0088] After the P-phase count period CT1 of pixel PIX1 is completed, the P-phase AD conversion result PN1 is stored in the P-phase register 161 (ST1). After the P-phase count period CT2 of pixel PIX2 is completed, the P-phase AD conversion result PN2 is stored in the P-phase register 162 (ST2).

[0089] After the D-phase count period CT3 for pixel PIX1 is completed, CDS calculation is performed, and the CDS processing result CS1 is stored in the output register 164 (ST3). After the D-phase count period CT4 for pixel PIX2 is completed, CDS calculation is performed, and the CDS processing result CS2 is stored in the output register 164 (ST4). At this time, a readout period RD1 for the CDS processing result CS1 for pixel PIX1 is set between the storage timing ST3 for the CDS processing result CS1 and the storage timing ST4 for the CDS processing result CS2.

[0090] As described above, in the first embodiment, pixel signals read from pixels in different rows in the same column are AD converted in a time-division manner based on the switching operation of the two comparators CM1 and CM2. This allows the pixel signals read from each of the pixels PIX1 and PIX2 in the same column to be AD converted without providing a waiting period before AD conversion for each of the pixels PIX1 and PIX2. Therefore, in the charge domain global shutter system, the frame rate can be improved without changing the configuration of each of the pixels PIX1 and PIX2.

[0091] 2. Second Embodiment In the first embodiment described above, pixel signals read from pixels in different rows in the same column are AD converted in a time-division manner based on the switching operation of two comparators CM1 and CM2. In this second embodiment, pixel signals read from pixels in different rows in the same column are AD converted in a time-division manner based on the switching operation of two comparators, and an unused comparator is put on standby.

[0092] FIG. 11 is a block diagram showing an example of the configuration of an AD conversion unit for one column of a solid-state imaging device according to the second embodiment.

[0093] In the figure, this solid-state imaging device includes comparators CM1' and CM2' instead of the comparators CM1 and CM2 of the first embodiment. Other configurations of the solid-state imaging device of the second embodiment are the same as those of the solid-state imaging device of the first embodiment.

[0094] Enable signals EN1 and EN2 are input to the comparators CM1' and CM2', respectively. The comparators CM1' and CM2' are activated based on the enable signals EN1 and EN2. Other configurations of the comparators CM1' and CM2' in the second embodiment are similar to the configurations of the comparators CM1 and CM2 in the first embodiment described above.

[0095] FIG. 12 is a timing chart showing an example of the operation of the AD conversion unit for one column of the solid-state imaging device according to the second embodiment.

[0096] In the figure, during the P-phase settling period PS1 and P-phase AD conversion period PA1 of pixel PIX1, enable signal EN1 is set to high level and enable signal EN2 is set to low level. When enable signal EN1 is at high level, comparator CM1' is selected by selector SEC. At this time, comparator CM1' is activated, enabling AD conversion, and comparator CM2' is deactivated, causing a transition to waiting period WA2.

[0097] On the other hand, during the P-phase settling period PS2 and the P-phase AD conversion period PA2 of pixel PIX2, the enable signal EN1 is set to low level and the enable signal EN2 is set to high level. When the enable signal EN2 is at high level, the comparator CM2' is selected by the selector SEC. At this time, the comparator CM1' is deactivated, and the process shifts to the waiting period WA1, while the comparator CM2' is activated, enabling AD conversion.

[0098] As described above, in the second embodiment, pixel signals read from pixels in different rows in the same column are AD converted in a time-division manner based on the switching operation of the two comparators CM1' and CM2', and the unused comparators CM1' and CM2' are put into standby. This makes it unnecessary to use the comparators CM1' and CM2' in an overlapping manner. Therefore, it is possible to reduce the power consumption of the comparators CM1' and CM2' while AD converting pixel signals read from pixels in different rows in the same column in a time-division manner based on the switching operation of the two comparators CM1' and CM2'.

[0099] 3. Third Embodiment In the first embodiment described above, pixel signals read from pixels in different rows in the same column are AD converted in a time-division manner based on the switching operation of two comparators CM1 and CM2. In this third embodiment, pixel signals read from pixels in different rows in the same column are AD converted in a time-division manner based on the switching operation of the input of a single comparator.

[0100] FIG. 13 is a block diagram showing an example of the configuration of an AD conversion unit for one column of a solid-state imaging device according to the third embodiment.

[0101] In the figure, this solid-state imaging device includes a comparator CM and switches SW11A, SW11B, SW12A, and SW12B instead of the comparators CM1 and CM2 of the first embodiment. Other configurations of the solid-state imaging device of the third embodiment are similar to those of the solid-state imaging device of the first embodiment.

[0102] The switches SW11A and SW12A can switch the input of the pixel signals of the pixels PIX1 and PIX2 transmitted via the same vertical signal line VSL to the comparator CM. The switches SW11B and SW12B can switch the capacitors C1B and C2B used to input the reference signal VRF in accordance with the switching of the input of the pixel signals of the pixels PIX1 and PIX2 to the comparator CM.

[0103] The switch SW11A is connected between the inverting input terminal of the comparator CM and the capacitor C1A. The switch SW12A is connected between the inverting input terminal of the comparator CM and the capacitor C2A. The switch SW11B is connected between the non-inverting input terminal of the comparator CM and the capacitor C1B. The switch SW12B is connected between the non-inverting input terminal of the comparator CM and the capacitor C2B. The output of the comparator CM is input to the counter CNT.

[0104] FIG. 14 is a timing chart showing an example of the operation of the AD conversion unit for one column of the solid-state imaging device according to the third embodiment.

[0105] In the figure, during a P-phase settling period PS1 and a P-phase AD conversion period PA1 of pixel PIX1, switches SW11A and SW11B are on and switches SW12A and SW12B are off. At this time, the pixel signal of pixel PIX1 is input to comparator CM. Furthermore, by turning on the auto-zero switches SW1A and SW1B during the P-phase settling period PS1, charge is accumulated in capacitors C1A and C1B so that the inverting input and non-inverting input of comparator CM are balanced.

[0106] During the P-phase settling period PS2 and the P-phase AD conversion period PA2 of pixel PIX2, the switches SW11A and SW11B are turned off and the switches SW12A and SW12B are turned on. At this time, the pixel signal of pixel PIX2 is input to the comparator CM. Furthermore, by turning on the auto-zero switches SW2A and SW2B during the P-phase settling period PS2, charge is accumulated in the capacitors C2A and C2B so that the inverting input and non-inverting input of the comparator CM are balanced.

[0107] In this way, in the third embodiment described above, pixel signals read from pixels in different rows in the same column are AD converted in a time-division manner based on the input switching operation of a single comparator CM, which makes it possible to suppress an increase in the circuit size of the AD conversion unit and eliminate the need for a waiting period before AD conversion for each of the pixels PIX1 and PIX2 in the same column.

[0108] 4. Fourth Embodiment In the above-described third embodiment, pixel signals read from pixels in different rows in the same column are AD converted in a time-division manner based on the input switching operation of a single comparator CM. In this fourth embodiment, pixel signals read from pixels in different rows in the same column are AD converted in a time-division manner based on the input switching operation of a single comparator, and a switch for switching the input is built into the comparator.

[0109] FIG. 15 is a block diagram showing an example of the configuration of an AD conversion unit for one column of a solid-state imaging device according to the fourth embodiment.

[0110] In the figure, this solid-state imaging device includes a comparator CM' instead of the comparator CM of the third embodiment. The comparator CM' incorporates the switches SW11A, SW11B, SW12A, and SW12B of the third embodiment. In this case, the comparator CM' is provided with inverting input terminals corresponding to the switches SW11A and SW11B, and with non-inverting input terminals corresponding to the switches SW12A and SW12B. The remaining configuration of the solid-state imaging device of the fourth embodiment is the same as that of the solid-state imaging device of the third embodiment. The comparator CM' can operate at the same timing as the comparator CM of the third embodiment.

[0111] FIG. 16 is a diagram showing an example of the configuration of a comparator for one column of a solid-state imaging device according to the fourth embodiment.

[0112] In the figure, the comparator CM' includes a differential amplifier 201 and a post-amplifier 202. The post-amplifier 202 is connected to the post-stage of the differential amplifier 201. The post-amplifier 202 may be a multi-stage amplifier.

[0113] The differential amplifier 201 includes P-channel field effect transistors M0A and M0B, N-channel field effect transistors M1A, M1B, M2A, and M2B, switches SW11A, SW11B, SW12A, and SW12B, and a current source 211.

[0114] The P-channel field-effect transistor M0A can form a differential pair with each of the N-channel field-effect transistors M1A and M2A. The P-channel field-effect transistor M0B can form a differential pair with each of the N-channel field-effect transistors M1B and M2B. The P-channel field-effect transistors M0A and M0B can form a current mirror.

[0115] The source of each of the P-channel field effect transistors M0A and M0B is connected to the power supply potential VDD, and the gate of each of the P-channel field effect transistors M0A and M0B is connected to the drain of the P-channel field effect transistor M0B.

[0116] A switch SW11A is connected between the drain of the P-channel field effect transistor M0A and the drain of the N-channel field effect transistor M1A. A switch SW12A is connected between the drain of the P-channel field effect transistor M0A and the drain of the N-channel field effect transistor M2A. A switch SW11B is connected between the drain of the P-channel field effect transistor M0B and the drain of the N-channel field effect transistor M1B. A switch SW12B is connected between the drain of the P-channel field effect transistor M0B and the drain of the N-channel field effect transistor M2B. The sources of the N-channel field effect transistors M1A, M2A, M1B, and M2B are grounded via a current source 211.

[0117] An auto-zero switch SW1A is connected between the drain of the P-channel field-effect transistor M0A and the gate of the N-channel field-effect transistor M1A. An auto-zero switch SW2A is connected between the drain of the P-channel field-effect transistor M0A and the gate of the N-channel field-effect transistor M2A. An auto-zero switch SW1B is connected between the drain of the P-channel field-effect transistor M0B and the gate of the N-channel field-effect transistor M1B. An auto-zero switch SW2B is connected between the drain of the P-channel field-effect transistor M0B and the gate of the N-channel field-effect transistor M2B.

[0118] A capacitor C1A is connected between the vertical signal line VSL and the gate of the N-channel field effect transistor M1A. A capacitor C2A is connected between the vertical signal line VSL and the gate of the N-channel field effect transistor M2A. A reference signal VRF is input to the gate of the N-channel field effect transistor M1B via a capacitor C1B. A reference signal VRF is input to the gate of the N-channel field effect transistor M2B via a capacitor C2B.

[0119] As described above, in the fourth embodiment, pixel signals read from pixels in different rows but in the same column are AD converted in a time-division manner based on the input switching operation of a single comparator CM'. At this time, switches SW11A, SW11B, SW12A, and SW12B for switching the input are built into the comparator CM'. This makes it possible to AD convert pixel signals read from pixels PIX1 and PIX2 in different rows but in the same column in a time-division manner while suppressing the effects of charge injection and feedthrough caused by the input switching operation of the single comparator CM' from being transmitted to capacitors C1A, C1B, C2A, and C2B.

[0120] In addition to AD conversion of pixel signals, the comparator CM' may also be used for AD conversion of analog signals such as audio signals, temperature, pressure, flow velocity, wind speed, and vehicle speed. Alternatively, the comparator CM' may be used to compare a signal other than the signal used for AD conversion with a threshold value.

[0121] 5. Fifth Embodiment In the above-described fourth embodiment, the switches SW11A, SW11B, SW12A, and SW12B for switching inputs are built into the comparator CM'. In this fifth embodiment, the switches SW11A and SW11B for switching inputs are built into the comparator, and the auto-zero operation on the input side of the reference signal VRF is omitted.

[0122] FIG. 17 is a diagram showing an example of the configuration of a comparator for one column of a solid-state imaging device according to the fifth embodiment.

[0123] In the figure, this solid-state imaging device includes a differential amplifier 301 instead of the differential amplifier 201 of the fourth embodiment. Furthermore, this solid-state imaging device does not include the auto-zero switches SW1B and SW2B and the capacitors C1B and C2B of the fourth embodiment. Other configurations of the solid-state imaging device of the fifth embodiment are the same as those of the solid-state imaging device of the fourth embodiment.

[0124] The differential amplifier 301 is the same as the differential amplifier 201 of the fourth embodiment except that the N-channel field-effect transistor M2B and the switches SW11B and SW12B are removed. In this case, the drain of the N-channel field-effect transistor M1B is connected to the drain of the P-channel field-effect transistor M0B. The remaining configuration of the differential amplifier 301 of the fifth embodiment is the same as the configuration of the differential amplifier 201 of the fourth embodiment.

[0125] In the differential amplifier 301, the switching of the auto-zero switches SW1A and SW2A and the switches SW11A and SW12A is similar to the switching of the differential amplifier 201 in the above-described fourth embodiment. At this time, in the differential amplifier 301, the auto-zero operation is performed on the input side of the pixel signal via the vertical signal line VSL, and the auto-zero operation is omitted on the input side of the reference signal VRF. For this reason, it is desirable that the auto-zero potential depends on the potential of the reference signal VRF, and that the absolute value precision of the potential of the reference signal VRF be ensured.

[0126] As described above, in the fifth embodiment, the switches SW11A and SW11B for switching inputs are built into the comparator, and the auto-zero operation on the input side of the reference signal VRF is omitted. This eliminates the need for the auto-zero switches SW1B and SW2B, the switches SW11B and SW12B, and the capacitors C1B and C2B on the input side of the reference signal VRF. This prevents an increase in the circuit size of the AD conversion unit and suppresses the effects of charge injection and feedthrough caused by the input switching operation of a single comparator.

[0127] 6. Sixth Embodiment In the first embodiment described above, pixel signals read out from pixels in different rows but in the same column for pixels to which a charge domain is applied are AD converted in a time-division manner. In this sixth embodiment, pixel signals read out from pixels in different rows but in the same column for a four-pixel shared cell to which a charge domain is applied are AD converted in a time-division manner.

[0128] FIG. 18 is a diagram showing an example of a circuit configuration of a pixel of a solid-state imaging device according to the sixth embodiment.

[0129] In the figure, this solid-state imaging device includes a four-pixel shared cell CEL instead of the pixel PIX of the first embodiment. Other configurations of the solid-state imaging device of the sixth embodiment are the same as those of the solid-state imaging device of the first embodiment.

[0130] The four-pixel shared cell CEL adds to the pixel PIX1 of the first embodiment photodiodes PD2 to PD4, capacitors CA2 to CA4, transfer transistors 223, 224, 323, 324, 423, and 424, and overflow control transistors 222 to 422. The connection relationships of the photodiodes PD2 to PD4, the capacitors CA2 to CA4, the transfer transistors 223, 224, 323, 324, 423, and 424, and the overflow control transistors 222 to 422 are the same as the connection relationships of the photodiode PD1, capacitor CA1, transfer transistors 123 and 124, and overflow control transistor 122.

[0131] In this case, the four photodiodes PD1 to PD4 and the four capacitors CA1 to CA4 share the floating diffusion FD1, reset transistor 125, output transistor 126, and selection transistor 127. A reset signal RST is applied to the gate of the reset transistor 125, and a selection signal SEL is applied to the gate of the selection transistor 127. In the four-pixel sharing cell CEL, pixels can be arranged in a 2x2 array. In this case, colorization can be implemented in the four-pixel sharing cell CEL based on the Bayer arrangement.

[0132] FIG. 19 is a diagram showing the pixel readout order of the solid-state imaging device according to the sixth embodiment.

[0133] In the figure, the four-pixel shared cells CEL are arranged in a matrix along the row and column directions. In this case, assuming that vertical signal lines VSL1 to VSLn (n is an even number) are arranged in each column, adjacent four-pixel shared cells CEL in the column direction are connected to different vertical signal lines VSL1 to VSLn. In this case, every other four-pixel shared cell CEL in the same column is connected to the same vertical signal line VSL1 to VSLn. For example, of four-pixel shared cells CEL1 to CEL4 arranged adjacently in the same column, four-pixel shared cells CEL1 and CEL3 are connected to the direct signal line VSL1, and four-pixel shared cells CEL2 and CEL4 are connected to the direct signal line VSL2.

[0134] When reading from the four-pixel sharing cell CEL, for example, pixel signals can be read alternately from each pixel of the four-pixel sharing cells CEL1 and CEL3 while simultaneously reading pixel signals alternately from each pixel of the four-pixel sharing cells CEL2 and CEL4. At this time, pixel signals are read from each pixel of the four-pixel sharing cell while straddling two four-pixel sharing cells adjacent in the column direction. For example, pixel signals are read from each pixel of the four-pixel sharing cells CEL1 to CEL4 in the order of 1 → 2 → 3 → 4 → 5 → 6 → 7 → 8, traveling back and forth in the column direction between the four-pixel sharing cells CEL1 and CEL3 and between the four-pixel sharing cells CEL2 and CEL4.

[0135] 20 is a timing chart showing the operation of the solid-state imaging device according to the sixth embodiment, where R indicates a reset period, PS indicates a P-phase settling period, PA indicates a P-phase AD conversion period, K indicates a transfer period from the capacitor to the floating diffusion, DS indicates a D-phase settling period, and DA indicates a D-phase AD conversion period.

[0136] In the figure, in the first readout period PX1, P-phase pixel signals and D-phase pixel signals are sequentially read out from the first pixel of each of the 4-pixel sharing cells CEL1 and CEL2, and sequentially transmitted via each of the vertical signal lines VSL1 and VSL2.

[0137] In the second readout period PX2, the P-phase pixel signals and the D-phase pixel signals are sequentially read out from the first pixel of each of the four-pixel sharing cells CEL3 and CEL4 and sequentially transmitted via the vertical signal lines VSL1 and VSL2. At this time, the reset period R, the P-phase settling period PS, and the P-phase AD conversion period PA for the first pixel of each of the four-pixel sharing cells CEL3 and CEL4 overlap with the transfer period K for the first pixel of each of the four-pixel sharing cells CEL1 and CEL2.

[0138] In the third readout period PX3, P-phase pixel signals and D-phase pixel signals are sequentially read out from the second pixel of each of the four-pixel sharing cells CEL1 and CEL2 and sequentially transmitted via the vertical signal lines VSL1 and VSL2. At this time, the reset period R, P-phase settling period PS, and P-phase AD conversion period PA for the second pixel of each of the four-pixel sharing cells CEL1 and CEL2 overlap with the transfer period K for the first pixel of each of the four-pixel sharing cells CEL3 and CEL4.

[0139] In the fourth readout period PX4, P-phase pixel signals and D-phase pixel signals are sequentially read out from the second pixel of each of the four-pixel sharing cells CEL3 and CEL4 and sequentially transmitted via the vertical signal lines VSL1 and VSL2. At this time, the reset period R, P-phase settling period PS, and P-phase AD conversion period PA for the second pixel of each of the four-pixel sharing cells CEL3 and CEL4 overlap with the transfer period K for the second pixel of each of the four-pixel sharing cells CEL1 and CEL2.

[0140] In the fifth readout period PX5, the P-phase pixel signal and the D-phase pixel signal are sequentially read out from the third pixel of each of the four-pixel sharing cells CEL1 and CEL2 and sequentially transmitted via the vertical signal lines VSL1 and VSL2. At this time, the reset period R, the P-phase settling period PS, and the P-phase AD conversion period PA for the third pixel of each of the four-pixel sharing cells CEL1 and CEL2 overlap with the transfer period K for the second pixel of each of the four-pixel sharing cells CEL3 and CEL4.

[0141] In this case, under the condition that the total time of the reset period R, P-phase settling period PS, and P-phase AD conversion period PA is equal to the time of the transfer period K, a speed increase of 1.67 times can be achieved compared to when the reset period R, P-phase settling period PS, and P-phase AD conversion period PA are waited for during the transfer period K. However, in the sixth embodiment, rows in the transfer mode and rows in the P-phase mode exist at the same time. For this reason, control is required to operate one row in the P-phase mode at the same time as operating another row in the transfer mode.

[0142] In this way, in the sixth embodiment described above, for a four-pixel shared cell to which a charge domain is applied, pixel signals read from pixels in different rows in the same column are AD converted in a time-division manner, thereby making it possible to suppress an increase in the size of pixels to which a charge domain is applied and to eliminate the need for a waiting period before AD conversion for pixels in different rows in the same column.

[0143] 7. Seventh Embodiment In the sixth embodiment described above, the reset period R, P-phase settling period PS, and P-phase AD conversion period PA of the four-pixel shared cells CEL in different rows in the same column are overlapped with the transfer period K. In this seventh embodiment, the reset period R of the four-pixel shared cells CEL in different rows in the same column is prevented from overlapping with the transfer period K.

[0144] FIG. 21 is a timing chart showing the operation of the solid-state imaging device according to the seventh embodiment.

[0145] In the figure, the configuration and readout order of the four-pixel shared cell CEL of the seventh embodiment are the same as those of the four-pixel shared cell CEL of the sixth embodiment. However, in the seventh embodiment, the P-phase settling period PS and the P-phase AD conversion period PA of the four-pixel shared cells CEL in different rows in the same column overlap with the transfer period K, but the reset period R does not overlap with the transfer period K. In this case, by individually controlling the selection signal SEL for each row, it is not necessary to prepare a P-phase mode and a D-phase mode. Furthermore, since rows in reset mode and rows in transfer mode do not exist at the same time, they can be treated as a common mode. However, because the reset period R does not overlap with the transfer period K, the time required for the reset period R is added to the time required for the transfer period K.

[0146] In this way, in the seventh embodiment described above, the reset period R of the four-pixel shared cells CEL in different rows in the same column is prevented from overlapping with the transfer period K. This eliminates the need to provide a P-phase mode and a D-phase mode, and also makes it possible to prevent rows in the reset mode and rows in the transfer mode from existing at the same time, thereby simplifying the read control.

[0147] 8. Eighth Embodiment In the sixth embodiment described above, pixel signals read out from pixels in different rows but in the same column for a four-pixel shared cell CEL to which a charge domain is applied are AD converted in a time-division manner. In this eighth embodiment, pixel signals read out from pixels in different rows but in the same column for a two-pixel shared cell to which a charge domain is applied are AD converted in a time-division manner, and the reset period R is prevented from overlapping with the transfer period K.

[0148] FIG. 22 is a timing chart showing the operation of the solid-state imaging device according to the eighth embodiment.

[0149] In the figure, the two-pixel sharing cells CEA1 to CEA4 and CEB1 to CEB4 are arranged in a matrix along the row and column directions. In each of the two-pixel sharing cells CEA1 to CEA4 and CEB1 to CEB4, pixels can be arranged in a 1×2 array. In this case, assuming that the vertical signal lines VSL1 to VSLn are arranged for each column, the two-pixel sharing cells in the same column are connected to the same vertical signal line VSL1 to VSLn, and the two-pixel sharing cells in different columns are connected to different vertical signal lines VSL1 to VSLn. For example, the two-pixel sharing cells CEA1 to CEA4 in the same column are connected to the vertical signal line VSL1, and the two-pixel sharing cells CEB1 to CEB4 in the same column are connected to the vertical signal line VSL2.

[0150] In reading from the two-pixel sharing cells, for example, pixel signals are simultaneously read out from the first pixels of the two-pixel sharing cells CEA1 and CEA2 to the vertical signal lines VSL1 and VSL2, and then pixel signals are simultaneously read out from the first pixels of the two-pixel sharing cells CEB1 and CEB2 to the vertical signal lines VSL1 and VSL2. Furthermore, pixel signals are simultaneously read out from the second pixels of the two-pixel sharing cells CEA1 and CEA2 to the vertical signal lines VSL1 and VSL2, and then pixel signals are simultaneously read out from the second pixels of the two-pixel sharing cells CEB1 and CEB2 to the vertical signal lines VSL1 and VSL2. Thereafter, pixel signals are simultaneously read out from the first pixels of the two-pixel sharing cells CEA3 and CEA4 to vertical signal lines VSL1 and VSL2, and then pixel signals are simultaneously read out from the first pixels of the two-pixel sharing cells CEB3 and CEB4 to vertical signal lines VSL1 and VSL2. Furthermore, pixel signals are simultaneously read out from the second pixels of the two-pixel sharing cells CEA3 and CEA4 to vertical signal lines VSL1 and VSL2, and then pixel signals are simultaneously read out from the second pixels of the two-pixel sharing cells CEB3 and CEB4 to vertical signal lines VSL1 and VSL2. At this time, pixel signals are read out from each pixel of the two-pixel sharing cells CEA1, CEA2, CEB1, and CEB2 in the order of 1 → 2 → 3 → 4, and then pixel signals are read out from each pixel of the two-pixel sharing cells CEA3, CEA4, CEB3, and CEB4 in the order of 5 → 6 → 7 → 8. When reading out from each pixel of the two-pixel sharing cells CEA1, CEA2, CEB1, and CEB2, there is no going back and forth between the two-pixel sharing cells CEA1, CEA2, CEB1, and CEB2 in the column direction.

[0151] In the first readout period PX1, the P-phase pixel signal and the D-phase pixel signal are sequentially read out from the first pixel of each of the two-pixel sharing cells CEA1 and CEA2, and sequentially transmitted via the vertical signal lines VSL1 and VSL2.

[0152] In the second readout period PX2, P-phase pixel signals and D-phase pixel signals are sequentially read out from the second pixel of each of the two-pixel sharing cells CEA1 and CEA2 and sequentially transmitted via the vertical signal lines VSL1 and VSL2. At this time, the P-phase settling period PS and the P-phase AD conversion period PA for the second pixel of each of the two-pixel sharing cells CEA1 and CEA2 overlap with the transfer period K for the first pixel of each of the two-pixel sharing cells CEA1 and CEA2. The reset period R for the second pixel of each of the two-pixel sharing cells CEA1 and CEA2 does not overlap with the transfer period K for the first pixel of each of the two-pixel sharing cells CEA1 and CEA2.

[0153] In the third readout period PX3, P-phase pixel signals and D-phase pixel signals are sequentially read out from the first pixel of each of the two-pixel sharing cells CEB1 and CEB2 and sequentially transmitted via the vertical signal lines VSL1 and VSL2. At this time, the P-phase settling period PS and the P-phase AD conversion period PA for the first pixel of each of the two-pixel sharing cells CEB1 and CEB2 overlap with the transfer period K for the second pixel of each of the two-pixel sharing cells CEA1 and CEA2. The reset period R for the first pixel of each of the two-pixel sharing cells CEB1 and CEB2 does not overlap with the transfer period K for the second pixel of each of the two-pixel sharing cells CEA1 and CEA2.

[0154] In the fourth readout period PX4, P-phase pixel signals and D-phase pixel signals are sequentially read out from the second pixel of each of the two-pixel sharing cells CEB1 and CEB2 and sequentially transmitted via the vertical signal lines VSL1 and VSL2. At this time, the P-phase settling period PS and the P-phase AD conversion period PA for the second pixel of each of the two-pixel sharing cells CEB1 and CEB2 overlap with the transfer period K for the first pixel of each of the two-pixel sharing cells CEB1 and CEB2. The reset period R for the second pixel of each of the two-pixel sharing cells CEB1 and CEB2 does not overlap with the transfer period K for the first pixel of each of the two-pixel sharing cells CEB1 and CEB2.

[0155] In the fifth readout period PX5, P-phase pixel signals and D-phase pixel signals are sequentially read out from the first pixel of each of the two-pixel sharing cells CEA3 and CEA4 and sequentially transmitted via the vertical signal lines VSL1 and VSL2. At this time, the P-phase settling period PS and the P-phase AD conversion period PA for the first pixel of each of the two-pixel sharing cells CEA3 and CEA4 overlap with the transfer period K for the second pixel of each of the two-pixel sharing cells CEB1 and CEB2. The reset period R for the first pixel of each of the two-pixel sharing cells CEA3 and CEA4 does not overlap with the transfer period K for the second pixel of each of the two-pixel sharing cells CEB1 and CEB2.

[0156] As described above, in the eighth embodiment, for a two-pixel sharing cell to which a charge domain is applied, pixel signals read out from pixels in different rows in the same column are AD converted in a time-division manner, and the reset period R is prevented from overlapping with the transfer period K. This eliminates the need to jump over two-pixel sharing cells in the column direction when reading out from each pixel of each two-pixel sharing cell, making it possible to suppress an increase in the time lag until reading out from each pixel of each two-pixel sharing cell is completed.

[0157] 9. Ninth Embodiment In the seventh embodiment described above, the reset period R of the four-pixel shared cells CEL in different rows in the same column is made not to overlap with the transfer period K. In this ninth embodiment, the reset period R of the four-pixel shared cells CEL in different rows in the same column is made not to overlap with the transfer period K, but is made to overlap with the D-phase AD conversion period DA.

[0158] FIG. 23 is a timing chart showing the operation of the solid-state imaging device according to the ninth embodiment.

[0159] In the figure, four-pixel sharing cells CEL1 to CEL6 are arranged in the column direction. When reading from the four-pixel sharing cells CEL1 to CEL6, for example, pixel signals can be sequentially read from each of the four-pixel sharing cells CEL1, CEL3, and CEL5 while simultaneously sequentially reading pixel signals from each of the four-pixel sharing cells CEL2, CEL4, and CEL6. At this time, pixel signals are read from each pixel of the four-pixel sharing cells while spanning three four-pixel sharing cells adjacent in the column direction. For example, pixel signals are read from each of the four-pixel sharing cells CEL1 to CEL6 in the order 1 → 2 → 3 → 4 → 5 → 6 → 7 → 8 → 9 → 10 → 11 → 12.

[0160] During the first readout period PX1, P-phase pixel signals and D-phase pixel signals are sequentially read out from the first pixel of each of the four-pixel sharing cells CEL1 and CEL2 and sequentially transmitted via the vertical signal lines VSL1 and VSL2. At this time, the reset period R for the first pixel of each of the four-pixel sharing cells CEL3 and CEL4 is carried out ahead of the readout period PX1. Here, the reset period R for the first pixel of each of the four-pixel sharing cells CEL3 and CEL4 does not overlap with the transfer period K for the first pixel of each of the four-pixel sharing cells CEL1 and CEL2.

[0161] During the second readout period PX2, P-phase pixel signals and D-phase pixel signals are sequentially read out from the first pixel of each of the four-pixel-shared cells CEL3 and CEL4 and transmitted sequentially via the vertical signal lines VSL1 and VSL2. At this time, the reset period R for the first pixel of each of the four-pixel-shared cells CEL5 and CEL6 is advanced to the readout period PX2. The P-phase settling period PS and the P-phase AD conversion period PA for the first pixel of each of the four-pixel-shared cells CEL3 and CEL4 overlap with the transfer period K for the first pixel of each of the four-pixel-shared cells CEL1 and CEL2. Furthermore, the reset period R for the first pixel of each of the four-pixel-shared cells CEL5 and CEL6 overlaps with the D-phase AD conversion period DA for the first pixel of each of the four-pixel-shared cells CEL1 and CEL2, but does not overlap with the transfer period K for the first pixel of each of the four-pixel-shared cells CEL3 and CEL4.

[0162] During the third readout period PX3, P-phase pixel signals and D-phase pixel signals are sequentially read out from the first pixel of each of the four-pixel-shared cells CEL5 and CEL6 and transmitted sequentially via the vertical signal lines VSL1 and VSL2. At this time, the reset period R for the second pixel of each of the four-pixel-shared cells CEL1 and CEL2 is advanced to the readout period PX3. The P-phase settling period PS and the P-phase AD conversion period PA for the first pixel of each of the four-pixel-shared cells CEL5 and CEL6 overlap with the transfer period K for the first pixel of each of the four-pixel-shared cells CEL3 and CEL4. Furthermore, the reset period R for the second pixel of each of the four-pixel-shared cells CEL1 and CEL2 overlaps with the D-phase AD conversion period DA for the first pixel of each of the four-pixel-shared cells CEL3 and CEL4, but does not overlap with the transfer period K for the first pixel of each of the four-pixel-shared cells CEL5 and CEL6.

[0163] During the fourth readout period PX4, P-phase pixel signals and D-phase pixel signals are sequentially read out from the second pixel of each of the four-pixel-shared cells CEL1 and CEL2 and transmitted sequentially via the vertical signal lines VSL1 and VSL2. At this time, the reset period R for the second pixel of each of the four-pixel-shared cells CEL3 and CEL4 is performed ahead of the readout period PX4. The P-phase settling period PS and the P-phase AD conversion period PA for the second pixel of each of the four-pixel-shared cells CEL1 and CEL2 overlap with the transfer period K for the first pixel of each of the four-pixel-shared cells CEL5 and CEL6. Furthermore, the reset period R for the second pixel of each of the four-pixel-shared cells CEL3 and CEL4 overlaps with the D-phase AD conversion period DA for the second pixel of each of the four-pixel-shared cells CEL1 and CEL2, but does not overlap with the transfer period K for the second pixel of each of the four-pixel-shared cells CEL1 and CEL2.

[0164] In the fifth readout period PX5, the P-phase pixel signal and the D-phase pixel signal are sequentially read out from the second pixel of each of the 4-pixel sharing cells CEL3 and CEL4, and sequentially transmitted via the vertical signal lines VSL1 and VSL2.

[0165] In this way, in the ninth embodiment described above, the reset period R of the 4-pixel shared cells in different rows in the same column does not overlap with the transfer period K, but overlaps with the D-phase AD conversion period DA. This allows the reset period R to be carried out earlier during the D-phase AD conversion period DA of the 4-pixel shared cells in different rows in the same column, thereby speeding up readout from the 4-pixel shared cells.

[0166] 10. Tenth Embodiment In the above-described ninth embodiment, the reset period R of four-pixel shared cells in different rows in the same column does not overlap with the transfer period K, but overlaps with the D-phase AD conversion period DA. In this tenth embodiment, the reset period R of two-pixel shared cells in different rows in the same column does not overlap with the transfer period K, but overlaps with the D-phase AD conversion period DA.

[0167] FIG. 24 is a timing chart showing the operation of the solid-state imaging device according to the tenth embodiment.

[0168] In the figure, in reading from the two-pixel sharing cells, for example, pixel signals are simultaneously read out from the first pixels of the two-pixel sharing cells CEA1 and CEA2 to vertical signal lines VSL1 and VSL2, and then pixel signals are simultaneously read out from the first pixels of the two-pixel sharing cells CEA3 and CEA4 to vertical signal lines VSL1 and VSL2. Furthermore, pixel signals are simultaneously read out from the first pixels of the two-pixel sharing cells CEB1 and CEB2 to vertical signal lines VSL1 and VSL2, and then pixel signals are simultaneously read out from the first pixels of the two-pixel sharing cells CEB3 and CEB4 to vertical signal lines VSL1 and VSL2. Thereafter, pixel signals are simultaneously read out to vertical signal lines VSL1 and VSL2 from the second pixels of the two-pixel sharing cells CEA1 and CEA2, and then pixel signals are simultaneously read out to vertical signal lines VSL1 and VSL2 from the second pixels of the two-pixel sharing cells CEA3 and CEA4. Furthermore, pixel signals are simultaneously read out to vertical signal lines VSL1 and VSL2 from the second pixels of the two-pixel sharing cells CEB1 and CEB2, and then pixel signals are simultaneously read out to vertical signal lines VSL1 and VSL2 from the second pixels of the two-pixel sharing cells CEB3 and CEB4. At this time, pixel signals are read out from the pixels of the two-pixel sharing cells CEA1 to CEA4 and CEB1 to CEB4 in the order of 1 → 2 → 3 → 4 → 5 → 6 → 7 → 8.

[0169] In the first readout period PX1, P-phase pixel signals and D-phase pixel signals are sequentially read out from the first pixel of each of the two-pixel sharing cells CEA1 and CEA2 and sequentially transmitted via the vertical signal lines VSL1 and VSL2. At this time, the reset period R for the first pixel of each of the two-pixel sharing cells CEA3 and CEA4 is carried out ahead of the readout period PX1. Here, the reset period R for the first pixel of each of the two-pixel sharing cells CEA3 and CEA4 does not overlap with the transfer period K for the first pixel of each of the two-pixel sharing cells CEA1 and CEA2.

[0170] In the second readout period PX2, P-phase pixel signals and D-phase pixel signals are sequentially read out from the first pixel of each of the two-pixel sharing cells CEA3 and CEA4 and sequentially transmitted via the vertical signal lines VSL1 and VSL2. At this time, the reset period R of the first pixel of each of the two-pixel sharing cells CEB1 and CEB2 is carried out ahead of the readout period PX2. Here, the P-phase settling period PS and the P-phase AD conversion period PA for the first pixel of each of the two-pixel sharing cells CEA3 and CEA4 overlap with the transfer period K for the first pixel of each of the two-pixel sharing cells CEA1 and CEA2. The reset period R for the first pixel of each of the two-pixel sharing cells CEB1 and CEB2 overlaps with the D-phase AD conversion period DA for the first pixel of each of the two-pixel sharing cells CEA1 and CEA2, but does not overlap with the transfer period K for the first pixel of each of the two-pixel sharing cells CEA3 and CEA4.

[0171] In the third readout period PX3, P-phase pixel signals and D-phase pixel signals are sequentially read out from the first pixel of each of the two-pixel sharing cells CEB1 and CEB2 and sequentially transmitted via the vertical signal lines VSL1 and VSL2. At this time, the reset period R of the first pixel of each of the two-pixel sharing cells CEB3 and CEB4 is carried out ahead of the readout period PX3. Here, the P-phase settling period PS and the P-phase AD conversion period PA for the first pixel of each of the two-pixel sharing cells CEB1 and CEB2 overlap with the transfer period K for the first pixel of each of the two-pixel sharing cells CEA3 and CEA4. The reset period R for the first pixel of each of the two-pixel sharing cells CEB3 and CEB4 overlaps with the D-phase AD conversion period DA for the first pixel of each of the two-pixel sharing cells CEA3 and CEA4, but does not overlap with the transfer period K for the first pixel of each of the two-pixel sharing cells CEB1 and CEB2.

[0172] In the fourth readout period PX4, P-phase pixel signals and D-phase pixel signals are sequentially read out from the first pixel of each of the two-pixel sharing cells CEB3 and CEB4 and sequentially transmitted via the vertical signal lines VSL1 and VSL2. At this time, the reset period R of the second pixel of each of the two-pixel sharing cells CEA1 and CEA2 is carried out ahead of schedule in the readout period PX4. Here, the P-phase settling period PS and the P-phase AD conversion period PA for the first pixel of each of the two-pixel sharing cells CEB3 and CEB4 overlap with the transfer period K for the first pixel of each of the two-pixel sharing cells CEB1 and CEB2. The reset period R for the second pixel of each of the two-pixel sharing cells CEA1 and CEA2 overlaps with the D-phase AD conversion period DA for the first pixel of each of the two-pixel sharing cells CEB1 and CEB2, but does not overlap with the transfer period K for the first pixel of each of the two-pixel sharing cells CEB3 and CEB4.

[0173] In the fifth readout period PX5, the P-phase pixel signal and the D-phase pixel signal are sequentially read out from the second pixel of each of the two-pixel sharing cells CEA1 and CEA2, and sequentially transmitted via the vertical signal lines VSL1 and VSL2.

[0174] As described above, in the tenth embodiment, the reset period R of two-pixel shared cells in different rows but in the same column does not overlap with the transfer period K, but overlaps with the D-phase AD conversion period DA. This allows the reset period R to be performed earlier during the D-phase AD conversion period DA of two-pixel shared cells in different rows but in the same column, thereby speeding up readout from the two-pixel shared cells. In this case, for a four-pixel shared cell, readout spans three four-pixel shared cells adjacent in the column direction, whereas for a two-pixel shared cell, readout spans only two two-pixel shared cells adjacent in the column direction. This makes it possible to speed up readout from the two-pixel shared cells while suppressing an increase in the time lag until readout from each pixel of each two-pixel shared cell is completed.

[0175] 11. Eleventh Embodiment In the sixth embodiment described above, pixel signals read from pixels in different rows in the same column are AD converted in a time-division manner for a four-pixel shared cell to which a charge domain is applied. In this eleventh embodiment, it is possible to switch between a process of performing AD conversion overlapping with the transfer period of the charge held in the capacitor of the charge domain, and a process of suspending AD conversion during the transfer period of the charge held in the capacitor of the charge domain.

[0176] 25 is a diagram showing the pixel readout order of the solid-state imaging device according to the eleventh embodiment. Note that the diagram shows an example in which AD conversion is suspended during the transfer period of the charges held in the capacitors of each of the four-pixel shared cells CEL1 to CEL4.

[0177] In the figure, the solid-state imaging device can switch between a process of performing AD conversion overlapping with the transfer period of the electric charges held in the capacitors of each of the four-pixel shared cells CEL1 to CEL4 and a process of suspending AD conversion during the transfer period of the electric charges held in the capacitors of each of the four-pixel shared cells CEL1 to CEL4. The configuration of the four-pixel shared cells CEL1 to CEL4 is the same as the configuration of the four-pixel shared cells CEL1 to CEL4 described above in the sixth embodiment. Furthermore, for example, the comparator CM' described in the fourth embodiment can be used as the AD conversion unit. In this case, in the process of performing AD conversion overlapping with the transfer period of the electric charges held in the capacitors of each of the four-pixel shared cells CEL1 to CEL4, the pixel readout order is set in the same manner as in the sixth embodiment. In this case, pixel signals are read out from each pixel of the four-pixel shared cells CEL1 to CEL4, straddling two four-pixel shared cells CEL1 to CEL4 adjacent to each other in the column direction.

[0178] On the other hand, in the process of putting AD conversion on hold during the transfer period of the charges held in the capacitors of each of the four-pixel shared cells CEL1 to CEL4, pixel signals are read out from each pixel of the four-pixel shared cells CEL1 to CEL4 without crossing the four-pixel shared cells CEL1 to CEL4 arranged in the column direction.

[0179] At this time, pixel signals are simultaneously read out from the first pixels of the four-pixel sharing cells CEL1 and CEL2 to vertical signal lines VSL1 and VSL2, and then pixel signals are simultaneously read out from the second pixels of the four-pixel sharing cells CEL1 and CEL2 to vertical signal lines VSL1 and VSL2. Furthermore, pixel signals are simultaneously read out from the third pixels of the four-pixel sharing cells CEL1 and CEL2 to vertical signal lines VSL1 and VSL2, and then pixel signals are simultaneously read out from the fourth pixels of the four-pixel sharing cells CEL1 and CEL2 to vertical signal lines VSL1 and VSL2. Thereafter, pixel signals are simultaneously read out from the first pixels of the four-pixel sharing cells CEL3 and CEL4 to vertical signal lines VSL1 and VSL2, and then pixel signals are simultaneously read out from the second pixels of the four-pixel sharing cells CEL3 and CEL4 to vertical signal lines VSL1 and VSL2. Furthermore, pixel signals are simultaneously read out to vertical signal lines VSL1 and VSL2 from the third pixels of the four-pixel sharing cells CEL3 and CEL4, and then pixel signals are simultaneously read out to vertical signal lines VSL1 and VSL2 from the fourth pixels of the four-pixel sharing cells CEL3 and CEL4. At this time, pixel signals are read out from the pixels of the four-pixel sharing cells CEL1 and CEL2 in the order of 1 → 2 → 3 → 4, and then pixel signals are read out from the pixels of the four-pixel sharing cells CEL3 and CEL4 in the order of 5 → 6 → 7 → 8.

[0180] 26 is a timing chart showing the operation of the solid-state imaging device according to the eleventh embodiment. Note that this figure shows an example in which AD conversion is suspended during the transfer period of the charges held in the capacitors of each of the four-pixel shared cells CEL1 to CEL4.

[0181] In the process of performing AD conversion overlapping with the transfer period of the charges held in the capacitors of each of the four-pixel shared cells CEL1 to CEL4, the operation is performed at the same timing as in the sixth embodiment described above, as shown in FIG. 20 .

[0182] On the other hand, the process of putting AD conversion on hold during the transfer period of the charges held in the capacitors of each of the four-pixel shared cells CEL1 to CEL4 operates according to the timing shown in FIG.

[0183] At this time, in the first readout period PX1, P-phase pixel signals and D-phase pixel signals are sequentially read out from the first pixel of each of the four-pixel sharing cells CEL1, CEL2 and sequentially transmitted via the vertical signal lines VSL1, VSL2. At this time, the reset period R, P-phase settling period PS, and P-phase AD conversion period PA for the first pixel of each of the four-pixel sharing cells CEL1, CEL2 do not overlap with the transfer period K for the first pixel of each of the four-pixel sharing cells CEL1, CEL2.

[0184] In the second readout period PX2, P-phase pixel signals and D-phase pixel signals are sequentially read out from the second pixel of each of the four-pixel sharing cells CEL1 and CEL2 and sequentially transmitted via the vertical signal lines VSL1 and VSL2. At this time, the reset period R, P-phase settling period PS, and P-phase AD conversion period PA for the second pixel of each of the four-pixel sharing cells CEL1 and CEL2 do not overlap with the transfer period K for the second pixel of each of the four-pixel sharing cells CEL1 and CEL2.

[0185] In the third readout period PX3, the P-phase pixel signal and the D-phase pixel signal are sequentially read out from the third pixel of each of the four-pixel sharing cells CEL1 and CEL2 and sequentially transmitted via the vertical signal lines VSL1 and VSL2. At this time, the reset period R, the P-phase settling period PS, and the P-phase AD conversion period PA for the third pixel of each of the four-pixel sharing cells CEL1 and CEL2 do not overlap with the transfer period K for the third pixel of each of the four-pixel sharing cells CEL1 and CEL2.

[0186] 27 is a timing chart showing an example of the operation of the AD conversion unit for one column of the solid-state imaging device according to the eleventh embodiment. Note that this figure shows an example in which AD conversion is put on hold during the transfer period of the charges held in the capacitors of each of the four-pixel shared cells CEL1 to CEL4.

[0187] In the figure, the comparator CM' of the fourth embodiment is used to suspend AD conversion during the transfer period of the charges held in the capacitors of each of the four-pixel shared cells CEL1 to CEL4. In this case, only one of the two pixel signal inputs to the comparator CM' is used. In this case, the auto-zero switches SW2A and SW2B and the switches SW12A and SW12B can be kept off at all times.

[0188] Then, the auto-zero switches SW1A and SW1B are turned on, thereby setting the auto-zero period AZ1 of the comparator CM'. At this time, the P-phase settling period PS is set during the auto-zero period AZ1.

[0189] Between the current auto-zero period AZ1 and the next auto-zero period AZ1, the current P-phase AD conversion period PA, transfer period K, D-phase settling period DS, and D-phase AD conversion period DA are set in sequence. Comparator CM1 is in use during period AK from the current P-phase AD conversion period PA to the D-phase AD conversion period DA.

[0190] 28 is a timing chart showing the operation of the CDS process of the solid-state imaging device according to the eleventh embodiment. Note that this figure shows an example in which AD conversion is put on hold during the transfer period of the charges held in the capacitors of each of the four-pixel shared cells CEL1 to CEL4.

[0191] In the same figure, in the process of putting AD conversion on hold during the transfer period of the charges held in the capacitors of each of the four-pixel shared cells CEL1 to CEL4, of the P-phase registers 161 and 162 in the first embodiment described above, only the P-phase register 161 is used, and the P-phase register 162 is not used.

[0192] At this time, a P-phase count period CT1 is provided in a P-phase AD conversion period PA of each pixel of each of the four-pixel sharing cells CEL1 and CEL2. A D-phase count period CT3 is provided in a D-phase AD conversion period DA of each of the four-pixel sharing cells CEL1 and CEL2.

[0193] After the P-phase count period CT1 for each pixel of each of the four-pixel sharing cells CEL1 and CEL2 is completed, the P-phase AD conversion result PN1 is stored in the P-phase register 161 (ST1). After the D-phase count period CT3 for each pixel of each of the four-pixel sharing cells CEL1 and CEL2 is completed, CDS calculation is performed, and the CDS processing result CS1 is stored in the output register 164 (ST3). At this time, a readout period RD for each CDS processing result CS1 is set during the storage timing ST3 for each CDS processing result CS1.

[0194] In this way, in the eleventh embodiment described above, it is possible to switch between processing in which the reset period R, the P-phase settling period PS, and the P-phase AD conversion period PA of the four-pixel shared cells CEL in different rows in the same column overlap with the transfer period K and processing in which they do not overlap with the transfer period K. This makes it possible to switch between low power consumption operation and high frame rate operation according to the imaging environment, etc.

[0195] 12. Twelfth Embodiment In the sixth embodiment described above, pixel signals read from pixels in different rows in the same column are AD converted in a time-division manner for a four-pixel shared cell to which a charge domain is applied. In this twelfth embodiment, semiconductor chips each having a pixel array unit in which pixels are arranged in a matrix are stacked.

[0196] FIG. 29 is a perspective view showing an example of a stack of pixel array units according to the fifth embodiment.

[0197] In the figure, the solid-state imaging device includes semiconductor chips 921 and 922. The semiconductor chip 922 is stacked on the semiconductor chip 921.

[0198] A pixel array section 923 is formed in the semiconductor chip 922. In the pixel array section 923, pixels 931 are arranged in a matrix in the row and column directions. The pixels 931 may be pixels PIX1 and PIX2 of FIG. 3 , a four-pixel shared cell CEL of FIG. 18 , or a two-pixel shared cell CEL of FIG. 22 . Pad electrodes 932 and via electrodes 933 are formed around the pixel array section 923. The via electrodes 933 penetrate the semiconductor chip 922 and can electrically connect the semiconductor chips 921 and 922 to each other.

[0199] A peripheral circuit 924 is formed on the semiconductor chip 921. A column readout circuit 925, a column ADC 926, a communication interface 927, and an oscillation circuit 928 are formed in the peripheral circuit 924. The column readout circuit 925 and the column ADC 926 may be formed so as to correspond to positions on both sides of the pixel array unit 923 in the column direction. The column ADC 926 can be provided with an AD conversion unit according to any of the first to eleventh embodiments described above.

[0200] The semiconductor chips 921 and 922 may be directly bonded to each other. Hybrid bonding can be used for directly bonding the semiconductor chips 921 and 922. In this case, the semiconductor chips 921 and 922 may be electrically connected based on Cu-Cu bonding. The material of the semiconductor substrate used for the semiconductor chips 921 and 922 may be Si, InGaAs, or InP.

[0201] As described above, in the twelfth embodiment, the semiconductor chip 922 on which the pixel array unit 923 is formed is stacked on the semiconductor chip 921 on which the peripheral circuit 924 is formed. This makes it possible to increase the sensitivity of the solid-state imaging device while suppressing an increase in the mounting area of ​​the semiconductor chip on which the solid-state imaging device is formed.

[0202] 13. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0203] FIG. 30 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0204] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 30, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0205] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0206] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0207] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0208] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0209] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0210] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0211] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0212] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0213] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 30, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0214] FIG. 31 is a diagram showing an example of the installation position of the imaging unit 12031.

[0215] In FIG. 31 , the imaging unit 12031 includes imaging units 12101 , 12102 , 12103 , 12104 , and 12105 .

[0216] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0217] 31 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0218] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0219] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0220] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0221] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0222] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, for example, the imaging device according to the above-described embodiment can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the vehicle control system 12000, it is possible to improve the frame rate in a charge domain global shutter system without changing the pixel configuration.

[0223] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology with the same title correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist. Furthermore, the effects described in this specification are merely examples and are not limited, and other effects may also be present.

[0224] The present technology may also be configured as follows: (1) An imaging device comprising: a pixel capable of transferring and holding photoelectrically converted charges; and an AD conversion unit capable of time-division switching of AD (Analog to Digital) conversion of pixel signals read out from pixels in different rows in the same column. (2) The imaging device according to (1), wherein the pixel comprises: a photoelectric conversion unit; a capacitor that holds the charges photoelectrically converted by the photoelectric conversion unit; a first transfer transistor that transfers the charges photoelectrically converted by the photoelectric conversion unit to the capacitor; a second transfer transistor that transfers the charges held in the capacitor to a floating diffusion; an output transistor that outputs the pixel signal based on the charges transferred to the floating diffusion; and a selection transistor that selects the output of the pixel signal. (3) The imaging device according to (2), wherein the AD conversion unit performs AD conversion on a pixel signal read from a second pixel in a second row in the first column during an AD conversion period that overlaps with a transfer period during which charge held in a capacitor of a first pixel in a first row in a first column is transferred to a floating diffusion. (4) The imaging device according to (3), further comprising: vertical signal lines that transmit the pixel signals in a column direction; a first comparator whose input is connected to the vertical signal lines; and a second comparator whose input is connected to the vertical signal lines. (5) The imaging device according to (4), wherein after an auto-zero operation of the first comparator, the first comparator performs AD conversion of a P-phase of a pixel signal read out from the first pixel; after performing AD conversion of the P-phase of a pixel signal read out from the first pixel, the second comparator performs AD conversion of a P-phase of a pixel signal read out from the second pixel; after performing AD conversion of the P-phase of a pixel signal read out from the second pixel, the first comparator performs AD conversion of a D-phase of a pixel signal read out from the first pixel; and after performing AD conversion of the D-phase of a pixel signal read out from the first pixel, the second comparator performs AD conversion of a D-phase of a pixel signal read out from the second pixel.(6) The imaging device according to (5), wherein the AD conversion of the second comparator is put on hold during the AD conversion of the first comparator, and the AD conversion of the first comparator is put on hold during the AD conversion of the second comparator. (7) The imaging device according to (3), comprising: vertical signal lines that transmit the pixel signals in a column direction; a comparator having an input connected to the vertical signal line; a first switch connected between the input of the comparator and the vertical signal line; and a second switch connected between the input of the comparator and the vertical signal line. (8) The imaging device according to (7), wherein the AD conversion of the pixel signal read out from the first pixel is performed when the first switch is on and the second switch is off, and the AD conversion of the pixel signal read out from the second pixel is performed by the comparator when the first switch is off and the second switch is on. (9) The imaging device described in (3) above, comprising: a vertical signal line that transmits the pixel signal in a column direction; and a comparator having a first input and a second input connected to the vertical signal line, wherein the comparator comprises: a first transistor; a second transistor; a third transistor that can form a differential pair with each of the first transistor and the second transistor; a fourth transistor that can form a differential pair with each of the first transistor and the second transistor; a first switch connected in series to the first transistor; a second switch connected in series to the second transistor; a third switch connected in series to the third transistor; and a fourth switch connected in series to the fourth transistor.(10) The imaging device described in (9), comprising: a first capacitor connected in series to the gate of the first transistor; a second capacitor connected in series to the gate of the second transistor; a third capacitor connected in series to the gate of the third transistor; a fourth capacitor connected in series to the gate of the fourth transistor; a first auto-zero switch connected between the gate of the first transistor and the first switch; a second auto-zero switch connected between the gate of the second transistor and the second switch; a third auto-zero switch connected between the gate and drain of the third transistor; and a fourth auto-zero switch connected between the gate and drain of the fourth transistor. (11) The imaging device according to (10), wherein when the first switch and the third switch are on and the second switch and the fourth switch are off, the first auto-zero switch and the third auto-zero switch are on to perform an auto-zero operation, and then the comparator performs AD conversion of the P phase of the pixel signal read out from the first pixel; when the first switch and the third switch are off and the second switch and the fourth switch are on, the second auto-zero switch and the fourth auto-zero switch are on to perform an auto-zero operation, and then the comparator performs AD conversion of the P phase of the pixel signal read out from the second pixel; when the first switch and the third switch are on and the second switch and the fourth switch are off, the comparator performs AD conversion of the D phase of the pixel signal read out from the first pixel; and when the first switch and the third switch are off and the second switch and the fourth switch are on, the comparator performs AD conversion of the D phase of the pixel signal read out from the second pixel.(12) The imaging device according to any one of (3) to (11), further comprising: a first P-phase register that holds a P-phase AD conversion result of a pixel signal read from the first pixel, a second P-phase register that holds the P-phase AD conversion result of a pixel signal read from the second pixel, and a CDS processing unit that performs a first CDS (Correlated Double Sampling) process based on the P-phase AD conversion result of the pixel signal read from the first pixel held in the first P-phase register and the D-phase AD conversion result of the pixel signal read from the first pixel output from the AD conversion unit, and that performs a second CDS process based on the P-phase AD conversion result of the pixel signal read from the second pixel held in the second P-phase register and the D-phase AD conversion result of the pixel signal read from the second pixel output from the AD conversion unit. (13) The imaging device according to any one of (1) to (12), wherein the pixel transfers and holds the photoelectrically converted charge based on a global shutter operation. (14) A comparator comprising: a first transistor; a second transistor; a third transistor capable of forming a differential pair with each of the first transistor and the second transistor; a fourth transistor capable of forming a differential pair with each of the first transistor and the second transistor; a first switch connected in series with the first transistor; a second switch connected in series with the second transistor; a third switch connected in series with the third transistor; and a fourth switch connected in series with the fourth transistor.(15) The comparator according to (14), wherein a first capacitor is connected in series to the gate of the first transistor, a second capacitor is connected in series to the gate of the second transistor, a third capacitor is connected in series to the gate of the third transistor, a fourth capacitor is connected in series to the gate of the fourth transistor, a first auto-zero switch is connected between the gate of the first transistor and the first switch, a second auto-zero switch is connected between the gate of the second transistor and the second switch, a third auto-zero switch is connected between the gate and drain of the third transistor, and a fourth auto-zero switch is connected between the gate and drain of the fourth transistor. (16) The comparator according to (15), wherein when the first switch and the third switch are turned on, the second switch and the fourth switch are turned off, and when the first switch and the third switch are turned off, the second switch and the fourth switch are turned on. (17) The comparator according to (16), wherein the first auto-zero switch and the third auto-zero switch are turned on when the first switch and the third switch are turned on, and the second auto-zero switch and the fourth auto-zero switch are turned on when the second switch and the fourth switch are turned on. (18) The comparator according to any of (14) to (17), wherein a gate of the first transistor and a gate of the second transistor are connected to the same signal line, and a same reference signal is input to a gate of the third transistor and a gate of the fourth transistor. (19) An imaging method, wherein a first pixel in a first row and a first column transfers photoelectrically converted charge to a capacitor in the first pixel to hold it, and a second pixel in a second row and a first column transfers photoelectrically converted charge to a capacitor in the second pixel to hold it, and an AD conversion unit performs AD conversion on a pixel signal read out from the second pixel during an AD conversion period that overlaps with a transfer period in which the charge held in the capacitor of the first pixel is transferred to a floating diffusion.

[0225] REFERENCE SIGNS LIST 100 Imaging device 101 Optical system 102 Solid-state imaging device 103 Imaging control unit 104 Image processing unit 105 Memory unit 106 Display unit 107 Operation unit 108 Bus 111 Pixel array unit 112 Vertical scanning circuit 113 Column readout circuit 114 Column signal processing unit 115 Horizontal scanning circuit 116 Control circuit PIX1, PIX2 Pixel HSL Horizontal drive line VSL Vertical signal line PD1, PD2 Photodiode FD1, FD2 Floating diffusion CA1, CA2 Capacitor 122, 222 Overflow control transistor 123, 124, 223, 224 Transfer transistor 125, 225 Reset transistor 126, 226 Output transistor 127, 227 Selection transistor 131-1 to 131-3: Comparison section 132-1 to 132-3: Counter

Claims

1. An imaging device having pixels capable of transferring and holding photoelectrically converted electric charges, and an AD conversion unit capable of time-division switching of AD (Analog to Digital) conversion of pixel signals read out from pixels in different rows in the same column.

2. The imaging device of claim 1, wherein the pixel comprises: a photoelectric conversion unit; a capacitor that holds charge photoelectrically converted by the photoelectric conversion unit; a first transfer transistor that transfers the charge photoelectrically converted by the photoelectric conversion unit to the capacitor; a second transfer transistor that transfers the charge held in the capacitor to a floating diffusion; an output transistor that outputs the pixel signal based on the charge transferred to the floating diffusion; and a selection transistor that selects the output of the pixel signal.

3. The imaging device described in claim 2, wherein the AD conversion unit performs AD conversion of a pixel signal read out from a second pixel in a second row in the first column during an AD conversion period that overlaps with a transfer period during which charge held in a capacitor of a first pixel in a first row in a first column is transferred to a floating diffusion.

4. The imaging device according to claim 3, comprising: a vertical signal line that transmits the pixel signal in a column direction; a first comparator whose input is connected to the vertical signal line; and a second comparator whose input is connected to the vertical signal line.

5. The imaging device according to claim 4, wherein the first comparator performs an auto-zero operation after the first comparator performs an AD conversion of the P phase of the pixel signal read out from the first pixel, the second comparator performs an auto-zero operation after the first comparator performs an AD conversion of the P phase of the pixel signal read out from the first pixel, the second comparator performs an AD conversion of the P phase of the pixel signal read out from the second pixel after the auto-zero operation of the second comparator, the first comparator performs an AD conversion of the D phase of the pixel signal read out from the first pixel after the P phase of the pixel signal read out from the second pixel, and the second comparator performs an AD conversion of the D phase of the pixel signal read out from the first pixel after the D phase of the pixel signal read out from the first pixel.

6. The imaging device according to claim 5, wherein the AD conversion of the second comparator is put on hold during AD conversion of the first comparator, and the AD conversion of the first comparator is put on hold during AD conversion of the second comparator.

7. An imaging device as described in claim 3, comprising: a vertical signal line that transmits the pixel signal in a column direction; a comparator whose input is connected to the vertical signal line; a first switch connected between the input of the comparator and the vertical signal line; and a second switch connected between the input of the comparator and the vertical signal line.

8. The imaging device according to claim 7, wherein when the first switch is on and the second switch is off, AD conversion of the pixel signal read out from the first pixel is performed, and when the first switch is off and the second switch is on, AD conversion of the pixel signal read out from the second pixel is performed by the comparator.

9. An imaging device as described in claim 3, comprising: a vertical signal line that transmits the pixel signal in a column direction; and a comparator having a first input and a second input connected to the vertical signal line, the comparator comprising: a first transistor, a second transistor, a third transistor capable of forming a differential pair with each of the first transistor and the second transistor, a fourth transistor capable of forming a differential pair with each of the first transistor and the second transistor, a first switch connected in series to the first transistor, a second switch connected in series to the second transistor, a third switch connected in series to the third transistor, and a fourth switch connected in series to the fourth transistor.

10. The imaging device of claim 9, comprising: a first capacitor connected in series to a gate of the first transistor; a second capacitor connected in series to a gate of the second transistor; a third capacitor connected in series to a gate of the third transistor; a fourth capacitor connected in series to a gate of the fourth transistor; a first auto-zero switch connected between the gate of the first transistor and the first switch; a second auto-zero switch connected between the gate of the second transistor and the second switch; a third auto-zero switch connected between the gate and drain of the third transistor; and a fourth auto-zero switch connected between the gate and drain of the fourth transistor.

11. The imaging device according to claim 10, wherein when the first switch and the third switch are on and the second switch and the fourth switch are off, the first auto-zero switch and the third auto-zero switch are on to perform an auto-zero operation, and then the comparator performs AD conversion of the P phase of the pixel signal read out from the first pixel; when the first switch and the third switch are off and the second switch and the fourth switch are on, the comparator performs AD conversion of the P phase of the pixel signal read out from the second pixel after the second auto-zero switch and the fourth auto-zero switch are on to perform an auto-zero operation; when the first switch and the third switch are on and the second switch and the fourth switch are off, the comparator performs AD conversion of the D phase of the pixel signal read out from the first pixel; and when the first switch and the third switch are off and the second switch and the fourth switch are on, the comparator performs AD conversion of the D phase of the pixel signal read out from the second pixel.

12. The imaging device according to claim 3, further comprising: a first P-phase register that holds a P-phase AD conversion result of a pixel signal read out from the first pixel; a second P-phase register that holds a P-phase AD conversion result of a pixel signal read out from the second pixel; and a CDS processing unit that performs a first CDS (Correlated Double Sampling) process based on the P-phase AD conversion result of the pixel signal read out from the first pixel held in the first P-phase register and the D-phase AD conversion result of the pixel signal read out from the first pixel output from the AD conversion unit, and performs a second CDS process based on the P-phase AD conversion result of the pixel signal read out from the second pixel held in the second P-phase register and the D-phase AD conversion result of the pixel signal read out from the second pixel output from the AD conversion unit.

13. The imaging device according to claim 1, wherein the pixel transfers and holds the photoelectrically converted charge based on a global shutter operation.

14. A comparator comprising: a first transistor; a second transistor; a third transistor capable of forming a differential pair with each of the first transistor and the second transistor; a fourth transistor capable of forming a differential pair with each of the first transistor and the second transistor; a first switch connected in series with the first transistor; a second switch connected in series with the second transistor; a third switch connected in series with the third transistor; and a fourth switch connected in series with the fourth transistor.

15. The comparator of claim 14, wherein a first capacitor is connected in series to a gate of the first transistor, a second capacitor is connected in series to a gate of the second transistor, a third capacitor is connected in series to a gate of the third transistor, a fourth capacitor is connected in series to a gate of the fourth transistor, a first auto-zero switch is connected between a gate of the first transistor and the first switch, a second auto-zero switch is connected between a gate of the second transistor and the second switch, a third auto-zero switch is connected between the gate and drain of the third transistor, and a fourth auto-zero switch is connected between a gate and drain of the fourth transistor.

16. The comparator of claim 15, wherein when the first switch and the third switch are turned on, the second switch and the fourth switch are turned off, and when the first switch and the third switch are turned off, the second switch and the fourth switch are turned on.

17. The comparator of claim 16, wherein when the first switch and the third switch are turned on, the first auto-zero switch and the third auto-zero switch are turned on, and when the second switch and the fourth switch are turned on, the second auto-zero switch and the fourth auto-zero switch are turned on.

18. The comparator according to claim 14, wherein the gate of the first transistor and the gate of the second transistor are connected to the same signal line, and the gate of the third transistor and the gate of the fourth transistor receive the same reference signal.

19. An imaging method, in which a first pixel in a first row and a first column transfers a photoelectrically converted charge to a capacitor in the first pixel and holds the charge, and a second pixel in a second row and a first column transfers a photoelectrically converted charge to a capacitor in the second pixel and holds the charge, and an AD conversion unit performs AD conversion of a pixel signal read out from the second pixel during an AD conversion period that overlaps with a transfer period during which the charge held in the capacitor of the first pixel is transferred to a floating diffusion.

Images