Imaging device

Abstract

[Problem] To provide an imaging device that suppresses high-frequency noise from a comparator. [Solution] This imaging device comprises: a first power line; a second power line; a first input unit that inputs a reference signal; a second input unit that inputs a pixel signal; a comparison circuit that includes first and second paths which are in a voltage state corresponding to a magnitude relationship between a voltage of the first input unit and a voltage of the second input unit, and an output unit which is connected to the second path, and that logically inverts a signal from the output unit on the basis of the voltage of the first input unit and the voltage of the second input unit; at least one of a first capacitance element provided between the first power line and the first input unit or the first path or between the second power line and the first input unit or the first path, or a second capacitance element provided between the first power line and the second input unit or the second path or between the second power supply line and the second input unit or the second path; and at least one of a first adjustment unit that can adjust the capacitance of the first capacitance element or a second adjustment unit that can adjust the capacitance of the second capacitance element.

Description

Imaging device

[0001] The present disclosure relates to an imaging device.

[0002] In imaging devices such as CIS (CMOS (Complementary Metal Oxide Semiconductor) Image Sensors), fluctuations in the power supply voltage cause noise that appears as horizontal stripes in images. Reducing power supply noise is desirable as a countermeasure against this PSRR (Power Supply Rejection Ratio).

[0003] Japanese Patent Application Laid-Open No. 2021-093697

[0004] However, as imaging devices become more miniaturized, the spacing between adjacent wiring lines becomes narrower, increasing the parasitic capacitance that causes PSRR. Furthermore, narrower spacing between adjacent wiring lines makes it difficult to arrange shield wiring between the adjacent wiring lines. Therefore, with conventional noise cancellation devices (see Patent Document 1), it was difficult to suppress PSSR caused by high-frequency noise generated in the comparator.

[0005] Therefore, the present disclosure provides an imaging device that can suppress high-frequency noise in a comparator.

[0006] An imaging device according to one aspect of the present disclosure includes a first power supply line that transmits a first power supply voltage, a second power supply line that transmits a second power supply voltage different from the first power supply voltage, a first input unit that inputs a reference signal to be compared with a pixel signal from a pixel that photoelectrically converts light into a pixel signal, a second input unit that inputs the pixel signal, first and second paths that are in a voltage state according to the magnitude relationship between the voltage of the first input unit and the voltage of the second input unit, and an output unit connected to the second path, and outputs a voltage from the output unit based on the voltage of the first input unit and the voltage of the second input unit. The device comprises a comparison circuit that logically inverts an output signal, at least one of a first capacitance element provided between a first power supply line and a first input section or a first path, or between a second power supply line and a first input section or a first path, and a second capacitance element provided between the first power supply line and a second input section or a second path, or between the second power supply line and a second input section or a second path, and at least one of a first adjustment section that can adjust the capacitance of the first capacitance element and a second adjustment section that can adjust the capacitance of the second capacitance element.

[0007] The capacitance of the first capacitive element and the capacitance of the second capacitive element may be approximately equal.

[0008] The imaging device may further include a third capacitance element provided between the first power supply line and the output section.

[0009] The first capacitance element may be composed of a plurality of first partial capacitance elements, the first electrodes of the plurality of first partial capacitance elements being commonly connected to either the first input section or the first path, and the second electrodes of the plurality of first partial capacitance elements being selectively connected to the first or second power supply line, respectively, via the first adjustment section.

[0010] The second capacitance element may be composed of a plurality of second partial capacitance elements, the third electrodes of the plurality of second partial capacitance elements being commonly connected to either the second input section or the second path, and the fourth electrodes of the plurality of second partial capacitance elements being selectively connected to the first or second power supply line, respectively, via the second adjustment section.

[0011] The first adjustment unit may include a first switch connected between the first capacitance element and the first and second power supply lines, and configured to selectively connect the first capacitance element to either the first or second power supply line.

[0012] The second adjustment section may include a second switch connected between the second capacitance element and the first and second power supply lines, and configured to selectively connect the second capacitance element to either the first or second power supply line.

[0013] The first adjustment unit may include a plurality of first switches connected between the second electrodes of the plurality of first partial capacitance elements and the first and second power supply lines, and selectively connecting the second electrodes of the plurality of first partial capacitance elements to either the first or second power supply line, respectively.

[0014] The second adjustment unit may include a plurality of second switches connected between the fourth electrodes of the plurality of second partial capacitance elements and the first and second power supply lines, and selectively connecting the fourth electrodes of the plurality of second partial capacitance elements to either the first or second power supply line, respectively.

[0015] The imaging device may further include a register that stores a control signal for controlling the first switch.

[0016] The imaging device may further include a register that stores a control signal for controlling the second switch.

[0017] The first switch may be any logic circuit such as a CMOS (Complementary MOS) inverter, a NAND gate, or a NOR gate.

[0018] The second switch may be a logic circuit such as a CMOS inverter, a NAND gate, or a NOR gate.

[0019] The first adjustment unit may include a third switch connected between the first capacitance element and the first path and between the first capacitance element and the first power supply line, and configured to selectively connect the first capacitance element to either the first path or the first power supply line; and the second adjustment unit may include a fourth switch connected between the second capacitance element and the output unit and between the second capacitance element and the first power supply line, and configured to selectively connect the second capacitance element to either the output unit or the first power supply line.

[0020] The first adjustment unit may include a third switch connected between the first capacitance element and the first path and between the first capacitance element and the second power supply line, and configured to selectively connect the first capacitance element to either the first path or the second power supply line; and the second adjustment unit may include a fourth switch connected between the second capacitance element and the output unit and between the second capacitance element and the second power supply line, and configured to selectively connect the second capacitance element to either the output unit or the second power supply line.

[0021] The first adjustment unit may include a plurality of third switches connected between the plurality of first partial capacitance elements and the first path, and between the plurality of first partial capacitance elements and the first power supply line, and configured to selectively connect each of the plurality of first partial capacitance elements to either the first path or the first power supply line.

[0022] The second adjustment section may include a plurality of second switches connected between the plurality of second partial capacitance elements and the output section, and between the plurality of second partial capacitance elements and the first power supply line, and configured to selectively connect each of the plurality of second partial capacitance elements to either the output section or the first power supply line.

[0023] The first adjustment unit may include a plurality of third switches connected between the plurality of first partial capacitance elements and the first path, and between the plurality of first partial capacitance elements and the second power supply line, and configured to selectively connect each of the plurality of first partial capacitance elements to either the first path or the second power supply line.

[0024] The second adjustment section may include a plurality of second switches connected between the plurality of second partial capacitance elements and the output section, and between the plurality of second partial capacitance elements and the second power supply line, and configured to selectively connect each of the plurality of second partial capacitance elements to either the output section or the second power supply line.

[0025] an output section connected to the first path, the output section having a voltage state corresponding to the magnitude relationship between the voltage of the first input section and the voltage of the second input section; a comparator circuit that logically inverts an output signal from the output section based on the voltage of the first input section and the voltage of the second input section; at least one of a first capacitive element provided between the first power supply line and the first input section, or between the second power supply line and the first input section, and a second capacitive element provided between the first power supply line and the second input section, or between the second power supply line and the second input section; and at least one of a first adjustment section that can adjust the capacitance of the first capacitive element and a second adjustment section that can adjust the capacitance of the second capacitive element.

[0026] An imaging device according to one aspect of the present disclosure includes: a first power supply line transmitting a first power supply voltage; a second power supply line transmitting a second power supply voltage different from the first power supply voltage; an input unit that inputs a signal corresponding to a differential voltage between a reference signal and a pixel signal, the reference signal being compared with a pixel signal from a pixel that photoelectrically converts light into a pixel signal; a first path that assumes a voltage state corresponding to the voltage of the input unit; and an output unit connected to the first path, a comparison circuit that logically inverts an output signal from the output unit based on the voltage of the input unit; a first capacitance element provided between the first power supply line and the input unit or between the second power supply line and the input unit; and a first adjustment unit that is capable of adjusting the capacitance of the first capacitance element.

[0027] FIG. 1 is a block diagram showing a schematic configuration example of an imaging device according to a first embodiment. FIG. 2 is a conceptual diagram showing an example of an imaging device in which a semiconductor chip in a pixel region and a semiconductor chip in a peripheral circuit region are stacked. FIG. 3 is a diagram showing a more detailed configuration example of an imaging device. FIG. 4 is a circuit diagram showing a configuration example of a comparator according to a first embodiment. FIG. 5 is a diagram showing a configuration example of a capacitive element adjustment unit. FIG. 6 is a diagram showing a configuration example of a capacitive element adjustment unit according to a fifth embodiment. FIG. 7 is a circuit diagram showing a configuration example of a comparator according to an eighth embodiment. FIG. 8 is a diagram showing a configuration example of a capacitive element adjustment unit. FIG. 9 is a diagram showing a configuration example of a capacitive element adjustment unit according to a tenth embodiment. FIG. 11 is a diagram showing a configuration example of a capacitive element adjustment unit according to an eleventh embodiment. FIG. 12 is a diagram showing a configuration example of a capacitive element adjustment unit according to a twelfth embodiment. 13. A diagram showing an example of the configuration of an adjuster of a capacitance element according to a 13th embodiment. A circuit diagram showing an example of the configuration of a comparator according to a 14th embodiment. A circuit diagram showing an example of the configuration of a capacitance element according to a 15th embodiment. A circuit diagram showing an example of the configuration of a capacitance element according to a 16th embodiment. A block diagram showing an example of a schematic configuration of a vehicle control system. An explanatory diagram showing an example of the installation positions of a vehicle outside information detection unit and an imaging unit. A circuit diagram showing an example of the configuration of a capacitance element according to a 17th embodiment. A circuit diagram showing an example of the configuration of a capacitance element according to an 18th embodiment. A circuit diagram showing an example of the configuration of a capacitance element according to a 19th embodiment. A circuit diagram showing an example of the configuration of a capacitance element according to a 20th embodiment. A circuit diagram showing an example of the configuration of a capacitance element according to a 21st embodiment. A circuit diagram showing an example of the configuration of a capacitance element according to a 22nd embodiment. A circuit diagram showing an example of the configuration of a capacitance element according to a 23rd embodiment. A circuit diagram showing an example of the configuration of a capacitance element according to a 24th embodiment. A circuit diagram showing an example of the configuration of a capacitance element according to a 25th embodiment. A circuit diagram showing an example of the configuration of a capacitance element according to a 26th embodiment. A circuit diagram showing an example of the configuration of a capacitance element according to a 27th embodiment. A circuit diagram showing an example of the configuration of a capacitance element according to a 28th embodiment. 29. A circuit diagram showing a configuration example of a capacitive element according to a twenty-ninth embodiment. 30. A circuit diagram showing a configuration example of a capacitive element according to a thirty-first embodiment.

[0028] Hereinafter, specific embodiments to which the present technology is applied will be described in detail with reference to the drawings. The drawings are schematic or conceptual, and the proportions of each part are not necessarily the same as those in reality. In the specification and drawings, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0029] 1 is a block diagram showing a schematic configuration example of an image pickup apparatus according to Embodiment 1. The image pickup apparatus 1 can be used, for example, in a CIS such as an in-vehicle distance measuring device.

[0030] The imaging device 1 has a pixel region 21 provided on a semiconductor substrate (not shown) and a peripheral circuit section provided on the same semiconductor substrate. The peripheral circuit section is composed of, for example, a vertical drive section 22, a column processing section 23, a horizontal drive section 24, a system control section 25, a signal processing section 26, a data storage section 27, etc.

[0031] The pixel region 21 has a plurality of pixels 10 arranged two-dimensionally in a matrix of rows and columns. Each pixel 10 generates an electric charge according to the amount of light it receives and outputs a signal according to the electric charge. That is, each pixel 10 performs photoelectric conversion on the incident light and outputs a signal (pixel signal) according to the resulting electric charge. Note that the row direction is the horizontal direction in FIG. 1 and the column direction is the vertical direction.

[0032] In the pixel region 21, a pixel drive line 28 is wired in the row direction for each pixel row in the matrix-like pixel array, and two vertical signal lines VSL are wired in the column direction for each pixel column. For example, the pixel drive line 28 transmits a drive signal for driving the pixels 10 when reading out a signal. Note that although FIG. 1 shows the pixel drive line 28 as a single line, the number of pixel drive lines 28 is not limited to one. One end of the pixel drive line 28 is connected to an output terminal of the vertical drive unit 22 corresponding to each row.

[0033] The vertical drive unit 22 is configured with a shift register, an address decoder, etc., and drives each pixel 10 in the pixel region 21 simultaneously for all pixels or in row units, etc. In other words, the vertical drive unit 22, together with the system control unit 25 that controls the vertical drive unit 22, configures a drive unit that controls the operation of each pixel 10 in the pixel region 21.

[0034] Detection signals output from each pixel 10 in a pixel row in response to drive control by the vertical drive unit 22 are input to the column processing unit 23 through vertical signal lines VSL. The column processing unit 23 performs predetermined signal processing on the detection signals output from each pixel 10 through the vertical signal lines VSL, and temporarily stores the processed detection signals. Specifically, the column processing unit 23 performs signal processing such as noise removal processing and AD (Analog-to-Digital) conversion processing.

[0035] The horizontal driving unit 24 is configured with a shift register, an address decoder, etc., and sequentially selects unit circuits corresponding to pixel columns in the column processing unit 23. By selective scanning by the horizontal driving unit 24, detection signals that have been signal-processed for each unit circuit in the column processing unit 23 are sequentially output.

[0036] The system control unit 25 is composed of a timing generator that generates various timing signals, and controls the driving of the vertical driving unit 22, column processing unit 23, horizontal driving unit 24, etc. based on the various timing signals generated by the timing generator.

[0037] The signal processing unit 26 has an arithmetic processing function and performs various signal processing such as arithmetic processing based on the detection signal output from the column processing unit 23. For example, the signal processing unit 26 includes a data storage unit 27 that temporarily stores data required for signal processing in the signal processing unit 26.

[0038] Incidentally, all or part of the peripheral circuit section may be provided on a substrate separate from the pixel region 21. In this case, the substrate for all or part of the peripheral circuit section and the substrate for the pixel region 21 may be bonded together for wiring bonding (Cu-Cu bonding).

[0039] 2 is a conceptual diagram showing an example of an imaging device 1 in which a semiconductor chip 511 of the pixel region 21 and a semiconductor chip 512 of the peripheral circuit unit are stacked. In this way, the imaging device 1 may be configured with two stacked semiconductor chips 511 and 512.

[0040] The pixel region 21 of the semiconductor chip 511 and the peripheral circuit section of the semiconductor chip 512 may be electrically connected using, for example, through electrodes such as TSVs (Through Silicon Vias) provided in the via regions 513 and 514. Alternatively, the two semiconductor chips may be bonded together (Cu-Cu bonding) so that the wiring of the semiconductor chip 511 in the pixel region 21 contacts the wiring of the semiconductor chip 511 in the peripheral circuit section. Furthermore, the pixel region 21 and part of the peripheral circuit section may be configured as one semiconductor chip, and the remaining components may be configured as other semiconductor chips. The number of stacked semiconductor chips may be three or more.

[0041] 3 is a diagram showing a more detailed example configuration of the imaging device. The imaging device 1 includes a noise cancellation device 11, a power supply unit 12, a pixel 10, a DAC circuit 100, capacitors C3 and C4, a comparator CM1, and a constant current source V2. The pixel 10 is one of a plurality of pixels 10 arranged two-dimensionally. The noise cancellation device 11, the power supply unit 12, the DAC circuit 100, the capacitors C3 and C4, the comparator CM1, and the constant current source V2 are components included in a signal processing unit 26.

[0042] The noise cancellation device 11 samples and holds (hereinafter referred to as S / H) the voltage of the power supply unit 12 to obtain a DC component, converts the DC component into a current, adjusts the gain, and then superimposes the current on a ramp signal RMP output by the DAC circuit 100 and inputs the signal to the comparator CM1, thereby removing (canceling) noise caused by power supply fluctuations (hereinafter also referred to as power supply noise).

[0043] The power supply unit 12 is a power supply that supplies power to the pixels 10 via a power supply line 12 a. The power supply unit 12 also supplies the power to the pixels 10 to the noise cancellation device 11.

[0044] The pixel 10 includes transistors t1 to t5, which are MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and capacitors C1 and C2. Of the transistors t1 to t5, transistors t1 to t3 are P-type MOSFETs, and transistors t4 and t5 are N-type MOSFETs. Transistors t1 to t3 may also be N-type MOSFETs.

[0045] The source of transistor t1 is connected to power supply line 12a of power supply unit 12, and the drain of transistor t1 is connected to the connection node of the source of transistor t2, capacitor C1, and constant current source V1. The drain of transistor t2 is connected to the connection node of the drain of transistor t3, the gate of transistor t4, and capacitor C2. The source of transistor t3 is connected to power supply line 12a. The drain of transistor t4 is connected to the power supply line, and the source of transistor t4 is connected to the drain of transistor t5. The source of transistor t5 is connected to capacitor C3 and constant current source V2.

[0046] The DAC circuit 100 inputs a ramp signal RMP to the inverting input terminal of a comparator CM1. This ramp signal RMP is used as a reference signal for A / D (Analog to Digital) conversion of pixel signals output from the pixels 10. The DAC circuit 100 includes a constant voltage source V3, such as a band gap reference (BGR), transistors t100 to t106, resistors R100 and R101, and an amplifier AMP1. Of the transistors t100 to t105, transistors t100, t101, t104, and t105 are P-type MOSFETs, and transistors t102, t103, and t106 are N-type MOSFETs.

[0047] The source of transistor t100 is connected to a predetermined power supply line, and the drain of transistor t100 is connected to the drain of transistor t106. Amplifier AMP1 has a non-inverting input terminal connected to a constant voltage source V3, and an inverting input terminal connected to one end of resistor R100 and the source of transistor t106. The source of transistor t101 is connected to a predetermined power supply line. The drain of transistor t101 is connected to the drain of transistor t102 and is connected between its gate and the gate of transistor t103. The source of transistor t102 is connected to a ground line. The source of transistor t103 is connected to a ground line. The drain of transistor t103 is connected to the drain of transistor t104 and is connected between the gate of transistor t104 and the gate of transistor t105. The source of transistor t104 is connected to a predetermined power supply line. The source of the transistor t105 is connected to a predetermined power supply line, and the drain of the transistor t105 is connected between the comparator CM1 and the resistor R101.

[0048] The comparator CM1 has a non-inverting input terminal (hereinafter also referred to as a positive terminal) to which a pixel signal is input from the pixel 10, and a non-inverting input terminal (hereinafter also referred to as a negative terminal) to which a signal in which the noise cancellation signal of the noise cancellation device 1 is superimposed on the ramp signal RMP of the DAC circuit 100 is input.

[0049] That is, the pixel signal containing power supply noise is input to the positive terminal of the comparator CM1, and the ramp signal RMP on which a signal identical to the power supply noise generated by the noise cancellation device 1 is superimposed is input to the negative terminal. As a result, the power supply noise contained in the pixel signal is cancelled in phase in the comparator CM.

[0050] However, high-frequency power supply noise is mixed into the comparator CM1 due to parasitic capacitance between wires, and the noise cancellation device 11 alone cannot remove high-frequency power supply noise from the comparator CM1.

[0051] Therefore, the imaging device 1 according to this embodiment includes a comparator CM1 as shown in FIG.

[0052] 4 is a circuit diagram showing an example of the configuration of a comparator according to the first embodiment. The comparator CM1 includes a first power supply line Lvdd, a second power supply line Lvss, a first input unit IN_DAC, a second input unit IN_VSL, transistors M1 to M7, and capacitance elements Cin_DAC, Cin_VSL, Cbandw, and Cv ＤＩＦＦ１＿ＶＳＳ , CvDIFFOUT0_VSS, Cout, and an output section DIFF_VOUT0. ＤＩＦＦ１＿ＶＤＤ , Cp ＤＩＦＦ１＿ＶＳＳ , CpDIFFOUT0_VDD, and CpDIFFOUT0_VSS are parasitic capacitances, which are shown virtually.

[0053] The first power supply line Lvdd is a power supply line that transmits a high-level voltage VDD. The second power supply line Lvss is a power supply line that transmits a low-level voltage (e.g., ground voltage) VSS. The comparator CM1 is connected between the first power supply line Lvdd and the second power supply line Lvss and receives power.

[0054] The first input unit IN_DAC is connected to the output SFOUT of the DAC circuit 100 via a capacitive element Cin_DAC. The first input unit IN_DAC receives a ramp signal RMP from the DAC circuit 100 as a reference signal to be compared with the pixel signal. The ramp signal RMP is a signal having a slope voltage that decreases or increases at a substantially constant gradient over time.

[0055] The second input section IN_VSL is connected to the vertical signal line VSL via a capacitance element Cin_VSL. The second input section IN_VSL receives a pixel signal from the pixel 10. The pixel signal is an electrical signal of the pixel 10 in a reset state or an electrical signal corresponding to the amount of incident light, and is a substantially constant voltage during one detection.

[0056] The transistors M1, M2, M5, and M7 are, for example, N-type metal oxide semiconductor field effect transistors (MOSFETs), and the transistors M3, M4, and M6 are, for example, P-type MOSFETs.

[0057] The drain of the transistor M1 is connected to the drain and gate of the transistor M3 and the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ The source of the transistor M1 is connected to the drain of the transistor M5 and the source of the transistor M2. The gate of the transistor M1 is connected to the first input IN_DAC.

[0058] The drain of transistor M2 is connected to the drain of transistor M4 and the output DIFF_VOUT0. The source of transistor M2 is connected to the source of transistor M1 and the drain of transistor M5. The gate of transistor M2 is connected to the second input IN_VSL.

[0059] The drain of the transistor M3 is connected to its own gate, the drain of the transistor M1, and the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ The source of the transistor M3 is connected to the first power supply line Lvdd. The gate of the transistor M3 is connected to its own drain and the gate of the transistor M4.

[0060] The drain of the transistor M4 is connected to the drain of the transistor M2 and the output DIFF_VOUT0. The source of the transistor M4 is connected to the first power supply line Lvdd. The gate of the transistor M4 is connected to the gate and drain of the transistor M3. The transistors M3 and M4 form a current mirror circuit.

[0061] The drain of transistor M5 is connected to the sources of transistors M1 and M2. The source of transistor M5 is connected to the second power supply line Lvss. The gate of transistor M5 is connected to the system control unit 25, and a voltage is set so that a constant current flows. Transistors M1 to M5 form a differential circuit. Hereinafter, transistors M1 to M5 as a whole will be referred to as the "differential circuit."

[0062] The drain of transistor M6 is connected to the drain of transistor M7. The source of transistor M6 is connected to the first power supply line Lvdd. The gate of transistor M6 is connected to the drains of transistors M2 and M4, one electrode of capacitive element Cbandw, and one electrode of capacitive element CvDIFFOUT0_VSS. The gate of transistor M6 is connected to the output node DIFF_VOUT0 of the differential circuit. Transistor M6 is controlled to be in a conductive state (ON) or a non-conductive state (OFF) by the voltage of the output node DIFF_VOUT0 of the differential circuit.

[0063] The drain of the transistor M7 is connected to the drain of the transistor M6. The source of the transistor M7 is connected to the second power supply line Lvss. The gate of the transistor M7 is connected to one electrode of the capacitance element Cout, and a predetermined voltage is sampled and held. The transistor M7 functions as a constant current source.

[0064] The transistors M1 to M5 form a differential circuit. The transistors M3 and M4 form a current mirror circuit, causing equal currents to flow through the transistors M1 and M2. The transistors M1 and M3 form a first path P1, causing current to flow from the first power supply line Lvdd to the second power supply line Lvss via the transistor M5. The first path P1 has a voltage state that corresponds to the magnitude relationship between the voltage of the first input section IN_DAC, which is determined by the voltage Vrmp of the ramp signal RMP, and the voltage of the second input section IN_VSL, which is determined by the voltage Vvsl of the vertical signal line VSL (pixel signal voltage). The transistors M2 and M4 form a second path P2, causing current to flow from the first power supply line Lvdd to the second power supply line Lvss via the transistor M5. The second path P2 has a voltage state that corresponds to the magnitude relationship between the voltage of the first input section IN_DAC and the voltage of the second input section IN_VSL. As a result, when the voltage of the first input IN_DAC, which is determined by the voltage Vrmp of the ramp signal RMP, is higher than the voltage of the second input IN_VSL, which is determined by the voltage Vvsl of the vertical signal line VSL, the output DIFF_VOUT0 becomes a high-level voltage, and the transistor M6 becomes non-conductive. As a result, the drain voltage of the transistor M6 (the output voltage of the comparator CM1) becomes a low-level voltage. When the voltage of the first input IN_DAC is lower than the voltage of the second input IN_VSL, the output DIFF_VOUT0 becomes a low-level voltage, and the transistor M6 becomes conductive. As a result, the drain voltage of the transistor M6 (the output voltage of the comparator CM1) becomes a high-level voltage. That is, when the voltage of the first input section IN_DAC crosses from a higher voltage to a lower voltage than the voltage of the second input section IN_VSL, the differential circuits M1 to M5 logically invert the output signal of the output section DIFF_VOUT0 from a high-level voltage to a low-level voltage, thereby logically inverting the output voltage of the comparator CM1 from a low-level voltage to a high-level voltage.

[0065] One electrode of the capacitance element Cbandw is connected to the drains of transistors M2 and M4, the gate of transistor M6, and one electrode of the capacitance element CvDIFFOUT0_VSS. The other electrode of the capacitance element Cbandw is connected to the first power supply line Lvdd. That is, the capacitance element Cbandw is connected between the first power supply line Lvdd and the output section DIFF_VOUT0. The capacitance element Cbandw is a band-limiting capacitance that transmits noise mixed in the power supply voltage VDD of the first power supply line Lvdd to the gate of transistor M6. The noise of the power supply voltage VDD is also transmitted to the source of transistor M6. Therefore, ideally, the noise of the power supply voltage VDD is canceled out by the voltage difference Vgs between the source and gate of transistor M6. In this case, transistor M6 can operate using the voltage of the output section DIFF_VOUT0 of the differential circuits M1 to M5 without relying on the noise of the power supply voltage VDD.

[0066] However, the spacing between adjacent column wirings such as the vertical signal line VSL is narrowed, and the parasitic capacitance that causes PSRR is increased in the comparator CM1. For example, the parasitic capacitance Cp ＤＩＦＦ１＿ＶＤＤ is a parasitic capacitance generated between the first power supply line Lvdd and the connection node DIFF1 of the transistor M3 and the transistor M1. ＤＩＦＦ１＿ＶＳＳ is a parasitic capacitance occurring between the second power supply line Lvss and the node DIFF1. The parasitic capacitance CpDIFFOUT0_VDD is a parasitic capacitance occurring between the first power supply line Lvdd and the output section DIFF_VOUT0. The parasitic capacitance CpDIFFOUT0_VSS is a parasitic capacitance occurring between the second power supply line Lvss and the output section DIFF_VOUT0.

[0067] The parasitic capacitance CpDIFFOUT0_VDD is smaller than the capacitance element Cbandw and is connected in the same way, so it can be regarded as a bandwidth-limiting capacitance and can be ignored. ＤＩＦＦ１＿ＶＳＳ If CvDIFFOUT0_VSS is not provided, the parasitic capacitances CpDIFFOUT0_VDD and Cp ＤＩＦＦ１＿ＶＳＳ and CpDIFFOUT0_VSS cannot be ignored. ＤＩＦＦ１＿ＶＳＳand CpDIFFOUT0_VSS cause noise components (especially high-frequency components) of the power supply voltage VDD to be mixed into the node DIFF1 and the output DIFF_VOUT0. Such high-frequency components of noise cannot be removed by the noise cancellation device 11 and the capacitive element Cbandw.

[0068] Therefore, in this embodiment, the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ and CvDIFFOUT0_VSS. ＤＩＦＦ１＿ＶＳＳ and CvDIFFOUT0_VSS may be a capacitance element such as MOM (Metal Oxide Metal), MIM (Metal Insulator Metal), PIP (Poly-Si Insulator Poly-Si), MOSFET, etc. ＤＩＦＦ１＿ＶＳＳ and CvDIFFOUT0_VSS may be the parasitic capacitance between an element and a wiring, the parasitic capacitance between wirings, the parasitic capacitance between an element and a well, the parasitic capacitance between a wiring and a well, the parasitic capacitance between wells (diffusion capacitance), the parasitic capacitance between a resistive element and a well, etc.

[0069] Capacitance element Cv ＤＩＦＦ１＿ＶＳＳ One electrode of the capacitance element Cv is connected to the drains of the transistors M1 and M3 (node ​​DIFF1). ＤＩＦＦ１＿ＶＳＳ The other electrode of the capacitance element Cv is connected to the second power supply line Lvss. ＤＩＦＦ１＿ＶＳＳ is connected between the node DIFF1 of the first path P1 and the second power line Lvss. ＤＩＦＦ１＿ＶＳＳ is the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ Since the capacitance elements Cv ＤＩＦＦ１＿ＶＳＳ and displays:

[0070] One electrode of the capacitance element CvDIFFOUT0_VSS is connected to the drains of transistors M2 and M4 and the gate of transistor M6 (output section DIFF_VOUT0). The other electrode of the capacitance element CvDIFFOUT0_VSS is connected to the second power supply line Lvss. That is, the capacitance element CvDIFFOUT0_VSS is connected between the second path P2 and the second power supply line Lvss. The parasitic capacitance CpDIFFOUT0_VSS is equal to or smaller than the capacitance element CvDIFFOUT0_VSS and is connected in the same way, so they are collectively referred to as the capacitance element CvDIFFOUT0_VSS.

[0071] Capacitance element Cv ＤＩＦＦ１＿ＶＳＳ and CvDIFFOUT0_VSS are variable capacitances. ＤＩＦＦ１＿ＶＳＳ is the parasitic capacitance Cp ＤＩＦＦ１＿ＶＤＤ The capacitance element CvDIFFOUT0_VSS divides the power supply voltage VDD between the capacitance element Cbandw and the output node DIFF_VOUT0, and adjusts noise that is mixed into the output node DIFF_VOUT0. ＤＩＦＦ１＿ＶＳＳ By adjusting the capacitance of each of the capacitance elements CvDIFFOUT0_VSS and CvDIFFOUT0_VSS, the noise mixed into the node DIFF1 and the output section DIFF_VOUT0 is adjusted. By adjusting the noise mixed into the node DIFF1 and the output section DIFF_VOUT0, the noise of the voltage difference Vgs between the source and gate of the transistor M6 can be canceled. That is, in this embodiment, ＤＩＦＦ１＿ＶＳＳ between the node DIFF1 and the second power supply line Lvss, and the capacitive element CvDIFFOUT0_VSS between the output section DIFF_VOUT0 and the second power supply line Lvss, thereby mixing power supply noise into the node DIFF1 and the output section DIFF_VOUT0, thereby canceling the noise of the power supply voltage VDD at the transistor M6. It is also possible to remove high frequency components of the noise of the power supply voltage VDD.

[0072] For example, if the noise (fluctuation) of the power supply voltage VDD is ΔVDD, the amplitude of the output DIFF_VOUT0 is ΔVDD×(Cbandw) / (Cbandw+CvDIFFVOUT0_VSS). The fluctuation of the voltage difference Vgs between the source and gate of the transistor M6 is ΔVDD×(CvDIFFVOUT0_VSS) / (Cbandw+CvDIFFVOUT0_VSS). The capacitance element Cv ＤＩＦＦ１＿ＶＳＳ That is, a current equivalent to the high-frequency current flowing through the capacitance element CvDIFFVOUT0_VSS flows through the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ The current mirror circuits M3 and M4 copy the current and supply it to the capacitive element CvDIFFVOUT0_VSS. This cancels out the noise component without affecting the operation of the differential circuit, making it possible to reduce fluctuations in the voltage difference Vgs of the transistor M6 to almost zero.

[0073] Capacitance element Cv ＤＩＦＦ１＿ＶＳＳ and the capacitance element CvDIFFVOUT0_VSS may basically be approximately equal. However, noise may be mixed in due to other parasitic capacitances, and in reality, the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ For example, the capacitance element Cv DIFFVOUT0_VSS needs to be adjusted so that the frequency characteristics (frequency-gain characteristics) on the first input section IN_DAC side and the frequency characteristics on the second input section IN_VSL side are equal. ＤＩＦＦ１＿ＶＳＳ and the capacitance element CvDIFFVOUT0_VSS is adjusted, thereby suppressing the PSRR.

[0074] Capacitance element Cv ＤＩＦＦ１＿ＶＳＳ and CvDIFFVOUT0_VSS may be set in a test process before shipping the image pickup device 1. This allows for setting that also accommodates process variations. ＤＩＦＦ１＿ＶＳＳ and CvDIFFVOUT0_VSS may be set to a substantially constant capacitance value depending on the type of the image pickup device 1. In this case, ＤＩＦＦ１＿ＶＳＳ and CvDIFFVOUT0_VSS may be set for each type of image pickup device 1. When setting them before product shipment, the capacitance element Cv ＤＩＦＦ１＿ＶＳＳThe capacitance of the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ and CvDIFFVOUT0_VSS may be set during adjustment after product shipment. ＤＩＦＦ１＿ＶＳＳ The capacitance of CvDIFFVOUT0_VSS can be changed even after shipping.

[0075] FIG. 5 shows the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ 1 is a diagram illustrating an example of a configuration of an adjustment unit for CvDIFFVOUT0_VSS and CvDIFFVOUT0_VSS. The comparator CM1 further includes a switch SW1, a switch SW2, and a register RG. The switch SW1 and the register RG are an example of a first adjustment unit. The switch SW2 and the register RG are an example of a second adjustment unit.

[0076] The switch SW1 is connected to the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ The switch SW1 is connected between the other electrode of the capacitor Cv ＤＩＦＦ１＿ＶＳＳ The other electrode of the capacitance element Cv is selectively connected to either the first power supply line Lvdd or the second power supply line Lvss. ＤＩＦＦ１＿ＶＳＳ When the other electrode of the capacitor Cv is connected to the second power supply line Lvss, ＤＩＦＦ１＿ＶＳＳ 4 and is used for noise cancellation. ＤＩＦＦ１＿ＶＳＳ When the other electrode of the capacitor Cv is connected to the first power supply line Lvdd, ＤＩＦＦ１＿ＶＳＳ is connected to the power supply voltage VDD. In this case, the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ is not used for noise cancellation.

[0077] The switch SW2 is connected between the other electrode of the capacitive element CvDIFFVOUT0_VSS and the power supply lines Lvdd and Lvss. The switch SW2 selectively connects the other electrode of the capacitive element CvDIFFVOUT0_VSS to either the first power supply line Lvdd or the second power supply line Lvss. When the switch SW2 connects the other electrode of the capacitive element CvDIFFVOUT0_VSS to the second power supply line Lvss, the capacitive element CvDIFFVOUT0_VSS is in the state shown in FIG. 4 and is used for noise cancellation. On the other hand, when the switch SW2 connects the other electrode of the capacitive element CvDIFFVOUT0_VSS to the first power supply line Lvdd, the capacitive element CvDIFFVOUT0_VSS is connected to the power supply voltage VDD. In this case, the capacitive element CvDIFFVOUT0_VSS is not used for noise cancellation.

[0078] In this way, the switches SW1 and SW2 are connected to the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ , CvDIFFVOUT0_VSS can be effectively connected or disconnected to node DIFF1 or output DIFF_VOUT0 for noise cancellation.

[0079] The switches SW1 and SW2 may be logic circuits such as, for example, a CMOS (Complementary MOS) inverter, a NAND gate, or a NOR gate.

[0080] The register RG stores control signals for individually switching the switches SW1 and SW2. For example, the register RG stores a digital value with the same number of bits as the number of switches as the control signal. When two switches SW1 and SW2 are provided, the register RG stores a 2-bit digital value corresponding to each of the switches SW1 and SW2 as the control signal. For example, when the digital value is "00", the switches SW1 and SW2 are connected to the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ , CvDIFFVOUT0_VSS to the first power supply line Lvdd. When the digital value is “11”, the switches SW1 and SW2 connect the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ, CvDIFFVOUT0_VSS to the second power supply line Lvss. When the digital value is “10” or “01”, the switches SW1 and SW2 connect the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ , CvDIFFVOUT0_VSS is connected to the first power supply line Lvdd, and the other is connected to the second power supply line Lvss.

[0081] As a result, the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ , CvDIFFVOUT0_VSS is effectively connected or disconnected to node DIFF1 or output DIFF_VOUT0 for noise cancellation.

[0082] Second Embodiment FIG. 6 shows a capacitance element Cv according to a second embodiment. ＤＩＦＦ１＿ＶＳＳ 6 is a diagram illustrating an example of the configuration of an adjustment unit for the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ includes a plurality of partial capacitance elements CvDIFF1_VSS_1 to CvDIFF1_VSS_n (n is an integer of 2 or more).

[0083] One electrode of each of the plurality of partial capacitance elements CvDIFF1_VSS_1 to CvDIFF1_VSS_n is commonly connected to the node DIFF1. The other electrodes of each of the plurality of partial capacitance elements CvDIFF1_VSS_1 to CvDIFF1_VSS_n are connected to the first power supply line Lvdd or the second power supply line Lvss via the corresponding plurality of switches SW1_1 to SW1_n.

[0084] The plurality of switches SW1_1 to SW1_n serving as a first adjustment unit are respectively connected between the other electrodes of the plurality of partial capacitance elements CvDIFF1_VSS_1 to CvDIFF1_VSS_n and the first and second power supply lines Lvdd and Lvss. The plurality of switches SW1_1 to SW1_n selectively connect the other electrodes of the partial capacitance elements CvDIFF1_VSS_1 to CvDIFF1_VSS_n to either the first power supply line Lvdd or the second power supply line Lvss. The plurality of switches SW1_1 to SW1_n are individually controlled to be turned on or off by a control signal from the register RG. As a result, the switches SW1_1 to SW1_n change the number of partial capacitance elements connected between the node DIFF1 and the second power supply line Lvss, and adjust the capacitance elements Cv ＤＩＦＦ１＿ＶＳＳ The capacity can be adjusted.

[0085] Furthermore, the capacitive element CvDIFFVOUT0_VSS includes a plurality of partial capacitive elements CvDIFFVOUT0_VSS_1 to CvDIFFVOUT0_VSS_n.

[0086] One electrode of each of the plurality of partial capacitance elements CvDIFFVOUT0_VSS_1 to CvDIFFVOUT0_VSS_n is commonly connected to the output section DIFF_VOUT0. The other electrodes of each of the plurality of partial capacitance elements CvDIFFVOUT0_VSS_1 to CvDIFFVOUT0_VSS_n are connected to the first power supply line Lvdd or the second power supply line Lvss via a corresponding plurality of switches SW2_1 to SW2_n.

[0087] The plurality of switches SW2_1 to SW2_n serving as a second adjustment unit are connected between the other electrodes of the plurality of partial capacitance elements CvDIFFVOUT0_VSS_1 to CvDIFFVOUT0_VSS_n and the first and second power supply lines Lvdd and Lvss, respectively. The plurality of switches SW2_1 to SW2_n selectively connect the other electrodes of the partial capacitance elements CvDIFFVOUT0_VSS_1 to CvDIFFVOUT0_VSS_n to either the first power supply line Lvdd or the second power supply line Lvss. The plurality of switches SW2_1 to SW2_n are individually controlled to be turned on or off by control signals from the register RG. As a result, the switches SW2_1 to SW2_n selectively connect partial capacitance elements between the output section DIFF_VOUT0 and the second power supply line Lvss, and by changing the number of partial capacitance elements connected, the capacitance of the capacitance element CvDIFFVOUT0_VSS can be adjusted.

[0088] The switches SW1_1 to SW1_n and SW2_1 to SW2_n may be logic circuits such as CMOS inverters, NAND gates, and NOR gates.

[0089] The register RG stores control signals for switching the switches SW1_1 to SW1_n and SW2_1 to SW2_n. For example, the register RG stores a digital value with the same number of bits as the number of switches as a control signal. Therefore, the register RG only needs to store a 2×n-bit digital value. This allows the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ , CvDIFFVOUT0_VSS are variable capacitance elements that can be changed in units of partial capacitance elements.

[0090] Capacitance element Cv ＤＩＦＦ１＿ＶＳＳ and CvDIFFOUT0_VSS, the noise mixed into the node DIFF1 and the output DIFF_VOUT0 is adjusted. By adjusting the noise mixed into the node DIFF1 and the output DIFF_VOUT0, the noise of the voltage difference Vgs between the source and gate of the transistor M6 can be canceled.

[0091] Other configurations of the second embodiment are the same as those of the first embodiment, and therefore the second embodiment can also achieve the same effects as the first embodiment.

[0092] Third Embodiment FIG. 7 shows a capacitance element Cv according to a third embodiment. ＤＩＦＦ１＿ＶＳＳ 7 is a diagram illustrating an example of the configuration of an adjustment unit for the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ Switches SW1 and SW11 are provided on both sides of the capacitance element CvDIFFVOUT0_VSS. Switches SW2 and SW12 are provided on both sides of the capacitance element CvDIFFVOUT0_VSS.

[0093] The switches SW1 and SW2 may have the same configuration as those in FIG.

[0094] The switch SW11 is connected to the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ and the node DIFF1, and the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ The switch SW11 is connected between one electrode of the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ The switch SW11 selectively switches one electrode of the switch SW11 to either the node DIFF1 or the first power supply line Lvdd. The switch SW11 is controlled to be turned on or off by a control signal from the register RG.

[0095] The switches SW1 and SW11 are controlled in synchronization. ＤＩＦＦ１＿ＶＳＳ When the other electrode of the capacitor Cv is connected to the first power supply line Lvdd, the switch SW11 ＤＩＦＦ１＿ＶＳＳ One electrode of the capacitance element Cv is connected to the first power supply line Lvdd. ＤＩＦＦ１＿ＶＳＳ is not connected to node DIFF1 and is not used for noise cancellation.

[0096] On the other hand, the switch SW1 ＤＩＦＦ１＿ＶＳＳ When the other electrode of the capacitor Cv is connected to the second power supply line Lvss, the switch SW11 ＤＩＦＦ１＿ＶＳＳ One electrode of the capacitance element Cv is connected to the node DIFF1. ＤＩＦＦ１＿ＶＳＳ is connected between the node DIFF1 and the second power supply line Lvss and is used for noise cancellation.

[0097] The switch SW12 is connected between one electrode of the capacitance element CvDIFFVOUT0_VSS and the output section DIFF_VOUT0, and between one electrode of the capacitance element CvDIFFVOUT0_VSS and the first power supply line Lvdd. The switch SW12 selectively switches one electrode of the capacitance element CvDIFFVOUT0_VSS to either the output section DIFF_VOUT0 or the first power supply line Lvdd. The switch SW12 is controlled to be turned on or off by a control signal from the register RG.

[0098] The switches SW2 and SW12 are controlled synchronously. When the switch SW2 connects the other electrode of the capacitive element CvDIFFVOUT0_VSS to the first power supply line Lvdd, the switch SW12 connects one electrode of the capacitive element CvDIFFVOUT0_VSS to the first power supply line Lvdd. As a result, the capacitive element CvDIFFVOUT0_VSS is not connected to the output section DIFF_VOUT0 and is not used for noise cancellation.

[0099] On the other hand, when the switch SW2 connects the other electrode of the capacitive element CvDIFFVOUT0_VSS to the second power supply line Lvss, the switch SW12 connects one electrode of the capacitive element CvDIFFVOUT0_VSS to the output section DIFF_VOUT0. As a result, the capacitive element CvDIFFVOUT0_VSS is connected between the output section DIFF_VOUT0 and the second power supply line Lvss and is used for noise cancellation.

[0100] The switches SW11 and SW12 may be implemented by, for example, a logic circuit such as a CMOS inverter, an NMOS switch, a PMOS switch, or a CMOS switch.

[0101] The register RG stores a control signal for switching the switches SW1, SW2, SW11, and SW12. In this case, the control signal may be a 4-bit digital value.

[0102] As a result, the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ, CvDIFFVOUT0_VSS is effectively connected or disconnected to node DIFF1 or output DIFF_VOUT0 for noise cancellation.

[0103] In the example of FIG. 7, the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ , CvDIFFVOUT0_VSS is not used for noise cancellation, ＤＩＦＦ１＿ＶＳＳ , CvDIFFVOUT0_VSS can be separated from DIFF1 and DIFF_VOUT0. This reduces the capacitive load and has the effect of reducing the inversion delay of the comparator CM1. ＤＩＦＦ１＿ＶＳＳ , CvDIFFVOUT0_VSS is not used for noise cancellation, ＤＩＦＦ１＿ＶＳＳ , CvDIFFVOUT0_VSS are connected to the first power supply line Lvdd, ＤＩＦＦ１＿ＶＳＳ 7, the switches SW1 and SW2 are omitted, and the other electrode of the capacitance element CvDIFFVOUT0_VSS and the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ The other electrode may be directly connected to the first power supply line Lvdd.

[0104] Other configurations of the third embodiment are the same as those of the first embodiment, and therefore the third embodiment can also achieve the same effects as the first embodiment.

[0105] Fourth Embodiment FIG. 8 shows a capacitance element Cv according to a fourth embodiment. ＤＩＦＦ１＿ＶＳＳ 8 is a diagram illustrating an example of the configuration of an adjustment unit for the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ 7. Switches SW1 and SW11 are provided on both sides of the capacitance element CvDIFFVOUT0_VSS, respectively. Switches SW2 and SW12 are provided on both sides of the capacitance element CvDIFFVOUT0_VSS, respectively. In these respects, this is the same as the example in FIG.

[0106] However, in the example of FIG. 8, the switch SW11 is connected to the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ The switch SW11 is connected between one electrode of the capacitance element Cv ＤＩＦＦ１＿ＶＳＳOne electrode of the first power supply line Lvss is selectively switched to either the node DIFF1 or the second power supply line Lvss.

[0107] Capacitance element Cv ＤＩＦＦ１＿ＶＳＳ When the capacitor Cv is not used for noise cancellation, the switch SW1 ＤＩＦＦ１＿ＶＳＳ The other electrode of the capacitor Cv is connected to the second power supply line Lvss, and the switch SW11 is connected to the capacitor Cv ＤＩＦＦ１＿ＶＳＳ One electrode of the first electrode is connected to the second power supply line Lvss.

[0108] On the other hand, the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ When used for noise cancellation, the switch SW1 ＤＩＦＦ１＿ＶＳＳ The switch SW11 connects the other electrode of the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ One electrode of the capacitance element Cv is connected to the node DIFF1. ＤＩＦＦ１＿ＶＳＳ is connected between the node DIFF1 and the second power supply line Lvss and is used for noise cancellation.

[0109] The switch SW12 is connected between one electrode of the capacitance element CvDIFFVOUT0_VSS and the second power supply line Lvss. The switch SW12 selectively switches one electrode of the capacitance element CvDIFFVOUT0_VSS to either the output section DIFF_VOUT0 or the second power supply line Lvss.

[0110] When the capacitive element CvDIFFVOUT0_VSS is not used for noise cancellation, the switch SW2 connects the other electrode of the capacitive element CvDIFFVOUT0_VSS to the second power supply line Lvss, and the switch SW12 connects one electrode of the capacitive element CvDIFFVOUT0_VSS to the second power supply line Lvss.

[0111] On the other hand, when the capacitive element CvDIFFVOUT0_VSS is used for noise cancellation, the switch SW2 keeps the other electrode of the capacitive element CvDIFFVOUT0_VSS connected to the second power supply line Lvss, while the switch SW12 connects one electrode of the capacitive element CvDIFFVOUT0_VSS to the output unit DIFF_VOUT0. As a result, the capacitive element CvDIFFVOUT0_VSS is connected between the output unit DIFF_VOUT0 and the second power supply line Lvss, and is used for noise cancellation.

[0112] In the example of FIG. 8, the switches SW1 and SW2 are omitted, and the other electrode of the capacitance element CvDIFFVOUT0_VSS and the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ The other electrode may be directly connected to the second power line Lvss.

[0113] Other configurations of the example in FIG. 8 may be the same as those of the example in FIG.

[0114] The third and fourth embodiments may be combined with the second embodiment.

[0115] Fifth Embodiment FIG. 9 shows a capacitance element Cv ＤＩＦＦ１＿ＶＳＳ 10 is a diagram illustrating an example of the configuration of an adjustment unit for CvDIFFVOUT0_VSS and CvDIFFVOUT0_VSS. The fifth embodiment is a combination of the second and third embodiments.

[0116] Capacitance element Cv ＤＩＦＦ１＿ＶＳＳ comprises a plurality of partial capacitance elements CvDIFF1_VSS_1 to CvDIFF1_VSS_n, and the capacitance element CvDIFFVOUT0_VSS comprises a plurality of partial capacitance elements CvDIFFVOUT0_VSS_1 to CvDIFFVOUT0_VSS_n.

[0117] In this case, a plurality of switches SW1_1 to SW1_n and a plurality of switches SW11_1 to SW11_n are provided corresponding to the partial capacitance elements CvDIFF1_VSS_1 to CvDIFF1_VSS_n.

[0118] The configuration of the multiple switches SW1_1 to SW1_n may be the same as that of the second embodiment.

[0119] The multiple switches SW11_1 to SW11_n are connected between one electrode of each of the partial capacitance elements CvDIFF1_VSS_1 to CvDIFF1_VSS_n and the node DIFF1, and between one electrode of each of the capacitance elements CvDIFF1_VSS_1 to CvDIFF1_VSS_n and the first power supply line Lvdd. The multiple switches SW11_1 to SW11_n selectively connect one electrode of each of the partial capacitance elements CvDIFF1_VSS_1 to CvDIFF1_VSS_n to either the node DIFF1 or the first power supply line Lvdd. The multiple switches SW11_1 to SW11_n are individually controlled to be turned on or off by a control signal from the register RG. The switches SW11_1 to SW11_n are controlled in synchronization with the switches SW1_1 to SW1_n, respectively. As a result, the switches SW1_1 to SW1_n and the switches SW11_1 to SW11_n change the number of partial capacitance elements connected between the node DIFF1 and the second power line Lvss, and the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ The capacity can be adjusted.

[0120] When the partial capacitive element CvDIFF1_VSS_k (k=1 to n) is not used for noise cancellation, the switch SW1_k connects the other electrode of the partial capacitive element CvDIFF1_VSS_k to the first power supply line Lvdd, and the switch SW11_k connects one electrode of the partial capacitive element CvDIFF1_VSS_k to the first power supply line Lvdd. As a result, the partial capacitive element CvDIFF1_VSS_k is not connected to the node DIFF1 and is not used for noise cancellation.

[0121] On the other hand, when the partial capacitive element CvDIFF1_VSS_k is used for noise cancellation, the switch SW1_k connects the other electrode of the partial capacitive element CvDIFF1_VSS_k to the second power supply line Lvss, and the switch SW11_k connects one electrode of the partial capacitive element CvDIFF1_VSS_k to the node DIFF 1. As a result, the partial capacitive element CvDIFF1_VSS_k is connected between the node DIFF1 and the second power supply line Lvss, and is used for noise cancellation.

[0122] Furthermore, a plurality of switches SW2_1 to SW2_n and a plurality of switches SW12_1 to SW12_n are provided corresponding to the partial capacitance elements CvDIFFVOUT0_1 to CvDIFFVOUT0_n.

[0123] The configuration of the multiple switches SW2_1 to SW2_n may be the same as that of the second embodiment.

[0124] The multiple switches SW12_1 to SW12_n are connected between one electrode of each of the partial capacitance elements CvDIFFVOUT0_VSS_1 to CvDIFFVOUT0_VSS_n and the output section DIFF_VOUT0, and between one electrode of each of the capacitance elements CvDIFFVOUT0_VSS_n and the first power supply line Lvdd. The multiple switches SW12_1 to SW12_n selectively connect one electrode of each of the partial capacitance elements CvDIFFVOUT0_VSS_1 to CvDIFFVOUT0_VSS_n to either the output section DIFF_VOUT0 or the first power supply line Lvdd. The multiple switches SW12_1 to SW12_n are individually controlled to be turned on or off by a control signal from the register RG. The switches SW12_1 to SW12_n are controlled in synchronization with the switches SW2_1 to SW2_n, respectively, so that the switches SW2_1 to SW2_n and the switches SW12_1 to SW12_n can change the number of partial capacitance elements connected between the output section DIFF_VOUT0 and the second power supply line Lvss, thereby adjusting the capacitance of the capacitance element CvDIFFVOUT0_VSS.

[0125] When the partial capacitance element CvDIFFVOUT0_VSS_k (k is any value from 1 to n) is not used for noise cancellation, the switch SW2_k connects the other electrode of the partial capacitance element CvDIFFVOUT0_VSS_k to the first power supply line Lvdd, and the switch SW12_k connects one electrode of the partial capacitance element CvDIFFVOUT0_VSS_k to the first power supply line Lvdd.

[0126] On the other hand, when the partial capacitance element CvDIFFVOUT0_VSS_k is used for noise cancellation, the switch SW2_k connects the other electrode of the partial capacitance element CvDIFFVOUT0_VSS_k to the second power supply line Lvss, and the switch SW12_k connects one electrode of the partial capacitance element CvDIFFVOUT0_VSS_k to the output section DIFF_VOUT0. As a result, the partial capacitance element CvDIFFVOUT0_VSS_k is connected between the output section DIFF_VOUT0 and the second power supply line Lvss, and is used for noise cancellation.

[0127] The fifth embodiment can obtain the effects of the second and third embodiments.

[0128] Sixth Embodiment FIG. 10 shows a capacitance element Cv according to a sixth embodiment. ＤＩＦＦ１＿ＶＳＳ 10 is a diagram illustrating an example of the configuration of an adjustment unit for CvDIFFVOUT0_VSS and CvDIFFVOUT0_VSS. The sixth embodiment is a combination of the second and fourth embodiments.

[0129] 10, the switches SW11_1 to SW11_n are connected between one electrode of each of the capacitance elements CvDIFF1_VSS_1 to CvDIFF1_VSS_n and the second power supply line Lvss. The switches SW11_1 to SW11_n selectively switch one electrode of each of the capacitance elements CvDIFF1_VSS_1 to CvDIFF1_VSS_n to either the node DIFF1 or the second power supply line Lvss.

[0130] When the capacitive element CvDIFF1_VSS_k is not used for noise cancellation, the switch SW1_k connects the other electrode of the capacitive element CvDIFF1_VSS_k to the second power supply line Lvss, and the switch SW11_k connects one electrode of the capacitive element CvDIFF1_VSS_k to the second power supply line Lvss.

[0131] On the other hand, when the capacitive element CvDIFF1_VSS_k is used for noise cancellation, the switch SW1_k keeps the other electrode of the capacitive element CvDIFF1_VSS_k connected to the second power supply line Lvss, while the switch SW11_k connects one electrode of the capacitive element CvDIFF1_VSS_k to the node DIFF1. As a result, the capacitive element CvDIFF1_VSS_k is connected between the node DIFF1 and the second power supply line Lvss, and is used for noise cancellation.

[0132] The switch SW12_k is connected between one electrode of the capacitance element CvDIFFVOUT0_VSS_k and the second power supply line Lvss. The switch SW12_k selectively switches one electrode of the capacitance element CvDIFFVOUT0_VSS_k to either the output section DIFF_VOUT0 or the second power supply line Lvss.

[0133] When the capacitive element CvDIFFVOUT0_VSS_k is not used for noise cancellation, the switch SW2_k connects the other electrode of the capacitive element CvDIFFVOUT0_VSS_k to the second power supply line Lvss, and the switch SW12_k connects one electrode of the capacitive element CvDIFFVOUT0_VSS_k to the second power supply line Lvss.

[0134] On the other hand, when the capacitive element CvDIFFVOUT0_VSS_k is used for noise cancellation, the switch SW2_k keeps the other electrode of the capacitive element CvDIFFVOUT0_VSS_k connected to the second power supply line Lvss, while the switch SW12_k connects one electrode of the capacitive element CvDIFFVOUT0_VSS_k to the output unit DIFF_VOUT0. As a result, the capacitive element CvDIFFVOUT0_VSS_k is connected between the output unit DIFF_VOUT0 and the second power supply line Lvss, and is used for noise cancellation.

[0135] In the example of FIG. 10, the switches SW1_1 to SW1_n and SW2_1 to SW2_n may be omitted, and the other electrodes of the capacitive elements CvDIFF1_VSS_1 to CvDIFFVOUT0_VSS_n and the other electrodes of the capacitive elements CvDIFF1_VSS_1 to CvDIFF1_VSS_n may be directly connected to the second power line Lvss.

[0136] Other configurations of the example in FIG. 10 may be the same as those of the example in FIG.

[0137] 11 is a circuit diagram showing an example of the configuration of a comparator according to a seventh embodiment. In the seventh embodiment, a transistor M5 functioning as a constant current source is connected between the first power supply line Lvdd and the sources of the transistors M1 and M2. Transistors M3 and M4 functioning as a current mirror are connected between the second power supply line Lvss and the drains of the transistors M1 and M2. A capacitance element Cout and a transistor M7 are also provided on the first power supply line Lvdd side.

[0138] Accordingly, the conductivity types of the transistors M1 to M7 are reversed from those of the first embodiment: the transistors M1, M2, M5 and M7 are P-type MOSFETs, and the transistors M3, M4 and M6 are N-type MOSFETs.

[0139] In addition, the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ is connected between the node DIFF1 and the first power supply line Lvdd, and CvDIFFVOUT0_VSS is connected between the output section DIFF_VOUT0 and the first power supply line Lvdd. The capacitive element Cbandw is connected between the output section DIFF_VOUT0 and the second power supply line Lvss.

[0140] Other configurations of the seventh embodiment may be the same as those of the first embodiment.

[0141] In such a configuration, power supply noise is mixed in from the first power supply line Lvdd, but the effect of the present technology is not lost.

[0142] Capacitance element Cv ＤＩＦＦ１＿ＶＳＳ and CvDIFFOUT0_VSS, the noise mixed into the node DIFF1 and the output DIFF_VOUT0 is adjusted. By adjusting the noise mixed into the node DIFF1 and the output DIFF_VOUT0, the noise of the voltage difference Vgs between the source and gate of the transistor M6 can be canceled.

[0143] The capacitance element CvＤＩＦＦ１＿ＶＳＳ That is, a current equivalent to the high-frequency current flowing through the capacitance element CvDIFFVOUT0_VSS flows through the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ The current mirror circuits M3 and M4 copy the current and supply it to the capacitive element CvDIFFVOUT0_VSS. This cancels out the noise component without affecting the operation of the differential circuit, making it possible to reduce fluctuations in the voltage difference Vgs of the transistor M6 to almost zero.

[0144] Capacitance element Cv ＤＩＦＦ１＿ＶＳＳ and the capacitance element CvDIFFVOUT0_VSS may basically be approximately equal. However, noise may be mixed in due to other parasitic capacitances, and in reality, the capacitance element Cv ＤＩＦＦ１＿ＶＳＳ For example, the capacitance element Cv DIFFVOUT0_VSS needs to be adjusted so that the frequency characteristics (frequency-gain characteristics) on the first input section IN_DAC side and the frequency characteristics on the second input section IN_VSL side are equal. ＤＩＦＦ１＿ＶＳＳ and the capacitance element CvDIFFVOUT0_VSS is adjusted, thereby suppressing the PSRR.

[0145] Capacitance element Cv ＤＩＦＦ１＿ＶＳＳ and CvDIFFOUT0_VSS, and the configuration of the switches and registers serving as the capacitance adjustment unit may be any of the configurations shown in Figures 5 to 10. However, the first power supply line Lvdd and the second power supply line Lvss must be interchanged.

[0146] 12 is a circuit diagram showing a configuration example of a comparator according to an eighth embodiment. ＤＩＦＦ１＿ＶＳＳ and instead of CvDIFFOUT0_VSS, a capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ and Cv ＶＳＬ＿ＶＤＤ is provided.

[0147] Capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ One electrode of the capacitance element Cv is connected to the gate of the transistor M1 via the capacitance element Cin_DAC. ＳＦＯＵＴ＿ＶＤＤ The other electrode of the capacitance element Cv is connected to the first power supply line Lvdd. ＳＦＯＵＴ＿ＶＤＤis connected between the input section IN_DAC (input of the ramp signal RMP) of the differential circuits M1 to M5 and the first power supply line Lvdd.

[0148] Capacitance element Cv ＶＳＬ＿ＶＤＤ One electrode of the capacitance element Cv is connected to the gate of the transistor M2 via the capacitance element Cin_VSL. ＶＳＬ＿ＶＤＤ The other electrode of the capacitance element Cv is connected to the first power supply line Lvdd. ＶＳＬ＿ＶＤＤ is connected between the input section IN_VSL (input of pixel signals) of the differential circuits M1 to M5 and the first power supply line Lvdd.

[0149] Capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ and Cv ＶＳＬ＿ＶＤＤ is a variable capacitance. ＳＦＯＵＴ＿ＶＤＤ is the parasitic capacitance Cp ＳＦＯＵＴ＿ＶＳＳ The power supply voltage VDD is divided between the parasitic capacitance Cp ＳＦＯＵＴ＿ＶＳＳ is the parasitic capacitance between the input section IN_DAC and the second power supply line Lvss. ＶＳＬ＿ＶＤＤ is the parasitic capacitance Cp ＶＳＬ＿ＶＳＳ The power supply voltage VDD is divided between the capacitor Cv and the capacitor Cv, and noise that gets mixed into the input section IN_VSL is adjusted. ＳＦＯＵＴ＿ＶＤＤ and Cv ＶＳＬ＿ＶＤＤ The noise mixed into the input sections IN_DAC and IN_VSL can be adjusted by adjusting the capacitance of each of these. By adjusting the noise mixed into the input sections IN_DAC and IN_VSL, the noise of the voltage difference Vgs between the source and gate of the transistor M6 can be canceled.

[0150] For example, if the noise (fluctuation) of the power supply voltage VDD is ΔVDD, the amplitude of the input section IN_DAC is ΔVDD × * (Cv ＳＦＯＵＴ＿ＶＤＤ ) / (CV ＳＦＯＵＴ＿ＶＤＤ +Cp ＳＦＯＵＴ＿ＶＳＳ ) The amplitude of the input IN_VSL is ΔVDD×(Cp ＶＳＬ＿ＶＤＤ ) / (Cp ＶＳＬ＿ＶＤＤ +Cp ＶＳＬ＿ＶＳＳ )

[0151] The amplitude difference between the inputs IN_DAC and IN_VSL due to fluctuations in the power supply voltage is converted into a difference current in the differential pair M1 and M2, and the current mirror circuits M3 and M4 output the difference current of the differential pair M1 and M2 to the output DIFF_VOUT0. The output difference current is converted into a voltage by the output resistance of the differential circuit and the band-limiting capacitance Cbandw, causing fluctuations in the voltage difference Vgs of the transistor M6. The capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ and Cv ＶＳＬ＿ＶＤＤ By adjusting the magnitude of the noise component, a high-frequency noise current flows through the inputs IN_DAC and IN_VSL. This cancels out the noise component without affecting the operation of the differential circuit, and the fluctuation of the voltage difference Vgs of the transistor M6 can be reduced to almost zero.

[0152] Capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ and the capacitance element Cv ＶＳＬ＿ＶＤＤ However, noise may be mixed in due to other parasitic capacitances, and in reality, the capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ and the capacitance element Cv ＶＳＬ＿ＶＤＤ For example, the capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ and the capacitance element Cv ＶＳＬ＿ＶＤＤ This reduces the PSRR. ＳＦＯＵＴ＿ＶＤＤ An example is shown in which the capacitance element CvSFOUT_VDD is connected to the first input section IN_DAC and the capacitance element CvVSL_VDD is connected to the second input section IN_VSL, but the same effect can be obtained by connecting the capacitance element CvSFOUT_VDD to the gate of transistor M1 and the capacitance element CvVSL_VDD to the gate of transistor M2.

[0153] Other configurations of the eighth embodiment may be the same as those of the first embodiment, so that the eighth embodiment can obtain the same effects as those of the first embodiment.

[0154] FIG. 13 shows the capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ and Cv ＶＳＬ＿ＶＤＤ1 is a diagram showing an example of the configuration of an adjustment unit of the first embodiment. A switch SW1 and a register RG are an example of a first adjustment unit. A switch SW2 and a register RG are an example of a second adjustment unit. The configurations of the switches SW1, SW2, and the register RG may be the same as those in the first embodiment. However, the operations of the switches SW1 and SW2 are reversed from those in the first embodiment.

[0155] The switch SW1 is connected to the capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ The switch SW1 is connected between the other electrode of the capacitor Cv ＳＦＯＵＴ＿ＶＤＤ The other electrode of the capacitance element Cv is selectively connected to either the first power supply line Lvdd or the second power supply line Lvss. ＳＦＯＵＴ＿ＶＤＤ When the other electrode of the capacitor Cv is connected to the first power supply line Lvdd, ＳＦＯＵＴ＿ＶＤＤ 12 and is used for noise cancellation. ＳＦＯＵＴ＿ＶＤＤ When the other electrode of the capacitor Cv is connected to the second power supply line Lvss, ＳＦＯＵＴ＿ＶＤＤ is connected to the ground voltage VSS. In this case, the capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ is not used for noise cancellation.

[0156] The switch SW2 is connected to the capacitance element Cv ＶＳＬ＿ＶＤＤ The switch SW2 is connected between the other electrode of the capacitance element Cv ＶＳＬ＿ＶＤＤ The other electrode of the capacitance element Cv is selectively connected to either the first power supply line Lvdd or the second power supply line Lvss. ＶＳＬ＿ＶＤＤ When the other electrode of the capacitor Cv is connected to the first power supply line Lvdd, ＶＳＬ＿ＶＤＤ 12 and is used for noise cancellation. ＶＳＬ＿ＶＤＤ When the other electrode of the capacitor Cv is connected to the second power supply line Lvss, ＶＳＬ＿ＶＤＤ is connected to the ground voltage VSS. In this case, the capacitance element Cv ＶＳＬ＿ＶＤＤ is not used for noise cancellation.

[0157] In this way, the switches SW1 and SW2 are connected to the capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ , CvＶＳＬ＿ＶＤＤ can be effectively connected or disconnected to the input IN_DAC or IN_VSL for noise cancellation.

[0158] The register RG stores control signals for individually switching the switches SW1 and SW2. For example, the register RG stores a digital value with the same number of bits as the number of switches as the control signal. When two switches SW1 and SW2 are provided, the register RG stores a 2-bit digital value corresponding to each of the switches SW1 and SW2 as the control signal. For example, when the digital value is "00", the switches SW1 and SW2 are connected to the capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ , Cv ＶＳＬ＿ＶＤＤ When the digital value is “11”, the switches SW1 and SW2 connect the capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ , Cv ＶＳＬ＿ＶＤＤ When the digital value is “10” or “01”, the switches SW1 and SW2 connect the capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ , Cv ＶＳＬ＿ＶＤＤ One of these is connected to the second power supply line Lvss, and the other is connected to the first power supply line Lvdd.

[0159] As a result, the capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ , Cv ＶＳＬ＿ＶＤＤ is effectively connected to or disconnected from the input IN_DAC or IN_VSL for noise cancellation.

[0160] Similarly, the adjustment units of FIGS. 6 to 10 may be applied to the comparator CM1 of the eighth embodiment.

[0161] Ninth Embodiment FIG. 14 shows a capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ and Cv ＶＳＬ＿ＶＤＤ FIG. 1 is a diagram illustrating a configuration example of an adjustment unit of a capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ comprises a plurality of partial capacitance elements CvSFOUT_VDD_1 to CvSFOUT_VDD_n.

[0162] One electrode of each of the plurality of partial capacitance elements CvSFOUT_VD_1 to CvSFOUT_VD_n is commonly connected to the input unit IN_DAC, and the other electrodes of each of the plurality of partial capacitance elements CvSFOUT_VD_1 to CvSFOUT_VD_n are connected to the first power supply line Lvdd or the second power supply line Lvss via the corresponding plurality of switches SW1_1 to SW1_n.

[0163] The configuration of the plurality of switches SW1_1 to SW1_n may be the same as that of the second embodiment. As a result, the switches SW1_1 to SW1_n change the number of partial capacitance elements connected between the input section IN_DAC and the first power supply line Lvdd, and ＳＦＯＵＴ＿ＶＤ The capacity can be adjusted.

[0164] In addition, the capacitance element Cv ＶＳＬ＿ＶＤＤ is a plurality of partial capacitance elements Cv ＶＳＬ＿ＶＤＤ＿１ ~CV ＶＳＬ＿ＶＤＤ＿ｎ Equipped with.

[0165] A plurality of partial capacitance elements Cv ＶＳＬ＿ＶＤＤ＿１ ~CV ＶＳＬ＿ＶＤＤ＿ｎ One electrode of each of the partial capacitance elements Cv is commonly connected to the input section IN_VSL. ＶＳＬ＿ＶＤＤ＿１ ~CV ＶＳＬ＿ＶＤＤ＿ｎ The other electrodes of the transistors are connected to the first power supply line Lvdd or the second power supply line Lvss via a plurality of corresponding switches SW2_1 to SW2_n.

[0166] The configuration of the plurality of switches SW2_1 to SW2_n may be the same as that of the second embodiment. As a result, the switches SW2_1 to SW2_n selectively connect partial capacitance elements between the input section IN_VSL and the first power supply line Lvdd, and by changing the number of partial capacitance elements connected, the capacitance element Cv ＶＳＬ＿ＶＤＤ＿１ ~CV ＶＳＬ＿ＶＤＤ＿ｎ The capacity can be adjusted.

[0167] The configuration of the register RG may be the same as that of the second embodiment. ＶＳＬ＿ＶＤＤ＿１ ~CV ＶＳＬ＿ＶＤＤ＿ｎis used for noise cancellation by being connected to the first power supply line Lvdd, and is not used for noise cancellation by being connected to the second power supply line Lvss.

[0168] Other configurations of the ninth embodiment are the same as those of the second embodiment, and therefore the ninth embodiment can achieve the same effects as the second embodiment.

[0169] Tenth Embodiment FIG. 15 shows a capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ and Cv ＶＳＬ＿ＶＤＤ 15 is a diagram illustrating an example of the configuration of the adjustment unit of the capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ The switches SW1 and SW11 are provided on both sides of the capacitance element Cv ＶＳＬ＿ＶＤＤ Switches SW2 and SW12 are provided on both sides of the switch.

[0170] The switches SW1, SW11, SW2, and SW12 may have the same configuration as those shown in FIG.

[0171] The switch SW1 is connected to the capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ The other electrode of the capacitor Cv is connected to the first power supply line Lvdd, and the switch SW11 is ＳＦＯＵＴ＿ＶＤＤ When one electrode of the capacitor Cv is connected to the first power supply line Lvdd, ＳＦＯＵＴ＿ＶＤＤ is not used for noise cancellation.

[0172] On the other hand, the switch SW1 ＳＦＯＵＴ＿ＶＤＤ The other electrode of the capacitance element Cv is connected to the first power supply line Lvdd. ＳＦＯＵＴ＿ＶＤＤ When one electrode of the capacitor Cv is connected to the input section IN_DAC, ＳＦＯＵＴ＿ＶＤＤ is connected between the input unit IN_DAC and the first power supply line Lvdd and is used for noise cancellation.

[0173] The switch SW2 is connected to the capacitance element Cv ＶＳＬ＿ＶＤＤ The other electrode of the capacitor Cv is connected to the first power supply line Lvdd, and the switch SW12 is ＶＳＬ＿ＶＤＤ When one electrode of the capacitor Cv is connected to the first power supply line Lvdd, ＶＳＬ＿ＶＤＤ is not used for noise cancellation.

[0174] On the other hand, the switch SW2 ＶＳＬ＿ＶＤＤ While the other electrode of the capacitor Cv is connected to the first power supply line, the switch SW12 ＶＳＬ＿ＶＤＤ When one electrode of the capacitor Cv is connected to the input terminal IN_VSL, ＶＳＬ＿ＶＤＤ is connected between the input section IN_VSL and the first power supply line Lvdd and is used for noise cancellation.

[0175] Other configurations of the tenth embodiment are the same as those of the third embodiment. Therefore, the tenth embodiment can achieve the same effects as those of the third embodiment. Note that the switches SW1 and SW2 are omitted and the capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ The other electrode and the capacitance element Cv ＶＳＬ＿ＶＤＤ The other electrode may be directly connected to the first power supply line Lvdd.

[0176] Eleventh Embodiment FIG. 16 shows a capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ and Cv ＶＳＬ＿ＶＤＤ 16 is a diagram illustrating an example of the configuration of an adjustment unit of the capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ The switches SW1 and SW11 are provided on both sides of the capacitance element Cv ＶＳＬ＿ＶＤＤ Switches SW2 and SW12 are provided on both sides of the switch.

[0177] The switch SW11 is connected to the capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ The switch SW11 is connected between one electrode of the capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ One of the electrodes is selectively switched to either the input section IN_DAC or the second power supply line Lvss.

[0178] Capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ When the capacitor Cv is not used for noise cancellation, the switch SW1 ＳＦＯＵＴ＿ＶＤＤ The other electrode of the capacitor Cv is connected to the second power supply line Lvss, and the switch SW11 is connected to the capacitor Cv ＳＦＯＵＴ＿ＶＤＤ One electrode of the first electrode is connected to the second power supply line Lvss.

[0179] On the other hand, the capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ When used for noise cancellation, the switch SW1 is connected to the capacitance element Cv ＳＦＯＵＴ＿ＶＤＤThe other electrode of the capacitor Cv is connected to the first power supply line Lvdd, and the switch SW11 is connected to the capacitor Cv ＳＦＯＵＴ＿ＶＤＤ One electrode of the capacitance element Cv is connected to the input section IN_DAC. ＳＦＯＵＴ＿ＶＤＤ is connected between the input unit IN_DAC and the first power supply line Lvdd and is used for noise cancellation.

[0180] The switch SW12 is connected to the capacitance element Cv ＶＳＬ＿ＶＤＤ The switch SW12 is connected between one electrode of the capacitance element Cv ＶＳＬ＿ＶＤＤ One electrode of the first power supply line Lvss is selectively switched to either the input section IN_VSL or the second power supply line Lvss.

[0181] Capacitance element Cv ＶＳＬ＿ＶＤＤ When the capacitor Cv is not used for noise cancellation, the switch SW2 ＶＳＬ＿ＶＤＤ The other electrode of the capacitor Cv is connected to the second power supply line Lvss, and the switch SW12 is connected to the capacitor Cv ＶＳＬ＿ＶＤＤＳ One electrode of the first electrode is connected to the second power supply line Lvss.

[0182] On the other hand, the capacitance element Cv ＶＳＬ＿ＶＤＤ When used for noise cancellation, the switch SW2 is connected to the capacitance element Cv ＶＳＬ＿ＶＤＤ The other electrode of the capacitor Cv is connected to the first power supply line Lvdd, and the switch SW12 is connected to the capacitor Cv ＶＳＬ＿ＶＤＤ One electrode of the capacitance element Cv is connected to the input section IN_VSL. ＶＳＬ＿ＶＤＤ is connected between the input section IN_VSL and the first power supply line Lvdd and is used for noise cancellation.

[0183] Other configurations of the eleventh embodiment are the same as those of the fourth embodiment, and therefore the eleventh embodiment can achieve the same effects as the fourth embodiment.

[0184] Twelfth Embodiment FIG. 17 shows a capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ and Cv ＶＳＬ＿ＶＤＤ FIG. 2 is a diagram illustrating a configuration example of an adjustment unit.

[0185] Capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ has a plurality of partial capacitance elements CvSFOUT_VDD_1 to CvSFOUT_VDD_n, and the capacitance element CvＶＳＬ＿ＶＤＤ is a plurality of partial capacitance elements Cv ＶＳＬ＿ＶＤＤ＿１ ~CV ＶＳＬ＿ＶＤＤ＿ｎ Equipped with.

[0186] The configurations of the plurality of switches SW1_1 to SW1_n, SW2_1 to SW2_n, SW11_1 to SW11_n, and SW12_1 to SW12_n may be the same as those in the fifth embodiment.

[0187] The switches SW1_1 to SW1_n and the switches SW11_1 to SW11_n change the number of partial capacitance elements connected between the input section IN_DAC and the first power supply line Lvdd, and the capacitance element C ＳＦＯＵＴ＿ＶＤＤ The capacity can be adjusted.

[0188] When the partial capacitive element CvSFOUT_VDD_k is not used for noise cancellation, the switch SW1_k connects the other electrode of the partial capacitive element CvSFOUT_VDD_k to the first power supply line Lvdd, and the switch SW11_k connects one electrode of the partial capacitive element CvSFOUT_VDD_k to the first power supply line Lvdd. This prevents the partial capacitive element CvSFOUT_VDD_k from being used for noise cancellation.

[0189] On the other hand, when the partial capacitive element CvSFOUT_VDD_k is used for noise cancellation, the switch SW1_k keeps the other electrode of the partial capacitive element CvSFOUT_VDD_k connected to the first power supply line Lvdd, while the switch SW11_k connects one electrode of the partial capacitive element CvSFOUT_VDD_k to the input unit IN_DAC. This allows the partial capacitive element CvSFOUT_VDD_k to be used for noise cancellation.

[0190] The switches SW2_1 to SW2_n and the switches SW12_1 to SW12_n change the number of partial capacitance elements connected between the input section IN_VSL and the first power supply line Lvdd, and the capacitance element Cv ＶＳＬ＿ＶＤＤ The capacity can be adjusted.

[0191] Partial capacitance element Cv ＶＳＬ＿ＶＤＤ＿ｋ When the switch SW2_k is not used for noise cancellation, the partial capacitance element Cv ＶＳＬ＿ＶＤＤ＿ｋThe other electrode of the switch SW12_k is connected to the first power supply line Lvdd, and the switch SW12_k is connected to the partial capacitance element Cv ＶＳＬ＿ＶＤＤ＿ｋ One electrode of the first power supply line Lvdd is connected to the first power supply line Lvdd.

[0192] On the other hand, the partial capacitance element Cv ＶＳＬ＿ＶＤＤ＿ｋ When used for noise cancellation, the switch SW2_k is connected to the partial capacitance element Cv ＶＳＬ＿ＶＤＤ＿ｋ While the other electrode of the switch SW12_k is connected to the first power supply line Lvdd, the switch SW12_k ＶＳＬ＿ＶＤＤ＿ｋ One electrode of the partial capacitance element Cv is connected to the input section IN_VSL. ＶＳＬ＿ＶＤＤ＿ｋ is used for noise cancellation.

[0193] Other configurations of the twelfth embodiment are the same as those of the fifth embodiment, and therefore the twelfth embodiment can achieve the same effects as the fifth embodiment.

[0194] Thirteenth Embodiment FIG. 18 shows a capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ and Cv ＶＳＬ＿ＶＤＤ FIG. 2 is a diagram illustrating a configuration example of an adjustment unit.

[0195] 18, the switches SW11_1 to SW11_n are connected between one electrode of the capacitance elements CvSFOUT_VDD_1 to CvSFOUT_VDD_n and the second power line Lvss. ＶＳＬ＿ＶＤＤ＿１ ~CV ＶＳＬ＿ＶＤＤ＿ｎ One of the electrodes is selectively switched to either the input section IN_DAC or the second power supply line Lvss.

[0196] When the capacitive element CvSFOUT_VDD_k is not used for noise cancellation, the switch SW1_k connects the other electrode of the capacitive element CvSFOUT_VDD_k to the second power supply line Lvss, and the switch SW11_k connects one electrode of the capacitive element CvSFOUT_VDD_k to the second power supply line Lvss.

[0197] On the other hand, when the capacitive element CvSFOUT_VDD_k is used for noise cancellation, the switch SW1_k connects the other electrode of the capacitive element CvSFOUT_VDD_k to the first power supply line Lvdd, and the switch SW11_k connects one electrode of the capacitive element CvSFOUT_VDD_k to the input unit IN_DAC. This allows the capacitive element CvSFOUT_VDD_k to be used for noise cancellation.

[0198] The switch SW12_k is connected to the capacitance element Cv ＶＳＬ＿ＶＤＤ＿ｋ The switch SW12_k is connected between one electrode of the capacitance element Cv ＶＳＬ＿ＶＤＤ＿ｋ One electrode of the first power supply line Lvss is selectively switched to either the input section IN_VSL or the second power supply line Lvss.

[0199] Capacitance element Cv ＶＳＬ＿ＶＤＤ＿ｋ When the switch SW2_k is not used for noise cancellation, the capacitance element Cv ＶＳＬ＿ＶＤＤ＿ｋ The other electrode of the capacitor Cv is connected to the second power supply line Lvss, and the switch SW12_k is connected to the capacitor Cv ＶＳＬ＿ＶＤＤ＿ｋ One electrode of the first electrode is connected to the second power supply line Lvss.

[0200] On the other hand, the capacitance element Cv ＶＳＬ＿ＶＤＤ＿ｋ When the switch SW2_k is used for noise cancellation, the capacitance element Cv ＶＳＬ＿ＶＤＤ＿ｋ The other electrode of the capacitor Cv is connected to the first power supply line Lvdd, and the switch SW12_k is connected to the capacitor Cv ＶＳＬ＿ＶＤＤ＿ｋ One electrode of the capacitance element Cv is connected to the input section IN_VSL. ＶＳＬ＿ＶＤＤ＿ｋ is used for noise cancellation.

[0201] Other configurations of the thirteenth embodiment are the same as those of the sixth embodiment, and therefore the thirteenth embodiment can achieve the same effects as the sixth embodiment.

[0202] Fourteenth Embodiment FIG. 19 is a circuit diagram showing an example of the configuration of a comparator according to a fourteenth embodiment.

[0203] The fourteenth embodiment is a differential circuit according to the seventh embodiment, in which the capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ and Cv ＶＳＬ＿ＶＤＤThe configurations and operations of the differential circuits M1 to M5 and the transistors M6 and M7 may be the same as those of the seventh embodiment. ＳＦＯＵＴ＿ＶＤＤ and Cv ＶＳＬ＿ＶＤＤ The configuration and operation of the eighth embodiment may be the same as those of the eighth embodiment.

[0204] In addition, the capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ and Cv ＶＳＬ＿ＶＤＤ The configuration of (2) may be any of the configurations shown in FIGS.

[0205] Other configurations of the fourteenth embodiment may be the same as those of the seventh or eighth embodiment, so the fourteenth embodiment can obtain the same effects as the seventh or eighth embodiment.

[0206] Fifteenth Embodiment FIG. 20 is a circuit diagram showing an example of the configuration of a capacitive element according to a fifteenth embodiment.

[0207] The capacitance element Cbandw includes a plurality of partial capacitance elements Cbandw0 and Cbandw1 and transistors M11 to M14.

[0208] One end of the partial capacitance element Cbandw0 is connected to the first power supply line Lvdd. The other end of the partial capacitance element Cbandw0 is connected to the first power supply line Lvdd via a transistor M11 and to the output section DIFF_VOUT0 via a transistor M12.

[0209] One end of the partial capacitance element Cbandw1 is connected to the first power supply line Lvdd. The other end of the partial capacitance element Cbandw1 is connected to the first power supply line Lvdd via a transistor M13 and to the output section DIFF_VOUT0 via a transistor M14.

[0210] The transistor M11 is connected to the first power supply line Lvdd and the other end of the partial capacitance element Cbandw0. The transistor M12 is connected to the output section DIFF_VOUT0 and the other end of the partial capacitance element Cbandw0. The transistor M13 is connected to the first power supply line Lvdd and the other end of the partial capacitance element Cbandw1. The transistor M14 is connected to the output section DIFF_VOUT0 and the other end of the partial capacitance element Cbandw1. The transistors M11 and M12 receive inverse logic control signals SW1 and XSW1 at their gates and are controlled to be turned on / off in a complementary manner. The transistors M13 and M14 receive inverse logic control signals SW2 and XSW2 at their gates and are controlled to be turned on / off in a complementary manner. The transistors M11 to M14 are configured, for example, by P-type MOSFETs.

[0211] When the control signals SW1 and XSW1 are logic high and logic low, respectively, the partial capacitive element Cbandw0 is connected between the first power supply line Lvdd and the output section DIFF_VOUT0, and the capacitance of the capacitive element Cbandw increases.

[0212] When the control signals SW1 and XSW1 are logic low and logic high, respectively, both ends of the partial capacitance element Cbandw0 are connected to the first power supply line Lvdd, and therefore the partial capacitance element Cbandw0 is not added to the capacitance element Cbandw.

[0213] When the control signals SW2 and XSW2 are logic high and logic low, respectively, the partial capacitive element Cbandw1 is connected between the first power supply line Lvdd and the output section DIFF_VOUT0, and the capacitance of the capacitive element Cbandw increases.

[0214] When the control signals SW2 and XSW2 are logic low and logic high, respectively, both ends of the partial capacitance element Cbandw1 are connected to the first power supply line Lvdd, and therefore the partial capacitance element Cbandw1 is not added to the capacitance element Cbandw.

[0215] In this way, the capacitance element Cbandw can be adjusted as a variable capacitance. Note that the number of partial capacitance elements included in the capacitance element Cbandw is not limited, and may be three or more.

[0216] Sixteenth Embodiment FIG. 21 is a circuit diagram showing a configuration example of a capacitive element according to a sixteenth embodiment.

[0217] In the fifteenth embodiment, when the transistors M12 and M14 are both turned on, the partial capacitance elements Cbandw0 and Cbandw1 are added to the capacitance element Cbandw. In this case, the gates of the transistors M12 and M14 are connected to the second power line Lvss, so the capacitance element CvDIFFOUT0_VSS in FIG. 4 appears to be larger.

[0218] In this way, in order to suppress the apparent change in the capacitance element CvDIFFOUT0_VSS due to the variation of the capacitance element Cbandw, in the sixteenth embodiment, the transistors M15 and M16 are connected to the node DIFF1.

[0219] The transistors M15 and M16 are P-type MOSFETs of the same size as the transistors M12 and M14. The sources and drains of the transistors M15 and M16 are connected to the node DIFF1. The gates of the transistors M15 and M16 receive the control signals XSW1 and XSW2, respectively, in the same manner as the gates of the transistors M12 and M14.

[0220] This allows the transistors M12 and M14 to turn on, and thereby the capacitance component added to the output node DIFF_VOUT0 can be added to the node DIFF1 by the transistors M15 and M16. As a result, it is possible to suppress changes in the apparent capacitance of the capacitive element CvDIFFOUT0_VSS due to the on / off switching of the transistors M12 and M14.

[0221] (Application Example to a Mobile Body) The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0222] FIG. 22 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0223] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 22, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0224] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0225] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0226] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0227] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0228] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0229] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0230] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0231] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12030 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0232] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 22, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0233] FIG. 23 is a diagram showing an example of the installation position of the imaging unit 12031.

[0234] In FIG. 23, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0235] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0236] 23 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0237] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0238] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0239] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0240] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0241] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the image capturing unit 12031, etc., among the components described above.

[0242] 24 is a circuit diagram showing a configuration example of a capacitance element according to a seventeenth embodiment. ＳＦＯＵＴ＿ＶＤＤ is connected between the first power supply line Lvdd and the first input section IN_DAC (the gate of the transistor M1), and the capacitance element Cv ＶＳＬ＿ＶＤＤ is connected between the first power supply line Lvdd and the second input section IN_VSL (the gate of the transistor M2). The other configurations of the seventeenth embodiment may be the same as those of the eighth embodiment.

[0243] In this way, noise can be canceled by adjusting the capacitance between the first power supply line Lvdd and the first input section IN_DAC and / or the capacitance between the first power supply line Lvdd and the second input section IN_VSL. Therefore, the seventeenth embodiment can obtain the same effects as the eighth embodiment.

[0244] 25 is a circuit diagram showing a configuration example of a capacitance element according to an eighteenth embodiment. ＳＦＯＵＴ＿ＶＤＤ is connected between the first power supply line Lvdd and the first input section IN_DAC (the gate of the transistor M1), and the capacitance element Cv ＶＳＬ＿ＶＤＤ is connected between the first power supply line Lvdd and the second input section IN_VSL (the gate of the transistor M2). The other configurations of the eighteenth embodiment may be the same as those of the fourteenth embodiment.

[0245] In this way, noise can be canceled by adjusting the capacitance between the first power supply line Lvdd and the first input section IN_DAC and / or the capacitance between the first power supply line Lvdd and the second input section IN_VSL. Therefore, the eighteenth embodiment can obtain the same effects as the fourteenth embodiment.

[0246] 26 is a circuit diagram showing a configuration example of a capacitance element according to a 19th embodiment. ＳＦＯＵＴ＿ＶＳＳ is connected between the second power supply line Lvss and the first input section IN_DAC (input of the ramp signal RMP), and the capacitance element Cv ＶＳＬ＿ＶＳＳ is connected between the second power supply line Lvss and the second input section IN_VSL (input of pixel signals). The other configurations of the nineteenth embodiment may be the same as those of the eighth embodiment.

[0247] In this way, noise can be canceled by adjusting the capacitance between the second power supply line Lvss and the input section IN_DAC and / or the capacitance between the second power supply line Lvss and the second input section IN_VSL. Therefore, the 19th embodiment can obtain the same effects as the 8th embodiment.

[0248] 20th Embodiment FIG. 27 is a circuit diagram showing a configuration example of a capacitance element according to a 20th embodiment. ＳＦＯＵＴ＿ＶＳＳ is connected between the second power supply line Lvss and the first input section IN_DAC (the gate of the transistor M1), and the capacitance element Cv ＶＳＬ＿ＶＳＳis connected between the second power supply line Lvss and the second input section IN_VSL (the gate of the transistor M2). The other configurations of the twentieth embodiment may be the same as those of the eighth embodiment.

[0249] In this way, noise can be canceled by adjusting the capacitance between the second power supply line Lvss and the input section IN_DAC and / or the capacitance between the second power supply line Lvss and the second input section IN_VSL. Therefore, the twentieth embodiment can obtain the same effects as the eighth embodiment.

[0250] 21st Embodiment FIG. 28 is a circuit diagram showing a configuration example of a capacitance element according to a 21st embodiment. ＳＦＯＵＴ＿ＶＳＳ is connected between the second power supply line Lvss and the first input section IN_DAC (input of the ramp signal RMP), and the capacitance element Cv ＶＳＬ＿ＶＳＳ is connected between the second power supply line Lvss and the second input section IN_VSL (input of pixel signals). The other configurations of the twenty-first embodiment may be the same as those of the fourteenth embodiment.

[0251] In this way, noise can be canceled by adjusting the capacitance between the second power supply line Lvss and the input section IN_DAC and / or the capacitance between the second power supply line Lvss and the second input section IN_VSL. Therefore, the twenty-first embodiment can obtain the same effects as the fourteenth embodiment.

[0252] 29 is a circuit diagram showing a configuration example of a capacitance element according to a 22nd embodiment. ＳＦＯＵＴ＿ＶＳＳ is connected between the second power supply line Lvss and the first input section IN_DAC (the gate of the transistor M1), and the capacitance element Cv ＶＳＬ＿ＶＳＳ is connected between the second power supply line Lvss and the second input section IN_VSL (the gate of the transistor M2). The other configurations of the twenty-second embodiment may be the same as those of the fourteenth embodiment.

[0253] In this way, noise can be canceled by adjusting the capacitance between the second power supply line Lvss and the input section IN_DAC and / or the capacitance between the second power supply line Lvss and the second input section IN_VSL. Therefore, the twenty-second embodiment can obtain the same effects as the fourteenth embodiment.

[0254] 23rd Embodiment Fig. 30 is a circuit diagram showing an example of the configuration of a capacitive element according to the 23rd embodiment. In the 23rd embodiment, a differential signal corresponding to a differential voltage between the ramp signal RMP and the pixel signal from the vertical signal line VSL is input to the input section DIFF_DAC (the gate of the transistor M1). A reference signal corresponding to a reference voltage VREF is input to the second input section IN_REF. Differential circuits M1 to M5 compare the differential signal with the reference signal. Differential circuits M1 to M5 invert the logic of the output DIFF_VOUT0 when the differential signal intersects with the reference signal.

[0255] The capacitance element Cin_VSL is connected between the vertical signal line VSL and the gate of the transistor M1. The pixel signal is input to the input unit IN_VSL and input to the gate of the transistor M1 via the capacitance element Cin_VSL. At this time, the ramp signal RMP is input to the input unit IN_DAC and input to the gate of the transistor M1 via the capacitance element Cin_DAC. As a result, a differential signal corresponding to the differential voltage between the ramp signal RMP and the pixel signal is input to the input unit DIFF_DAC.

[0256] The capacitive element Cin_REF is connected between the system control unit 25 and the gate of the transistor M2. The reference voltage VREF is input to the second input part IN_REF via the capacitive element Cin_REF.

[0257] For example, the differential circuits M1 to M5 invert the logic of the output DIFF_VOUT0 when the differential signal becomes smaller than the reference signal.By making the reference signal approach zero, the differential circuits M1 to M5 can invert the logic of the output DIFF_VOUT0 when the differential signal approaches zero.

[0258] Other configurations of the 23rd embodiment may be similar to those of the seventh embodiment, and therefore the 23rd embodiment can achieve the same effects as the seventh embodiment.

[0259] 31 is a circuit diagram showing a configuration example of a capacitance element according to a 24th embodiment. In the 24th embodiment, two capacitance elements Cv ＳＦＯＵＴ＿ＶＤＤ and one capacitance element Cv ＶＳＬ＿ＶＤＤ This is an example in which one capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ is connected between the first power supply line Lvdd and the input section IN_DAC (input of the ramp signal RMP). ＳＦＯＵＴ＿ＶＤＤ is connected between the first power supply line Lvdd and the pixel signal input section IN_VSL (a node between the vertical signal line VSL and the capacitance element Cin_VSL). A differential signal corresponding to a differential voltage between the ramp signal RMP and the pixel signal is input to the input section IN_DAC_VSL. Therefore, in order to cancel noise, the capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ and a capacitance element Cv connected to the input section IN_VSL on the vertical signal line VSL side. ＳＦＯＵＴ＿ＶＤＤ Each of these may be adjusted.

[0260] Capacitance element Cv ＲＥＦ＿ＶＤＤ is connected between the first power supply line Lvdd and the input part of the reference voltage VREF.

[0261] Other configurations of the 24th embodiment may be the same as those of the 23rd embodiment, and therefore the 24th embodiment can achieve the same effects as the 23rd embodiment.

[0262] 32 is a circuit diagram showing a configuration example of a capacitance element according to a 25th embodiment. ＳＦＯＵＴ＿ＶＤＤ is connected between the first power supply line Lvdd and the gate of the transistor M1. ＲＥＦ＿ＶＤＤis connected between the first power supply line Lvdd and the gate of the transistor M2. The other configurations of the 25th embodiment may be the same as those of the 23rd embodiment. Even with this configuration, the 25th embodiment can achieve the same effects as the 23rd embodiment.

[0263] 33 is a circuit diagram showing a configuration example of a capacitance element according to the 26th embodiment. ＳＦＯＵＴ＿ＶＤＤ , Cv ＲＥＦ＿ＶＤＤ Instead, a capacitance element Cv connected to the second power line Lvss ＳＦＯＵＴ＿ＶＳＳ and Cv ＲＥＦ＿ＶＳＳ This is an example in which the capacitance element Cv ＳＦＯＵＴ＿ＶＳＳ is connected between the second power supply line Lvss and the gate of the transistor M1. ＲＥＦ＿ＶＳＳ is connected between the second power supply line Lvss and the gate of the transistor M2. The other configurations of the 26th embodiment may be the same as those of the 25th embodiment. Therefore, even with this configuration, the 26th embodiment can achieve the same effects as the 25th embodiment.

[0264] 34 is a circuit diagram showing a configuration example of a capacitance element according to the 27th embodiment. The 27th embodiment is a circuit diagram showing a configuration example of a capacitance element according to the 24th embodiment. ＳＦＯＵＴ＿ＶＤＤ and one capacitance element Cv ＲＥＦ＿ＶＤＤ Instead, two capacitance elements Cv ＳＦＯＵＴ＿ＶＳＳ and one capacitance element Cv ＲＥＦ＿ＶＳＳを This is an example of application. ＳＦＯＵＴ＿ＶＳＳ is connected between the second power supply line Lvss and the input section IN_DAC of the ramp signal RMP. ＳＦＯＵＴ＿ＶＤＤ is connected between the second power supply line Lvss and the pixel signal input section IN_VSL. A differential signal corresponding to the differential voltage between the ramp signal RMP and the pixel signal is input to the input section DIFF_DAC. Therefore, in order to cancel noise, a capacitance element Cv ＳＦＯＵＴ＿ＶＳＳ and a capacitance element Cv connected to the input section IN_VSL on the vertical signal line VSL side. ＲＥＦ＿ＶＳＳ Each of these may be adjusted.

[0265] Capacitance element Cv ＲＥＦ＿ＶＳＳ is connected between the second power supply line Lvss and the input of the reference voltage VREF.

[0266] Other configurations of the 27th embodiment may be the same as those of the 24th embodiment. Even with this configuration, the 24th embodiment can obtain the same effects as the 24th embodiment.

[0267] 4, 11, 12, 19, 24 to 34, the capacitance element Cin_DAC can be omitted. In this case, the capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ or Cv ＳＦＯＵＴ＿ＶＳＳ However, the capacitance value setting of the capacitance element Cv ＳＦＯＵＴ＿ＶＤＤ or Cv ＳＦＯＵＴ＿ＶＳＳ If the capacitance value is set appropriately, the effect of the present disclosure can be obtained.

[0268] 35 is a circuit diagram showing a configuration example of a capacitive element according to the 28th embodiment. The 28th embodiment is a single-type amplifier, and is configured with a single first path P1 including transistors M1 and M5. Transistors M2 to M4, i.e., the second path P2, are omitted.

[0269] The configuration on the input section DIFF_DAC side may be the same as the configuration in Fig. 33 or 34. That is, the capacitive element Cin_DAC is connected between the gate of the transistor M1 and the input section IN_DAC. The capacitive element Cin_VSL is connected between the gate of the transistor M1 and the input section IN_VSL. As a result, a differential signal corresponding to the differential voltage between the ramp signal RMP and the pixel signal from the vertical signal line VSL is input to the first input section DIFF_DAC (the gate of the transistor M1).

[0270] The capacitance element CvSFOUT_VSS1 is connected between the gate of the transistor M1 and the second power supply line Lvss. One of the two capacitance elements CvSFOUT_VSS2 is connected between the input unit IN_DAC and the second power supply line Lvss. The other of the two capacitance elements CvSFOUT_VSS2 is connected between the input unit IN_VSL and the second power supply line Lvss. Both the capacitance element CvSFOUT_VSS1 and the two capacitance elements CvSFOUT_VSS2 may be provided, or only one of the capacitance element CvSFOUT_VSS1 or the two capacitance elements CvSFOUT_VSS2 may be provided. When the capacitance element CvSFOUT_VSS1 is provided, the configuration on the input unit DIFF_DAC side is the same as that in FIG. 33 . When the capacitive element CvSFOUT_VSS2 is provided, the configuration on the input section DIFF_DAC side becomes the same as that in FIG.

[0271] On the other hand, the output section DIFF_VOUT0 is connected to the first path P1 between the transistor M1 and the transistor M5. The output section DIFF_VOUT0 is also connected to the gate of the transistor M6. The configurations of the transistors M6 and M7 and the capacitance element Cout may be the same as those in the other embodiments. As a result, the voltage of the output section DIFF_VOUT0 becomes an amplified signal based on the differential signal, and is output as the output signal CMout corresponding to the amplified signal via the transistor M6.

[0272] The capacitive element Cbandw is connected between the output section DIFF_VOUT0 and the second power supply line Lvss.

[0273] The capacitive element CvDIFFOUT0_VDD is connected between the first power supply line Lvdd and the gate of the transistor M6.

[0274] In the twenty-eighth embodiment, power supply noise can be canceled by adjusting the capacitance elements CvSFOUT_VSS1, CvSFOUT_VSS2 and / or CvDIFFOUT0_VDD.

[0275] 36 is a circuit diagram showing an example of the configuration of a capacitance element according to a 29th embodiment. In the 29th embodiment, capacitance elements CvSFOUT_VDD1 and CvSFOUT_VDD2 connected to the first power supply line Lvdd are provided instead of the input-side capacitance elements CvSFOUT_VSS1 and CvSFOUT_VSS2. The capacitance element CvSFOUT_VDD1 is connected between the gate of the transistor M1 and the first power supply line Lvdd. One of the two capacitance elements CvSFOUT_VDD2 is connected between the input unit IN_DAC and the first power supply line Lvdd. The other of the two capacitance elements CvSFOUT_VDD2 is connected between the input unit IN_VSL and the first power supply line Lvdd. Both the capacitive element CvSFOUT_VDD1 and the two capacitive elements CvSFOUT_VDD2 may be provided, or only one of the capacitive element CvSFOUT_VDD1 or the two capacitive elements CvSFOUT_VDD2 may be provided. When the capacitive element CvSFOUT_VDD1 is provided, the input side configuration is the same as that shown in Figure 32. When two capacitive elements CvSFOUT_VSS2 are provided, the input side configuration is the same as that shown in Figure 31.

[0276] On the other hand, the configuration on the output side may be the same as that of the 28th embodiment.

[0277] In the twenty-ninth embodiment, power supply noise can be canceled by adjusting the capacitance elements CvSFOUT_VDD1, CvSFOUT_VDD2 and / or CvDIFFOUT0_VDD.

[0278] 30th Embodiment FIG. 37 is a circuit diagram showing an example of the configuration of a capacitive element according to the 30th embodiment. The 30th embodiment is a single-ended amplifier, but the positional relationship and conductivity type of transistors M1 and M5 differ from those of the 28th embodiment. The positional relationship and conductivity type of transistors M6 and M7 also differ from those of the 28th embodiment. Transistor M1 is connected between the first power supply line Lvdd and the drain of transistor M5. Transistor M1 is a P-type MOSFET. Transistor M5 is connected between the second power supply line Lvss and the drain of transistor M1. Transistor M5 is an N-type MOSFET. Transistor M6 is connected between the first power supply line Lvdd and the drain of transistor M7. Transistor M6 is a P-type MOSFET. Transistor M7 is connected between the second power supply line Lvss and the drain of transistor M6. Transistor M7 is an N-type MOSFET.

[0279] The configuration on the input section DIFF_DAC side may be the same as the configuration in Fig. 36. That is, the capacitance element CvSFOUT_VDD1 is connected between the gate of the transistor M1 and the first power supply line Lvdd. One of the two capacitance elements CvSFOUT_VDD2 is connected between the input section IN_DAC and the first power supply line Lvdd. The other of the two capacitance elements CvSFOUT_VDD2 is connected between the input section IN_VSL and the first power supply line Lvdd. Both the capacitance element CvSFOUT_VDD1 and the two capacitance elements CvSFOUT_VDD2 may be provided, or only one of the capacitance element CvSFOUT_VDD1 or the two capacitance elements CvSFOUT_VDD2 may be provided.

[0280] On the other hand, on the output section DIFF_VOUT0 side, the capacitive element Cbandw is connected between the output section DIFF_VOUT0 and the first power supply line Lvdd.

[0281] The capacitive element CvDIFFOUT0_VSS is connected between the second power supply line Lvss and the gate of the transistor M6.

[0282] In the thirtieth embodiment, power supply noise can be canceled by adjusting the capacitance elements CvSFOUT_VDD1, CvSFOUT_VDD2 and / or CvDIFFOUT0_VSS.

[0283] 31st Embodiment Fig. 38 is a circuit diagram showing an example of the configuration of a capacitance element according to the 31st embodiment. In the 31st embodiment, capacitance elements CvSFOUT_VSS1 and CvSFOUT_VSS2 connected to the second power supply line Lvdd are provided instead of the input-side capacitance elements CvSFOUT_VDD1 and CvSFOUT_VDD2. The capacitance element CvSFOUT_VSS1 is connected between the gate of the transistor M1 and the second power supply line Lvss. One of the two capacitance elements CvSFOUT_VSS2 is connected between the input unit IN_DAC and the second power supply line Lvss. The other of the two capacitance elements CvSFOUT_VSS2 is connected between the input unit IN_VSL and the second power supply line Lvss. Both the capacitive element CvSFOUT_VSS1 and the two capacitive elements CvSFOUT_VSS2 may be provided, but only one of the capacitive element CvSFOUT_VSS1 or the two capacitive elements CvSFOUT_VSS2 may be provided.

[0284] On the other hand, the configuration on the output side may be the same as that of the 30th embodiment.

[0285] In the thirty-first embodiment, power supply noise can be canceled by adjusting the capacitance elements CvSFOUT_VSS1, CvSFOUT_VSS2 and / or CvDIFFOUT0_VSS.

[0286] The present technology can be configured as follows.

[0287] (1) A first power supply line transmitting a first power supply voltage; a second power supply line transmitting a second power supply voltage different from the first power supply voltage; a first input unit receiving a reference signal to be compared with a pixel signal from a pixel that photoelectrically converts light into a pixel signal; a second input unit receiving the pixel signal; first and second paths having voltage states according to the magnitude relationship between the voltage of the first input unit and the voltage of the second input unit, and an output unit connected to the second path, a comparator circuit that logically inverts an output signal from the output unit based on the voltage of the first input unit and the voltage of the second input unit; at least one of a first capacitance element provided between the first power supply line and the first input unit or the first path, or between the second power supply line and the first input unit or the first path, and a second capacitance element provided between the first power supply line and the second input unit or the second path, or between the second power supply line and the second input unit or the second path; An imaging device comprising: at least one of a first adjustment unit capable of adjusting the capacitance of the first capacitance element and a second adjustment unit capable of adjusting the capacitance of the second capacitance element.

[0288] (2) The imaging device according to (1), wherein the capacitance of the first capacitance element and the capacitance of the second capacitance element are substantially equal.

[0289] (3) The imaging device according to (1) or (2), further comprising a third capacitance element provided between the first power supply line and the output section.

[0290] (4) The imaging device described in any one of (1) to (3), wherein the first capacitance element is composed of a plurality of first partial capacitance elements, first electrodes of the plurality of first partial capacitance elements are commonly connected to either the first input section or the first path, and second electrodes of the plurality of first partial capacitance elements are selectively connected to the first or second power supply line, respectively, via the first adjustment section.

[0291] (5) The imaging device described in any one of (1) to (4), wherein the second capacitance element is composed of a plurality of second partial capacitance elements, third electrodes of the plurality of second partial capacitance elements are commonly connected to either the second input section or the second path, and fourth electrodes of the plurality of second partial capacitance elements are selectively connected to the first or second power supply line, respectively, via the second adjustment section.

[0292] (6) The imaging device according to any one of (1) to (5), wherein the first adjustment unit includes a first switch connected between the first capacitance element and the first and second power supply lines and configured to selectively connect the first capacitance element to either the first or second power supply line.

[0293] (7) The imaging device according to any one of (1) to (6), wherein the second adjustment unit includes a second switch connected between the second capacitance element and the first and second power supply lines and configured to selectively connect the second capacitance element to either the first or second power supply line.

[0294] (8) The imaging device described in (4), wherein the first adjustment unit includes a plurality of first switches connected between second electrodes of the plurality of first partial capacitance elements and the first and second power supply lines, and each of the second electrodes of the plurality of first partial capacitance elements selectively connecting to either the first or second power supply line.

[0295] (9) The imaging device described in (5), wherein the second adjustment unit includes a plurality of second switches connected between fourth electrodes of the plurality of second partial capacitance elements and the first and second power supply lines, and configured to selectively connect the fourth electrodes of the plurality of second partial capacitance elements to either the first or second power supply line, respectively.

[0296] (10) The imaging device according to (6) or (8), further comprising a register that stores a control signal for controlling the first switch.

[0297] (11) The imaging device according to (7) or (9), further comprising a register that stores a control signal for controlling the second switch.

[0298] (12) The imaging device according to any one of (6), (8), and (10), wherein the first switch is a logic circuit selected from the group consisting of a CMOS inverter, a NAND gate, and a NOR gate.

[0299] (13) The imaging device according to any one of (7), (9), and (11), wherein the second switch is a logic circuit selected from the group consisting of a CMOS inverter, a NAND gate, and a NOR gate.

[0300] (14) The imaging device described in (1), wherein the first adjustment unit includes a third switch connected between the first capacitance element and the first path and between the first capacitance element and the first power supply line, and selectively connects the first capacitance element to either the first path or the first power supply line; and the second adjustment unit includes a fourth switch connected between the second capacitance element and the output unit and between the second capacitance element and the first power supply line, and selectively connects the second capacitance element to either the output unit or the first power supply line.

[0301] (15) The imaging device described in (1), wherein the first adjustment unit includes a third switch connected between the first capacitance element and the first path and between the first capacitance element and the second power supply line, and configured to selectively connect the first capacitance element to either the first path or the second power supply line; and the second adjustment unit includes a fourth switch connected between the second capacitance element and the output unit and between the second capacitance element and the second power supply line, and configured to selectively connect the second capacitance element to either the output unit or the second power supply line.

[0302] (16) The imaging device according to (8), wherein the first adjustment unit includes a plurality of third switches connected between the plurality of first partial capacitance elements and the first path and between the plurality of first partial capacitance elements and the first power supply line, and configured to selectively connect each of the plurality of first partial capacitance elements to either the first path or the first power supply line.

[0303] (17) The imaging device according to (9), wherein the second adjustment unit includes a plurality of second switches connected between the plurality of second partial capacitance elements and the output unit and between the plurality of second partial capacitance elements and the first power supply line, and configured to selectively connect each of the plurality of second partial capacitance elements to either the output unit or the first power supply line.

[0304] (18) The imaging device according to (8), wherein the first adjustment unit includes a plurality of third switches connected between the plurality of first partial capacitance elements and the first path and between the plurality of first partial capacitance elements and the second power supply line, and configured to selectively connect each of the plurality of first partial capacitance elements to either the first path or the second power supply line.

[0305] (19) The imaging device according to (9), wherein the second adjustment unit includes a plurality of second switches connected between the plurality of second partial capacitance elements and the output unit and between the plurality of second partial capacitance elements and the second power supply line, and configured to selectively connect each of the plurality of second partial capacitance elements to either the output unit or the second power supply line.

[0306] (20) An imaging device comprising: a first power supply line transmitting a first power supply voltage; a second power supply line transmitting a second power supply voltage different from the first power supply voltage; a first input unit inputting a reference signal to be compared with a pixel signal from a pixel that photoelectrically converts light into a pixel signal; a second input unit inputting the pixel signal; a first path that is set to a voltage state according to a magnitude relationship between a voltage of the first input unit and a voltage of the second input unit, and an output unit connected to the first path, a comparison circuit that logically inverts an output signal from the output unit based on a voltage of the first input unit and a voltage of the second input unit; at least one of a first capacitance element provided between the first power supply line and the first input unit, or between the second power supply line and the first input unit, and a second capacitance element provided between the first power supply line and the second input unit, or between the second power supply line and the second input unit; and at least one of a first adjustment unit capable of adjusting a capacitance of the first capacitance element and a second adjustment unit capable of adjusting a capacitance of the second capacitance element.

[0307] (21) An imaging device comprising: a first power supply line transmitting a first power supply voltage; a second power supply line transmitting a second power supply voltage different from the first power supply voltage; an input unit that inputs a signal corresponding to a differential voltage between a reference signal to be compared with a pixel signal from a pixel that photoelectrically converts light into a pixel signal; a comparison circuit including a first path that assumes a voltage state corresponding to the voltage of the input unit and an output unit connected to the first path, and that logically inverts an output signal from the output unit based on the voltage of the input unit; a first capacitance element provided between the first power supply line and the input unit or between the second power supply line and the input unit; and a first adjustment unit that can adjust the capacitance of the first capacitance element.

[0308] The present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present disclosure. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be obtained.

[0309] 21 Pixel area 22 Vertical drive section 23 Column processing section 24 Horizontal drive section 25 System control section 26 Signal processing section 27 Data storage section 1 Imaging device 10 Pixel 11 Noise cancellation device 12 Power supply section 100 DAC circuit C3, C4 Capacitor CM1 Comparator V2 Constant current source Lvdd First power supply line Lvss Second power supply line IN_DAC First input section IN_VSL Second input section M1 to M7 Transistors Cin_DAC, Cin_VSL, Cbandw, Cv ＤＩＦＦ１＿ＶＳＳ , CvDIFFOUT0_VSS, Cout Capacitor element DIFF_VOUT0 Output section

Claims

a first input section for inputting a reference signal to be compared with a pixel signal from a pixel that photoelectrically converts light into a pixel signal; a second input section for inputting the pixel signal; a comparison circuit including first and second paths whose voltage states correspond to the magnitude relationship between the voltage of the first input section and the voltage of the second input section, and an output section connected to the second path, and which logically inverts an output signal from the output section based on the voltage of the first input section and the voltage of the second input section; at least one of a first capacitance element provided between the first power supply line and the first input section or the first path, or between the second power supply line and the first input section or the first path, and a second capacitance element provided between the first power supply line and the second input section or the second path, or between the second power supply line and the second input section or the second path; An imaging device comprising: at least one of a first adjustment unit capable of adjusting a capacitance of the first capacitive element and a second adjustment unit capable of adjusting a capacitance of the second capacitive element.

2. The imaging device according to claim 1, wherein the capacitance of the first capacitive element and the capacitance of the second capacitive element are substantially equal.

3. The imaging device according to claim 1, further comprising a third capacitance element provided between the first power supply line and the output section.

4. The imaging device of claim 1, wherein the first capacitance element is composed of a plurality of first partial capacitance elements, first electrodes of the plurality of first partial capacitance elements are commonly connected to either the first input section or the first path, and second electrodes of the plurality of first partial capacitance elements are selectively connected to the first or second power supply line, respectively, via the first adjustment section.

5. The imaging device described in claim 1, wherein the second capacitance element is composed of a plurality of second partial capacitance elements, third electrodes of the plurality of second partial capacitance elements are commonly connected to either the second input section or the second path, and fourth electrodes of the plurality of second partial capacitance elements are selectively connected to the first or second power supply line, respectively, via the second adjustment section.

6. An imaging device as described in claim 1, wherein the first adjustment unit includes a first switch connected between the first capacitance element and the first and second power supply lines, and selectively connecting the first capacitance element to either the first or second power supply line.

7. An imaging device as described in claim 1, wherein the second adjustment unit includes a second switch connected between the second capacitance element and the first and second power supply lines, and selectively connecting the second capacitance element to either the first or second power supply line.

8. An imaging device as described in claim 4, wherein the first adjustment section includes a plurality of first switches connected between the second electrodes of the plurality of first partial capacitance elements and the first and second power supply lines, and selectively connecting the second electrodes of the plurality of first partial capacitance elements to either the first or second power supply line, respectively.

9. An imaging device as described in claim 5, wherein the second adjustment section includes a plurality of second switches connected between the fourth electrodes of the plurality of second partial capacitance elements and the first and second power supply lines, and selectively connecting the fourth electrodes of the plurality of second partial capacitance elements to either the first or second power supply line, respectively.

10. The imaging device according to claim 6, further comprising a register for storing a control signal for controlling said first switch.

11. The imaging device according to claim 7, further comprising a register for storing a control signal for controlling said second switch.

12. The imaging device according to claim 6, wherein the first switch is a logic circuit selected from the group consisting of a CMOS (Complementary Metal Oxide Semiconductor) inverter, a NAND gate, and a NOR gate.

13. The imaging device according to claim 7, wherein the second switch is a logic circuit selected from the group consisting of a CMOS inverter, a NAND gate, and a NOR gate.

14. The imaging device of claim 1, wherein the first adjustment unit includes a third switch connected between the first capacitance element and the first path and between the first capacitance element and the first power supply line, and selectively connects the first capacitance element to either the first path or the first power supply line, and the second adjustment unit includes a fourth switch connected between the second capacitance element and the output unit, and between the second capacitance element and the first power supply line, and selectively connects the second capacitance element to either the output unit or the first power supply line.

15. The imaging device of claim 1, wherein the first adjustment unit includes a third switch connected between the first capacitance element and the first path and between the first capacitance element and the second power supply line, and configured to selectively connect the first capacitance element to either the first path or the second power supply line; and the second adjustment unit includes a fourth switch connected between the second capacitance element and the output unit, and between the second capacitance element and the second power supply line, and configured to selectively connect the second capacitance element to either the output unit or the second power supply line.

16. The imaging device of claim 8, wherein the first adjustment section includes a plurality of third switches connected between the plurality of first partial capacitance elements and the first path, and between the plurality of first partial capacitance elements and the first power supply line, and selectively connecting each of the plurality of first partial capacitance elements to either the first path or the first power supply line.

17. An imaging device as described in claim 9, wherein the second adjustment section includes a plurality of second switches connected between the plurality of second partial capacitance elements and the output section, and between the plurality of second partial capacitance elements and the first power supply line, and selectively connecting each of the plurality of second partial capacitance elements to either the output section or the first power supply line.

18. The imaging device described in claim 8, wherein the first adjustment section includes a plurality of third switches connected between the plurality of first partial capacitance elements and the first path, and between the plurality of first partial capacitance elements and the second power supply line, and selectively connecting each of the plurality of first partial capacitance elements to either the first path or the second power supply line.

19. An imaging device as described in claim 9, wherein the second adjustment section includes a plurality of second switches connected between the plurality of second partial capacitance elements and the output section, and between the plurality of second partial capacitance elements and the second power supply line, and selectively connecting each of the plurality of second partial capacitance elements to either the output section or the second power supply line.

20. An imaging device comprising: a first power supply line transmitting a first power supply voltage; a second power supply line transmitting a second power supply voltage different from the first power supply voltage; a first input unit inputting a reference signal to be compared with a pixel signal from a pixel that photoelectrically converts light into a pixel signal; a second input unit inputting the pixel signal; a first path having a voltage state corresponding to the magnitude relationship between the voltage of the first input unit and the voltage of the second input unit, and an output unit connected to the first path, a comparison circuit that logically inverts an output signal from the output unit based on the voltage of the first input unit and the voltage of the second input unit; at least one of a first capacitive element provided between the first power supply line and the first input unit, or between the second power supply line and the first input unit, and a second capacitive element provided between the first power supply line and the second input unit, or between the second power supply line and the second input unit; and at least one of a first adjustment unit capable of adjusting the capacitance of the first capacitive element and a second adjustment unit capable of adjusting the capacitance of the second capacitive element.

21. An imaging device comprising: a first power supply line transmitting a first power supply voltage; a second power supply line transmitting a second power supply voltage different from the first power supply voltage; an input unit for inputting a signal corresponding to a differential voltage between a reference signal to be compared with a pixel signal from a pixel that photoelectrically converts light into a pixel signal and the pixel signal; a comparison circuit including a first path that is in a voltage state corresponding to the voltage of the input unit and an output unit connected to the first path, and which logically inverts an output signal from the output unit based on the voltage of the input unit; a first capacitance element provided between the first power supply line and the input unit or between the second power supply line and the input unit; and a first adjustment unit capable of adjusting the capacitance of the first capacitance element.

Images