Bit spreading technique for radiation hardened error resistant memory system

The bit spreading technique in memory systems addresses the challenge of radiation-induced errors in space-based applications by distributing data bits and error correction codes across multiple RAMs, enhancing reliability and reducing weight and cost.

WO2025064009A2 Publication Date: 2025-03-27BAE SYSTEMS INFORMATION ANDELECTRONIC SYSTEMS INTEGRATION INC
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Patent Information

Application Number
PCT/US2024/024571
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2023-04-20
Filing Date
2024-04-15
Publication Date
2025-03-27

AI Technical Summary

Technical Problem

Memory systems in space-based applications are susceptible to radiation-induced single event effects, leading to increased errors and potential memory failure, with existing solutions like shielding being impractical due to weight constraints and redundant memories increasing cost and complexity.

Method used

The implementation of a bit spreading technique in memory systems, where data bits and error correction codes are distributed across multiple separated RAMs, allowing for error correction and reduced susceptibility to radiation-induced errors.

Benefits of technology

This approach enhances memory reliability in high-radiation environments by enabling successful error recovery and reducing the likelihood of memory failure, while also minimizing weight and cost compared to traditional shielding and redundant memory solutions.

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Abstract

Techniques are provided for an error resistant radiation hardened memory system based on spreading of data bits among multiple random access memories (RAMs). A memory system implementing the techniques according to an embodiment includes a first plurality of RAMs configured to store data bits written to the memory system, the data bits distributed over the first plurality of RAMs. The system also includes an error correction coding (ECC) circuit configured to generate ECC codes, each of the codes associated with a unique group of the data bits. The system further includes a second plurality of RAMs configured to store bits of the ECC codes such that the bits of each ECC code are distributed over the second plurality of RAMs. The system further includes a reporting circuit configured to report a single bit error correction or a double bit error detection, resulting from a read operation on the memory system.
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