Display substrate and manufacturing method therefor, and display apparatus

Abstract

A display substrate and a manufacturing method therefor, and a display apparatus. The display substrate comprises: a base substrate, and a first electrode and a pixel define layer which are sequentially arranged on the base substrate. The pixel define layer is provided with a pixel opening exposing the first electrode. The regions in which the first electrode is located comprise: a first electrode region, a second electrode region, and a smooth transition region. The smooth transition region is located between the first electrode region and the second electrode region. The orthographic projection of the first electrode located in the first electrode region on the base substrate coincides with the orthographic projection of the pixel opening on the base substrate, and the orthographic projection of the first electrode located in the second electrode region on the base substrate partially overlaps with the orthographic projection of the pixel define layer on the base substrate. The thickness of the first electrode located in the first electrode region is less than the thickness of the first electrode located in the second electrode region.

Description

Display substrate, manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0002] Micro-OLEDs (Micro Organic Light-Emitting Diodes) are a type of microdisplay that has been developed in recent years. Silicon-based OLEDs are a type of microdisplay. Fabricated using the mature complementary metal oxide semiconductor (CMOS) integrated circuit process, silicon-based OLEDs offer advantages such as compact size, high pixel per inch (PPI) resolution, and high refresh rate. They are widely used in near-eye displays for virtual reality (VR) and augmented reality (AR).

[0003] SUMMARY OF THE INVENTION

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, an embodiment of the present disclosure provides a display substrate, comprising: a base substrate, and a first electrode and a pixel definition layer sequentially disposed on the base substrate, the pixel definition layer being provided with a pixel opening exposing the first electrode, the region where the first electrode is located comprising: a first electrode region, a second electrode region, and a smooth transition region, the smooth transition region being located between the first electrode region and the second electrode region, the orthographic projection of the first electrode in the first electrode region on the base substrate coinciding with the orthographic projection of the pixel opening on the base substrate, and the orthographic projection of the first electrode in the second electrode region on the base substrate partially overlapping with the orthographic projection of the pixel definition layer on the base substrate;

[0006] The thickness of the first electrode located in the first electrode region is smaller than the thickness of the first electrode located in the second electrode region.

[0007] In some possible implementations, an orthographic projection of an edge of a top layer of the pixel definition layer on the base substrate is located within an orthographic projection of the transition region on the base substrate.

[0008] In some possible implementations, the first electrode includes: a first structure and a second structure, wherein the first structure is located on a side of the second structure away from the substrate;

[0009] The orthographic projection of the first structure on the base substrate covers the orthographic projection of the second structure on the base substrate, and the thickness of the second structure is greater than the thickness of the first structure;

[0010] The first structure covers sidewalls of the second structure.

[0011] In some possible implementations, the surface of the second structure close to the pixel definition layer is flat;

[0012] The first thickness is the thickness of the second structure located in the first electrode region, and the second thickness is the thickness of the second structure located in the second electrode region. The first thickness is smaller than the second thickness.

[0013] In some possible implementations, a ratio of the second thickness to the first thickness ranges from 1.3 / 1 to 4 / 1.

[0014] In some possible implementations, the thickness of the pixel definition layer that overlaps with the orthographic projection of the surface of the second structure close to the pixel definition layer on the substrate is a third thickness;

[0015] The ratio of the third thickness to the thickness difference ranges from 10:1 to 20:1, wherein the thickness difference is the difference between the second thickness and the first thickness.

[0016] In some possible implementations, the first structure is a transparent electrode structure, and the thickness of the first structure is greater than 80 angstroms.

[0017] In some possible implementations, the second structure includes: a first sublayer, a second sublayer, a third sublayer, and a fourth sublayer sequentially stacked on the base substrate; the thickness of the third sublayer is greater than the thickness of any of the first sublayer, the second sublayer, and the fourth sublayer;

[0018] The orthographic projection of the surface of the first sub-layer away from the base substrate on the base substrate covers the orthographic projection of the second sub-layer on the base substrate, the orthographic projection of the surface of the second sub-layer away from the base substrate on the base substrate covers the orthographic projection of the third sub-layer on the base substrate, and the orthographic projection of the surface of the third sub-layer away from the base substrate on the base substrate covers the orthographic projection of the fourth sub-layer on the base substrate;

[0019] The sidewall of the second structure is an inclined surface.

[0020] In some possible implementations, the conductivity of the third sub-layer is greater than the conductivity of any film layer among the first sub-layer, the second sub-layer, and the fourth sub-layer.

[0021] In some possible implementations, the first sublayer is made of titanium, the second sublayer is made of titanium nitride, the third sublayer is made of aluminum, and the fourth sublayer is made of titanium nitride.

[0022] In some possible implementations, the pixel definition layer includes: a first inorganic layer, a second inorganic layer, a third inorganic layer, and a fourth inorganic layer sequentially stacked on the base substrate;

[0023] The surface of the first inorganic layer away from the substrate is flat, and the distance between the surface of the first inorganic layer away from the substrate and the substrate is equal to the distance between the surface of the first structure located in the second electrode region and on the second structure and the substrate.

[0024] In some possible implementations, an orthographic projection of a surface of the first inorganic layer close to the base substrate on the base substrate at least partially overlaps with an orthographic projection of a surface of the first structure on the base substrate on the base substrate.

[0025] In some possible implementations, the orthographic projection of the second inorganic layer on the base substrate covers the orthographic projection of the first inorganic layer on the base substrate, and the second inorganic layer is provided with a first via hole, which exposes the first electrode located in the first electrode region.

[0026] In some possible implementations, an orthographic projection of the third inorganic layer on the base substrate at least partially overlaps with an orthographic projection of any one of the first inorganic layer and the second inorganic layer on the base substrate;

[0027] The third inorganic layer is provided with a second via hole and a third via hole, wherein the second via hole exposes the first electrode located in the first electrode region, and the third via hole exposes the second inorganic layer;

[0028] The orthographic projection of the first via hole on the base substrate coincides with the orthographic projection of the second via hole on the base substrate.

[0029] In some possible implementations, an orthographic projection of the fourth inorganic layer on the base substrate at least partially overlaps with an orthographic projection of any one of the first inorganic layer and the third inorganic layer on the base substrate;

[0030] The fourth inorganic layer is provided with a fourth via hole and a fifth via hole, the fourth via hole exposing the first electrode located in the first electrode region, and the fifth via hole exposing the second inorganic layer;

[0031] The orthographic projection of the fourth via hole on the base substrate coincides with the orthographic projection of the second via hole on the base substrate, and the orthographic projection of the fifth via hole on the base substrate partially overlaps with the orthographic projection of the third via hole on the base substrate.

[0032] In some possible implementations, the third via hole and the fourth via hole constitute a groove formed on the pixel definition layer, and the groove is an undercut structure.

[0033] In some possible implementations, the thickness of the first inorganic layer is greater than the thickness of any of the second inorganic layer, the third inorganic layer, and the fourth inorganic layer, and the thickness of the third inorganic layer is greater than the thickness of any of the second inorganic layer and the fourth inorganic layer;

[0034] The etching rate of the third inorganic layer is greater than the etching rate of the fourth inorganic layer.

[0035] In some possible implementations, the first inorganic layer is made of silicon oxide, the second inorganic layer is made of silicon oxide, the third inorganic layer is made of silicon nitride, and the fourth inorganic layer is made of silicon oxide.

[0036] In some possible implementations, the display substrate further includes: an organic light-emitting layer, a second electrode, an encapsulation layer, a filter layer, and an optical device layer sequentially stacked on the pixel definition layer; the filter layer includes: a plurality of filters; the optical device layer includes: a plurality of optical devices;

[0037] The orthographic projections of adjacent filters on the substrate at least partially overlap, and the multiple filters correspond to the multiple optical devices one-to-one;

[0038] The orthographic projection of the filter on the substrate partially overlaps with the orthographic projection of the corresponding optical device on the substrate; and there is a gap between adjacent optical devices.

[0039] In a second aspect, an embodiment of the present disclosure provides a display device, comprising: a display substrate as described in any embodiment of the first aspect.

[0040] In a third aspect, an embodiment of the present disclosure provides a method for preparing a display substrate, configured to prepare the display substrate according to any embodiment of the first aspect, the method comprising:

[0041] forming a first electrode on the base substrate;

[0042] A pixel definition layer is formed on the first electrode.

[0043] In some possible implementations, forming the first electrode on the base substrate includes: depositing a first metal film, a second metal film, a third metal film, and a fourth metal film on the base substrate, and patterning the first metal film, the second metal film, the third metal film, and the fourth metal film through a patterning process to form a second structure;

[0044] A transparent metal film is deposited on the second structure, and the transparent metal film is patterned by a composition process to form a first structure, thereby forming a first electrode including the first structure and the second structure.

[0045] In some possible implementations, forming a pixel definition layer on the first electrode includes: depositing a first inorganic thin film on the first electrode, and forming the first inorganic layer through two patterning processes;

[0046] Depositing a second inorganic film, a third inorganic film, and a fourth inorganic film on the first inorganic layer, patterning the second inorganic film, the third inorganic film, and the fourth inorganic film through a composition process to form a second inorganic layer, a third inorganic layer, and a fourth inorganic layer, thereby forming a pixel definition layer including the first inorganic layer, the second inorganic layer, the third inorganic layer, and the fourth inorganic layer;

[0047] The selectivity ratio of etching the second inorganic thin film to the transparent metal thin film is in the range of 20:1 to 40:1;

[0048] The selectivity ratio of etching of the fourth inorganic thin film to the third inorganic thin film is in a range of 1:6 to 1:9.

[0049] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0050] Summary of the Figures

[0051] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0052] FIG1 is a schematic structural diagram of a display substrate provided in an exemplary embodiment of the present disclosure;

[0053] FIG2 is a schematic diagram showing differences among a first thickness, a second thickness, and a third thickness according to an exemplary embodiment of the present disclosure;

[0054] FIG3 is a schematic diagram of a transmission electron microscope (TEM) slice of FIG2 ;

[0055] FIG4 is a schematic diagram showing a mapping between thickness and reflectivity of a first structure provided by an exemplary embodiment of the present disclosure;

[0056] FIG5 is a schematic structural diagram of a second structure provided by an embodiment of the present disclosure;

[0057] FIG6 is a schematic structural diagram of a substrate provided in an embodiment of the present disclosure;

[0058] FIG7 is a schematic diagram of a circuit principle provided by an exemplary embodiment;

[0059] FIG8 is a schematic diagram of a circuit implementation of a voltage control circuit and a pixel driving circuit;

[0060] FIG9 is a schematic structural diagram of a display substrate provided by another exemplary embodiment of the present disclosure;

[0061] FIG10 is a schematic structural diagram of an organic light-emitting layer provided in an embodiment of the present disclosure;

[0062] FIG11A is a first schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0063] FIG11B is a second schematic diagram of an organic light emitting diode display substrate provided in an embodiment of the present disclosure;

[0064] FIG11C is a third schematic diagram of an organic light emitting diode display substrate provided in an embodiment of the present disclosure;

[0065] FIG11D is a fourth schematic diagram of an organic light emitting diode display substrate provided in an embodiment of the present disclosure.

[0066] Details

[0067] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings below. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0068] In the drawings, the sizes of various components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0069] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0070] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately modified depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced as appropriate.

[0071] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0072] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0073] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0074] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0075] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0076] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0077] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0078] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0079] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0080] An OLED display substrate consists of a silicon-based backplane with integrated driver circuitry, a pixel definition layer formed on top of the silicon-based backplane, and an OLED light-emitting element array. The OLED light-emitting element array comprises an anode, an organic light-emitting layer, and a cathode. The uneven transition of the anode's edge bump results in uneven light output from the display substrate, reducing the display quality.

[0081] FIG1 is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure. As shown in FIG1 , the display substrate includes: a base substrate 10, a first electrode 20, and a pixel definition layer (PDL) 30 sequentially disposed on the base substrate 10. The pixel definition layer is provided with a pixel opening exposing the first electrode. The region where the first electrode is located includes: a first electrode region R1, a second electrode region R2, and a smooth transition region R0. The smooth transition region R0 is located between the first electrode region R1 and the second electrode region R2. The orthographic projection of the first electrode 20 in the first electrode region R1 on the base substrate 10 coincides with the orthographic projection of the pixel opening on the base substrate 10. The orthographic projection of the first electrode 20 in the second electrode region R2 on the base substrate 10 partially overlaps with the orthographic projection of the pixel definition layer on the base substrate 10. The thickness H1 of the first electrode in the first electrode region is less than the thickness H2 of the first electrode in the second electrode region. A smooth transition refers to a curvature with no sudden change at the bottom edge.

[0082] In an exemplary embodiment, as shown in FIG. 1 , structurally, the region where the first electrode 20 is located includes a first electrode region R1 , two smooth regions R0 , and two second electrode regions R2 .

[0083] There is a smooth transition region R0 between the first electrode region R1 and the second electrode region R2. The smooth transition region R0 can improve the uniformity of light output of the OLED device, enhance the display effect, and avoid uneven light output caused by the uneven transition of the first electrode protrusion.

[0084] In one exemplary embodiment, by controlling the difference in thickness between the first electrode below the non-opening portion of the PDL and the first electrode below the PDL opening, the thickness of the first electrode in the first electrode region is made thinner than that in the second electrode region. This reduces light leakage from the PDL edge (non-opening portion) and improves light extraction efficiency at the PDL opening, thereby enhancing the display quality of the display substrate. This addresses the issue of light leakage from the edges of individual pixels, resulting in color impurities, as pixel density (PPI) increases and the distance between pixels decreases for the same size.

[0085] In an exemplary embodiment, the base substrate 10 may be a driving backplane.

[0086] In one exemplary embodiment, the display substrate may further include an organic light-emitting layer (EL) and a second electrode stacked sequentially on the pixel definition layer. The organic light-emitting layer is located between the first electrode and the second electrode and emits light under the combined action of the first electrode and the second electrode.

[0087] In an exemplary embodiment, the first electrode may be an anode, and the second electrode may be a cathode.

[0088] The display substrate provided by the embodiment of the present disclosure has a smooth transition area set between the first electrode area and the second electrode area to improve the uniformity of light output of the OLED device, enhance the display effect, and avoid uneven light output caused by the uneven transition of the first electrode protrusion.

[0089] In an exemplary embodiment of the present disclosure, the orthographic projection of the edge W of the top layer of the pixel definition layer shown in FIG. 1 on the base substrate 10 is located within the orthographic projection of the transition region R0 on the base substrate 10 .

[0090] In an exemplary embodiment, the thickness of the first electrode located in the smooth transition region R0 increases sequentially from the second electrode region to the first electrode region.

[0091] In an exemplary embodiment of the present disclosure, the first electrode 20 may include: a first structure 201 and a second structure 202 , wherein the first structure is located on a side of the second structure away from the substrate;

[0092] The orthographic projection of the first structure on the base substrate covers the orthographic projection of the second structure on the base substrate, and the thickness of the second structure is greater than that of the first structure; the first structure covers the sidewall of the second structure.

[0093] In an exemplary embodiment, the second structure includes a metallic material.

[0094] In an exemplary embodiment, as shown in FIG1 , the orthographic projection of the first structure on the substrate covers the orthographic projection of the second structure on the substrate, that is, the cross-sectional area of ​​the first structure is larger than the cross-sectional area of ​​the second structure, and the first structure can protect the metal in the second structure from corrosion.

[0095] In an exemplary embodiment, as shown in FIG. 1 , the thickness of the second structure may be greater than the thickness of the first structure in a direction perpendicular to the base substrate.

[0096] In an exemplary embodiment, as shown in FIG1 , the angle between the sidewall of the second structure and the base substrate is an acute angle, which may be greater than or equal to 50 degrees and less than 90 degrees.

[0097] In an exemplary embodiment, the first structure may be a transparent electrode structure, and the first structure may include indium tin oxide (ITO).

[0098] In an exemplary embodiment, as shown in Figure 1 , the longitudinal cross-section of the second structure may be rectangular or trapezoidal. Figure 1 illustrates the case where the longitudinal cross-section of the second structure is trapezoidal.

[0099] In an exemplary embodiment, as shown in FIG. 1 , the sidewall of the second structure may be a slope.

[0100] Figure 2 is a schematic diagram of the difference between the first thickness, the second thickness and the third thickness provided in an example embodiment of the present disclosure, and Figure 3 is a schematic diagram of a transmission electron microscope (TEM) slice of Figure 2. As shown in Figures 2 and 3, the surface of the second structure close to the pixel definition layer is flat; the first thickness Thk1 can be the thickness of the second structure located in the first electrode area, and the second thickness Thk2 can be the thickness of the second structure located in the second electrode area, and the first thickness is less than the second thickness.

[0101] The embodiment of the present disclosure can reduce light leakage from the side of the product by controlling the difference between the thickness of the second structure below the PDL non-opening and the thickness of the second structure below the PDL opening, so that the thickness of the second structure below the PDL non-opening is less than the thickness of the second structure below the PDL opening, thereby reducing the expected light leakage characteristics and improving color stability at low voltage.

[0102] In an exemplary embodiment of the present disclosure, a ratio of the second thickness Thk2 to the first thickness Thk1 is approximately 1.3 / 1 to 4 / 1.

[0103] Figure 4 is a schematic diagram showing the mapping of the thickness and reflectivity of a first structure provided in an exemplary embodiment of the present disclosure. As shown in Figure 4 , the effect of the thickness of the first structure on the reflectivity fluctuates periodically, with the reflectivity decreasing with each period. In Figure 4 , the abscissa represents time, expressed in units of period T, and the ordinate represents reflectivity. The thickness of the first structure along line L1 is 460 micrometers (μm), the thickness of the first structure along line L2 is 525 μm, and the thickness of the first structure along line L3 is 610 μm.

[0104] From the perspective of light emission, within the first period of film thickness, if the thickness of the first structure is relatively small, the transmittance of the first electrode will be increased, thereby increasing the reflectivity of the first electrode.

[0105] From the perspective of light leakage, within the first period of film thickness, if the thickness of the first structure is relatively large, the transmittance of the first electrode will be reduced, thereby reducing light leakage at the PDL edge.

[0106] In an exemplary embodiment, the thickness of the first structure is greater than 80 angstroms, which ensures that the first structure can protect the metal in the second structure from being affected by acids, bases, and / or oxidation during subsequent processes.

[0107] From the perspective of structural stability, increasing the thickness of the first structure will increase the protection of the second structure, thereby reducing the risk of oxidation and corrosion of the metal film layer in the second structure and improving the stability of the overall anode structure.

[0108] In an exemplary embodiment, the display substrate in the present disclosure further includes an organic light-emitting layer.

[0109] Based on the luminescence, light leakage and structural stability factors shown above, the ITO thickness Thk2 below the non-opening part (edging) of the PDL and the ITO thickness Thk1 at the PDL opening can be differentiated, Thk2:Thk1=1.3:1~4:1, and the ITO thickness below the non-opening part of the PDL is 1.3~4 times the ITO thickness at the PDL opening. This can reduce the overall transmittance of the PDL non-opening and increase the overall transmittance of the PDL opening. The efficiency of the organic light-emitting layer in the PDL edging area is reduced to about 80% of the original, and the efficiency of the organic light-emitting layer at the PDL opening is increased to about 120% of the original, reducing the light leakage in the PDL edging area to about 40% of the original.

[0110] In an exemplary embodiment of the present disclosure, as shown in Figures 2 and 3, the thickness of the pixel definition layer, which overlaps the orthographic projection of the second structure's surface proximal to the pixel definition layer on the substrate, is a third thickness, Thk3. The ratio of the third thickness to the thickness difference, where the thickness difference is the difference between the second thickness and the first thickness, is approximately 10:1 to 20:1. This disclosure maintains a certain thickness ratio between the third thickness, Thk3, and the difference between the second thickness and the first thickness, |Thk2-Thk1|, to ensure stable deformation of the organic light-emitting layer at the PDL edge, thereby controlling the internal electrical balance of the organic light-emitting layer.

[0111] In one exemplary embodiment, Thk3:|Thk2-THk1|=10:1 to 20:1, ensuring stable deformation of the organic light-emitting layer at non-opening portions of the PDL, thereby maintaining internal electrical balance within the organic light-emitting layer. This prevents an imbalance in the internal resistance distribution of the organic light-emitting layer caused by Thk3:|Thk2-THk1| being lower than 10:1, and avoids severe distortion of the organic light-emitting layer material at PDL discontinuities, resulting in misaligned material overlaps in the organic light-emitting layer, caused by Thk3:|Thk2-THk1| being higher than 20:1.

[0112] Figure 5 is a structural schematic diagram of the second structure provided in an embodiment of the present disclosure. As shown in Figure 5, the second structure may include: a first sublayer 2021, a second sublayer 2022, a third sublayer 2023, and a fourth sublayer 2024 stacked in sequence on the base substrate; the thickness of the third sublayer is greater than the thickness of any film layer among the first sublayer, the second sublayer, and the fourth sublayer.

[0113] The orthographic projection of the surface of the first sub-layer 2021 away from the base substrate 10 on the base substrate 10 covers the orthographic projection of the second sub-layer 2022 on the base substrate 10, the orthographic projection of the surface of the second sub-layer 2022 away from the base substrate 10 on the base substrate 10 covers the orthographic projection of the third sub-layer 2023 on the base substrate 10, and the orthographic projection of the surface of the third sub-layer 2023 away from the base substrate 10 on the base substrate 10 covers the orthographic projection of the fourth sub-layer 2024 on the base substrate 10. That is, the cross-sectional area of ​​the first sub-layer 2021 is greater than the cross-sectional area of ​​the second sub-layer 2022, the cross-sectional area of ​​the second sub-layer 2022 is greater than the cross-sectional area of ​​the third sub-layer 2023, and the cross-sectional area of ​​the third sub-layer 2023 is greater than the cross-sectional area of ​​the fourth sub-layer 2024.

[0114] In an exemplary embodiment of the present disclosure, the conductivity of the third sub-layer 2023 is greater than the conductivity of any of the first sub-layer 2021 , the second sub-layer 2022 , and the fourth sub-layer 2024 .

[0115] In an exemplary embodiment of the present disclosure, the first sublayer 2021 is made of titanium (Ti), the second sublayer 2022 is made of titanium nitride (TiN), the third sublayer 2023 is made of aluminum (Al), and the fourth sublayer 2024 is made of titanium nitride (TiN).

[0116] The anode of the substrate is coated with titanium (Ti), titanium nitride (TiN), aluminum (Al), and titanium nitride (TiN) in order from bottom to top. The first structure has TiN coated over the Al. The TiN and the second structure's ITO layers protect the Al from yellow light after coating, preventing damage to the Al from etching plasma and cleaning solutions. Plating TiN over the Al prevents the more active Al from directly contacting the ITO, where it could extract oxygen from the ITO, leading to indium precipitation and affecting the ITO's infusion efficiency during vapor deposition.

[0117] In an exemplary embodiment of the present disclosure, as shown in FIG1 , the pixel definition layer may include: a first inorganic layer 301 , a second inorganic layer 302 , a third inorganic layer 303 and a fourth inorganic layer 304 sequentially stacked on a base substrate.

[0118] The surface of the first inorganic layer 301 away from the base substrate 10 is flat, and the distance between the surface of the first inorganic layer 301 away from the base substrate 10 and the base substrate 10 is equal to the distance between the surface of the first structure 201 located in the second electrode region R2 and on the second structure 202 and the base substrate 10.

[0119] In an exemplary embodiment of the present disclosure, as shown in FIG. 1 , the orthographic projection of the surface of the first inorganic layer 301 close to the base substrate 10 on the base substrate 10 at least partially overlaps with the orthographic projection of the surface of the first structure 201 on the base substrate 10 on the base substrate 10 .

[0120] In an exemplary embodiment of the present disclosure, as shown in FIG1 , the orthographic projection of the second inorganic layer 302 on the base substrate 10 covers the orthographic projection of the first inorganic layer 301 on the base substrate 10 , and the second inorganic layer 302 is provided with a first via hole V1 , which exposes the first electrode 20 located in the first electrode region R1 .

[0121] In an exemplary embodiment of the present disclosure, as shown in FIG1 , the orthographic projection of the third inorganic layer 303 on the base substrate 10 at least partially overlaps with the orthographic projection of any one of the first inorganic layer 301 and the second inorganic layer 302 on the base substrate 10; the third inorganic layer 303 is provided with a second via hole V2 and a third via hole V3, the second via hole V2 exposes the first electrode 20 located in the first electrode region R1, and the third via hole V3 exposes the second inorganic layer 302; the orthographic projection of the first via hole V1 on the base substrate 10 coincides with the orthographic projection of the second via hole V2 on the base substrate 10.

[0122] In an exemplary embodiment of the present disclosure, as shown in FIG1 , the orthographic projection of the fourth inorganic layer 304 on the base substrate 10 at least partially overlaps with the orthographic projection of any one of the first inorganic layer 301 and the third inorganic layer 303 on the base substrate 10; the fourth inorganic layer 304 is provided with a fourth via hole V4 and a fifth via hole V5, the fourth via hole V4 exposes the first electrode 20 located in the first electrode region R1, and the fifth via hole V5 exposes the second inorganic layer 302; the orthographic projection of the fourth via hole V4 on the base substrate 10 coincides with the orthographic projection of the second via hole V2 on the base substrate 10, and the orthographic projection of the fifth via hole V5 on the base substrate 10 partially overlaps with the orthographic projection of the third via hole V3 on the base substrate 10.

[0123] In an exemplary embodiment of the present disclosure, as shown in FIG1 , the third via hole V3 and the fourth via hole V4 constitute a groove D formed on the pixel definition layer. The groove is an undercut structure, which can cause the light-emitting structure layer to break at the groove, thereby avoiding the transmission of lateral leakage current and improving the reliability of the display substrate.

[0124] In an exemplary embodiment of the present disclosure, as shown in FIG1 , the thickness of the first inorganic layer 301 is greater than the thickness of any of the second inorganic layer 302, the third inorganic layer 303, and the fourth inorganic layer 304, and the thickness of the third inorganic layer 303 is greater than the thickness of any of the second inorganic layer 302 and the fourth inorganic layer 304; the etching rate of the third inorganic layer 303 is greater than the etching rate of the fourth inorganic layer.

[0125] In an exemplary embodiment of the present disclosure, as shown in FIG1 , the material for producing the first inorganic layer 301 may include silicon oxide (SiO), the material for producing the second inorganic layer 302 may include silicon oxide (SiO), the material for producing the third inorganic layer 303 may include silicon nitride (SiN), and the material for producing the fourth inorganic layer 304 may include silicon oxide (SiO).

[0126] FIG6 is a schematic structural diagram of a substrate provided in an embodiment of the present disclosure. As shown in FIG6 , the substrate 10 may include: a base 11, a transistor 12 disposed in the base 11, and a first conductive pillar 13, a connecting electrode 14, and a second conductive pillar 15 sequentially disposed on the base 11. The first conductive pillar 13 is electrically connected to the transistor 12 and the connecting electrode 14, respectively, and the second conductive pillar 15 is electrically connected to the connecting electrode 14 and the first electrode 30, respectively.

[0127] In an exemplary embodiment, as shown in FIG. 6 , the base substrate 10 may further include a first insulating layer 16 between the base 11 and the connection electrode 14 , and a second insulating layer 17 between the connection electrode 14 and the first electrode 30 .

[0128] In an exemplary embodiment, as shown in FIG6 , the first insulating layer 16 is provided with a via hole exposing the transistor 12 , and the first conductive pillar 13 is located in the via hole of the first insulating layer.

[0129] In an exemplary embodiment, as shown in FIG6 , the second insulating layer 17 is provided with a via hole exposing the connecting electrode 14 , and the second conductive pillar 15 is located in the via hole of the second insulating layer.

[0130] In an exemplary embodiment, the active layer of the transistor 12 is disposed inside the substrate 11 .

[0131] In an exemplary embodiment, the transistor 12 may be a metal oxide semiconductor field effect transistor (MOS).

[0132] In one exemplary embodiment, a transistor may include an active layer, a gate electrode, a source electrode, a drain electrode, and a gate connection electrode. The source electrode and the drain electrode are respectively connected to the active layer, and the gate connection electrode is connected to the gate electrode. The transistor may have a bottom-gate structure or a top-gate structure.

[0133] In an exemplary embodiment, the active layer may be formed of a material including metal oxide.

[0134] In one exemplary embodiment, the first insulating layer 16 and the second insulating layer 17 are made of at least one of an organic material and an inorganic material, for example, silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON). The first insulating layer 16 and the second insulating layer 17 may be a single layer structure or a multilayer composite structure.

[0135] In an exemplary embodiment, the first conductive pillar 13 and the second conductive pillar 15 may be made of tungsten.

[0136] In an exemplary embodiment, the connection electrode 14 is made of a metal, such as silver or aluminum. The connection electrode 14 may be a single-layer structure or a multi-layer composite structure.

[0137] In an exemplary embodiment, the display substrate may include a pixel driving circuit including a plurality of transistors 12 on a substrate 11 . The transistors may include at least one of a switching transistor, a driving transistor, a reset transistor, and a compensation transistor.

[0138] FIG7 is a schematic diagram of a circuit principle provided by an exemplary embodiment. As shown in FIG7 , multiple sub-pixels in a display area are regularly arranged to form multiple display rows and multiple display columns. Each sub-pixel includes a pixel driving circuit 101 and a light-emitting device 102 connected to the pixel driving circuit 101. The pixel driving circuit 101 includes at least a driving transistor. The control circuit includes at least multiple voltage control circuits 110, each of which is connected to multiple pixel driving circuits 101. For example, a voltage control circuit 110 is connected to a pixel driving circuit 101 in a display row, the first electrodes of the driving transistors in the pixel driving circuit 101 in the display row are commonly connected to the voltage control circuit 110, the second electrode of each driving transistor is connected to the anode of the light-emitting device 102 of the sub-pixel, and the cathode of the light-emitting device 102 is connected to the input terminal of the second power supply signal VSS. The voltage control circuit 110 is respectively connected to the input terminal of the first power supply signal VDD, the input terminal of the initialization signal Vinit, the input terminal of the reset control signal RE, and the input terminal of the emission control signal EM. The voltage control circuit 110 is configured to output an initialization signal Vinit to the first electrode of the driving transistor in response to the reset control signal RE, thereby controlling the corresponding light-emitting device 102 to reset. The voltage control circuit 110 is also configured to output a first power supply signal VDD to the first electrode of the driving transistor in response to the light-emitting control signal EM, thereby driving the light-emitting device 102 to emit light. By connecting the pixel driving circuits 101 in a display row to the voltage control circuit 110, the structure of the pixel driving circuit 101 can be simplified, and the occupied area of ​​the pixel driving circuit 101 can be reduced, thereby allowing the display substrate to be provided with more pixel driving circuits 101 and light-emitting devices 102, thereby achieving high PPI display. Under the control of the reset control signal RE, the voltage control circuit 110 outputs the initialization signal Vinit to the first electrode of the driving transistor, thereby controlling the corresponding light-emitting device 102 to reset. This can avoid the influence of the voltage loaded on the light-emitting device 102 during the previous frame of light emission on the next frame of light emission, thereby improving the ghosting phenomenon.

[0139] In an exemplary embodiment, one voltage control circuit 110 may be connected to the pixel driving circuits 101 in two adjacent sub-pixels in the same display row, or may be connected to the pixel driving circuits 101 in three or more sub-pixels in the same display row.

[0140] FIG8 is a schematic diagram of a circuit implementation of a voltage control circuit and a pixel driving circuit. As shown in FIG8 , the light emitting device may include an OLED. The anode of the OLED is connected to the second electrode D of the driving transistor M0, and the cathode of the OLED is connected to the input terminal of the second power supply signal VSS.

[0141] In an exemplary embodiment, the voltage of the second power signal VSS may be a negative voltage or a ground voltage V GND(usually 0V). The voltage of the initialization signal Vinit can be the ground voltage V GND .

[0142] In an exemplary embodiment, the OLED may be a Micro-OLED or a Mini-OLED to facilitate high PPI display.

[0143] In one exemplary embodiment, the voltage control circuit 110 is connected to two pixel driving circuits 101 in a display row. The pixel driving circuit 101 includes a driving transistor M0, a third transistor M3, a fourth transistor M4, and a storage capacitor Cst. The voltage control circuit 110 includes a first transistor M1 and a second transistor M2. The driving transistor M0, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all transistors fabricated in the substrate.

[0144] As shown in FIG8 , the control electrode of the first transistor M1 is connected to the input terminal of the reset control signal RE and is configured to receive the reset control signal RE. The first electrode of the first transistor M1 is connected to the input terminal of the initialization signal Vinit and is configured to receive the initialization signal Vinit. The second electrode of the first transistor M1 is respectively connected to the first electrode S of the corresponding drive transistor M0 and the second electrode of the second transistor M2. The control electrode of the second transistor M2 is connected to the input terminal of the emission control signal EM and is configured to receive the emission control signal EM. The first electrode of the second transistor M2 is connected to the input terminal of the first power signal VDD and is configured to receive the first power signal VDD. The second electrode of the second transistor M2 is respectively connected to the first electrode S of the corresponding drive transistor M0 and the second electrode of the first transistor M1. In an exemplary embodiment, the first transistor M1 and the second transistor M2 can be of different types. For example, the first transistor M1 is an N-type transistor and the second transistor M2 is a P-type transistor, or the first transistor M1 is a P-type transistor and the second transistor M2 is an N-type transistor. In some possible implementations, the first transistor M1 and the second transistor M2 can be of the same type, which can be designed and determined based on the actual application environment.

[0145] As shown in FIG8 , the pixel driving circuit 101 includes a driving transistor M0, a third transistor M3, a fourth transistor M4, and a storage capacitor Cst. The control electrode G of the driving transistor M0 is connected. The first electrode S of the driving transistor M0 is connected to the second electrode of the first transistor M1 and the second electrode of the second transistor M2. The second electrode D of the driving transistor M0 is connected to the anode of the OLED. The control electrode of the third transistor M3 is connected to the input terminal of the first control scan signal S1 and is configured to receive the first control scan signal S1. The first electrode of the third transistor M3 is connected to the input terminal of the data signal DA and is configured to receive the data signal DA. The second electrode of the third transistor M3 is connected to the control electrode G of the driving transistor M0. The control electrode of the fourth transistor M4 is connected to the input terminal of the second control scan signal S2 and is configured to receive the second control scan signal S2. The first electrode of the fourth transistor M4 is connected to the input terminal of the data signal DA and is configured to receive the data signal DA. The second electrode of the fourth transistor M4 is connected to the control electrode G of the driving transistor M0. The first end of the storage capacitor Cst is connected to the control electrode G of the driving transistor M0, and the second end of the storage capacitor Cst is connected to the ground terminal GND. In an exemplary embodiment, the driving transistor M0 may be an N-type transistor, and the third transistor M3 and the fourth transistor M4 may be of different types. For example, the third transistor M3 may be an N-type transistor, and the fourth transistor M4 may be a P-type transistor. When the voltage of the data signal DA is a voltage corresponding to a high grayscale, the P-type fourth transistor M4 is turned on to transmit the data signal DA to the control electrode G of the driving transistor M0. This can prevent the voltage of the data signal DA from being affected by, for example, the threshold voltage of the N-type third transistor M3. When the voltage of the data signal DA is a voltage corresponding to a low grayscale, the N-type third transistor M3 is turned on to transmit the data signal DA to the control electrode G of the driving transistor M0. This can prevent the voltage of the data signal DA from being affected by the threshold voltage of the P-type fourth transistor M4. In this way, the voltage range input to the control electrode G of the driving transistor M0 can be increased.

[0146] In an exemplary embodiment, the third transistor M3 is a P-type transistor, and the fourth transistor M4 is an N-type transistor.

[0147] In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 5T1C, or 7T1C circuit structure, or may be a circuit structure having an internal compensation function or an external compensation function.

[0148] FIG9 is a schematic structural diagram of a display substrate provided by another exemplary embodiment of the present disclosure. As shown in FIG9 , the display substrate may further include: an organic light-emitting layer 40, a second electrode 50, an encapsulation layer 60, a filter layer 70, and an optical device layer 80 sequentially stacked on the pixel definition layer; the filter layer includes: a plurality of filters; the optical device layer includes: a plurality of optical devices; the orthographic projections of adjacent filters on the base substrate at least partially overlap, and the plurality of filters and the plurality of optical devices correspond one to one;

[0149] The orthographic projection of the filter on the substrate partially overlaps with the orthographic projection of the corresponding optical device on the substrate; and there is a gap between adjacent optical devices.

[0150] In an exemplary embodiment of the present disclosure, as shown in Figure 9, the filter layer 70 may include a red filter (CFR) and a green filter (CFG). The optical device layer may have optical devices corresponding to the red filter (CFR) and the green filter (CFG).

[0151] In an exemplary embodiment of the present disclosure, as shown in FIG. 9 , the display substrate may further include a bonding layer (CT) 90 .

[0152] In an exemplary embodiment, the interval between adjacent optical devices is smaller than the length of the optical devices along a direction perpendicular to the substrate and is in a range of 0.2 μm to 0.4 μm.

[0153] In an exemplary embodiment, the length of the optical device 41 along a direction perpendicular to the substrate is smaller than the length of the optical device along a direction in which the substrate extends.

[0154] In an exemplary embodiment, the length of the optical device 41 along the direction perpendicular to the substrate is 1 micrometer to 2 micrometers, and the length of the optical device along the extending direction of the substrate is 2-4 micrometers.

[0155] In an exemplary embodiment, the optical device 41 is a lens.

[0156] In an exemplary embodiment, the lens may be made of a photoresist material.

[0157] In an exemplary embodiment, the lens may be hemispherical, or may be other shapes that can focus light.

[0158] Figure 10 is a schematic diagram of the structure of an organic light-emitting layer provided in an embodiment of the present disclosure. As shown in Figure 10, an organic light-emitting layer provided in an exemplary embodiment includes a first light-emitting sublayer 331, a first charge generation layer 332, a second light-emitting sublayer 333, a second charge generation layer 334, and a third light-emitting sublayer 335, stacked sequentially between a first electrode and a second electrode.

[0159] As shown in Figure 10, the first luminescent sublayer 331 is configured to emit light of the first color and includes a first hole transport layer (HTL) 3311, a first luminescent material layer (EML) 3312, and a first electron transport layer (ETL) 3313 stacked in sequence. The second luminescent sublayer 333 is configured to emit light of the second color and includes a second hole transport layer 3331, a second luminescent material layer 3332, and a second electron transport layer 3333 stacked in sequence. The third luminescent sublayer 335 is configured to emit light of the third color and includes a third hole transport layer 3351, a third luminescent material layer 3352, and a third electron transport layer 3353 stacked in sequence. The first charge generation layer 332 is disposed between the first luminescent sublayer 331 and the second luminescent sublayer 333, connecting the two luminescent sublayers in series to facilitate carrier transfer. The second charge generation layer 334 is disposed between the second luminescent sublayer 333 and the third luminescent sublayer 335, connecting the two luminescent sublayers in series to facilitate carrier transfer. Because the organic light-emitting layer includes a first light-emitting material layer that emits a first color of light, a second light-emitting material layer that emits a second color of light, and a third light-emitting material layer that emits a third color of light, the light ultimately emitted by the organic light-emitting layer is mixed light. For example, the first light-emitting material layer can be a red light-emitting material layer that emits red light, the second light-emitting material layer can be a green light-emitting material layer that emits green light, and the third light-emitting material layer can be a blue light-emitting material layer that emits blue light, so that the organic light-emitting layer ultimately emits white light.

[0160] In actual implementation, the structure of the organic light-emitting layer can be designed according to actual needs. Within each light-emitting sublayer, a hole injection layer and an electron injection layer can be provided to improve the efficiency of electron and hole injection into the light-emitting material layer. To simplify the structure of the organic light-emitting layer, the first electron transport layer 3313, the first charge generation layer 332, and the second hole transport layer 3331 can be eliminated. That is, the second light-emitting material layer 3332 can be provided directly on the first light-emitting material layer 3312.

[0161] In an exemplary embodiment, the organic light emitting layer may include an organic light emitting layer emitting a first color light and an organic light emitting layer emitting complementary light of the first color light, and the two organic light emitting layers are sequentially stacked relative to the base substrate, thereby emitting white light as a whole.

[0162] In an exemplary embodiment, the second electrode may be a planar electrode.

[0163] In an exemplary embodiment, the second electrode is a transmissive electrode for transmitting light emitted by the organic light emitting layer.

[0164] In an exemplary embodiment, the second electrode may be made of indium tin oxide or zinc tin oxide, or may be other transparent conductive materials.

[0165] In an exemplary embodiment, the display substrate may further include: an encapsulation layer and a color filter layer located on a side of the second electrode away from the substrate.

[0166] In an exemplary embodiment, the encapsulation layer may have a stacked structure and may include a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer.

[0167] In one exemplary embodiment, the first inorganic encapsulation layer may be made of silicon nitride. This first inorganic encapsulation layer can prevent damage to the light-emitting structure layer during the fabrication of the second inorganic encapsulation layer. Because the first inorganic encapsulation layer is inorganic, it not only has excellent encapsulation properties but also has good adhesion to the second electrode, ensuring the encapsulation effect of the encapsulation layer.

[0168] In an exemplary embodiment, the second inorganic encapsulation layer may be made of silicon oxide. The second inorganic encapsulation layer can block water and oxygen from entering the light-emitting structure layer, thereby extending the service life of the light-emitting structure layer.

[0169] In one exemplary embodiment, the material used to make the third organic encapsulation layer may include polyparaxylene. Because the third organic encapsulation layer has organic properties, it not only has excellent organic encapsulation properties but also has excellent particle encapsulation capabilities, effectively encapsulating particles on the film layer and preventing them from piercing the film layer. Furthermore, materials with organic properties can effectively release stress between inorganic layers, preventing defects such as microcracks or peeling in the film layer due to high stress. The third organic encapsulation layer 43 also has excellent flatness, providing a relatively flat substrate for the subsequent color filter layer production, preventing damage to the second inorganic encapsulation layer during the color filter layer production process.

[0170] In an exemplary embodiment, the first inorganic encapsulation layer and the second inorganic encapsulation layer are formed using a deposition process; and the deposition density of the first inorganic encapsulation layer is less than the deposition density of the second inorganic encapsulation layer.

[0171] In an exemplary embodiment, the display substrate may further include a cover plate, wherein the cover plate is located on a side of the optical device layer away from the base substrate.

[0172] In one exemplary embodiment, the display substrate further comprises: a frame sealant. The cover plate is fixed to the base substrate by the frame sealant. The frame sealant is disposed between the base substrate and the cover plate, which can provide protection against water and oxygen intrusion, thereby significantly improving the life of the silicon-based OLED display substrate. In another exemplary embodiment, the frame sealant can be disposed on the side of the cover plate, and the four sides of the cover plate and the base substrate are sealed by the frame sealant. The end face of the frame sealant away from the base substrate is located between the surface of the cover plate adjacent to the base substrate and the surface of the cover plate away from the base substrate, thereby ensuring the sealing effect and preventing the frame sealant from protruding above the cover plate, thereby preventing the thickness of the display substrate from increasing.

[0173] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and removal of photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0174] In an exemplary embodiment of the present disclosure, taking the display substrate provided in FIG. 1 as an example, the preparation process of the display substrate may include the following operations.

[0175] (1) Forming a second structure of the first electrode: FIG11A is a schematic diagram of a display substrate provided in an embodiment of the present disclosure. As shown in FIG11A , a first metal film, a second metal film, a third metal film, and a fourth metal film are deposited on a base substrate 10, and the first metal film, the second metal film, the third metal film, and the fourth metal film are patterned through a composition process to form a second structure 202.

[0176] In an exemplary embodiment, the first metal film, the second metal film, the third metal film and the fourth metal film may be titanium (Ti), titanium nitride (TiN), aluminum (Al), titanium nitride TiN and indium tin oxide (ITO), respectively, that is, titanium (Ti), titanium nitride (TiN), aluminum (Al), titanium nitride TiN and indium tin oxide (ITO) may be sequentially plated on the anode on the CMOS substrate from bottom to top.

[0177] In one exemplary embodiment, TiN and ITO can be deposited over the Al. Both TiN and ITO are very thin. These two layers protect the Al from yellow light after deposition and from damage caused by etching plasma and cleaning solutions. Plating TiN over the Al prevents the Al, which is more active and unable to come into direct contact with the ITO, from extracting oxygen from the ITO, leading to indium precipitation and affecting the ITO implantation efficiency during evaporation.

[0178] (2) Forming a first structure of a first electrode: FIG11B is a second schematic diagram of an organic light-emitting diode display substrate provided in an embodiment of the present disclosure. As shown in FIG11B , a transparent metal film is deposited on the second structure obtained in FIG11A , and the transparent metal film is patterned through a composition process to form a first structure 201, thereby forming a first electrode 20 including the first structure 201 and the second structure 202.

[0179] In one exemplary embodiment, the transparent metal film can be indium tin oxide (ITO). Using ITO to coat the anode metal sidewalls protects the aluminum, preventing aluminum corrosion on the pixel sidewalls during subsequent manufacturing processes. Furthermore, the direct overlap between the aluminum and ITO on the pixel sidewalls means that even if indium precipitates due to the aluminum robbing the ITO of oxygen, this area is non-luminescent and does not affect light extraction.

[0180] (3) Forming a First Inorganic Layer of a Pixel Definition Layer: FIG11C is a third schematic diagram of an organic light-emitting diode display substrate provided in an embodiment of the present disclosure. As shown in FIG11C , a first inorganic thin film is deposited on the first electrode 20 obtained in FIG11B , and a first inorganic layer 301 is formed through two patterning processes. The first inorganic thin film may be silicon oxide (SiO).

[0181] In an exemplary embodiment, the present disclosure may use a plasma enhanced chemical vapor deposition (PECVD) process to deposit silicon oxide.

[0182] In an exemplary embodiment, etching can be performed in two steps: the first step is to etch the entire surface of the photoresist. After the photoresist (PR) above the pixel is completely etched, the second step is performed; the second step controls the photoresist and SiO selectivity ratio to 1:1, and simultaneously thins the photoresist and SiO to expose the ITO above the pixel.

[0183] (4) Forming the second inorganic layer 302, the third inorganic layer 303 and the fourth inorganic layer 304 of the pixel definition layer: FIG11D is a fourth schematic diagram of the organic light emitting diode display substrate provided by an embodiment of the present disclosure. As shown in FIG11D , a second inorganic film, a third inorganic film and a fourth inorganic film are deposited on the first inorganic layer 301 obtained in FIG11C , and the second inorganic film, the third inorganic film and the fourth inorganic film are patterned by a composition process to form the second inorganic layer 302, the third inorganic layer 303 and the fourth inorganic layer 304, thereby forming a pixel definition layer 301 including the first inorganic layer 301, the second inorganic layer 302, the third inorganic layer 303 and the fourth inorganic layer 304.

[0184] In an exemplary embodiment, a groove D is provided on the pixel definition layer.

[0185] In an exemplary embodiment, the second inorganic thin film, the third inorganic thin film, and the fourth inorganic thin film may be plated with silicon oxide (SiO), silicon nitride (SiN), and silicon oxide (SiO), respectively.

[0186] In an exemplary embodiment, the etching selectivity of the second inorganic thin film to the transparent metal thin film is about 20:1 to 40:1; and the etching selectivity of the fourth inorganic thin film to the third inorganic thin film is about 1:6 to 1:9.

[0187] In one exemplary embodiment, the present disclosure can sequentially deposit silicon oxide (SiO), silicon nitride (SiN), and silicon oxide (SiO) on the first inorganic layer 301 using a chemical vapor deposition (PECVD) process, apply photoresist, perform exposure and development, and then dry etch to create a PDL opening. During the PDL etching process, the SiO to underlying ITO selectivity ratio is controlled between 20:1 and 40:1, and the overetching amount is controlled to achieve a thickness of 1.3 to 4 times the thickness of the ITO at the PDL opening.

[0188] In an exemplary embodiment, the groove D is formed on the pixel definition layer by utilizing the difference in etching selectivity between SiO and SiN, and the groove has an undercut structure.

[0189] In an exemplary embodiment, sulfur hexafluoride (SF6) may be used for etching to control the selectivity of SiO to SiN to be in a range of 1:6 to 1:9.

[0190] The present disclosure also provides a method for preparing a display substrate, which is configured to prepare a display substrate. The method for preparing a display substrate may include:

[0191] Step 100: forming a first electrode on a base substrate.

[0192] In one exemplary embodiment, the sidewall of the first electrode is stepped;

[0193] Step 200: forming a pixel definition layer on the first electrode.

[0194] In an exemplary embodiment, the pixel definition layer is provided with a pixel opening exposing the first electrode, and the area where the first electrode is located includes: a first electrode area and a second electrode area, the orthographic projection of the first electrode located in the first electrode area on the substrate coincides with the orthographic projection of the pixel opening on the substrate, and the orthographic projection of the first electrode located in the second electrode area on the substrate partially overlaps with the orthographic projection of the pixel definition layer on the substrate; the thickness of the first electrode located in the first electrode area is less than the thickness of the first electrode located in the second electrode area.

[0195] The display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and implementation effect are similar, which will not be repeated here.

[0196] In an example embodiment of the present disclosure, forming a first electrode on a base substrate may include:

[0197] Depositing a first metal film, a second metal film, a third metal film and a fourth metal film on a base substrate, and patterning the first metal film, the second metal film, the third metal film and the fourth metal film through a composition process to form a second structure;

[0198] A transparent metal film is deposited on the second structure, and the transparent metal film is patterned by a composition process to form a first structure, thereby forming a first electrode including the first structure and the second structure.

[0199] In an example embodiment of the present disclosure, forming a pixel definition layer on the first electrode may include:

[0200] Depositing a first inorganic thin film on the first electrode and forming a first inorganic layer through two patterning processes;

[0201] Depositing a second inorganic film, a third inorganic film, and a fourth inorganic film on the first inorganic layer, patterning the second inorganic film, the third inorganic film, and the fourth inorganic film through a composition process to form a second inorganic layer, a third inorganic layer, and a fourth inorganic layer, thereby forming a pixel definition layer including the first inorganic layer, the second inorganic layer, the third inorganic layer, and the fourth inorganic layer;

[0202] The selectivity ratio of etching the second inorganic film to the transparent metal film is about 20:1 to 40:1;

[0203] The selectivity ratio of etching the fourth inorganic thin film to the third inorganic thin film is approximately 1:6 to 1:9.

[0204] An embodiment of the present disclosure further provides a display device, including: a display substrate.

[0205] The display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and implementation effect are similar, which will not be repeated here.

[0206] In an exemplary embodiment, the display device includes a VR device or an AR device.

[0207] In an exemplary embodiment, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc., and the embodiments of the present disclosure do not impose any limitation on this.

[0208] The drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure, and other structures may refer to general designs.

[0209] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0210] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate, comprising: A base substrate and a first electrode and a pixel definition layer sequentially arranged on the base substrate, the pixel definition layer is provided with a pixel opening exposing the first electrode, the area where the first electrode is located includes: a first electrode area, a second electrode area and a smooth transition area, the smooth transition area is located between the first electrode area and the second electrode area, the orthographic projection of the first electrode located in the first electrode area on the base substrate coincides with the orthographic projection of the pixel opening on the base substrate, and the orthographic projection of the first electrode located in the second electrode area on the base substrate partially overlaps with the orthographic projection of the pixel definition layer on the base substrate; The thickness of the first electrode located in the first electrode region is smaller than the thickness of the first electrode located in the second electrode region.

2. The display substrate according to claim 1, wherein: An orthographic projection of an edge of the top layer of the pixel definition layer on the substrate is located within an orthographic projection of the transition region on the substrate.

3. The display substrate according to claim 1, wherein: The first electrode comprises: a first structure and a second structure, wherein the first structure is located on a side of the second structure away from the substrate; The orthographic projection of the first structure on the base substrate covers the orthographic projection of the second structure on the base substrate, and the thickness of the second structure is greater than the thickness of the first structure; The first structure covers the sidewalls of the second structure.

4. The display substrate according to claim 3, wherein: The surface of the second structure close to the pixel definition layer is flat; The first thickness is the thickness of the second structure located in the first electrode region, and the second thickness is the thickness of the second structure located in the second electrode region. The first thickness is smaller than the second thickness.

5. The display substrate according to claim 4, wherein: The ratio of the second thickness to the first thickness ranges from 1.3 / 1 to 4 / 1.

6. The display substrate according to claim 4, wherein: The thickness of the pixel definition layer that overlaps with the surface of the second structure close to the pixel definition layer in the orthographic projection on the substrate is a third thickness; The ratio of the third thickness to the thickness difference is in the range of 10:1 to 20:1, wherein the thickness difference is The difference between the second thickness and the first thickness.

7. The display substrate according to claim 3, wherein: The first structure is a transparent electrode structure, and the thickness of the first structure is greater than 80 angstroms.

8. The display substrate according to claim 3, wherein: The second structure comprises: a first sublayer, a second sublayer, a third sublayer, and a fourth sublayer stacked in sequence on the base substrate; the thickness of the third sublayer is greater than the thickness of any film layer among the first sublayer, the second sublayer, and the fourth sublayer; The orthographic projection of the surface of the first sub-layer away from the substrate on the substrate covers the orthographic projection of the second sub-layer on the substrate, the orthographic projection of the surface of the second sub-layer away from the substrate on the substrate covers the orthographic projection of the third sub-layer on the substrate, and the orthographic projection of the surface of the third sub-layer away from the substrate on the substrate covers the orthographic projection of the fourth sub-layer on the substrate; The side wall of the second structure is an inclined surface.

9. The display substrate according to claim 8, wherein: The conductivity of the third sublayer is greater than the conductivity of any film layer among the first sublayer, the second sublayer and the fourth sublayer.

10. The display substrate according to claim 9, wherein: The first sub-layer is made of titanium, the second sub-layer is made of titanium nitride, the third sub-layer is made of aluminum, and the fourth sub-layer is made of titanium nitride.

11. The display substrate according to claim 3, wherein: The pixel definition layer includes: a first inorganic layer, a second inorganic layer, a third inorganic layer and a fourth inorganic layer sequentially stacked on the base substrate; The surface of the first inorganic layer away from the substrate is flat, and the distance between the surface of the first inorganic layer away from the substrate and the substrate is equal to the distance between the surface of the first structure located in the second electrode region and on the second structure and the substrate.

12. The display substrate according to claim 11, wherein: An orthographic projection of a surface of the first inorganic layer close to the substrate on the substrate at least partially overlaps with an orthographic projection of a surface of the substrate on the substrate on the substrate.

13. The display substrate according to claim 11, wherein: The orthographic projection of the second inorganic layer on the base substrate covers the orthographic projection of the first inorganic layer on the base substrate, and the second inorganic layer is provided with a first via hole, and the first via hole exposes the first electrode located in the first electrode region.

14. The display substrate according to claim 13, wherein: The orthographic projection of the third inorganic layer on the substrate at least partially overlaps with the orthographic projection of any one of the first inorganic layer and the second inorganic layer on the substrate; The third inorganic layer is provided with a second via hole and a third via hole, the second via hole exposes the first electrode located in the first electrode region, and the third via hole exposes the second inorganic layer; The orthographic projection of the first via hole on the base substrate coincides with the orthographic projection of the second via hole on the base substrate.

15. The display substrate according to claim 14, wherein: The orthographic projection of the fourth inorganic layer on the substrate at least partially overlaps with the orthographic projection of any one of the first inorganic layer and the third inorganic layer on the substrate; The fourth inorganic layer is provided with a fourth via hole and a fifth via hole, the fourth via hole exposes the first electrode located in the first electrode region, and the fifth via hole exposes the second inorganic layer; The orthographic projection of the fourth via hole on the base substrate coincides with the orthographic projection of the second via hole on the base substrate, and the orthographic projection of the fifth via hole on the base substrate partially overlaps with the orthographic projection of the third via hole on the base substrate.

16. The display substrate according to claim 15, wherein: The third via hole and the fourth via hole constitute a groove formed on the pixel definition layer, and the groove is an undercut structure.

17. The display substrate according to claim 11, wherein: The thickness of the first inorganic layer is greater than the thickness of any film layer among the second inorganic layer, the third inorganic layer and the fourth inorganic layer, and the thickness of the third inorganic layer is greater than the thickness of any film layer among the second inorganic layer and the fourth inorganic layer; The etching rate of the third inorganic layer is greater than the etching rate of the fourth inorganic layer.

18. The display substrate according to claim 11, wherein: The first inorganic layer is made of silicon oxide, the second inorganic layer is made of silicon oxide, the third inorganic layer is made of silicon nitride, and the fourth inorganic layer is made of silicon oxide.

19. The display substrate according to claim 1, wherein: The display substrate further comprises: an organic light emitting layer, a second electrode, a packaging layer, a filter layer and an optical device layer sequentially stacked on the pixel definition layer; the filter layer comprises: a plurality of filters; the optical device layer comprises: a plurality of optical devices; Orthographic projections of adjacent filters on the substrate at least partially overlap, and the multiple filters correspond to the multiple optical devices one by one; The orthographic projection of the filter on the substrate partially overlaps with the orthographic projection of the corresponding optical device on the substrate; and there is a gap between adjacent optical devices.

20. A display device, comprising: A display substrate as claimed in any one of claims 1 to 19.

21. A method for preparing a display substrate, configured to prepare the display substrate according to any one of claims 1 to 19, the method comprising: forming a first electrode on the base substrate; A pixel definition layer is formed on the first electrode.

22. The method according to claim 21, wherein: The forming of the first electrode on the substrate includes: depositing a first metal film, a second metal film, a third metal film and a fourth metal film on the substrate, and patterning the first metal film, the second metal film, the third metal film and the fourth metal film through a composition process to form a second structure; A transparent metal film is deposited on the second structure, and the transparent metal film is patterned by a composition process to form a first structure, thereby forming a first electrode including the first structure and the second structure.

23. The method according to claim 22, wherein: Forming a pixel definition layer on the first electrode includes: depositing a first inorganic thin film on the first electrode, and forming a first inorganic layer through two patterning processes; Depositing a second inorganic film, a third inorganic film and a fourth inorganic film on the first inorganic layer, patterning the second inorganic film, the third inorganic film and the fourth inorganic film through a composition process to form a second inorganic layer, a third inorganic layer and a fourth inorganic layer, and forming a pixel definition layer including: the first inorganic layer, the second inorganic layer, the third inorganic layer and the fourth inorganic layer; The etching selectivity of the second inorganic film to the transparent metal film is in the range of 20:1 to 40:1; The selectivity ratio of etching the fourth inorganic thin film to the third inorganic thin film is in a range of 1:6 to 1:9.

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