Display panel and display apparatus

Abstract

A display panel and a display apparatus comprising the display panel. The display panel comprises a pixel definition portion. A recessed region (2105) is formed between two adjacent pixel electrodes (221) on the surface of the pixel definition portion away from a drive backplane (1). A bottom surface of the recessed region (2105) comprises a first smooth curved section protruding in a direction away from the drive backplane (1). The bottom surface of the recessed region (2105) is provided with a partition recess (2102). A common electrode (222) forms a protruding portion (2221) in an orthographic projection region of the partition recess (2102). The protruding first smooth curved section can enable the contour of the protruding portion (2221) to become curved, and increases the distance between the protruding portion (2221) and the pixel electrodes (221), such that the probability that the protruding portion (2221) punctures and contacts the pixel electrodes (221) is greatly reduced, thereby reducing the risk of short circuits between the common electrode and the pixel electrodes while ensuring the partitioning of a light-emitting layer group.

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] OLED (Organic Light Emitting Diode) display panels have been widely used in various display devices. For display panels using stacked light-emitting devices, crosstalk problems occur between sub-pixels of different colors.

[0003] In order to minimize crosstalk problems, a partition groove is set between two adjacent sub-pixels to isolate the common layer. However, the existing partition groove easily leads to the formation of leakage paths or electric fields between the common electrode and the pixel electrode, causing crosstalk between different sub-pixels, thereby affecting the color gamut and quality of the displayed image.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0005] Public content

[0006] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and to provide a display panel and a display device.

[0007] According to one aspect of the present disclosure, a display panel is provided, comprising a driving backplane, a plurality of pixel electrodes, a pixel definition layer, a light-emitting layer group and a common electrode, wherein the plurality of pixel electrodes are arranged at intervals on one side of the driving backplane; the pixel definition layer is arranged on a side of the plurality of pixel electrodes away from the driving backplane, the pixel definition layer is provided with pixel openings exposing the pixel electrodes, a pixel definition portion is formed between two adjacent pixel openings, a side of the pixel definition portion away from the base substrate forms a recessed area between two adjacent pixel electrodes, the bottom surface of the recessed area comprises a first smooth curved surface convex in a direction away from the base substrate, and a partition groove is provided on the bottom surface of the recessed area; the light-emitting layer group is arranged on a side of the pixel definition layer away from the driving backplane, the light-emitting layer group is disconnected in the partition groove; the common electrode is arranged on a side of the light-emitting layer group away from the driving backplane, the common electrode forms a protrusion close to the base substrate in the positive projection area of ​​the partition groove, and the contour of the protrusion is a curve.

[0008] In one embodiment of the present disclosure, the partition groove includes a first groove section and a second groove section which are sequentially away from the drive back plate, the orthographic projection of the second groove section on the drive back plate is located within the orthographic projection of the first groove section on the drive back plate, and the area of ​​the orthographic projection of the second groove section on the drive back plate is smaller than the area of ​​the orthographic projection of the first groove section on the drive back plate.

[0009] In one embodiment of the present disclosure, the side surface of the first groove segment includes a second smooth curved surface that is concave toward the pixel opening.

[0010] In one embodiment of the present disclosure, the curvature of the second smooth curved surface is greater than the curvature of the first smooth curved surface.

[0011] In one embodiment of the present disclosure, the bottom surface of the first groove segment includes a third smooth curved surface that is concave toward the substrate.

[0012] In one embodiment of the present disclosure, the curvature of the first smooth curved surface is greater than the curvature of the third smooth curved surface.

[0013] In one embodiment of the present disclosure, the angle between the bottom surface of the recessed area and the first direction is smaller than the angle between the side surface of the recessed area and the first direction, the angle between the side surface of the recessed area and the first direction is smaller than the angle between the side wall of the pixel opening and the first direction, and the first direction is perpendicular to the thickness direction of the display panel.

[0014] In one embodiment of the present disclosure, the pixel electrode includes a first pixel electrode layer and a second pixel electrode layer, the first pixel electrode layer is arranged on one side of the driving backplane, the second pixel electrode layer includes a first covering portion, the first covering portion covers a side of the first pixel electrode layer away from the driving backplane and wraps the side of the first pixel electrode layer, and the material of the second pixel electrode layer is indium tin oxide.

[0015] In one embodiment of the present disclosure, the second pixel electrode layer also includes a second covering portion and a third covering portion, the second covering portion is connected to the first covering portion and extends toward the direction close to the base substrate, the third covering portion is connected to the second covering portion, and the third covering portion is located between two adjacent first pixel electrode layers.

[0016] In one embodiment of the present disclosure, an angle between the second covering portion and the first direction is smaller than an angle between the third covering portion and the first direction.

[0017] In one embodiment of the present disclosure, two adjacent pixel electrodes are defined as a first pixel electrode and a second pixel electrode, a size of the third covering portion of the first pixel electrode along the first direction is d2, a size of the third covering portion of the second pixel electrode along the first direction is d2', a width of a portion of the recessed area and the first pixel electrode located on the same side of the partition groove is D1, a width of a portion of the recessed area and the second pixel electrode located on the same side of the partition groove is D1', and (d2-d2')×(D1-D1')>0.

[0018] In one embodiment of the present disclosure, a dimension of the first groove segment along the second direction is greater than a dimension of the second covering portion along the second direction, and the second direction is a thickness direction of the display panel.

[0019] In one embodiment of the present disclosure, an orthographic projection of the protrusion on the driving backplane does not overlap with an orthographic projection of the pixel electrode on the driving backplane.

[0020] In one embodiment of the present disclosure, an edge of the third covering portion is closer to an edge of the pixel opening than an edge of the first groove segment in a first direction, and the first direction is perpendicular to a thickness direction of the display panel.

[0021] In one embodiment of the present disclosure, a pixel definition portion is located between two adjacent pixel openings. The pixel definition portion includes a first sub-portion and a second sub-portion that are sequentially arranged in a direction away from the driving backplane. The first slot section is a first through hole passing through the first sub-portion, and the second slot section is a second through hole passing through the second sub-portion.

[0022] In one embodiment of the present disclosure, the pixel defining portion further includes a third sub-portion, which fills a gap between two adjacent pixel electrodes and partially covers the two pixel electrodes.

[0023] In one embodiment of the present disclosure, the width of the first slot segment gradually increases in a direction away from the driving back plate.

[0024] In one embodiment of the present disclosure, the width of the second slot segment gradually decreases in a direction away from the substrate.

[0025] In one embodiment of the present disclosure, the width increase amplitude of the first slot segment gradually increases in the direction away from the substrate, and the width decrease amplitude of the second slot segment gradually decreases in the direction away from the substrate.

[0026] In one embodiment of the present disclosure, an orthographic projection of the second slot segment on the driving backplane overlaps with an orthographic projection of the first slot segment on the driving backplane.

[0027] In one embodiment of the present disclosure, the width of the partition groove gradually decreases in a direction away from the driving back plate.

[0028] In one embodiment of the present disclosure, the light-emitting layer group includes a sub-light-emitting layer group. A common layer is provided between the sub-light-emitting layer group and the pixel electrode. The common layer is disconnected between two adjacent partition grooves, and the sub-light-emitting layer group covers the common layer and its interruption.

[0029] In one embodiment of the present disclosure, the driving backplane includes a plurality of thin film transistors, and the thin film transistors are silicon-based thin film transistors.

[0030] According to another aspect of the present disclosure, a display device is provided, including the display panel provided in one aspect of the present disclosure.

[0031] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0033] FIG1 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure when the display panel includes a color filter layer and a microlens layer.

[0034] FIG2 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure, when the pixel defining portion includes a first sub-portion and a second sub-portion, and the bottom surface of the recessed area is a plane.

[0035] FIG3 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure when the pixel defining portion further includes a third sub-portion and the bottom surface of the recessed area is a plane.

[0036] 4 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure, when the pixel defining portion includes a first sub-portion and a second sub-portion, and the bottom surface of the recessed area is a first smooth curved surface.

[0037] FIG5 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure when the pixel defining portion further includes a third sub-portion and the bottom surface of the recessed area is a first smooth curved surface.

[0038] 6 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure, when the pixel defining portion includes a first sub-portion and a second sub-portion, and the side surface of the first groove segment is a second smooth curved surface.

[0039] 7 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure when the pixel defining portion further includes a third sub-portion and the side surface of the first groove segment is a second smooth curved surface.

[0040] FIG8 is a partial enlarged view of portion G in FIG7 .

[0041] FIG. 9 is a diagram showing the dimensions of various parts of the partition groove in the display panel shown in FIG. 7 .

[0042] FIG10 is a partial enlarged view of the H portion in FIG9 .

[0043] 11 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure, when the pixel defining portion further includes a third sub-portion and the width of the first groove segment gradually increases in a direction away from the driving backplane.

[0044] Figure 12 is a cross-sectional schematic diagram of a display panel involved in an embodiment of the present disclosure when the pixel definition portion further includes a third sub-portion, the width of the first groove segment gradually increases in the direction away from the driving backplane, and the width of the second groove segment gradually decreases in the direction away from the base substrate.

[0045] FIG13 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure when the pixel defining portion further includes a third sub-portion and the sidewalls of the partitioning groove are configured to be arc-shaped.

[0046] 14 is a cross-sectional schematic diagram of a display panel according to an embodiment of the present disclosure when the pixel defining portion further includes a third sub-portion and the width of the first groove segment and the width of the second groove segment gradually decrease in a direction away from the driving backplane.

[0047] 15 is a cross-sectional schematic diagram of a display panel according to an embodiment of the present disclosure when the pixel defining portion further includes a third sub-portion and the width of the first groove segment away from the base substrate is equal to the width of the second groove segment close to the base substrate.

[0048] 16 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure when the pixel defining portion further includes a third sub-portion and the width of the first groove segment is equal to the width of the second groove segment.

[0049] FIG17 is a schematic cross-sectional view of another display panel according to an embodiment of the present disclosure.

[0050] Description of reference numerals: 1- driving backplane, 10- substrate, 11- transistor, 111- gate, 112- active layer, 113- First source, 114-drain, 115-gate insulating layer, 116-second source, 12-first transistor, 13-second transistor, 14-contact hole, 15-insulating layer, 151-interlayer dielectric layer, 152-protective layer, 153-planarization layer, 16-third conductive layer, 18-buffer layer, 100-driving circuit layer, 2-pixel layer, 21-pixel definition layer, 211-first sublayer, 212-second sublayer, 213-third sublayer, 2101-pixel opening, 2102-partitioning groove, 2103-first groove section, 2104-second groove section, 2105-recessed area, 22-light-emitting device, 221-pixel electrode, 2211-first pixel electrode layer, 2212-second pixel Electrode layer, 2213-first covering portion, 2214-second covering portion, 2215-third covering portion, 222-common electrode, 2221-protrusion, 223-light-emitting layer group, 2231-light-emitting functional layer, 2232-common layer, 2201-first light-emitting device, 2202-second light-emitting device, 2203-third light-emitting device, 3-color filter layer, 31-black matrix, 32-sub-filter unit, 321-red sub-filter unit, 322-green sub-filter unit, 323-blue sub-filter unit, 33-packaging substrate, 4-packaging layer group, 41-first inorganic packaging layer, 42-organic packaging layer, 43-second inorganic packaging layer, 5-microlens layer, 51-microlens, 6-third planarization layer. DETAILED DESCRIPTION

[0051] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0052] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0053] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0054] Micro OLED (micro organic light-emitting diode) display panels use a monocrystalline silicon integrated circuit as a backplane and a top-emitting OLED (organic light-emitting transistor) device as a light source. They offer advantages such as small size, light weight, high contrast, fast response speed, and low power consumption, making them promising candidates for the next generation of mobile display terminals. Currently, Micro OLEDs utilize a white light-emitting layer (EL) combined with a color filter (CF) to achieve color display. The color filter (CF) absorbs light of specific wavelengths, allowing red, blue, or green monochromatic light to pass through.

[0055] Due to the small size and ultra-high pixel density (PPI) of micro-OLED display panels, crosstalk between different sub-pixels can occur, affecting the display panel's color purity and color gamut. In severe cases, this can cause leakage at low grayscale levels, thereby reducing product quality. These display panels typically use stacked light-emitting devices, which connect two light-emitting functional layers via a common layer. The charge generation layer has a strong ability to transmit signals laterally, which can easily cause lateral leakage and lead to crosstalk between different sub-pixels.

[0056] While ensuring that the common layer effectively connects the two adjacent light-emitting functional layers, it is necessary to laterally isolate the common layer to prevent lateral carrier transmission paths, which could cause color cross-talk between different sub-pixels. When isolating the common layer, the common electrode sinks in the area where the orthographic projection of the isolation groove is located, forming a protrusion and puncture close to the drive backplane. If there is a pixel electrode directly below the protrusion and puncture, a leakage path or electric field is likely to form between the two adjacent pixel electrodes, causing the gap between the two adjacent pixel electrodes to emit light, resulting in color cross-talk in some areas between the sub-pixels, thereby affecting the color gamut and quality of the displayed image.

[0057] Based on this, the embodiment of the present disclosure provides a display panel that can prevent color crosstalk between different sub-pixels. As shown in Figures 1 and 4 to 17, the display panel includes a driving backplane 1, a plurality of pixel electrodes 221, a pixel definition layer 21, a light-emitting layer group 223, and a common electrode 222. The plurality of pixel electrodes 221 are spaced apart on one side of the driving backplane 1; the pixel definition layer 21 is provided on a side of the plurality of pixel electrodes 221 away from the driving backplane 1. The pixel definition layer 21 is provided with a pixel opening 2101 exposing the pixel electrode 221. A pixel definition portion is provided between two adjacent pixel openings 2101. A side of the pixel definition portion away from the driving backplane forms a recessed area 2105 between two adjacent pixel electrodes 221. The bottom surface of the region 2105 includes a first smooth curved surface that bulges away from the driving backplane, and the bottom surface of the recessed region 2105 is provided with a partition groove; the light-emitting layer group 223 is provided on the side of the pixel definition layer 21 away from the driving backplane 1, and the light-emitting layer group 223 is disconnected within the partition groove 2102; the common electrode 222 is provided on the side of the light-emitting layer group 223 away from the driving backplane 1, and the common electrode 222 forms a protrusion 2221 approaching the driving backplane in the orthographic projection area of ​​the partition groove 2102, and the orthographic projection of the protrusion 2221 on the driving backplane 1 does not overlap with the orthographic projection of the pixel electrode 221 on the driving backplane 1.

[0058] A side of the pixel definition portion away from the driving backplane 1 forms a recessed area 2105 between two adjacent pixel electrodes 221. The bottom surface of the recessed area 2105 includes a first smooth curved surface that bulges in the direction away from the driving backplane 1. The bottom surface of the recessed area 2105 is provided with a partition groove 2102. The common electrode 222 forms a protrusion 2221 in the positive projection area of ​​the partition groove 2102. The puncture position of the common electrode 222 is usually located in the protrusion 2221. The raised first smooth curved surface can make the contour of the protrusion 2221 into a curve, and reduce the distance between the protrusion 2221 and the pixel electrode 221, so that the probability of the protrusion 2221 puncturing and contacting the pixel electrode 221 is greatly reduced, thereby ensuring the isolation of the organic light-emitting layer while reducing the risk of short circuit between the common electrode and the pixel electrode.

[0059] The display panel involved in the present disclosure is described in detail below with reference to specific embodiments.

[0060] As shown in Figures 1 to 16, the display panel includes a pixel layer 2 and a color filter layer 3. The light-emitting layer 2 may include multiple light-emitting devices 220. In Figure 1, the multiple light-emitting devices 220 are respectively a first light-emitting device 2201, a second light-emitting device 2202 and a third light-emitting device 2203. For example, the first light-emitting device 2201, the second light-emitting device 2202 and the third light-emitting device 2203 are respectively located in different sub-pixels, thereby forming a pixel unit PX. The pixel unit PX can emit full-color light in combination with the color filter layer 3. The color filter layer 3 includes three sub-filter units of different colors, which are respectively a red sub-filter unit 321, a green sub-filter unit 322 and a blue sub-filter unit 323.

[0061] As shown in Figures 2 to 16, the light-emitting device 220 is a stacked electroluminescent device, which includes a pixel electrode 221, a common electrode 222, and a light-emitting layer group 223. The pixel electrode 221 can be the anode of the light-emitting device 220, and the common electrode 222 can be the cathode of the light-emitting device 220. The pixel electrodes 221 of different light-emitting devices 220 are disconnected and insulated from each other in the plane, and the pixel electrodes 221 of all light-emitting devices 220 form a first conductive layer. The common electrodes 222 of different light-emitting devices 220 are an integrated structure, that is, the common electrodes 222 of different light-emitting devices 220 are a continuous and smooth structure formed by the same conductive material layer. The common electrodes 222 of all light-emitting devices 220 form a second conductive layer, and there is no interface between different regions in the second conductive layer. The light-emitting layer group 223 is arranged between the first conductive layer and the second conductive layer. The light-emitting layer group 223 includes two light-emitting functional layers 2231 spaced apart from each other, with a common layer 2232 disposed between adjacent light-emitting functional layers 2231. The common layer 2232 is a charge generation layer, which connects the two light-emitting functional layers 2231. The charge generation layer separates electrons and holes and transfers them to the two light-emitting functional layers 2231.

[0062] One of the pixel electrode 221 and the common electrode 222 is a reflective electrode, and the other is a semi-transparent and semi-reflective electrode. Regardless of whether the pixel electrode 221 is set as a transparent electrode or a semi-transparent electrode, or whether the common electrode 222 is set as a transparent electrode or a semi-transparent electrode, light is emitted from the transparent electrode or the semi-transparent electrode. It can be understood that one of the first conductive layer and the second conductive layer is reflective, and the other is semi-transparent or translucent. For example, the pixel electrode 221 and the common electrode 222 in the first light-emitting device 2201 form a microcavity, which can make the distance from each light-emitting functional layer 2231 to the reflective layer and the wavelength of the light emitted by the light-emitting functional layer 2231 satisfy 2Δ=mλ(m=1, 2, 3, ...), where Δ is the optical path, which is equal to the refractive index of the medium multiplied by the distance the light propagates in the medium multiplied by the refractive index of the medium, so that the emitted light and the reflected light resonate in the microcavity, thereby improving the purity of the light emission and further improving the color gamut and luminous brightness of the display panel.

[0063] Exemplarily, the first conductive layer is a high work function material, for example, also having high reflectivity, such as a stacked structure of Ti / Al / Ti / Mo, wherein metallic titanium can serve as a buffer layer to improve interlayer adhesion, Al serves as a highly reflective material, and Mo serves as a high work function material that directly contacts the organic functional layer to improve carrier injection capability.

[0064] Exemplarily, the material of the second conductive layer is a conductive material with low work function and high transmittance, for example, it can be a transparent metal oxide conductive material, such as indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), etc., or it can be a transparent nano-conductive material such as carbon nanotubes, graphene, nano silver wires, etc.

[0065] The display panel also includes a driving backplane 1, which includes a base substrate 10 and a driving circuit layer 100. For the sake of clarity, only the first sub-pixel area and the second sub-pixel area adjacent to the pixel layer 2 are shown in Figures 2 to 16, and for each sub-pixel area, only the light-emitting element and the transistor 11 directly connected to the light-emitting element in the driving circuit layer 100 are shown. For example, the transistor 11 can be a driving transistor configured to control the magnitude of the current that drives the light-emitting element to emit light. For example, the transistor 11 can also be a light-emitting control transistor for controlling whether the current that drives the light-emitting element to emit light flows. The embodiments of the present disclosure are not limited to this.

[0066] As shown in Figures 2 to 16, the driving backplane 1 includes a base substrate 10, a first conductive layer, an organic functional layer, and a second conductive layer disposed on the base substrate 10. The organic functional layer includes a carrier injection layer 229. The first conductive layer includes a pixel electrode 221 of a first light-emitting device 2201 and a pixel electrode 221 of a second light-emitting device 2202, which are respectively located in a first sub-pixel region and a second sub-pixel region, and are insulated from each other. The pixel electrodes 221 of the first light-emitting device 2201 and the pixel electrodes 221 of the second light-emitting device 2202 are disconnected from each other. The second conductive layer includes a common electrode 222 of the first light-emitting device 2201 and a common electrode 222 of the second light-emitting device 2202, which are respectively located in the first sub-pixel region and the second sub-pixel region, and are connected to each other.

[0067] The display panel provided in the embodiments of the present disclosure uses a silicon substrate as the base substrate 10. The driving circuit layer 100 can be integrated on the silicon substrate to form a driving backplane 1. In this case, the silicon-based circuit can achieve higher precision. The first and second light-emitting elements are formed on the driving backplane 1. The driving backplane 1 includes the base substrate 10 and the driving circuit layer 100 formed on the base substrate 10. The silicon substrate is, for example, single crystal silicon or high-purity silicon.

[0068] The driving circuit layer 100 is formed on the base substrate 10 through a semiconductor process. For example, the active layer 112 (i.e., semiconductor layer), first source electrode 113, and drain electrode 114 of the transistor 11 are formed in the base substrate 10 through a doping process, the insulating layer 15 is formed through a silicon oxidation process, and multiple third conductive layers 16 are formed through a sputtering process. The semiconductor layer of the transistor 11 (such as the active layer in Figures 2 to 14) is located within the base substrate 10 or is part of the base substrate 10.

[0069] The first light-emitting device 2201 is electrically connected to the first transistor 12, and the second light-emitting device 2202 is electrically connected to the second transistor 13. The embodiments of the present disclosure do not limit the specific types of the first transistor 12 and the second transistor 13. The following is an exemplary description of the first transistor 12, which also applies to the second transistor 13 and is therefore not repeated here.

[0070] The pixel electrode 221 of the first light-emitting element is formed on the surface of the driving backplane 1 and is electrically connected to the first source electrode 113 of the first transistor 12 through a contact hole 14 filled with a conductive material (e.g., tungsten) and the multiple conductive layers. Figures 2 to 16 exemplarily illustrate one insulating layer 15 and two third conductive layers 16 , however, the embodiments of the present disclosure do not limit the number of insulating layers 15 and conductive layers.

[0071] For example, the first transistor 12 includes a gate 111, a gate insulating layer 115, an active layer 112, a first source 113, and a drain 114. The embodiments of the present disclosure do not limit the type, material, and structure of the first transistor 12. For example, it can be a top-gate type, a bottom-gate type, etc. The active layer 112 of the first transistor 12 can be an inorganic semiconductor material such as microcrystalline silicon, amorphous silicon, polycrystalline silicon (low-temperature polycrystalline silicon or high-temperature polycrystalline silicon), an oxide semiconductor (such as IGZO), or an organic material such as PBTTT, PDBT-co-TT, PDQT, PDVT-10, dinaphtho-dithiophene (DNTT), or pentacene. For example, the first transistor 12 can be N-type or P-type.

[0072] It should be noted that the transistors used in the embodiments of the present disclosure can all be thin film transistors, field effect transistors or other switching devices with the same characteristics. Some embodiments of the present disclosure are described by taking a field effect transistor (such as a MOS field effect transistor) formed in a silicon substrate as an example. In this example, the silicon substrate is doped (p-type doping or n-type doping) to form an active layer of the transistor, that is, the active layer of the transistor is located in the silicon substrate, or the active layer of the transistor is part of the silicon substrate. The source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, for example, one of the poles can be directly described as the first source 113 and the other pole as the drain 114.

[0073] Some embodiments of the present disclosure are described by taking a field effect transistor (such as a MOS field effect transistor) formed in a silicon substrate as an example. In this example, the silicon substrate is doped (p-type doping or n-type doping) to form an active layer 112 of the transistor, that is, the active layer 112 of the transistor is located in the silicon substrate, or the active layer 112 of the transistor is part of the silicon substrate. The source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, for example, one of the poles can be directly described as the first source 113 and the other pole as the drain 114.

[0074] The topmost conductive layer in the driving backplane 1 can be reflective, for example, a stacked structure of titanium / titanium nitride / aluminum. For example, the conductive layer includes a plurality of sub-layers arranged at intervals, which are respectively arranged in one-to-one correspondence with the plurality of pixel electrodes 221 included in the first conductive layer. In the top emission structure, the conductive layer can be set as a reflective layer to reflect the light emitted by the light-emitting element to improve the light extraction efficiency. For example, the orthographic projection of each electrode in the first conductive layer on the base substrate 10 falls within the orthographic projection of the portion of the conductive layer corresponding to the electrode on the base substrate 10. In this case, the first conductive layer can adopt a transparent conductive oxide material with a high work function, such as ITO, IZO, IGZO, AZO, etc.

[0075] The light-emitting layer 2 of the pixel layer 2 includes a first light-emitting device 2201 and a second light-emitting device 2202 located in the first sub-pixel region and the second sub-pixel region, respectively. The first light-emitting device 2201 and the second light-emitting device 2202 each include a light-emitting layer group 223, as well as a pixel electrode 221 and a common electrode 222 facing the light-emitting layer group 223. For example, the first light-emitting device 2201 and the second light-emitting device 2202 can be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED), etc. The embodiment of the present disclosure does not limit the type of light-emitting element. For example, the light-emitting layer group 223 can be a small molecule organic material or a polymer organic material.

[0076] For example, the first light-emitting device 2201 and the second light-emitting device 2202 are top-emitting structures, and the pixel electrode 221 and the common electrode 222 are reflective. For example, the pixel electrode 221 includes a first pixel electrode layer 2211, and a material with high work function and high reflectivity serves as the first pixel electrode layer 2211, such as a stacked structure of Ti / Al / Ti / Mo, wherein metallic titanium can serve as a buffer layer to improve the adhesion between the layers, Al serves as a highly reflective material, and Mo serves as a high work function material that directly contacts the organic functional layer to improve the carrier injection capability. Accordingly, the second conductive layer serves as a cathode, for example, the second conductive layer can be a transparent conductive material or a stacked structure of a transparent conductive material and a metal material. For example, the second conductive layer can be a transparent metal oxide conductive material, such as indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), etc., or can be a transparent nano-conductive material such as carbon nanotubes, graphene, and nano silver wires.

[0077] To better ensure the accuracy of sub-pixel placement, a pixel definition layer 21 is provided on the side of the pixel electrode 221 away from the base substrate 10. This pixel definition layer 21 includes a pixel opening 2101 that exposes the pixel electrode. This pixel opening 2101 defines the position and size of each sub-pixel, thereby better controlling the accuracy of each sub-pixel. The pixel definition layer 21 includes a first sub-layer 211, a second sub-layer 212, and a third sub-layer 213, arranged sequentially away from the base substrate 10. The second and third sub-layers 212 and 213 can be made of silicon oxide, while the first sub-layer 211 can be made of silicon nitride.

[0078] The driver circuit layer 100 controls the emission of light from various light-emitting devices 220, enabling the pixel layer 2 to display images. Specifically, the source electrode can be connected to the pixel electrode 221 of the light-emitting device 220, and a signal can be applied to the pixel electrode 221 to drive the light-emitting device 220 to emit light. The specific light-emitting principle will not be described in detail here. At least some of the light-emitting devices 220 can utilize any of the stacked electroluminescent devices described above. Their structures and materials have been described in detail and will not be further described.

[0079] As shown in Figure 2, the pixel definition portion is located between two adjacent pixel openings 2101. The side of the pixel definition portion facing away from the substrate forms a recessed region 2105 between two adjacent pixel electrodes 221. To prevent crosstalk between different sub-pixels caused by the common layer 2232, a partitioning groove 2102 is provided at the bottom of the recessed region 2105. Because the light-emitting layer group 223 is located on the side of the pixel definition layer 21 facing away from the substrate 10, the light-emitting layer group 223 forms a recessed portion within the partitioning groove 2102, isolating the common layer 2232 within the recessed portion. The pixel definition portion includes a first sub-portion located in the first sub-layer 211, a second sub-portion located in the second sub-layer 212, and a third sub-portion located in the third sub-layer 213.

[0080] Partitioning slot 2102 comprises a first slot section 2103 and a second slot section 2104, which extend away from drive backplate 1 in sequence. First slot section 2103 is a first through-hole extending through the first subsection, while second slot section 2104 is a second through-hole extending through the second subsection. The orthographic projection of second slot section 2104 on drive backplate 1 is located within the orthographic projection of first slot section 2103 on drive backplate 1, and the area of ​​the orthographic projection of second slot section 2104 on drive backplate 1 is smaller than the area of ​​the orthographic projection of first slot section 2103 on drive backplate 1. It is understood that the longitudinal cross-section of partitioning slot 2102 is an inverted T-shape.

[0081] To further enhance the effectiveness of preventing leakage and forming an electric field, the pixel electrode 221 can be insulated. Specifically, a first sub-portion is provided that extends to cover the side of the second pixel electrode layer 2212. As shown in FIG3 , to enhance the insulation effect on the pixel electrode 221, the pixel defining portion can further include a third sub-portion that fills the gap between two adjacent second pixel electrode layers 2212 and partially covers the two second pixel electrode layers 2212.

[0082] The common electrode 222 is disposed on a side of the light-emitting layer group 223 away from the driver backplane 1. The common electrode 222 forms a protrusion 2221 in the orthographic projection area of ​​the partition groove 2102, which approaches the base substrate 10. In Figures 2 and 3, the outline of the protrusion 2221 is composed of a broken line. The protrusion 2221 easily forms a spike, and the distance between the bottom of the protrusion 2221 and the second pixel electrode layer 2212 is small, making it easy for the common electrode 2222 to pierce the light-emitting layer group 223 and contact the pixel electrode 221.

[0083] To enhance the corrosion resistance of the pixel electrode 221, the pixel electrode 221 further includes a second pixel electrode layer 2212 made of indium tin oxide (ITO). The second pixel electrode layer 2212 is disposed on a side of the first pixel electrode layer 2211 away from the base substrate 10. The second pixel electrode layer 2212 covers a side of the first pixel electrode layer 2211 away from the driving backplane 1 and wraps around the side surfaces of the first pixel electrode layer 2211. The orthographic projection of the protrusion 2221 on the driving backplane 1 overlaps with the orthographic projection of the second pixel electrode layer 2212 of the pixel electrode 221 on the driving backplane 1, which can easily form a leakage path or electric field between the gaps between two adjacent pixel electrodes 221.

[0084] As shown in Figures 4 and 5, in order to prevent the common electrode 222 from piercing the light-emitting layer group 223, the bottom surface of the recessed area 2105 is a first smooth curved surface that bulges away from the base substrate, so that part of the light-emitting layer group 223 flows into the periphery of the recessed area 2105, and the light-emitting layer group 223 flowing into the middle of the recessed area 2105 becomes less, the outline of the protrusion 2221 becomes a curve, and the distance between the protrusion 2221 and the second pixel electrode layer 2212 is reduced, so that the probability of the protrusion 2221 puncturing and contacting the pixel electrode 221 is greatly reduced, thereby ensuring that the organic light-emitting layer is isolated while reducing the risk of cathode puncture causing a short circuit between the anode and cathode.

[0085] As shown in Figures 6 and 7, the side of the first groove section 2103 is a second smooth curved surface that is concave in the direction close to the pixel opening 2101. This can reduce the static electricity generated during the display panel manufacturing process that causes the light-emitting device to fail. The curvature of the second smooth curved surface is greater than the curvature of the first smooth curved surface. It can be understood that the curvature of the first smooth curved surface is smaller, that is, the first smooth curved surface is flatter than the second smooth curved surface. Therefore, the structure of the partition groove 2102 ensures effective isolation of the common layer while making the curve profile of the protrusion 2221 relatively flat, which can reduce the possibility of the protrusion 2221 forming a spike, thereby reducing the probability of the common electrode 222 piercing the light-emitting layer group 223 and contacting the pixel electrode 221.

[0086] The bottom surface of the first groove segment 2103 is a third smooth curved surface that is concave toward the substrate. The curvature of the first smooth curved surface is greater than that of the third smooth curved surface, which is flatter than the first smooth curved surface. This ensures that the curvature of the bottom of the curved profile of the protrusion 2221 is less than that of the side, further reducing the possibility of the protrusion 2221 forming a spike. It should be noted that the bottom surface of the first groove segment 2103 is the side of the first sub-layer 211 within the partition groove 2102 that is away from the substrate.

[0087] The bottom surface of the recessed region 2105 forms a fourth slope angle D with the first direction, and the side surface of the recessed region 2105 forms a fifth slope angle E with the first direction, where the fourth slope angle D is smaller than the fifth slope angle E. The sidewall of the pixel opening 2101 forms a sixth slope angle F with the first direction, where the sixth slope angle F is smaller than the fifth slope angle E. The first direction is perpendicular to the thickness of the display panel. It can be understood that the slope angles of the various surfaces of the pixel definition portion gradually decrease from the pixel opening 2101 to the partitioning groove 2102, thereby achieving a gradually tighter bond between the light-emitting layer assembly 223 and the pixel definition layer 21. When subjected to the tension of the partitioning groove 2102, the light-emitting layer assembly 223 is less likely to delaminate from the pixel definition layer 21, thereby further facilitating the isolation of the common layer within the partitioning groove 2102.

[0088] The second pixel electrode layer 2212 includes a first covering portion 2213, which covers a surface of the first pixel electrode layer 2211 away from the driving backplane 1 and wraps around the side surfaces of the first pixel electrode layer 2211. When providing the partition groove 2102, a certain amount of over-etching is generally caused on the driving backplane 1, resulting in the formation of an etched groove on the surface of the driving backplane 1. Therefore, the second pixel electrode layer 2212 may further include a second covering portion 2214 and a third covering portion 2215. The second covering portion 2214 is connected to the first covering portion and extends along the side of the etched groove, covering at least a portion of the side surface of the etched groove. The third covering portion 2215 is connected to the second covering portion 2214 and extends to the area between the two first pixel electrode layers 2211.

[0089] As shown in Figures 7 and 8, the angle between the portion of the first covering portion that contacts the side of the first pixel electrode layer and the first direction is a first slope angle, and the angle between the second covering portion 2214 and the first direction is a second slope angle, where the first slope angle is smaller than the second slope angle. The second covering portion 2214 can fully cover the side of the first pixel electrode layer, but the second covering portion 2214 is actually a structure that does not want to be turned on, so the second slope angle is larger, which can reduce the probability of contact with the protrusion 2221 and the risk of crosstalk between light-emitting devices. The third slope angle is greater than 0, so the third covering portion 2215 is tilted toward the side closer to the base substrate, which can further reduce the risk of crosstalk by increasing the distance between the protrusion 2221 and the second pixel electrode layer 2212.

[0090] During the formation process of the pixel electrode 221, it is usually the case that the lengths of the third covering portions 2215 of two adjacent second pixel electrode layers 2212 are different. The two adjacent pixel electrodes 221 are defined as the first pixel electrode and the second pixel electrode, respectively. The size of the third covering portion 2215 of the first pixel electrode along the first direction is D2, and the size of the third covering portion 2215 of the second pixel electrode along the first direction is D2'. The width of the portion of the recessed area 2105 and the first pixel electrode located on the same side of the partition groove 2102 is D1, and the width of the portion of the recessed area 2105 and the second pixel electrode located on the same side of the partition groove 2102 is D1', and (D2-D2')×(D1-D1')>0.

[0091] It can be understood that the third covering portion 2215 is actually a structure that is not desired to be conductive. The larger the size of the third covering portion 2215 along the first direction, the larger the width of the recessed area 2105 and the portion of the third covering portion 2215 located on the same side of the partition groove 2102, thereby reducing the probability of forming a leakage path or electric field between the edge of the third covering portion 2215 and the protruding portion 2221 of the common electrode 222, reducing crosstalk between different light-emitting devices, and thereby reducing the generation of stray light on the display panel.

[0092] The size of the first groove section 2103 along the second direction is larger than the size of the second covering portion 2214 along the second direction. It can be understood that when the size of the first groove section 2103 is larger, more light-emitting layer groups 223 can enter the partition groove 2102, and greater tension can be applied to the common layer, so that the partition groove 2102 has a better partition effect. The second direction is the thickness direction of the display panel.

[0093] As shown in FIG9 , the orthographic projection of the protrusion 2221 on the driver backplane 1 does not overlap with the orthographic projection of the second pixel electrode layer 2212 of the pixel electrode 221 on the driver backplane 1 , thereby preventing the protrusion 2221 from forming a leakage path or electric field within the partitioning groove 2102 between adjacent pixel openings 2101 . The orthographic projection of the protrusion 2221 on the base substrate 10 is typically located within the orthographic projection of the second groove segment 2104 on the base substrate 10 . Therefore, the third covering portion 2215 can be positioned closer to the edge of the pixel opening 2101 relative to the second groove segment 2104 . Specifically, the orthographic projection of the edge of the third covering portion 2215 on the base substrate 10 is located between the orthographic projections of the first groove segment 2103 and the second groove segment 2104 on the base substrate 10 . This prevents the protrusion 2221 from forming a leakage path or electric field within the partitioning groove 2102 between adjacent pixel openings 2101 .

[0094] To improve the effectiveness of preventing leakage and forming an electric field, the third covering portion 2215 can be positioned closer to the edge of the pixel opening 2101 relative to the first groove segment 2103 in the first direction. That is, the orthographic projection of the third covering portion 2215 and the edge of the partition groove 2102 on the base substrate 10 is located between the orthographic projection of the edge of the pixel opening 2101 on the base substrate 10 and the orthographic projection of the first groove segment 2103 on the base substrate 10. This can better prevent the protrusion 2221 from forming a leakage path or an electric field within the partition groove 2102 between adjacent pixel openings 2101. It should be noted that the first direction is perpendicular to the thickness direction of the display panel.

[0095] As shown in Figures 9 and 10, the distance in the first direction between the end of the third covering portion 2215 away from the first covering portion 2213 and the first groove segment 2103 is d1, and 0.05 μm ≤ d1 ≤ 0.2 μm, so as to better control the safety distance between the edge of the second pixel electrode layer 2212 and the edge of the first groove segment 2103. In one feasible embodiment, 0.05 μm ≤ d1 ≤ 0.07 μm can be set.

[0096] The distance d5 between the end of the side of the first covering portion 2213 closest to the driver backplane 1 and the side of the pixel defining portion is greater than or equal to 1 and less than or equal to 8, that is, 0.05 μm ≤ d5 ≤ 1.6 μm. This provides a greater coverage of the edge of the second pixel electrode layer 2212, which helps prevent leakage at the edge of the pixel electrode 221 while also taking into account the size of the pixel opening 2101 to ensure a reasonable pixel aperture ratio. In one feasible embodiment, 0.2 μm ≤ d5 ≤ 0.4 μm can be set.

[0097] The maximum width of the second trench segment 2104 is d4, and the ratio of d4 to d1 is greater than or equal to 2 and less than or equal to 9, that is, 0.1 μm ≤ d5 ≤ 1.8 μm. While ensuring the isolation effect of the common layer 2232, minimizing the width of the second trench segment 2104 can narrow the protrusion 2221 formed on the common electrode 222 and reduce the amount of the light-emitting layer group 223 that enters the second trench segment 2104. This reduces the depth of the recess formed on the side of the light-emitting layer group 223 away from the substrate 10, thereby reducing the height of the protrusion 2221 and increasing the distance between the protrusion 2221 and the second pixel electrode layer 2212. This reduces the possibility of an electric field and leakage between the common electrode 222 and the second pixel electrode layer 2212 within the isolation trench 2102. In one practicable embodiment, 0.4 μm ≤ d4 ≤ 0.45 μm.

[0098] The distance between the third covering portions 2215 of two adjacent second pixel electrode layers 2212 is d3. The ratio of d3 to d1 is greater than or equal to 3.5 and less than or equal to 20, that is, 0.175 μm ≤ d3 ≤ 4 μm. This ensures that the orthographic projection of the protrusion 2221 on the driving backplane 1 does not overlap with the orthographic projection of the pixel electrode 221 on the driving backplane 1. In one achievable embodiment, d3 - 2d1 - d4 > 0.1 μm.

[0099] The ratio of the width D2 of the third covering portion 2215 to the width d1 is greater than or equal to 1 and less than or equal to 4, that is, 0.05 μm ≤ D2 ≤ 0.8 μm. The second pixel electrode layer 2212 can completely cover the first pixel electrode layer 2211, preventing corrosion of the first pixel electrode layer 2211. In a feasible embodiment, 0.07 μm ≤ D2 ≤ 0.12 μm can be set.

[0100] The distance between the edge of the second groove segment 2104 and the edge of the first groove segment 2103 is d6, and the ratio of d6 to d1 is greater than or equal to 0.5 and less than or equal to 2.5, that is, 0.025 μm ≤ d6 ≤ 0.5 μm, to ensure effective isolation of the common layer 2232. In one feasible embodiment, d6 can be set to ≥ 0.05 μm.

[0101] The distance between the protrusion 2221 and two adjacent pixel electrodes 221 in the second direction is d2. The ratio of d2 to d1 is greater than or equal to 5 and less than or equal to 70, that is, 0.25 μm ≤ d2 ≤ 14 μm. The second direction is the thickness direction of the display panel. In one feasible embodiment, 1.0 μm ≤ d2 ≤ 3.5 μm can be set.

[0102] As shown in FIG11 , the width of the first groove section 2103 can also be set to gradually increase in the direction away from the driving backplane 1. Without affecting the isolation effect of the partition groove 2102, the amount of the light-emitting layer group 223 entering the partition groove 2102 can be further reduced, so that the recessed portion formed on the side of the light-emitting layer group 223 away from the base substrate 10 becomes shallower, thereby further reducing the height of the protrusion 2221 formed by the common electrode 222, and increasing the distance between the protrusion 2221 and the second pixel electrode layer 2212, thereby reducing the possibility of forming an electric field between the common electrode 222 and the second pixel electrode layer 2212 in the partition groove 2102 and generating leakage.

[0103] As shown in Figure 12, based on Figure 11, the width of the second groove section 2104 can be set to gradually decrease in the direction away from the base substrate 10, so that the second groove section 2104 itself can form a partition structure to isolate the common layer 2232. In addition, the thickness of the third sub-section is usually less than the thickness of the second sub-section. Therefore, the partition groove 2102 of this structure can improve the partition effect while also reducing the amount of the light-emitting layer group 223 entering the partition groove 2102.

[0104] It should be noted that the first direction is the x direction in the figure, and the second direction is the y direction in the figure.

[0105] As shown in Figure 13, based on Figure 12, the side wall of the partition groove 2102 can be set to an arc shape, the width increase amplitude of the first groove section 2103 gradually increases in the direction away from the base substrate 10, and the width decrease amplitude of the second groove section 2104 gradually decreases in the direction away from the base substrate 10, which can further enhance the partition effect of the partition groove 2102.

[0106] As shown in FIG14 , the width of the first slot segment 2103 and the width of the second slot segment 2104 can also be configured to gradually decrease in a direction away from the driver backplane 1. In this way, the first slot segment 2103 and the second slot segment 2104 can each form a partition structure. In this way, the partition slot 2102 in FIG10 can form two partition structures, which can enhance the partitioning effect of the partition slot 2102.

[0107] As shown in FIG15 , in other embodiments, the width of the first groove section 2103 on the side away from the base substrate 10 can be set to be equal to the width of the second groove section 2104 on the side close to the base substrate 10, that is, the width of the partition groove 2102 gradually decreases in the direction away from the driver backplane 1. The partition groove 2102 can be formed through a single etching process, saving process costs.

[0108] As shown in FIG16 , the orthographic projection of the second groove segment 2104 on the driver backplate 1 can also be arranged to overlap with the orthographic projection of the first groove segment 2103 on the driver backplate 1 , that is, the width of the first groove segment 2103 can be reduced so that the width of the first groove segment 2103 is equal to the width of the second groove segment 2104 , that is, d6 is reduced to 0. This can also isolate the common layer 2232 and reduce the amount of the light-emitting layer group 223 entering the isolation groove 2102, making the recessed portion formed on the side of the light-emitting layer group 223 away from the base substrate 10 shallower, thereby further reducing the height of the protrusion 2221 formed by the common electrode 222.

[0109] As shown in Figure 1 , an encapsulation layer assembly 4 is provided on the side of the pixel layer 2 facing away from the base substrate 10, thereby encapsulating the pixel layer 2 and preventing corrosion by water and oxygen. Encapsulation layer assembly 4 can be a single-layer or multi-layer structure, and the material of encapsulation layer assembly 4 can include organic or inorganic materials, without particular limitation.

[0110] In this embodiment, the encapsulation layer group 4 may include a first inorganic encapsulation layer 41, an organic encapsulation layer 42 and a second inorganic encapsulation layer 43. The first inorganic encapsulation layer 41 is arranged on the side of the pixel layer 2 away from the base substrate 10, the organic encapsulation layer 42 is arranged on the side of the first inorganic encapsulation layer 41 away from the base substrate 10, and the second inorganic encapsulation layer 43 is arranged on the side of the organic encapsulation layer 42 away from the base substrate 10.

[0111] A color filter layer 3 can be set on the side of the packaging layer group 4 away from the driving backplane 1. The color filter layer 3 includes a packaging substrate 33. A black matrix 31 is provided on one side of the packaging substrate 33. An opening area array is defined on the black matrix 31. The opening area array includes multiple opening area rows arranged along the row direction. Each opening area row includes multiple opening areas. A sub-filter unit is provided in each opening area. The colors of two adjacent sub-filter units in the opening area row are different. Multiple sub-filter units located in the same opening area row constitute multiple filter units 32. Usually, one filter unit 32 can include a red sub-filter unit 321, a green sub-filter unit 322 and a blue sub-filter unit 323.

[0112] A third planarization layer may be provided between the layer where the multiple filter units are located and the second inorganic encapsulation layer 43 , so that the color filter layer 3 on the third planarization layer is relatively flat, ensuring the location of each sub-filter unit and further ensuring the pixel accuracy of the display panel.

[0113] Figure 17 shows another display panel, which uses an active matrix organic light-emitting diode (AMOLED). The driving circuit layer 100 of the display panel is arranged on the base substrate 10, and the pixel layer 2 is arranged on the side of the driving circuit layer 100 away from the base substrate 10. The driving circuit layer 100 includes thin film transistors, and a buffer layer 18 can also be provided between the driving circuit layer 100 and the base substrate 10.

[0114] When the transistor 11 is a thin film transistor, the substrate 10 may be made of an inorganic material or an organic material. For example, in one embodiment of the present disclosure, the substrate 10 may be made of a glass material such as soda-lime glass, quartz glass, or sapphire glass, or may be made of a metal material such as stainless steel, aluminum, or nickel.

[0115] In another embodiment of the present disclosure, the material of the base substrate 10 can be polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or a combination thereof.

[0116] In another embodiment of the present disclosure, the base substrate 10 may also be a flexible base substrate. For example, the base substrate 10 may be made of polyimide (PI). The base substrate 10 may also be a composite of multiple layers. For example, in one embodiment of the present disclosure, the base substrate 10 may include a bottom film layer, a pressure-sensitive adhesive layer, a first polyimide layer, and a second polyimide layer stacked in sequence.

[0117] The thin film transistor can be selected from a top-gate thin film transistor, a bottom-gate thin film transistor or a dual-gate thin film transistor, and the top-gate thin film transistor is taken as an example for description.

[0118] The thin film transistor may include an active layer 112, a gate insulating layer 115, a gate 111, a source electrode, and a drain electrode, wherein:

[0119] The active layer 112 is provided on one side of the substrate 10. The active layer 112 may be made of polycrystalline silicon, amorphous silicon, or the like. The active layer 112 may include a channel region and two source and drain regions of different doping types located on either side of the channel region. The channel region may retain semiconductor properties, while the semiconductor material of the source and drain regions may be partially or fully conductive.

[0120] The gate insulating layer 115 may cover the active layer 112 and the base substrate 10, and the material of the gate insulating layer 115 is an insulating material such as silicon oxide. The gate 111 is disposed on the side of the gate insulating layer 115 away from the base substrate 10 and directly opposite the active layer 112. That is, the projection of the gate 111 on the base substrate 10 is located within the projection of the active layer 112 on the base substrate 10. For example, the projection of the gate 111 on the base substrate 10 coincides with the projection of the channel region of the active layer 112 on the base substrate 10.

[0121] When transistor 11 is a thin film transistor, insulating layer 15 includes an interlayer dielectric layer 151. Interlayer dielectric layer 151 is disposed on a side of gate 111 away from substrate 10. Interlayer dielectric layer 151 covers gate 111 and gate insulating layer 115 and is made of an insulating material. A source electrode and a drain electrode are disposed on a surface of interlayer dielectric layer 151 away from substrate 10. The source electrode and the drain electrode are connected to active layer 112. For example, the source electrode and the drain electrode are connected to the corresponding source region and drain region of active layer 112 through vias, respectively.

[0122] The insulating layer 15 further includes a protective layer 152, which is disposed on the side of the source and drain electrodes away from the base substrate 10. The protective layer 152 covers the source and drain electrodes. The insulating layer 15 further includes a planarization layer 153, which is disposed on the side of the source and drain electrodes away from the base substrate 10. The planarization layer 153 is disposed on the side of the protective layer 152 away from the base substrate 10. The planarization layer 153 covers the protective layer 152, and the surface of the planarization layer 153 away from the base substrate 10 is flat.

[0123] A pixel layer 2 is provided on the side of the insulating layer 15 facing away from the base substrate. An encapsulation layer group 4 is provided on the side of the pixel layer 2 facing away from the base substrate 10, thereby encapsulating the pixel layer 2 and preventing corrosion from water and oxygen. A color filter layer 3 is provided on the side of the encapsulation layer group 4 facing away from the base substrate 10. The detailed structures of the encapsulation layer and color filter layer 3 can be found in the silicon-based display panel shown in FIG1 and will not be further described here.

[0124] The present disclosure also provides a display device, which may include any one of the display panels of the present disclosure. The specific structure and beneficial effects of the display panel have been described in detail above, so they will not be repeated here.

[0125] It should be noted that, in addition to the display panel, the display device also includes other necessary components and components, such as a housing, a circuit board, a power cord, etc. Those skilled in the art can make corresponding supplements based on the specific usage requirements of the display device, which will not be repeated here.

[0126] When the display panel has the structure shown in Figures 1 to 16 , the display device can also be an emerging wearable device, such as a virtual reality device or an augmented reality device. When the display panel has the structure shown in Figure 17 , the display device can be a traditional electronic device, such as a mobile phone, a computer, a television, and a camcorder. These are not listed here one by one.

[0127] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A display panel, wherein: include: Driver backplane; A plurality of pixel electrodes are arranged at intervals on one side of the driving backplane; A pixel definition layer is provided on a side of the plurality of pixel electrodes away from the driving backplane, the pixel definition layer is provided with a pixel opening exposing the pixel electrode, a pixel definition portion is provided between two adjacent pixel openings, a side of the pixel definition portion away from the driving backplane forms a recessed area between two adjacent pixel electrodes, a bottom surface of the recessed area comprises a first smooth curved surface convex in a direction away from the driving backplane, and a partition groove is provided on the bottom surface of the recessed area; A light-emitting layer group is provided on a side of the pixel definition layer away from the driving backplane, and the light-emitting layer group is disconnected in the partition groove; The common electrode is arranged on a side of the light emitting layer group away from the driving back plate. The common electrode forms a protrusion close to the driving back plate in the positive projection area of ​​the partition groove, and the contour of the protrusion is a curve.

2. The display panel according to claim 1, wherein: The partition groove includes a first groove section and a second groove section which are successively away from the driving back plate, the orthographic projection of the second groove section on the driving back plate is located within the orthographic projection of the first groove section on the driving back plate, and the area of ​​the orthographic projection of the second groove section on the driving back plate is smaller than the area of ​​the orthographic projection of the first groove section on the driving back plate.

3. The display panel according to claim 2, wherein: The side surface of the first groove segment includes a second smooth curved surface that is concave toward the direction close to the pixel opening.

4. The display panel according to claim 3, wherein: The curvature of the second smooth curved surface is greater than the curvature of the first smooth curved surface.

5. The display panel according to claim 2, wherein: The bottom surface of the first groove segment includes a third smooth curved surface that is concave toward the direction approaching the driving back plate.

6. The display panel according to claim 5, wherein: The curvature of the first smooth curved surface is greater than the curvature of the third smooth curved surface.

7. The display panel according to claim 1, wherein: The angle between the bottom surface of the recessed area and the first direction is smaller than the angle between the side surface of the recessed area and the first direction, the angle between the side surface of the recessed area and the first direction is smaller than the angle between the side wall of the pixel opening and the first direction, and the first direction is perpendicular to the thickness direction of the display panel.

8. The display panel according to claim 2, wherein: The pixel electrode includes a first pixel electrode layer and a second pixel electrode layer, the first pixel electrode layer is arranged on one side of the driving backplane, the second pixel electrode layer includes a first covering portion, the first covering portion covers a side of the first pixel electrode layer away from the driving backplane and wraps the side surface of the first pixel electrode layer, and the material of the second pixel electrode layer is indium tin oxide.

9. The display panel according to claim 8, wherein: The second pixel electrode layer also includes a second covering portion and a third covering portion, the second covering portion is connected to the first covering portion and extends toward the driving backplane, the third covering portion is connected to the second covering portion, and the third covering portion is located between the two adjacent first pixel electrode layers.

10. The display panel according to claim 9, wherein: An angle between a portion of the first covering portion contacting the side surface of the first pixel electrode layer and the first direction is smaller than an angle between the second covering portion and the first direction.

11. The display panel according to claim 9, wherein: The two adjacent pixel electrodes are defined as a first pixel electrode and a second pixel electrode, a size of the third covering portion of the first pixel electrode along the first direction is D2, a size of the third covering portion of the second pixel electrode along the first direction is D2', a width of a portion of the recessed area and the first pixel electrode located on the same side of the partition groove is D1, a width of a portion of the recessed area and the second pixel electrode located on the same side of the partition groove is D1', and (D2-D2')×(D1-D1')>0.

12. The display panel according to claim 9, wherein: A size of the first groove segment along a second direction is greater than a size of the second covering portion along the second direction, and the second direction is a thickness direction of the display panel.

13. The display panel according to claim 9, wherein: An orthographic projection of the protrusion on the driving backplane does not overlap with an orthographic projection of the pixel electrode on the driving backplane.

14. The display panel according to claim 13, wherein: An edge of the third covering portion is closer to an edge of the pixel opening than an edge of the first groove segment in a first direction, and the first direction is perpendicular to a thickness direction of the display panel.

15. The display panel according to claim 2, wherein: A pixel definition portion is located between two adjacent pixel openings, and the pixel definition portion includes a first sub-portion and a second sub-portion arranged in sequence along a direction away from the driving backplane, the first groove section is a first through hole passing through the first sub-portion, and the second groove section is a second through hole passing through the second sub-portion.

16. The display panel according to claim 3, wherein: The pixel definition portion further includes a third sub-portion, which fills a gap between two adjacent pixel electrodes and partially covers the two pixel electrodes.

17. The display panel according to claim 2, wherein: The width of the first slot section gradually increases in a direction away from the driving back plate.

18. The display panel according to claim 2, characterized in that: The width of the second slot section gradually decreases in a direction away from the driving back plate.

19. The display panel according to claim 18, characterized in that: The width of the first slot section increases gradually in a direction away from the driving back plate, and the width of the second slot section decreases gradually in a direction away from the driving back plate.

20. The display panel according to claim 2, wherein: The orthographic projection of the second slot segment on the driving backplane overlaps with the orthographic projection of the first slot segment on the driving backplane.

21. The display panel according to claim 2, wherein: The width of the partition groove gradually decreases in a direction away from the driving back plate.

22. The display panel according to claim 1, wherein: The light-emitting layer group includes a sub-light-emitting layer group. A common layer is provided between the sub-light-emitting layer group and the pixel electrode. The common layer is disconnected between two adjacent partition grooves. The sub-light-emitting layer group covers the common layer and its interruption.

23. The display panel according to claim 1, wherein: The driving backplane includes a plurality of thin film transistors, and the thin film transistors are silicon-based thin film transistors.

24. A display device, wherein: A display panel comprising any one of claims 1 to 23.

Images