Semiconductor structure and method for forming same

Abstract

Embodiments of the present disclosure disclose a semiconductor structure and a method for forming same. The semiconductor structure comprises: a substrate, and a number m of word lines. The substrate comprises multiple discrete active region columns, the multiple active region columns being located on a front surface of the substrate and all extending along a vertical direction. The multiple active region columns are arranged along a first direction and a second direction to form an array of m rows and n columns. The m word lines extend along the first direction and are arranged along the second direction, a (2i-1)th word line and a (2i)th word line being located between a (2i-1)th row and a (2i)th row of active region columns, and each covering side walls of the corresponding active region columns; an air gap is formed between the (2i-1)th word line and the (2i)th word line.

Description

A semiconductor structure and a method for forming the same

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure is based on the Chinese patent application with application number 202311272632.9, application date September 27, 2023, and invention name “A semiconductor structure and its formation method”, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into the present disclosure as a reference. Technical Field

[0003] The present disclosure relates to, but is not limited to, a semiconductor structure and a method for forming the same. Background Art

[0004] 3D stacking technology utilizes stacking techniques or interconnection and other microfabrication techniques to achieve three-dimensional integration in the vertical direction. 3D stacking can encapsulate two or more chips with different functions within a single package, thereby achieving functional diversification. In related technologies, the structure of the chips used for stacking still has room for further optimization.

[0005] Summary of the Invention

[0006] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, which can improve integration and electrical performance.

[0007] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0008] An embodiment of the present disclosure provides a semiconductor structure, which includes: a substrate, including a plurality of discrete active area pillars; the plurality of active area pillars are located on the front side of the substrate and all extend in a vertical direction; the plurality of active area pillars are arranged along a first direction and a second direction to form an array of m rows and n columns; wherein m and n are both greater than 1, and the first direction and the second direction intersect and are respectively perpendicular to the vertical direction; m word lines extend along the first direction and are arranged along the second direction; wherein the 2i-1th and 2ith word lines are located in the first trench between the 2i-1th and 2ith row active area pillars, and respectively cover the side walls of the corresponding active area pillars; there is an air gap between the 2i-1th and 2ith word lines; wherein i is greater than or equal to 1 and less than m / 2.

[0009] In the above scheme, the semiconductor structure also includes: multiple isolation structures, extending along the first direction and arranged in sequence along the second direction; multiple isolation structures are located in the second trench between the active area pillars in the 2i-th row and the 2i+1-th row; the depth of the second trench is greater than the depth of the first trench.

[0010] In the above solution, the semiconductor structure further includes: a gate oxide layer formed between each of the word lines and the sidewall of the corresponding active region pillar.

[0011] In the above scheme, the semiconductor structure also includes: multiple node contact structures, each of which is located at the top of a corresponding active area column; multiple bit line contact structures, the bottom ends of every two active area columns are connected to a corresponding bit line contact structure.

[0012] In the above solution, the semiconductor structure further includes: n bit lines extending along the second direction and located on the back side of the substrate; each of the bit lines is electrically connected to the bottom end of a corresponding column of the active region pillars through the bit line contact structure.

[0013] In the above solution, the semiconductor structure further includes: a plurality of capacitors; each of the capacitors is electrically connected to the top of a corresponding active region column through one of the node contact structures.

[0014] In the above solution, the angle between the first direction and the second direction is 60°; the plurality of capacitors are arranged in a honeycomb shape.

[0015] In the above solution, the semiconductor structure further includes: a dielectric layer covering the top ends of the plurality of active region pillars and surrounding the side walls of the plurality of node contact structures.

[0016] In the above solution, the semiconductor structure further includes: a pad structure, located on the back side of the substrate and electrically connected to the corresponding bit line.

[0017] The present disclosure also provides a method for forming a semiconductor structure, the method comprising: providing a substrate; forming a plurality of initial active region pillars extending in a vertical direction on the front side of the substrate; forming an array of m / 2 rows and n columns along a first direction and a second direction; forming a shallow trench isolation structure between adjacent initial active region pillars; wherein m and n are both greater than 1, and the first direction and the second direction are respectively perpendicular to the vertical direction; etching the shallow trench isolation structure to form a first trench extending along the first direction between two adjacent rows of the initial active region pillars; wherein the remaining A shallow trench isolation structure covers the sidewalls of the initial active area pillars to form a gate oxide layer; m word lines extending along the first direction are formed; wherein the 2i-1th and 2ith word lines are formed in a corresponding first trench and respectively cover the sidewalls of the corresponding initial active area pillars; wherein i is greater than or equal to 1 and less than m / 2; in the middle of each row of the initial active area pillars, a second trench extending along the first direction is etched to divide each row of the initial active area pillars into two rows of active area pillars; a dielectric layer is deposited to cover the top of the active area pillars and an air gap is formed between the 2i-1th and 2ith word lines.

[0018] In the above scheme, after depositing the dielectric layer to cover the top of the active area column, the method also includes: forming a patterned mask on the dielectric layer; etching the dielectric layer according to the mask to form a plurality of through holes in the dielectric layer; each of the through holes exposes the top of a corresponding active area column; depositing a plurality of node contact structures in the plurality of through holes; each of the node contact structures is connected to the top of a corresponding active area column; forming a plurality of capacitors; each of the capacitors is electrically connected to the top of a corresponding active area column through a node contact structure.

[0019] In the above scheme, after forming multiple capacitors, the method also includes: thinning the back side of the substrate; forming multiple bit line contact structures at the bottom ends of multiple active area pillars; connecting the bottom ends of every two active area pillars to a corresponding one of the bit line contact structures; filling metal material into the substrate from the back side of the substrate to form n bit lines; each of the bit lines is electrically connected to the bottom end of a corresponding column of the active area pillars through the bit line contact structure.

[0020] In the above solution, after forming n bit lines and a plurality of bit line contact structures, the method further comprises: forming a pad structure on the back surface of the substrate; the pad structure is electrically connected to the corresponding bit lines.

[0021] In the above scheme, forming m word lines extending along the first direction includes: filling the first trench with word line conductive material; etching the word line conductive material in each first trench to cut the word line conductive material into two parts to form two word lines.

[0022] In the above solution, after etching to form the second trench, the method further includes: depositing a dielectric material in the second trench to form an isolation structure extending along the first direction.

[0023] It can be seen that the embodiment of the present disclosure provides a semiconductor structure and a method for forming the same. The semiconductor structure includes: a substrate and m word lines. The substrate includes a plurality of discrete active region columns; the plurality of active region columns are located on the front side of the substrate and extend in a vertical direction; the plurality of active region columns are arranged along a first direction and a second direction to form an array of m rows and n columns; wherein m and n are both greater than 1, and the first direction and the second direction intersect and are respectively perpendicular to the vertical direction. The m word lines extend in the first direction and are arranged in the second direction; wherein the 2i-1th and 2ith word lines are located in the first groove between the 2i-1th and 2ith row active region columns and cover the side walls of the corresponding active region columns respectively; there is an air gap between the 2i-1th and 2ith word lines; wherein i is greater than or equal to 1 and less than m / 2. It is understood that the embodiment of the present disclosure sets an array of active area pillars, and further sets the 2i-1th and 2ith word lines in the first trench between the 2i-1th and 2ith rows of active area pillars, and sets an air gap between the 2i-1th and 2ith word lines 20. In this way, the air gap with better insulation and lower dielectric constant is used to electrically isolate the 2i-1th and 2ith word lines with a smaller spacing. At the same time, the spacing between the 2ith and 2i+1th word lines is increased, so that the parasitic capacitance C between each two adjacent word lines is reduced. wl That is, the embodiment of the present disclosure does not need to increase the spacing between adjacent active region pillars, so that the overall area occupied by the semiconductor structure is small, and at the same time, the parasitic capacitance C between adjacent word lines is guaranteed. wl That is, the embodiment of the present disclosure provides a semiconductor structure with high integration and good electrical performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] FIG1 is a structural schematic diagram 1 of a semiconductor structure provided by an embodiment of the present disclosure;

[0025] FIG2 is a second structural diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0026] FIG3 is a third structural diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0027] FIG4 is a fourth structural diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0028] FIG5 is a fifth structural diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0029] FIG6 is a sixth structural diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0030] FIG7 is a first flow chart of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0031] FIG8 is a second flow chart of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0032] FIG9 is a third flow chart of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0033] FIG10A is a structural schematic diagram 1 of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0034] FIG10B is a second structural diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0035] FIG11A is a third structural diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0036] FIG11B is a fourth structural diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0037] FIG12A is a fifth structural diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0038] FIG12B is a sixth structural diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0039] FIG13A is a seventh structural diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0040] FIG13B is a structural schematic diagram 8 of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0041] FIG14A is a ninth structural diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0042] FIG14B is a structural schematic diagram 10 of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0043] FIG15 is a structural schematic diagram eleven of the method for forming a semiconductor structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0045] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0046] If similar descriptions of "first / second" appear in the application documents, the following explanation is added. In the following description, the terms "first / second / third" are merely used to distinguish similar objects and do not represent a specific order for the objects. It is understandable that "first / second / third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0047] Herein, when a layer / element is referred to as being "on" another layer / element, it can be directly on the other layer / element or intervening layers / element may be present therebetween. Also, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0049] 1 and 2 are optional schematic structural diagrams of a semiconductor structure provided by an embodiment of the present disclosure, wherein FIG1 is a top view and FIG2 is a cross-sectional view along the cross-sectional line A-A1 in FIG1 .

[0050] As shown in Figures 1 and 2, the semiconductor structure includes a substrate 00 and m word lines 20. The substrate 00 includes a plurality of discrete active region pillars 10. The plurality of active region pillars 10 are located on the front surface of the substrate 00 and extend along a vertical direction Z. The plurality of active region pillars 10 are arranged along a first direction X and a second direction Y to form an array of m rows and n columns. Here, m and n are both greater than 1, and the first direction X and the second direction Y intersect and are perpendicular to the vertical direction Z.

[0051] m word lines 20 extend along a first direction X and are arranged along a second direction Y. The 2i-1th and 2ith word lines 20 are located in the first trench between the 2i-1th and 2ith rows of active area pillars 10, respectively covering the sidewalls of the corresponding active area pillars 10. An air gap 30 is defined between the 2i-1th and 2ith word lines 20. Here, i is greater than or equal to 1 and less than m / 2.

[0052] In the disclosed embodiment, referring to Figures 1 and 2 , a substrate 00 is made of a semiconductor material, such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. The substrate 00 includes a plurality of discrete active region pillars 10 , each of which can form a corresponding transistor; thus, the plurality of active region pillars 10 arranged in an array can form a transistor array.

[0053] In the embodiment of the present disclosure, with continued reference to Figures 1 and 2, the 2i-1th and 2ith word lines 20 are located in the first trench between the 2i-1th and 2ith rows of active area pillars 10, and respectively cover the sidewalls of the corresponding active area pillars 10. In other words, every two word lines 20 are located in the first trench between the two corresponding rows of active area pillars 10; here, each row of active area pillars 10 is arranged along the first direction X. At the same time, each word line 20 covers the sidewalls of the corresponding row of active area pillars 10; in this way, the portion of the active area pillars 10 covered by the word line 20 can form a channel of a transistor, and the voltage on the word line 20 can control whether the channel is turned on or off.

[0054] Further, referring to FIG. 1 and FIG. 2 , m word lines 20 are arranged along the second direction Y, and the spacing between two adjacent word lines 20 is different. On the one hand, the spacing between the 2i-th word line 20 and the 2i+1-th word line 20 (i.e., the two adjacent word lines 20 located in different first trenches) is larger, so the parasitic capacitance C between the 2i-th word line 20 and the 2i+1-th word line 20 is larger. wl On the other hand, the distance between the 2i-1st and 2i-th word lines 20 (i.e., the two adjacent word lines 20 located in the same first trench) is small, so an air gap 30 is provided between the 2i-1st and 2i-th word lines 20. Compared with general dielectrics, the air gap 30 has better insulation and lower dielectric constant, so that the parasitic capacitance C between the 2i-1st and 2i-th word lines 20 can be reduced. wl Also keep it small.

[0055] It can be understood that the embodiment of the present disclosure provides a novel semiconductor structure, in which an array of active region pillars 10 is provided. Furthermore, the 2i-1th and 2ith word lines 20 are provided in the first trench between the 2i-1th and 2ith rows of active region pillars 10, and an air gap 30 is provided between the 2i-1th and 2ith word lines 20. In this way, the air gap 30 with better insulation and lower dielectric constant is used to electrically isolate the 2i-1th and 2ith word lines 20 with a smaller spacing. At the same time, the spacing between the 2ith and 2i+1th word lines 20 is increased, thereby making the parasitic capacitance C between each two adjacent word lines smaller. wl All are kept in a small range.

[0056] That is, the embodiment of the present disclosure does not need to increase the spacing between adjacent active region pillars 10, so that the area occupied by the entire semiconductor structure is small, and at the same time, the parasitic capacitance C between adjacent word lines is guaranteed. wl That is, the embodiment of the present disclosure provides a semiconductor structure with high integration and good electrical performance.

[0057] In some embodiments of the present disclosure, referring to FIG1 and FIG2 , the semiconductor structure further includes: a plurality of isolation structures 40. The plurality of isolation structures 40 extend along a first direction X and are sequentially arranged along a second direction Y. The plurality of isolation structures 40 are located in the second trench between the 2i-th row and the 2i+1-th row of active region pillars 10. The depth of the second trench is greater than the depth of the first trench.

[0058] In the embodiment of the present disclosure, referring to Figures 1 and 2 , the air gap 30 is located in the first trench between the 2i-1th row and the 2ith row active area pillars 10, that is, the air gap 30 is located between the 2i-1th and 2ith word lines 20; and the isolation structure 40 is located in the second trench between the 2ith row and the 2i+1th row active area pillars 10, that is, the isolation structure 40 is located between the 2ith and 2i+1th word lines 20.

[0059] It can be understood that the air gaps 30 and the isolation structures 40 are arranged at intervals in the second direction Y. Among them, between the word lines 20 with smaller spacing (i.e., between the 2i-1 and 2i word lines 20), the air gaps 30 with better insulation and lower dielectric constant are used; and between the word lines 20 with larger spacing (i.e., between the 2i and 2i+1 word lines 20), the isolation structures 40 are used. Thus, the parasitic capacitance C between the word lines 20 is guaranteed to be wl Keep it small.

[0060] At the same time, compared with the air gap 30, the isolation structure 40 has stronger stability and can provide good support for the entire semiconductor structure; thus, the spaced air gap 30 and the isolation structure 40 can also take into account the stability of the entire semiconductor structure and avoid collapse or structural damage.

[0061] 1 and 2 , the depth of the second trench where the isolation structure 40 is located is greater than the depth of the first trench where the air gap 30 is located. Thus, the isolation structure 40 can better isolate active area pillars 10 in different rows, preventing short circuits and crosstalk.

[0062] In some embodiments of the present disclosure, referring to FIG. 2 , the semiconductor structure further includes a gate oxide layer 11. Gate oxide layer 11 is formed between each word line 20 and the sidewall of the corresponding active region pillar 10. Thus, the voltage on word line 20 can serve as the gate voltage of the transistor, controlling whether the channel in active region pillar 10 is turned on or off.

[0063] It can be understood that the word line 20 covers the sidewall of the active region pillar 10 to control the opening or closing of the channel; in this way, the contact area between the word line 20 and the channel is larger, thereby increasing the control force on the channel, making the opening or closing of the channel more thorough; furthermore, the on-state current I of the transistor can be increased. on , and reduce the transistor's off current I off , thereby reducing power consumption.

[0064] FIG3 is a schematic diagram of an optional structure of a semiconductor structure provided by an embodiment of the present disclosure, and FIG3 is a cross-sectional view.

[0065] In some embodiments of the present disclosure, referring to FIG3 , the semiconductor structure further includes: a plurality of node contact structures (NC) 12 and a plurality of bit line contact structures (BLC) 13. Each node contact structure 12 is located at the top of a corresponding active region pillar 10; and the bottom ends of every two active region pillars 10 are connected to a corresponding bit line contact structure 13.

[0066] It is understood that, on the one hand, multiple node contact structures 12 and multiple bit line contact structures 13 are respectively arranged at the top and bottom ends of the active region pillar 10 (i.e., the front and back ends of the substrate). In this way, there is sufficient space to arrange the node contact structures 12 and the bit line contact structures 13, and the node contact structures 12 and the bit line contact structures 13 can be designed to be larger in size, thereby reducing the resistance of the node contact structures 12 and the bit line contact structures 13, and further reducing the power consumption of the entire semiconductor structure. On the other hand, because the node contact structures 12 and the bit line contact structures 13 are respectively arranged at the two ends of the active region pillar 10, during the manufacturing process, the node contact structures 12 and the bit line contact structures 13 can be processed separately from the two ends without interfering with each other, thereby simplifying the manufacturing process.

[0067] In the disclosed embodiment, referring again to FIG3 , the bottom ends of every two active area pillars 10 are connected to a corresponding bit line contact structure 13. Compared to a case where each active area pillar corresponds to a corresponding bit line contact structure, the disclosed embodiment can make each bit line contact structure 13 larger. This, on the one hand, reduces the resistance of the bit line contact structure 13 itself, and on the other hand, increases the contact surface between the bit line contact structure 13 and the bit line, thereby reducing the power consumption of the entire semiconductor structure.

[0068] Figures 4 and 5 are schematic diagrams of alternative structures of a semiconductor structure provided by an embodiment of the present disclosure, wherein Figure 4 is a top view and Figure 5 is a cross-sectional view along line A-A1 in Figure 4. It should be noted that in Figure 4, due to shielding, the middle portion of each bit line 50 is shielded and not shown.

[0069] In some embodiments of the present disclosure, referring to FIG. 4 and FIG. 5 , the semiconductor structure further includes n bit lines 50 . The n bit lines 50 extend along the second direction Y and are located on the back surface of the substrate. Each bit line 50 is electrically connected to the bottom end of a corresponding column of active region pillars 10 via a bit line contact structure 13 .

[0070] It is understandable that by providing the bit lines 50 on the back side of the substrate, the bit lines can be cut from the back side during the manufacturing process, without the need to provide an array boundary, and the size of each unit can be designed to be smaller. This can, on the one hand, improve the integration level, and on the other hand, make it easier to arrange the various areas in chip design, reducing the design difficulty.

[0071] FIG6 is an optional structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure, and FIG6 is a cross-sectional view.

[0072] In some embodiments of the present disclosure, referring to FIG6 , the semiconductor structure further includes a plurality of capacitors 60 . Each capacitor 60 is electrically connected to the top of a corresponding active region pillar 10 through a node contact structure 12 .

[0073] In the disclosed embodiment, capacitor 60 may be a sleeve-type capacitor. The lower plate of each capacitor 60 is electrically connected to the top of a corresponding active region pillar 10. Thus, the active region pillar 10 forms a transistor, and one end of the transistor's source or drain is connected to the lower plate of capacitor 60, thereby forming a 1T1C (1 Transistor-1 Capacitor) storage cell.

[0074] In some embodiments of the present disclosure, referring to FIG. 1 or FIG. 4 , the angle between the first direction X and the second direction Y can be 60°. Accordingly, when viewed from above, the multiple capacitors 60 in FIG. 6 can be arranged in a honeycomb pattern. This, on the one hand, can increase the cross-sectional dimensions of each capacitor 60, thereby increasing the capacity of each capacitor 60; on the other hand, it also enhances the stability of the entire semiconductor structure.

[0075] In some embodiments of the present disclosure, referring to FIG5 , the semiconductor structure further includes a dielectric layer 41 . The dielectric layer 41 covers the tops of the active region pillars 10 and surrounds the sidewalls of the node contact structures 12 , electrically isolating different node contact structures 12 .

[0076] In some embodiments of the present disclosure, referring to FIG. 6 , the semiconductor structure further includes a pad structure 70. The pad structure 70 is located on the back side of the substrate and electrically connected to the corresponding bit line 50. The pad structure 70 can be bonded to corresponding pads on other chips, for example, by hybrid bonding a memory chip and a logic chip, thereby achieving a 3D stacked structure.

[0077] It should be noted that Figures 10A to 15 illustrate intermediate structures in the method for forming a semiconductor structure provided by an embodiment of the present disclosure, and are used to describe and clearly illustrate the steps of the method for forming a semiconductor structure. Figures 10A, 11A, 12A, 13A, and 14A are top views, and Figures 10B, 11B, 12B, 13B, and 14B are corresponding cross-sectional views (with the cross-sectional view line A-A1).

[0078] Figure 7 is a schematic diagram of an optional process of a method for forming a semiconductor structure according to an embodiment of the present disclosure. As shown in Figure 7 , the method for forming a semiconductor structure includes steps S101 to S105 , which will be described in conjunction with each step.

[0079] S101. Provide a substrate; a plurality of initial active area columns extending along a vertical direction are formed on the front side of the substrate; the plurality of initial active area columns form an array of m / 2 rows and n columns along a first direction and a second direction; a shallow trench isolation structure is formed between adjacent initial active area columns; wherein m and n are both greater than 1, and the first direction and the second direction are respectively perpendicular to the vertical direction.

[0080] In the disclosed embodiment, referring to Figures 10A and 10B , a plurality of initial active region pillars 01 are provided on the front surface of a substrate 00 extending along a vertical direction Z. The plurality of initial active region pillars 01 form an array of m / 2 rows and n columns along a first direction X and a second direction Y. Each row of initial active region pillars 01 is arranged along the first direction X, and each column of initial active region pillars 01 is arranged along the second direction Y. The first direction X and the second direction Y are both perpendicular to the vertical direction Z.

[0081] 10A and 10B , a shallow trench isolation structure 42 is formed between adjacent initial active region pillars 01 . The shallow trench isolation structure 42 is made of a dielectric material (eg, semiconductor oxide) to electrically isolate different initial active region pillars 01 .

[0082] S102 , etching the shallow trench isolation structure to form a first trench extending along a first direction between two adjacent rows of initial active area pillars; wherein the remaining shallow trench isolation structure covers the sidewalls of the initial active area pillars to form a gate oxide layer.

[0083] In the embodiment of the present disclosure, the shallow trench isolation structure 42 in FIG. 10A and FIG. 10B can be etched to form a first trench extending along the first direction X between two adjacent rows of initial active region pillars 01 . Furthermore, referring to FIG. 11A and FIG. 11B , the remaining shallow trench isolation structure 42 covers the sidewalls of the initial active region pillars 01 to form a gate oxide layer 11 .

[0084] S103, forming m word lines extending along the first direction; wherein the 2i-1th and 2ith word lines are formed in a corresponding first trench and respectively cover the sidewalls of the corresponding initial active area pillars; wherein i is greater than or equal to 1 and less than m / 2.

[0085] In the embodiment of the present disclosure, referring to FIG11A and FIG11B , word lines 20 extending along the first direction X can be formed in the first trench. Two word lines 20 are formed in a corresponding first trench, each word line 20 covers the sidewall of a corresponding initial active region pillar 01 , and the gate oxide layer 11 is located between the word lines 20 and the sidewall of the initial active region pillar 01 .

[0086] In some embodiments of the present disclosure, the word lines 20 shown in FIG. 11A and FIG. 11B can be formed by the following steps: first, a word line conductive material is filled into the first trench; then, the word line conductive material is etched in each first trench to cut the word line conductive material into two parts, thereby forming two word lines 20. In this way, two word lines 20 are formed in one first trench, and a gap is formed at the location where the etching is cut, thereby forming an air gap.

[0087] S104 , etching to form a second trench extending along the first direction in the middle of each row of initial active region pillars, dividing each row of initial active region pillars into two rows of active region pillars.

[0088] In the disclosed embodiment, after forming the word lines 20, etching can be performed in the middle of each row of initial active area pillars 01 in FIG. 11A and FIG. 11B to form a second trench extending along the first direction X. In this way, each row of initial active area pillars 01 in FIG. 11A and FIG. 11B is divided into two rows of active area pillars 10 in FIG. 12A and FIG. 12B . The initial active area pillars 01 at the outermost edge do not cover the word lines 20; therefore, after being etched and divided into two halves, only the half covering the word lines 20 serves as the active area pillars 10.

[0089] That is, each initial active area column 01 in Figures 11A and 11B is divided into two corresponding active area columns 10 in Figures 12A and 12B; in this way, multiple active area columns 10 form an array of m rows and n columns along the first direction X and the second direction Y.

[0090] At the same time, the 2i-1th and 2ith word lines 20 are located in the first trench between the 2i-1th and 2ith rows of active area pillars 10, and respectively cover the sidewalls of the corresponding active area pillars 10. The portion of the active area pillar 10 covered by the word line 20 can form the channel of the transistor, and the voltage on the word line 20 can control whether the channel is turned on or off.

[0091] It can be understood that the word line 20 covers the sidewall of the active region pillar 10 to control the opening or closing of the channel; in this way, the contact area between the word line 20 and the channel is larger, thereby increasing the control force on the channel, making the opening or closing of the channel more thorough; furthermore, the on-state current I of the transistor can be increased. on , and reduce the transistor's off current I off , thereby reducing power consumption.

[0092] In some embodiments of the present disclosure, referring to Figures 12A and 12B, after etching to form second trenches and dividing each row of initial active area columns into two corresponding rows of active area columns 10, a dielectric material can be deposited in the second trenches to form isolation structures 40 extending along the first direction X.

[0093] It is understood that the isolation structure 40 is located between the active area pillars 10 in the 2i-th row and the 2i+1-th row, and between the 2i-th and 2i+1-th word lines 20. Between the word lines 20 with a larger spacing (i.e., between the 2i-th and 2i+1-th word lines 20), the isolation structure 40 is used to ensure that the parasitic capacitance C between the word lines 20 is small. wl At the same time, the isolation structure 40 can play a good supporting role for the entire semiconductor structure, thereby ensuring the stability of the entire semiconductor structure.

[0094] 12B , the depth of the second trench where the isolation structure 40 is located is greater than the depth of the first trench where the air gap 30 is located. In this way, the isolation structure 40 can better isolate active area pillars 10 in different rows to avoid short circuits and crosstalk.

[0095] S105 , depositing a dielectric layer to cover the top of the active region pillar and forming an air gap between the 2i-1th and 2ith word lines.

[0096] In the embodiment of the present disclosure, referring to FIG12A and FIG12B, after forming the word line 20, a dielectric layer can be deposited to cover the top of the active region pillar 10. In this way, an air gap 30 is formed between the 2i-1st and 2ith word lines (i.e., between the word lines 20 located in the same first trench). Compared with general dielectrics, the air gap 30 has better insulation and a lower dielectric constant. In this way, the parasitic capacitance C between the 2i-1st and 2ith word lines 20 can be reduced. wl Keep it small.

[0097] It can be understood that the embodiment of the present disclosure forms a novel semiconductor structure, in which an array of active region pillars 10 is provided. Furthermore, the 2i-1th and 2ith word lines 20 are provided in the first trench between the 2i-1th and 2ith rows of active region pillars 10, and an air gap 30 is provided between the 2i-1th and 2ith word lines 20. In this way, the air gap 30 with better insulation and lower dielectric constant is used to electrically isolate the 2i-1th and 2ith word lines 20 with a smaller spacing. At the same time, the spacing between the 2ith and 2i+1th word lines 20 is increased, thereby making the parasitic capacitance C between each two adjacent word lines smaller. wl All are kept in a small range.

[0098] That is, the embodiment of the present disclosure does not need to increase the spacing between adjacent active region pillars 10, so that the area occupied by the entire semiconductor structure is small, and at the same time, the parasitic capacitance C between adjacent word lines is guaranteed. wl That is, the embodiment of the present disclosure forms a semiconductor structure with high integration and good electrical performance.

[0099] In some embodiments of the present disclosure, after S105 shown in FIG. 7 , the method for forming a semiconductor structure further includes S106 to S109 shown in FIG. 8 , which will be described in conjunction with each step.

[0100] S106 , forming a patterned mask on the dielectric layer.

[0101] S107 , etching the dielectric layer according to the mask to form a plurality of through holes in the dielectric layer; each through hole exposes the top of a corresponding active region pillar.

[0102] S108 , depositing a plurality of node contact structures in the plurality of through holes; each node contact structure is connected to a top end of a corresponding active region column.

[0103] 13A and 13B , in the disclosed embodiment, node contact structures 12 are formed at the tops of the active region pillars 10, with each node contact structure 12 connected to the top of a corresponding active region pillar 10. A dielectric layer 41 covers the tops of the active region pillars 10 and surrounds the sidewalls of the node contact structures 12, electrically isolating the different node contact structures 12.

[0104] S109 , forming a plurality of capacitors; each capacitor is electrically connected to a top end of a corresponding active region pillar through a node contact structure.

[0105] 13A and 13B , a plurality of capacitors 60 are formed above the dielectric layer 41 . Each capacitor 60 is electrically connected to the top of a corresponding active region pillar 10 through a node contact structure 12 .

[0106] In the disclosed embodiment, capacitor 60 may be a sleeve-type capacitor. The lower plate of each capacitor 60 is electrically connected to the top of a corresponding active region pillar 10. Thus, the active region pillar 10 forms a transistor, and one end of the transistor's source or drain is connected to the lower plate of capacitor 60, thereby forming a 1T1C memory cell.

[0107] In some embodiments of the present disclosure, referring to FIG13A , the angle between the first direction X and the second direction Y can be 60°. Accordingly, when viewed from above, the plurality of capacitors 60 can be arranged in a honeycomb pattern. This, on the one hand, can increase the cross-sectional dimensions of each capacitor 60, thereby increasing the capacity of each capacitor 60; on the other hand, it also enhances the stability of the entire semiconductor structure.

[0108] In some embodiments of the present disclosure, after S109 shown in FIG8 , the method for forming a semiconductor structure further includes S110 to S112 shown in FIG9 , which will be described in conjunction with each step.

[0109] S110, performing a thinning process on the back side of the substrate.

[0110] S111 , forming a plurality of bit line contact structures at the bottom ends of the plurality of active region pillars; the bottom ends of every two active region pillars are connected to a corresponding bit line contact structure.

[0111] S112 , filling metal material into the substrate from the back side of the substrate to form n bit lines; each bit line is electrically connected to the bottom end of a corresponding column of active region pillars through a bit line contact structure.

[0112] In the embodiment of the present disclosure, referring to FIG14A and FIG14B , n bit lines 50 are formed on the back surface of the substrate, extending along the second direction Y. Thus, during the manufacturing process, no array boundary is required, and the size of each unit can be designed to be smaller. This, on the one hand, can improve the integration density, and on the other hand, it is easier to arrange various areas in chip design, reducing the design difficulty.

[0113] In the embodiment of the present disclosure, referring to FIG14B, the bottom ends of every two active area pillars 10 are connected to a corresponding bit line contact structure 13. Each bit line 50 is electrically connected to the bottom end of a corresponding column of active area pillars 10 through the bit line contact structure 13. Compared with each active area pillar corresponding to a bit line contact structure, the size of each bit line contact structure 13 can be made larger in the embodiment of the present disclosure; in this way, on the one hand, the resistance of the bit line contact structure 13 itself is lower, and on the other hand, the contact surface between the bit line contact structure 13 and the bit line is larger, and the contact resistance is lower. At the same time, the size of the bit line contact structure 13 is larger, which improves the sensing capability of the bit line to the device. In summary, the power consumption of the entire semiconductor structure is reduced.

[0114] It is understood that, on the one hand, multiple node contact structures 12 and multiple bit line contact structures 13 are respectively arranged at the top and bottom ends of the active region pillar 10 (i.e., the front and back ends of the substrate). In this way, there is sufficient space to arrange the node contact structures 12 and the bit line contact structures 13, and the node contact structures 12 and the bit line contact structures 13 can be designed to be larger in size, thereby reducing the resistance of the node contact structures 12 and the bit line contact structures 13, and further reducing the power consumption of the entire semiconductor structure. On the other hand, because the node contact structures 12 and the bit line contact structures 13 are respectively arranged at the two ends of the active region pillar 10, during the manufacturing process, the node contact structures 12 and the bit line contact structures 13 can be processed separately from the two ends without interfering with each other, thereby simplifying the manufacturing process.

[0115] In some embodiments of the present disclosure, after S113 shown in FIG. 9 , the method for forming a semiconductor structure further includes S114 , which will be described in conjunction with each step.

[0116] S114 , forming a pad structure on the back side of the substrate; the pad structure is electrically connected to the corresponding bit line.

[0117] In an embodiment of the present disclosure, referring to FIG. 15 , after forming bit lines 50 on the back side of a substrate, a pad structure 70 may be formed on the back side of the substrate. The pad structure 70 electrically connects the corresponding bit lines 50. The pad structure 70 may be bonded to corresponding pads on other chips, for example, by hybrid bonding a memory chip and a logic chip, thereby achieving a 3D stacked structure.

[0118] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0119] The serial numbers of the embodiments of the present disclosure are for descriptive purposes only and do not represent the advantages or disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0120] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure. Industrial Applicability

[0121] The embodiment of the present disclosure does not need to increase the spacing between adjacent active region pillars, so that the area occupied by the entire semiconductor structure is small, and at the same time, the parasitic capacitance C between adjacent word lines is guaranteed. wl That is, the embodiment of the present disclosure provides a semiconductor structure with high integration and good electrical performance.

Claims

1. A semiconductor structure, comprising: A substrate (00) comprising a plurality of discrete active region pillars (10); the plurality of active region pillars (10) are located on the front surface of the substrate (00) and extend in a vertical direction; the plurality of active region pillars (10) are arranged in a first direction and a second direction to form an array of m rows and n columns; wherein m and n are both greater than 1, and the first direction and the second direction intersect and are respectively perpendicular to the vertical direction; m word lines (20) extend along the first direction and are arranged along the second direction; wherein the 2i-1th and 2ith word lines (20) are located in the first groove between the 2i-1th and 2ith active area pillars (10) and respectively cover the side walls of the corresponding active area pillars (10); an air gap (30) is provided between the 2i-1th and 2ith word lines (20); wherein i is greater than or equal to 1 and less than m / 2.

2. The semiconductor structure according to claim 1, wherein: The semiconductor structure further comprises: A plurality of isolation structures (40) extend along the first direction and are sequentially arranged along the second direction; the plurality of isolation structures (40) are located in the second trench between the active region pillars (10) in the 2i-th row and the 2i+1-th row.

3. The semiconductor structure according to claim 1 or 2, wherein: The semiconductor structure further comprises: A gate oxide layer (11) is formed between each word line (20) and the side wall of the corresponding active region column (10).

4. The semiconductor structure according to any one of claims 1 to 3, wherein: The semiconductor structure further comprises: A plurality of node contact structures (12), each of the node contact structures (12) being located at the top of a corresponding active region column (10); A plurality of bit line contact structures (13), the bottom ends of every two active region pillars (10) being connected to a corresponding bit line contact structure (13).

5. The semiconductor structure according to claim 4, wherein: The semiconductor structure further comprises: n bit lines (50) extending along the second direction and located on the back side of the substrate (00); each of the bit lines (50) is electrically connected to the bottom end of a corresponding column of active region pillars (10) through the bit line contact structure (13).

6. The semiconductor structure according to claim 4 or 5, wherein: The semiconductor structure further includes: a plurality of capacitors (60); Each of the capacitors (60) is electrically connected to the top of a corresponding active region column (10) through a node contact structure (12).

7. The semiconductor structure according to claim 6, wherein: The angle between the first direction and the second direction is 60°; The plurality of capacitors are arranged in a honeycomb shape.

8. The semiconductor structure according to any one of claims 4 to 7, wherein: The semiconductor structure further comprises: The dielectric layer (41) covers the tops of the plurality of active region pillars (10) and surrounds the side walls of the plurality of node contact structures (12).

9. The semiconductor structure according to claim 5, wherein: The semiconductor structure further comprises: The pad structure (70) is located on the back side of the substrate (00) and is electrically connected to the corresponding bit line (50).

10. A method for forming a semiconductor structure, the method comprising: A substrate (00) is provided; a front surface of the substrate (00) is formed with a plurality of initial active region pillars (01) extending in a vertical direction; A plurality of the initial active region pillars (01) form an array of m / 2 rows and n columns along a first direction and a second direction; a shallow trench isolation structure (42) is formed between adjacent initial active region pillars (01); wherein m and n are both greater than 1, and the first direction and the second direction are respectively perpendicular to the vertical direction; Etching the shallow trench isolation structure (42) to form a first trench extending along the first direction between two adjacent rows of the initial active region pillars (01); wherein the remaining shallow trench isolation structure (42) covers the side walls of the initial active region pillars (01) to form a gate oxide layer (11); m word lines (20) extending along the first direction are formed; wherein the 2i-1th and 2ith word lines (20) are formed in corresponding first trenches and respectively cover the side walls of the corresponding initial active region pillars (01); wherein i is greater than or equal to 1 and less than m / 2; In the middle of each row of the initial active region pillars (01), a second groove extending along the first direction is formed by etching, so as to divide each row of the initial active region pillars (01) into two rows of active region pillars (10); A dielectric layer (41) is deposited to cover the top of the active region column (10), and an air gap (30) is formed between the 2i-1th and 2ith word lines (20).

11. The method for forming a semiconductor structure according to claim 10, wherein: After depositing the dielectric layer (41) to cover the top of the active region column (10), the method further comprises: forming a patterned mask on the dielectric layer (41); According to the mask, the dielectric layer (41) is etched to form a plurality of through holes in the dielectric layer (41); each of the through holes exposes the top of a corresponding active region column (10); Depositing a plurality of node contact structures (12) in the plurality of through holes; each of the node contact structures (12) is connected to the top of a corresponding active region column (10); A plurality of capacitors (60) are formed; each of the capacitors (60) is electrically connected to the top of a corresponding active region column (10) through a node contact structure (12).

12. The method for forming a semiconductor structure according to claim 11, wherein: After forming a plurality of the capacitors (60), the method further comprises: Performing a thinning process on the back side of the substrate (00); A plurality of bit line contact structures (13) are formed at the bottom ends of the plurality of active region pillars (10); The bottom ends of the two active region pillars (10) are connected to a corresponding one of the bit line contact structures (13); Metal material is filled into the substrate (00) from the back side of the substrate (00) to form n bit lines (50); each of the bit lines (50) is electrically connected to the bottom end of a corresponding column of active region pillars (10) through the bit line contact structure (13).

13. The method for forming a semiconductor structure according to claim 12, wherein: After forming n bit lines (50) and a plurality of bit line contact structures (13), the method further comprises: A pad structure (70) is formed on the back side of the substrate (00); the pad structure (70) is electrically connected to the corresponding bit line (50).

14. The method for forming a semiconductor structure according to any one of claims 10 to 13, wherein: Forming m word lines (20) extending along the first direction, comprising: Filling the first trench with a word line conductive material; In each of the first trenches, the word line conductive material is etched to cut the word line conductive material into two parts to form two word lines (20).

15. The method for forming a semiconductor structure according to any one of claims 10 to 14, wherein: After etching to form the second groove, the method further includes: A dielectric material is deposited in the second trench to form an isolation structure (40) extending along the first direction.

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