Semiconductor device, memory and manufacturing method therefor, and electronic device

Abstract

The present disclosure relates to the technical field of storage, and to a semiconductor device, a memory and a manufacturing method therefor, and an electronic device, for use in improving the performance and reliability of the semiconductor device and the memory. The semiconductor device comprises: a first gate (11), a second gate (21), a third gate (31), a first semiconductor layer (14), a second semiconductor layer (24), and a common source line (SL). The first semiconductor layer (14) is arranged in insulated fashion around the periphery of a side wall of the first gate (11). The second gate (21) is located on the side of the first semiconductor layer (14) facing away from the first gate (11), and comprises: a first portion (A) electrically connected to the first semiconductor layer (14), and a second portion (B) located on the side of the first portion (A) facing away from the first semiconductor layer (14) and electrically connected to the first portion (A). The second semiconductor layer (24) is arranged in insulated fashion around the periphery of a side wall of the second portion (B) and the side of the second portion (B) facing away from a bottom wall of the first portion (A). The third gate (31) and the common source line (SL) are spaced and arranged in insulated fashion around the periphery of the second semiconductor layer (24) facing away from the side wall of the second portion (B).

Description

Semiconductor device, memory and manufacturing method thereof, and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to a Chinese patent application filed with the Patent Office of China on September 28, 2023, with application number 2023112715606 and invention name “Semiconductor device, memory and its preparation method, electronic device”. The entire contents of the patent application are incorporated into this disclosure by reference. Technical Field

[0003] The present disclosure relates to the field of storage technology, and in particular to a semiconductor device, a memory and a preparation method thereof, and an electronic device. Background Art

[0004] With the development of communication and digital technologies, people continue to pursue products with lower power consumption, lighter weight, and better performance. Memory, which can easily achieve higher integration density and larger storage capacity, has gradually become one of the important research directions in the current storage field.

[0005] Summary of the Invention

[0006] According to some embodiments, the present disclosure provides a semiconductor device on one hand, comprising: a first gate, a second gate, a third gate, a first semiconductor layer, a second semiconductor layer, and a common source line. The first semiconductor layer is insulated and surrounds the sidewall of the first gate. The second gate is located on the side of the first semiconductor layer facing away from the first gate, and comprises: a first portion electrically connected to the first semiconductor layer, and a second portion located on the side of the first portion facing away from the first semiconductor layer and electrically connected to the first portion. The second semiconductor layer is insulated and surrounds the sidewall of the second portion and the bottom wall of the second portion facing away from the first portion. The third gate and the common source line are spaced and surround the side of the second semiconductor layer facing away from the sidewall of the second portion, and the third gate is insulated from the second semiconductor layer.

[0007] According to some embodiments, the first semiconductor layer is electrically connected to a first bit line on a side facing away from the first gate and away from the first portion. The second semiconductor layer is electrically connected to a second bit line on a side facing away from the bottom wall of the second portion. The first bit line and the second bit line are arranged parallel to each other and extend along the first direction.

[0008] According to some embodiments, the first gate is electrically connected to the first word line and extends along a third direction. The centerline of the first semiconductor layer extends along the third direction. The second gate extends along a second direction, and the centerline of the second semiconductor layer extends along the second direction. The second direction intersects the first direction. The third gate and the centerline of the common source line extend along the second direction. The third gate is electrically connected to the second word line, and the second word line extends along the third direction. The common source line extends in a direction away from the second semiconductor layer. The third direction intersects both the first direction and the second direction.

[0009] According to some embodiments, the semiconductor device further comprises: a write transistor, a read transistor, and a read control transistor. The write transistor comprises a first gate, a first source and drain, and a second source and drain. The first source and drain are portions of the first semiconductor layer that are away from the first gate and located away from the first portion, and the second source and drain are portions of the first semiconductor layer that are away from the first gate and in contact with the first portion. The read transistor comprises a second gate, a third source and drain, and a fourth source and drain. The read control transistor comprises a third gate, a fifth source and drain, and a sixth source and drain. The third source and drain and the fifth source and drain are portions of the second semiconductor layer that are arranged around the circumference of the second portion and in contact with the common source line. The fourth source and drain and the sixth source and drain are portions of the second semiconductor layer that are away from the bottom wall of the second portion.

[0010] According to some embodiments, the semiconductor device further includes: a write transistor and a read transistor. The write transistor includes a first gate, a first source and drain, and a second source and drain. The first source and drain are portions of the first semiconductor layer that are away from the first gate and located away from the first portion, and the second source and drain are portions of the first semiconductor layer that are away from the first gate and in contact with the first portion. The read transistor includes a second gate, a third gate, a third source and drain, and a fourth source and drain. The third source and drain are portions of the second semiconductor layer that are disposed around the periphery of the second portion and in contact with a common source line. The fourth source and drain are portions of the second semiconductor layer that are away from the bottom wall of the second portion. The second gate is a storage gate of the read transistor. The third gate is a control gate of the read transistor.

[0011] According to some embodiments, the semiconductor device further includes: a first gate dielectric layer, a second gate dielectric layer, and a third gate dielectric layer. The first gate dielectric layer is located between the first gate and the first semiconductor layer. The second gate dielectric layer is located between the second gate and the second semiconductor layer. The third gate dielectric layer is located between the third gate and the second semiconductor layer.

[0012] According to some embodiments, a gap is formed between the second semiconductor layer and the first semiconductor layer along the second direction. The semiconductor device further includes: a fourth gate dielectric layer located in the gap between the first semiconductor layer and the second semiconductor layer and covering the sidewall of the first portion. The fourth gate dielectric layer is connected to the second gate dielectric layer.

[0013] According to some embodiments, a size of the first portion in the first direction is larger than a size of the second portion in the first direction, and a size of the first portion in the second direction is smaller than a size of the second portion in the second direction.

[0014] According to some embodiments, a dimension of the first semiconductor layer in the first direction is larger than a maximum dimension of the second gate in the first direction.

[0015] According to some embodiments, the present disclosure further provides a memory including one or more semiconductor devices according to any one of the aforementioned embodiments.

[0016] According to some embodiments, the present disclosure further provides a method for preparing a memory, comprising the following steps:

[0017] A first conductive material layer is formed and patterned to form a second bit line and a dummy first bit line that are spaced apart and arranged in parallel, and a dummy gate located between and connecting the second bit line and the dummy first bit line. The second bit line and the dummy first bit line extend in a first direction, and the dummy gate extends in a second direction.

[0018] A dielectric material is filled on two opposite sides of the dummy gate in the first direction.

[0019] The dummy gate and dielectric material are etched in a first target area of ​​the dummy gate close to the dummy first bit line to form an etched hole.

[0020] Based on the etched hole, a wet etching process is performed on the dummy first bit line and the retained dummy gate along the second direction and the first direction to form an accommodation space. The accommodation space exposes the corresponding sidewall of the second bit line.

[0021] A semiconductor material layer, a gate dielectric material layer and a second conductive material layer are sequentially deposited in the accommodating space.

[0022] The semiconductor material layer, the gate dielectric material layer and the second conductive material layer in the first target area, as well as the semiconductor material layer, the gate dielectric material layer and the second conductive material layer in the second target area and the third target area on both sides of the first target area along the second direction are removed, so that the retained semiconductor material layer constitutes the second semiconductor layer, the retained gate dielectric material layer constitutes the second gate dielectric layer, the second conductive material layer retained on the side of the second target area close to the second bit line is the second part of the second gate, and the second conductive material layer retained on the side of the third target area away from the second bit line is the first bit line.

[0023] A fourth gate dielectric layer is formed on the sidewalls of the second semiconductor layer and the second gate dielectric layer away from the second bit line, and the fourth gate dielectric layer is connected to the second gate dielectric layer.

[0024] A first portion of a second gate is formed in the second portion of the second target region and on a sidewall of the fourth gate dielectric layer facing away from the second bit line.

[0025] A first semiconductor layer, a first gate dielectric layer and a first gate are formed in sequence by etching a hole wall between the first portion and the first bit line.

[0026] According to some embodiments, the method for preparing a memory further includes the following steps:

[0027] A third gate dielectric layer and a third gate are sequentially arranged in a fourth target region of the second semiconductor layer extending along the second direction and away from the sidewall of the second gate.

[0028] A first word line electrically connected to the first gate is formed.

[0029] A second word line electrically connected to the third gate is formed.

[0030] A common source line is formed in a fifth target region on the periphery of the second semiconductor layer near the first portion. The common source line surrounds a sidewall of the second semiconductor layer extending along the second direction and facing away from the second gate. The fifth target region is located in the gap between the fourth target region and the first portion.

[0031] According to some embodiments, sequentially disposing a third gate dielectric layer and a third gate in a fourth target region of the second semiconductor layer extending along the second direction and facing away from the sidewall of the second gate comprises the following steps:

[0032] The dielectric material is etched along the third direction to expose a peripheral sidewall of the second semiconductor layer located in the fourth target area and facing away from the second gate dielectric layer.

[0033] A third gate dielectric layer is deposited on the peripheral sidewall surface of the second semiconductor layer in the fourth target region away from the second gate dielectric layer, and a third gate electrode is deposited on the peripheral sidewall surface of the third gate dielectric layer away from the second semiconductor layer.

[0034] According to some embodiments, the process of etching the hole, removing the dummy first bit line and the retained dummy gate to form an accommodation space further includes the following steps:

[0035] A wet etching process is performed on the dummy first bit line and the retained dummy gate along the second direction and the first direction to form an accommodating space.

[0036] According to some embodiments, the present disclosure further provides an electronic device on another aspect, comprising one or more memories as described in the aforementioned embodiments.

[0037] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, without paying any creative work, they can also obtain drawings of other embodiments based on these drawings.

[0039] FIG1 is a schematic structural diagram of a semiconductor device provided in some embodiments of the present disclosure;

[0040] FIG2 is a schematic cross-sectional view of the structure shown in FIG1 at section M1;

[0041] FIG3 is a schematic diagram of an equivalent circuit of a semiconductor device provided in some embodiments of the present disclosure;

[0042] FIG4 is another cross-sectional schematic diagram of the structure shown in FIG1 at section M1;

[0043] FIG5 is a schematic flow chart of a method for preparing a memory provided in some embodiments;

[0044] FIG6 is a schematic flow chart of another method for preparing a memory provided in some embodiments;

[0045] FIG7 is a schematic flow chart of step S100 in another method for preparing a memory provided in some embodiments;

[0046] FIG8 is a schematic cross-sectional view of a structure obtained in step S10 in a method for preparing a memory provided in some embodiments;

[0047] FIG9 is a schematic cross-sectional view of a structure obtained in step S20 in a method for preparing a memory provided in some embodiments;

[0048] FIG10 is a schematic cross-sectional view of a structure obtained in step S30 in a method for manufacturing a memory provided in some embodiments;

[0049] FIG11 is a schematic cross-sectional view of a structure obtained in step S40 in a method for manufacturing a memory provided in some embodiments;

[0050] FIG12 is a schematic cross-sectional view of a structure obtained in step S50 in a method for manufacturing a memory provided in some embodiments;

[0051] FIG13 is a schematic cross-sectional view of a structure obtained in step S60 in a method for manufacturing a memory provided in some embodiments;

[0052] FIG14 is a schematic cross-sectional view of a structure obtained in step S70 in a method for manufacturing a memory provided in some embodiments;

[0053] FIG15 is a schematic cross-sectional view of a structure obtained in step S80 in a method for manufacturing a memory provided in some embodiments;

[0054] FIG16 is a schematic cross-sectional view of a structure obtained in step S90 in a method for manufacturing a memory provided in some embodiments;

[0055] FIG17 is a schematic cross-sectional view of a structure obtained in step S101 in a method for manufacturing a memory device according to some embodiments;

[0056] FIG18 is a schematic cross-sectional view of a structure obtained in step S102 in a method for manufacturing a memory device according to some embodiments;

[0057] FIG19 is a schematic cross-sectional view of a structure obtained in step S130 in a method for preparing a memory provided in some embodiments. DETAILED DESCRIPTION

[0058] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0060] It should be understood that when an element or layer is referred to as being “on,” “adjacent,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

[0061] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0062] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0063] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, and variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, embodiments of the present disclosure should not be limited to the specific shapes of regions illustrated herein, but rather include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of regions of a device and do not limit the scope of the present disclosure.

[0064] Referring to Figures 1 and 2, some embodiments of the present disclosure provide a semiconductor device comprising: a first gate 11, a second gate 21, a third gate 31, a first semiconductor layer 14, a second semiconductor layer 24, and a common source line SL. The first semiconductor layer 14 is insulated and surrounds the sidewalls of the first gate 11. The second gate 21 is located on a side of the first semiconductor layer 14 facing away from the first gate 11, and comprises: a first portion A electrically connected to the first semiconductor layer 14, and a second portion B located on a side of the first portion A facing away from the first semiconductor layer 14 and electrically connected to the first portion A. The second semiconductor layer 24 is insulated and surrounds the sidewalls of the second portion B and the bottom wall of the second portion B facing away from the first portion A. The third gate 31 and the common source line SL are spaced apart and surround the side of the second semiconductor layer 24 facing away from the sidewalls of the second portion B, and the third gate 31 is insulated from the second semiconductor layer 24.

[0065] In some embodiments, referring again to Figures 1 and 2 , the first semiconductor layer 14 is electrically connected to the first bit line BL1 on a side facing away from the first gate 11 and away from the first portion A. The second semiconductor layer 24 is electrically connected to the second bit line BL2 on a side facing away from the bottom wall of the second portion B. The first bit line BL1 and the second bit line BL2 are arranged parallel to each other and extend along a first direction (e.g., the X direction).

[0066] The first gate 11 is electrically connected to the first word line WL1 and extends along a third direction (eg, direction Z). The center line of the first semiconductor layer 14 extends along the third direction (eg, direction Z).

[0067] The second gate 21 extends along a second direction (eg, Y direction), and the center line of the second semiconductor layer 24 extends along the second direction (eg, Y direction). The second direction (eg, Y direction) intersects with the first direction (eg, X direction).

[0068] The center line of the third gate 31 and the common source line SL extends along the second direction (eg, direction Y). The third gate 31 is electrically connected to the second word line WL2, and the second word line WL2 extends along the third direction (eg, direction Z).

[0069] The common source line SL extends in a direction away from the second semiconductor layer 24. The third direction (eg, Z direction) intersects with both the first direction (eg, X direction) and the second direction (eg, Y direction).

[0070] For example, the first word line WL1 and the first gate 11 may be formed simultaneously. For example, the first word line WL1 and the first gate 11 may be an integrated structure formed simultaneously using a synchronous process.

[0071] In some embodiments, referring again to Figures 1 and 2 , the semiconductor device further includes a first gate dielectric layer 15, a second gate dielectric layer 25, and a third gate dielectric layer 34. The first gate dielectric layer 15 is located between the first gate 11 and the first semiconductor layer 14. The second gate dielectric layer 25 is located between the second gate 21 and the second semiconductor layer 24. The third gate dielectric layer 34 is located between the third gate 31 and the second semiconductor layer 24.

[0072] In some embodiments, referring again to Figures 1 and 2 , a gap is formed between the second semiconductor layer 24 and the first semiconductor layer 14 along a second direction (e.g., the Y direction). The semiconductor device further includes a fourth gate dielectric layer 35 located within the gap between the first semiconductor layer 14 and the second semiconductor layer 24 and covering the sidewalls of the first portion A. The fourth gate dielectric layer 35 is connected to the second gate dielectric layer 25.

[0073] In some embodiments, referring again to FIG. 1 and FIG. 2 , the dimension of the first portion A in a first direction (e.g., the X direction) is larger than the dimension of the second portion B in the first direction (e.g., the X direction). The dimension of the first portion A in a second direction (e.g., the Y direction) is smaller than the dimension of the second portion B in the second direction (e.g., the Y direction).

[0074] In some embodiments, a dimension of the first semiconductor layer 14 in the first direction (eg, X direction) is larger than a maximum dimension of the second gate 21 in the first direction (eg, X direction).

[0075] In some embodiments, referring to Figures 2 and 3 , the semiconductor device further includes a write transistor T1, a read transistor T2, and a read control transistor T3. The write transistor T1 includes a first gate 11, a first source / drain 12, and a second source / drain 13. The first source / drain 12 is the portion of the first semiconductor layer 14 that faces away from the first gate 11 and is located away from the first portion A. The second source / drain 13 is the portion of the first semiconductor layer 14 that faces away from the first gate 11 and contacts the first portion A. The read transistor T2 includes a second gate 21, a third source / drain 22, and a fourth source / drain 23. The read control transistor T3 includes a third gate 31, a fifth source / drain 32, and a sixth source / drain 33. The third and fifth source / drain 22, 32 are portions of the second semiconductor layer 24 that surround the second portion B and contact the common source line SL. The fourth and sixth source / drain 23, 33 are portions of the second semiconductor layer 24 that face away from the bottom wall of the second portion B.

[0076] Here, it is particularly important to note that, please refer to Figure 2 for understanding, the fourth source and drain 23 and the sixth source and drain 33 respectively serve as electrodes for connecting to the second bit line BL2 in the corresponding transistor, and can be composed of the same part or connected parts in the second semiconductor layer 24; the third source and drain 22 and the fifth source and drain 32 respectively serve as electrodes for connecting to the common source line SL in the corresponding transistor, and can be composed of the same part or connected parts in the second semiconductor layer 24.

[0077] It can be understood that the semiconductor device may include one or more memory cells, each of which may include: a write transistor T1, a read transistor T2, and a read control transistor T3. The first word line WL1 is electrically connected to the first gate 11 of the write transistor T1 and can serve as a write word line to control the write transistor T1 to be turned on during the write phase to implement a data write operation. The first bit line BL1 is in contact with the first source and drain 12 of the write transistor T1 and can serve as a write bit line to provide data to be written. The second word line WL2 is electrically connected to the third gate 31 of the read control transistor T3 and can serve as a read word line to control the read control transistor T3 to be turned on during the read phase to implement a data read operation. The second bit line BL2 is in contact with the fourth source and drain 23 of the read transistor T2 and can serve as a read bit line to provide read data.

[0078] In the disclosed embodiment, a read control transistor T3 is added to the memory cell, and the third gate 31 of the read control transistor T3 is electrically connected to the second word line WL2 (i.e., the read word line). During a read operation, the second word line WL2 in the selected memory cell is set to a normal potential, while the second word lines WL2 in the unselected memory cells are set to a low potential. Thus, for the unselected memory cells, the third gate 31 connected to the corresponding low-potential second word line WL2 can draw more positive charge away from the read transistor channel, ensuring that the read transistors in the unselected memory cells are electrically disconnected. This solves the multipath problem caused by the read current detouring through multiple storage nodes when the same second word line WL2 controls the storage nodes of multiple read transistors during a read operation. It also avoids the voltage drop on the target second bit line BL2 caused by leakage current flowing from different second bit lines BL2 (i.e., the read bit line) controlled by the same second word line WL2, and prevents interference between different memory cells, thereby improving the performance and reliability of the memory cells and memory.

[0079] In addition, in the embodiment of the present disclosure, the fifth source-drain 32 of the read control transistor T3 is electrically connected to the common source line SL, which is conducive to connecting corresponding adjacent multiple memory cells into a piece through the common source line SL to solve the problem of current congestion and optimize the structure of the memory.

[0080] In other embodiments, referring to FIG. 4 , the semiconductor device further includes a write transistor T1 and a read transistor T2. The write transistor T1 includes a first gate 11, a first source / drain 12, and a second source / drain 13. The first source / drain 12 is the portion of the first semiconductor layer 14 that faces away from the first gate 11 and is located away from the first portion A. The second source / drain 13 is the portion of the first semiconductor layer 14 that faces away from the first gate 11 and is in contact with the first portion A. The read transistor T2 includes a second gate 21, a third gate 31, a third source / drain 22, and a fourth source / drain 23. The third source / drain 22 is the portion of the second semiconductor layer 24 that surrounds the second portion B and is in contact with the common source line SL. The fourth source / drain 23 is the portion of the second semiconductor layer 24 that faces away from the bottom wall of the second portion B. The second gate 21 is the storage gate of the read transistor. The third gate 31 is the control gate of the read transistor.

[0081] It can be understood that the semiconductor device may include one or more memory cells, each of which may include: a write transistor T1 and a read transistor T2. The first word line WL1 is electrically connected to the first gate 11 of the write transistor T1 and can serve as a write word line to control the write transistor T1 to be turned on during the write phase to implement a data write operation. The first bit line BL1 is in contact with the first source and drain 12 of the write transistor T1 and can serve as a write bit line to provide data to be written. The second word line WL2 is electrically connected to the third gate 31 of the read transistor T2 and can serve as a read word line to control the read transistor T2 to be turned on during the read phase to implement a data read operation. The second bit line BL2 is in contact with the fourth source and drain 23 of the read transistor T2 and can serve as a read bit line to provide read data.

[0082] In the disclosed embodiment, the third gate 31 within the memory cell is electrically connected to the second word line WL2 (i.e., the read word line). During a read operation, the second word line WL2 in the selected memory cell is set to a normal potential, while the second word lines WL2 in the unselected memory cells are set to a low potential. Thus, for the unselected memory cells, the third gate 31 connected to the corresponding low-potential second word line WL2 can draw more positive charge away from the channel of the read transistor, ensuring that the read transistors in the unselected memory cells are electrically disconnected. This solves the multipath problem caused by the read current detouring through multiple storage nodes when the same second word line WL2 controls the storage nodes of multiple read transistors during a read operation. It also avoids the voltage drop caused by leakage current flowing from different second bit lines BL2 (i.e., the read bit line) under the control of the same second word line WL2, as well as interference between different memory cells, thereby improving the performance and reliability of the memory cells and memory.

[0083] In addition, in the embodiment of the present disclosure, the third source and drain 22 are electrically connected to the common source line SL, which facilitates connecting corresponding adjacent multiple memory cells into a piece through the common source line SL to solve the current crowding problem and optimize the memory structure.

[0084] According to some embodiments, the present disclosure further provides a memory device comprising the semiconductor device according to any one of the aforementioned embodiments. The memory device also possesses the technical advantages of the aforementioned semiconductor device, which will not be described in detail here.

[0085] Some embodiments of the present disclosure also provide a method for preparing a memory, which is used to prepare the memory in some of the above embodiments. This method also possesses the technical advantages of the above memories.

[0086] Please refer to FIG. 5 and understand in combination with FIG. 1 to FIG. 4 that the preparation method includes steps S10 to S90.

[0087] S10: Forming a first conductive material layer and patterning the first conductive material layer to form a second bit line and a dummy first bit line that are spaced apart and arranged in parallel, and a dummy gate located between and connecting the second bit line and the dummy first bit line. The second bit line and the dummy first bit line extend along a first direction, and the dummy gate extends along a second direction.

[0088] S20 : ​​filling dielectric material on two opposite sides of the dummy gate in the first direction.

[0089] S30: etching the dummy gate and the dielectric material in a first target region of the dummy gate close to the dummy first bit line to form an etched hole.

[0090] S40: Based on the etched hole, a wet etching process is performed on the dummy first bit line and the retained dummy gate along the second direction and the first direction to form an accommodation space. The accommodation space exposes the corresponding sidewall of the second bit line.

[0091] S50: depositing a semiconductor material layer, a gate dielectric material layer, and a second conductive material layer in sequence in the accommodating space.

[0092] S60: Remove the semiconductor material layer, the gate dielectric material layer, and the second conductive material layer in the first target area, as well as the semiconductor material layer, the gate dielectric material layer, and the second conductive material layer in the second target area and the third target area on both sides of the first target area along the second direction, so that the retained semiconductor material layer constitutes the second semiconductor layer, the retained gate dielectric material layer constitutes the second gate dielectric layer, the second conductive material layer retained in the second target area close to the second bit line is the second part of the second gate, and the second conductive material layer retained in the third target area away from the second bit line is the first bit line.

[0093] S70: forming a fourth gate dielectric layer on sidewalls of the second semiconductor layer and the second gate dielectric layer away from the second bit line, wherein the fourth gate dielectric layer is connected to the second gate dielectric layer.

[0094] S80 : forming a first portion of a second gate in the second portion of the second target region and on a sidewall of the fourth gate dielectric layer facing away from the second bit line.

[0095] S90: etching the hole wall between the first portion and the first bit line to sequentially form a first semiconductor layer, a first gate dielectric layer, and a first gate.

[0096] In some embodiments, step S40 removes the dummy first bit line and the retained dummy gate based on etching the hole to form an accommodation space, and further includes the following steps.

[0097] A wet etching process is performed on the dummy first bit line and the retained dummy gate along the second direction and the first direction to form an accommodating space.

[0098] In some embodiments, referring to FIG. 6 , the memory manufacturing method further includes steps S100 to S130 .

[0099] S100 : sequentially and surroundingly disposing a third gate dielectric layer and a third gate in a fourth target region of the second semiconductor layer extending along the second direction and away from the sidewall of the second gate.

[0100] S110 : forming a first word line electrically connected to the first gate.

[0101] S120: forming a second word line electrically connected to the third gate.

[0102] S130: Forming a common source line in a fifth target region on a peripheral side of the second semiconductor layer near the first portion. The common source line is disposed around a sidewall of the second semiconductor layer extending along the second direction and facing away from the second gate. The fifth target region is located between the fourth target region and the first portion.

[0103] In some embodiments, referring to FIG. 7 , step S100 includes sequentially disposing a third gate dielectric layer and a third gate in a fourth target region of the second semiconductor layer extending along the second direction and away from the sidewall of the second gate.

[0104] S101 : etching the dielectric material along a third direction to expose a peripheral sidewall of the second semiconductor layer located in a fourth target region away from the second gate dielectric layer.

[0105] S102: depositing a third gate dielectric layer on a peripheral sidewall surface of the second semiconductor layer away from the second gate dielectric layer in the fourth target region, and depositing a third gate electrode on a peripheral sidewall surface of the third gate dielectric layer away from the second semiconductor layer.

[0106] In order to more clearly illustrate the memory manufacturing methods in some of the above embodiments, the following embodiments exemplarily provide some possible specific implementations of some steps.

[0107] In step S10, referring to FIG. 8 , a first conductive material layer (not shown) is formed and patterned to form a second bit line BL2 and a virtual first bit line VBL1 that are arranged in parallel and spaced apart, and a virtual gate GV located between and connecting the second bit line BL2 and the virtual first bit line VBL1; wherein the second bit line BL2 and the virtual first bit line VBL1 extend along a first direction (e.g., an X direction), and the virtual gate GV extends along a second direction (e.g., a Y direction).

[0108] It is important to note that in the three-dimensional stacked structure, the first semiconductor layers corresponding to different first conductive material layers are separated. This means that multiple first conductive material layers and multiple sacrificial layers are alternately stacked. The sacrificial layers are removed as needed to allow for subsequent lateral etching of the first semiconductor material layers to obtain the first semiconductor layers of each write transistor.

[0109] Illustratively, the first conductive material layer includes a metal layer, such as a metal tungsten layer.

[0110] Illustratively, the sacrificial layer includes, but is not limited to, a silicon nitride layer.

[0111] Here, each first conductive material layer and each sacrificial layer can be formed by a deposition process.

[0112] In step S20 , referring to FIG. 9 , a dielectric material L1 is filled on two opposite sides of the dummy gate GV in a first direction (eg, the X direction).

[0113] Illustratively, the dielectric material L1 includes but is not limited to silicon oxide.

[0114] Here, the dielectric material L1 may be formed by a deposition process. After the dielectric material L1 is formed by the deposition process, a chemical mechanical polishing (CMP) process may be used to polish the upper surface of the dielectric material L1 to ensure that the upper surface of the dielectric material L1 is flat.

[0115] In step S30 , referring to FIG. 10 , the dummy gate VG and the dielectric material L1 are etched in a first target region R1 of the dummy gate GV close to the dummy first bit line VBL1 to form an etched hole K1 .

[0116] Here, dry etching may be used to form the etching hole K1.

[0117] In step S40 , referring to FIG. 11 , based on the etching hole K1 , the dummy first bit line VBL1 and the retained dummy gate GV are removed to form an accommodating space C1 including the etching hole K1 ; the accommodating space C1 exposes the corresponding sidewall of the second bit line BL2 .

[0118] For example, based on the etching hole K1, the virtual first bit line VBL1 and the retained virtual gate GV are removed to form an accommodating space C1, and the process also includes: performing a wet etching process along the second direction (for example, the Y direction) and the first direction (for example, the X direction) on the virtual first bit line VBL1 and the retained virtual gate GV to form the accommodating space C1.

[0119] In step S50 , referring to FIG. 12 , a semiconductor material layer 1 , a gate dielectric material layer 2 , and a second conductive material layer 3 are sequentially deposited in the accommodating space C1 .

[0120] For example, the semiconductor material layer 1 includes but is not limited to a metal oxide semiconductor layer, such as an indium gallium zinc oxide (IGZO) layer.

[0121] For example, the gate dielectric material layer 2 includes but is not limited to a HK (high-K) dielectric layer. The HK dielectric layer refers to a dielectric layer with a high dielectric constant K, where the high dielectric constant K is, for example, greater than 3.9.

[0122] For example, the material of the second conductive material layer 3 includes but is not limited to metal tungsten.

[0123] Here, the semiconductor material layer 1 , the gate dielectric material layer 2 and the second conductive material layer 3 may be deposited in sequence using an ALD process.

[0124] In step S60, referring to Figure 13, the semiconductor material layer 1, the gate dielectric material layer 2 and the second conductive material layer 3 in the first target region R1, as well as the semiconductor material layer 1, the gate dielectric material layer 2 and the second conductive material layer 3 in the second target region R2 and the third target region R3 on both sides adjacent to the first target region R1 along the second direction (for example, the Y direction) are removed, so that the retained semiconductor material layer 1 constitutes the second semiconductor layer 24, the retained gate dielectric material layer 2 constitutes the second gate dielectric layer 25, the second conductive material layer 3 retained in the second target region R2 on the side close to the second bit line BL2 is the second part B of the second gate 21, and the second conductive material layer 3 retained in the third target region R3 on the side away from the second bit line BL2 is the first bit line BL1.

[0125] Here, dry etching can be used to first remove the semiconductor material layer 1, the gate dielectric material layer 2 and the second conductive material layer 3 in the first target area R1, and then wet etching can be used to remove the semiconductor material layer 1, the gate dielectric material layer 2 and the second conductive material layer 3 in the second target area R2 and the third target area R3 along the second direction (for example, the Y direction). The second conductive material layer 3 retained in the second target area R2 on the side close to the second bit line BL2 is the second part B of the second gate 21, and the second conductive material layer 3 retained in the third target area R3 away from the second bit line BL2 is the first bit line BL1.

[0126] In step S70 , referring to FIG. 14 , a fourth gate dielectric layer 35 is formed on sidewalls of the second semiconductor layer 24 and the second gate dielectric layer 25 away from the second bit line BL2 ; the fourth gate dielectric layer 35 is connected to the second gate dielectric layer 25 .

[0127] Illustratively, the fourth gate dielectric layer 35 includes but is not limited to an HK dielectric layer.

[0128] In step S80 , referring to FIG. 15 , a first portion A of the second gate 21 is formed in the second portion B of the second target region R2 and on the sidewall of the fourth gate dielectric layer 35 facing away from the read bit line BL2 .

[0129] Here, while forming the first portion A of the second gate 21 , the second conductive material layer 3 is backfilled in the third target region R3 .

[0130] In step S90 , referring to FIG. 16 , a first semiconductor layer 14 , a first gate dielectric layer 15 and a first gate electrode 11 are sequentially formed by etching a hole K1 between the first portion A and the first bit line BL1 .

[0131] For example, the first semiconductor layer 14 includes but is not limited to a metal oxide semiconductor layer, such as an indium gallium zinc oxide (IGZO) layer.

[0132] Illustratively, the first gate dielectric layer 15 includes but is not limited to a HK dielectric layer.

[0133] For example, the material of the first gate 11 includes but is not limited to metal tungsten.

[0134] Here, the first semiconductor layer 14 , the first gate dielectric layer 15 and the first gate 11 may be deposited in sequence by using an ALD process.

[0135] In step S101 , referring to FIG. 17 , the dielectric material L1 is etched along a third direction (eg, Z direction) to expose the peripheral sidewall of the second semiconductor layer 24 facing away from the second gate dielectric layer 25 in the fourth target region R4 .

[0136] In step S102 , referring to FIG. 18 , a third gate dielectric layer 34 is deposited on the peripheral sidewall surface of the second semiconductor layer 24 away from the second gate dielectric layer 25 in the fourth target region R4 ; and a third gate electrode 31 is deposited on the peripheral sidewall surface of the third gate dielectric layer 34 away from the second semiconductor layer 24 .

[0137] Illustratively, the third gate dielectric layer 34 includes but is not limited to a HK dielectric layer.

[0138] By way of example, the material of the third gate 31 includes but is not limited to metal tungsten.

[0139] Here, the third gate dielectric layer 34 and the third gate 31 may be deposited by using an ALD process.

[0140] In step S110 , referring to FIG. 18 , a first word line WL1 electrically connected to the first gate 11 is formed. The first word line WL1 extends along a third direction (eg, the Z direction).

[0141] By way of example, the material of the first word line WL1 includes, but is not limited to, metal tungsten.

[0142] Here, the first word line WL1 and the first gate 11 may be formed simultaneously.

[0143] In step S120 , referring to FIG. 18 , a second word line WL2 electrically connected to the third gate 31 is formed. The second word line WL2 extends along a third direction (eg, the Z direction).

[0144] By way of example, the material of the second word line WL2 includes, but is not limited to, metal tungsten.

[0145] In step S130, referring to FIG. 19 , a common source line SL is formed in a fifth target region R5 near the write transistor TW on the periphery of the second semiconductor layer 24. The common source line SL surrounds the sidewall of the second semiconductor layer 24 extending in the second direction (e.g., the Y direction) and facing away from the second gate 21. The fifth target region R5 is located between the fourth target region R4 and the write transistor TW.

[0146] Here, the common source line SL includes, but is not limited to, metal tungsten.

[0147] For example, forming a common source line SL in the fourth target area R4 near the write transistor TW on the peripheral side of the second semiconductor layer 24 includes: first etching the dielectric material L1 along a third direction (for example, the Z direction) to expose the peripheral side wall of the second semiconductor layer 24 located in the fourth target area R4 away from the second gate dielectric layer 25, and then backfilling the conductive material to form the common source line SL.

[0148] Please continue to refer to FIG. 19 and combine it with FIG. 2 to understand that in some embodiments, the first gate 11, the first source-drain 12, and the second source-drain 13 constitute a write transistor T1. The first source-drain 12 is the portion of the first semiconductor layer 14 that faces away from the first gate 11 and is located away from the first portion A. The second source-drain 13 is the portion of the first semiconductor layer 14 that faces away from the first gate 11 and contacts the first portion A. The second gate 21, the third source-drain 22, and the fourth source-drain 23 constitute a read transistor T2. The third gate 31, the fifth source-drain 32, and the sixth source-drain 33 constitute a read control transistor T3. The third source-drain 22 and the fifth source-drain 32 are the portions of the second semiconductor layer 24 that surround the second portion B and contact the common source line SL. The fourth source-drain 23 and the sixth source-drain 33 are the portions of the second semiconductor layer 24 that face away from the bottom wall of the second portion B.

[0149] In other embodiments, please continue to refer to FIG. 19 and understand in conjunction with FIG. 4 , the first gate 11, the first source-drain 12, and the second source-drain 13 constitute a write transistor T1. The first source-drain 12 is the portion of the first semiconductor layer 14 that faces away from the first gate 11 and is located away from the first portion A. The second source-drain 13 is the portion of the first semiconductor layer 14 that faces away from the first gate 11 and contacts the first portion A. The second gate 21, the third gate 31, the third source-drain 22, and the fourth source-drain 23 constitute a read transistor T2. The third source-drain 22 is the portion of the second semiconductor layer 24 that surrounds the second portion B and contacts the common source line SL. The fourth source-drain 23 is the portion of the second semiconductor layer 24 that faces away from the bottom wall of the second portion B. The second gate 21 is the storage gate of the read transistor T1. The third gate 31 is the control gate of the read transistor T2.

[0150] Some embodiments of the present disclosure further provide an electronic device comprising: one or more memories as described in the aforementioned embodiments. Examples include data storage devices, photocopiers, network equipment, household appliances, instruments, mobile phones, computers, and other devices with data storage capabilities. The electronic device may include a housing, a circuit board disposed within the housing, and a memory or data read / write circuit integrated on the circuit board. The structure of the memory can be found in the relevant descriptions of some of the aforementioned embodiments. The electronic device may also include other necessary elements or components, which are not limited in the present disclosure.

[0151] In some embodiments, the memory may be coupled to an external control device such as a processor or an actuator. The processor is coupled to the memory and can control the read and write operations of the memory.

[0152] In some embodiments, the memory is 3D-DRAM.

[0153] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0154] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims.

Claims

1. A semiconductor device, comprising: A first gate, a second gate, a third gate, a first semiconductor layer, a second semiconductor layer and a common source line; wherein, The first semiconductor layer is insulated and surrounds the sidewall of the first gate; The second gate is located on a side of the first semiconductor layer away from the first gate, and includes: a first portion electrically connected to the first semiconductor layer, and a second portion located on a side of the first portion away from the first semiconductor layer and electrically connected to the first portion; The second semiconductor layer is insulated and surrounds the sidewall of the second portion and the bottom wall of the second portion away from the first portion; The third gate and the common source line are spaced and surround the peripheral side of the second semiconductor layer away from the second portion sidewall, and the third gate is insulated from the second semiconductor layer.

2. The semiconductor device according to claim 1, wherein The first semiconductor layer is away from the first gate and is located at a side far away from the first portion and is electrically connected to the first bit line; A side of the second semiconductor layer facing away from the bottom wall of the second portion is electrically connected to a second bit line; The first bit lines and the second bit lines are arranged in parallel and spaced apart from each other, and extend along a first direction.

3. The semiconductor device according to claim 2, wherein: The first gate is electrically connected to the first word line and extends along a third direction; the surrounding center line of the first semiconductor layer extends along the third direction; The second gate extends along a second direction, and the surrounding center line of the second semiconductor layer extends along the second direction; the second direction intersects with the first direction; The surrounding center line of the third gate and the common source line extends along the second direction; the third gate is electrically connected to the second word line, and the second word line extends along the third direction; the common source line extends in a direction away from the second semiconductor layer; the third direction intersects with both the first direction and the second direction.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The semiconductor device further includes: a write transistor, a read transistor and a read control transistor; wherein, The write transistor includes the first gate, a first source and a drain, and a second source and a drain; the first source and a drain are portions of the first semiconductor layer that are away from the first gate and are located away from the first portion, and the second source and a drain are portions of the first semiconductor layer that are away from the first gate and are in contact with the first portion; The read transistor includes the second gate, a third source and drain, and a fourth source and drain; The read control tube includes the third gate, the fifth source and drain, and the sixth source and drain; Among them, the third source drain and the fifth source drain are the parts of the second semiconductor layer that are arranged around the circumference of the second part and contact the common source line; the fourth source drain and the sixth source drain are the parts of the second semiconductor layer that are away from the bottom wall of the second part.

5. The semiconductor device according to any one of claims 1 to 3, wherein: The semiconductor device further comprises: a write transistor and a read transistor; wherein, The write transistor includes the first gate, a first source and a drain, and a second source and a drain; the first source and a drain are portions of the first semiconductor layer that are away from the first gate and located away from the first portion, and the second source and a drain are portions of the first semiconductor layer that are away from the first gate and in contact with the first portion; The read transistor includes the second gate, the third gate, a third source and drain, and a fourth source and drain; the third source and drain is a portion of the second semiconductor layer disposed around the circumference of the second portion and in contact with the common source line; the fourth source and drain is a portion of the second semiconductor layer away from the bottom wall of the second portion; The second gate is a storage gate of the read transistor; and the third gate is a control gate of the read transistor.

6. The semiconductor device according to any one of claims 1 to 5, wherein: It also includes a first gate dielectric layer, a second gate dielectric layer and a third gate dielectric layer; wherein, The first gate dielectric layer is located between the first gate and the first semiconductor layer; The second gate dielectric layer is located between the second gate and the second semiconductor layer; The third gate dielectric layer is located between the third gate and the second semiconductor layer.

7. The semiconductor device according to claim 6, wherein: There is a gap between the second semiconductor layer and the first semiconductor layer along the second direction; the semiconductor device further comprises: a fourth gate dielectric layer located in the gap between the first semiconductor layer and the second semiconductor layer and covering the side wall of the first portion; The fourth gate dielectric layer is connected to the second gate dielectric layer.

8. The semiconductor device according to any one of claims 3 to 5, wherein: The size of the first portion in the first direction is greater than the size of the second portion in the first direction; A size of the first portion in the second direction is smaller than a size of the second portion in the second direction.

9. The semiconductor device according to any one of claims 2 to 5, wherein: A size of the first semiconductor layer in the first direction is greater than a maximum size of the second gate in the first direction.

10. A memory comprising: The semiconductor device according to any one of claims 1 to 9.

11. A method for preparing a memory, comprising: Forming a first conductive material layer, and patterning the first conductive material layer to form a second bit line and a virtual first bit line that are arranged in parallel and spaced apart, and a virtual gate located between and connecting the second bit line and the virtual first bit line; wherein the second bit line and the virtual first bit line extend along the first direction, and the virtual gate extends along the second direction; Filling dielectric material on two opposite sides of the virtual gate in the first direction; Etching the virtual gate and the dielectric material in a first target area of ​​the virtual gate close to the virtual first bit line to form an etching hole; Based on the etching hole, performing a wet etching process along the second direction and the first direction on the virtual first bit line and the retained virtual gate to form an accommodation space; the accommodation space exposes a corresponding side wall of the second bit line; Depositing a semiconductor material layer, a gate dielectric material layer and a second conductive material layer in the accommodating space in sequence; removing the semiconductor material layer, the gate dielectric material layer and the second conductive material layer in the first target region, as well as the semiconductor material layer, the gate dielectric material layer and the second conductive material layer in the second target region and the third target region on both sides of the first target region along the second direction, so that the remaining semiconductor material layer constitutes a second semiconductor layer, the remaining gate dielectric material layer constitutes a second gate dielectric layer, the second conductive material layer retained on the side of the second target region close to the second bit line is the second part of the second gate, and the second conductive material layer retained on the side of the third target region away from the second bit line is the first bit line; forming a fourth gate dielectric layer on the sidewalls of the second semiconductor layer and the second gate dielectric layer away from the second bit line; the fourth gate dielectric layer is connected to the second gate dielectric layer; forming a first portion of the second gate in the second target region at the second portion and a sidewall of the fourth gate dielectric layer away from the second bit line; A first semiconductor layer, a first gate dielectric layer and a first gate are sequentially formed on the hole wall of the etched hole between the first portion and the first bit line.

12. The method for preparing a memory according to claim 11, wherein: Also includes: A third gate dielectric layer and a third gate are sequentially disposed in a fourth target region on the side of the side wall of the second semiconductor layer extending along the second direction and away from the second gate; forming a first word line electrically connected to the first gate; forming a second word line electrically connected to the third gate; A common source line is formed in a fifth target area near the first portion on the peripheral side of the second semiconductor layer; The common source line is disposed around the side wall of the second semiconductor layer extending along the second direction and away from the second gate; the fifth target area is located in the interval between the fourth target area and the first portion.

13. The method for preparing a memory according to claim 12, wherein: The third gate dielectric layer and the third gate are sequentially arranged in a fourth target region extending along the second direction and away from the side wall of the second semiconductor layer of the second gate, and the third gate dielectric layer and the third gate are sequentially arranged in a surrounding manner, including: Etching the dielectric material along a third direction to expose a peripheral side wall of the second semiconductor layer away from the second gate dielectric layer located in the fourth target area; A third gate dielectric layer is deposited on a peripheral sidewall surface of the second semiconductor layer in the fourth target region away from the second gate dielectric layer; and a third gate electrode is deposited on a peripheral sidewall surface of the third gate dielectric layer away from the second semiconductor layer.

14. The method for preparing a memory according to any one of claims 11 to 13, wherein: The method of removing the virtual first bit line and the retained virtual gate based on the etching hole to form an accommodation space further includes: A wet etching process is performed on the virtual first bit line and the retained virtual gate along the second direction and the first direction to form the accommodation space.

15. An electronic device, comprising: One or more memories as claimed in claim 10.

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