Semiconductor structure and preparation method therefor

Abstract

The present disclosure provides a semiconductor structure and a preparation method therefor. The semiconductor structure comprises: a substrate; a plurality of resistive devices arranged in an array on the substrate along a first direction and a second direction, wherein the first direction and the second direction are directions parallel to the plane of the substrate, and the first direction intersects with the second direction, and the resistive devices and the first direction are at a preset angle; and a plurality of first metal layers located above the resistive devices and extending in the first direction.

Description

Semiconductor structure and preparation method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application No. 202311277388.5 filed with the China Patent Office on September 28, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0004] Resistive Random Access Memory (RRAM) is a non-volatile memory that uses the variable resistance properties of materials to store information. It has the advantages of low power consumption, high density, fast read and write speed, and good durability.

[0005] In existing resistive random access memories, the contact area between the upper metal layer and the resistive random access device is limited by the size of the resistive random access device, thereby increasing the resistance value of the memory and the voltage, thereby affecting the device performance.

[0006] Summary of the Invention

[0007] The present disclosure provides a semiconductor structure and a method for manufacturing the same, to at least solve the above technical problems existing in the prior art.

[0008] According to a first aspect of the present disclosure, there is provided a semiconductor structure comprising:

[0009] substrate;

[0010] A plurality of resistive switching devices arranged in an array along a first direction and a second direction on the substrate, wherein the first direction and the second direction are parallel to the plane of the substrate and intersect with each other; wherein the resistive switching devices form a predetermined angle with the first direction;

[0011] A plurality of first metal layers are located on the resistive switching device and extend along the first direction.

[0012] In one embodiment, the preset angle ranges from 5° to 10°.

[0013] In one embodiment, each of the resistive switching devices includes a lower electrode, a resistive switching layer, an oxide-capping layer, and an upper electrode stacked in sequence;

[0014] Along the first direction, among the plurality of resistive switching devices, the oxide-grabbing layers and the upper electrodes of every two adjacent resistive switching devices are connected respectively.

[0015] In one embodiment, the semiconductor structure further includes:

[0016] A first contact plug is located on the resistive device, and the first contact plug connects the resistive device and the first metal layer.

[0017] In one embodiment, the semiconductor structure further includes:

[0018] a second metal layer located on the substrate;

[0019] A second contact plug is located on the second metal layer; wherein the second contact plug connects the second metal layer and the resistive switching device.

[0020] According to a second aspect of the present disclosure, a method for preparing a semiconductor structure is provided, comprising:

[0021] providing a substrate;

[0022] A plurality of resistive switching devices are formed on the substrate and arranged in an array along a first direction and a second direction, wherein the first direction and the second direction are parallel to the plane of the substrate and intersect with each other; wherein the resistive switching devices form a preset angle with the first direction;

[0023] A plurality of first metal layers extending along the first direction are formed on the resistive switching device.

[0024] In one embodiment, the preset angle ranges from 5° to 10°.

[0025] In one embodiment, the forming of the resistive switching device includes: forming a lower electrode, a resistive switching layer, an oxide-capping layer, and an upper electrode stacked in sequence;

[0026] Along the first direction, among the plurality of resistive switching devices, the oxide-grabbing layers and the upper electrodes of every two adjacent resistive switching devices are connected respectively.

[0027] In one embodiment, the method further comprises:

[0028] Before forming the first metal layer, a first contact plug is formed on the resistive device, wherein the first contact plug connects the resistive device and the first metal layer.

[0029] In one embodiment, the method further comprises:

[0030] Before forming the resistive switching device, forming a second metal layer on the substrate;

[0031] A second contact plug is formed on the second metal layer; wherein the second contact plug connects the second metal layer and the resistive switching device.

[0032] The disclosed semiconductor structure and fabrication method thereof, by tilting the resistive switching device at a predetermined angle, facilitates increasing the size of the first metal layer located above the resistive switching device. This not only reduces the resistance of the first metal layer but also increases the contact area between the resistive switching device and the first metal layer. Furthermore, tilting the resistive switching device at a predetermined angle also facilitates increasing the size of the resistive switching device. This, combined with the increased contact area between the resistive switching device and the first metal layer, results in a voltage reduction effect.

[0033] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings, in which several embodiments of the present disclosure are shown by way of example and not limitation, wherein:

[0035] In the drawings, the same or corresponding reference numerals denote the same or corresponding parts.

[0036] FIG1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.

[0037] FIG2 is a top view of a semiconductor structure provided by an embodiment of the present disclosure.

[0038] FIG3 is a schematic structural diagram of a semiconductor structure provided by another embodiment of the present disclosure.

[0039] FIG4 is a flow chart of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.

[0040] FIG5 a is a first schematic diagram of the semiconductor structure during the preparation process provided by an embodiment of the present disclosure.

[0041] FIG5 b is a second schematic diagram of the semiconductor structure provided in an embodiment of the present disclosure during the preparation process.

[0042] FIG5 c is a third schematic diagram of the semiconductor structure during the preparation process provided by an embodiment of the present disclosure.

[0043] FIG5 d is a fourth schematic diagram of the semiconductor structure during the preparation process provided by an embodiment of the present disclosure.

[0044] FIG5e is a fifth schematic diagram of the semiconductor structure provided in an embodiment of the present disclosure during the preparation process.

[0045] FIG5f is a sixth schematic diagram of the semiconductor structure during the preparation process provided by an embodiment of the present disclosure.

[0046] FIG5g is a seventh schematic diagram of the semiconductor structure during the preparation process provided by an embodiment of the present disclosure.

[0047] FIG5h is an eighth schematic diagram of the semiconductor structure during the preparation process provided by an embodiment of the present disclosure.

[0048] FIG5i is a ninth schematic diagram of the semiconductor structure during the preparation process provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] To make the purposes, features, and advantages of the present disclosure more apparent and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative work shall fall within the scope of protection of the present disclosure.

[0050] An embodiment of the present disclosure provides a semiconductor structure, and FIG1 is a schematic structural diagram of the semiconductor structure provided by an embodiment of the present disclosure.

[0051] As shown in FIG1 , the semiconductor structure includes:

[0052] substrate 10;

[0053] A plurality of resistive switching devices 20 arranged in an array along a first direction and a second direction on the substrate 10, wherein the first direction and the second direction are parallel to the plane of the substrate 10 and intersect with each other; wherein the resistive switching devices 20 form a predetermined angle with the first direction;

[0054] A plurality of first metal layers 31 are located on the resistive device 20 and extend along the first direction.

[0055] In the disclosed embodiments, tilting the resistive switching device at a predetermined angle facilitates increasing the size of the first metal layer located above the resistive switching device. This not only reduces the resistance of the first metal layer but also increases the contact area between the resistive switching device and the first metal layer. Furthermore, tilting the resistive switching device at a predetermined angle also facilitates increasing the size of the resistive switching device. This, combined with the increased contact area between the resistive switching device and the first metal layer, results in a voltage reduction effect.

[0056] In some embodiments, the substrate 10 can be a single semiconductor material substrate (for example, a silicon substrate, a germanium substrate, etc.), a compound semiconductor material substrate (for example, a germanium silicon substrate, etc.), or a silicon on insulator (SOI) substrate, a germanium on insulator (GOI) substrate, etc.

[0057] In one embodiment, the semiconductor structure further includes: a first dielectric layer 51 located on the substrate 10 . The material of the first dielectric layer 51 may include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0058] The semiconductor structure further includes: a second metal layer 32 located on the substrate 10 ; and a second contact plug 42 located on the second metal layer 32 . The second contact plug 42 connects the second metal layer 32 and the resistive device 20 .

[0059] Specifically, as shown in FIG. 1 , the second metal layer 32 and the second contact plug 42 are located in the first dielectric layer 51 .

[0060] The material of the second metal layer 32 includes but is not limited to copper. The second contact plug 42 may have a double-layer structure, and the material of the second contact plug 42 may include titanium nitride in the outer layer and tungsten in the inner layer.

[0061] The resistive switching devices 20 are located on the second contact plugs 42 , and each of the resistive switching devices 20 includes a lower electrode 21 , a resistive switching layer 22 , an oxide-capping layer 23 and an upper electrode 24 stacked in sequence;

[0062] Along the first direction, among the plurality of resistive devices 20 , the oxide-capping layers 23 and the upper electrodes 24 of every two adjacent resistive devices 20 are connected respectively.

[0063] Specifically, as shown in FIG1 , the capping oxide layers 23 of each two adjacent resistive switching devices 20 are connected to each other, and the top electrodes 24 are connected to each other. The capping oxide layers and top electrodes of each two adjacent resistive switching devices are connected separately, which helps to increase the contact area between the top electrode and the capping oxide layer, thereby achieving the effect of reducing voltage.

[0064] The material of the lower electrode 21 includes, but is not limited to, titanium nitride. The resistive layer 22 includes a first resistive layer 221 and a second resistive layer 222 stacked in sequence. The material of the first resistive layer 221 includes, but is not limited to, hafnium oxide, and the material of the second resistive layer 222 includes, but is not limited to, aluminum oxide. The material of the grip oxide layer 23 may include, but is not limited to, at least one of aluminum, tantalum, tantalum nitride, titanium, and titanium nitride. In this embodiment, the material of the grip oxide layer 23 is, for example, titanium. The material of the upper electrode 24 includes, but is not limited to, titanium nitride.

[0065] FIG2 is a top view of a semiconductor structure provided by an embodiment of the present disclosure. It should be explained that FIG2 only shows the resistive switching device and the first metal layer.

[0066] As shown in Figure 2, the resistive device 20 forms a preset angle a with the first direction. The preset angle a ranges from 5° to 10°. Within this range, the size of the first metal layer can be increased, thereby increasing the contact area between the resistive device and the first metal layer, thereby reducing the voltage. At the same time, because the distance between two adjacent first metal layers is at least 50nm, setting the preset angle within this range can also avoid affecting the distance between two adjacent first metal layers due to excessive tilt angles.

[0067] Specifically, because the resistive switching device 20 is arranged at an angle, the width h1 of a single resistive switching device can be increased from 135 nm in the prior art to 150 nm, thereby increasing the size of the resistive switching device and reducing the voltage.

[0068] At the same time, the inclined arrangement of the resistive switching device also increases the width h2 of the resistive switching device in the second direction, thereby increasing the size of the first metal layer. The width h3 of the first metal layer in the second direction is increased from 144nm in the prior art to 170nm.

[0069] As shown in Fig. 1 , a first protective layer 61 is formed between the lower electrodes 21 and the resistive layer 22 of every two adjacent resistive devices 20. The material of the first protective layer 61 includes insulating materials such as silicon oxide, silicon nitride or silicon oxynitride.

[0070] In the prior art, the height of a resistive switching device is 1200 Å, so the distance between adjacent resistive switching devices cannot be too small. Otherwise, due to the large aspect ratio, voids will be left when filling the holes. However, in the disclosed embodiment, because the oxide-grabbing layer and the top electrode of each two adjacent resistive switching devices are interconnected, a first protective layer can be formed between the two adjacent resistive switching devices. The first protective layer has a small aspect ratio, so the distance between the two adjacent resistive switching devices can be reduced, thereby facilitating the increase in the area of ​​the resistive switching device. The increase in the area of ​​the entire resistive switching device is conducive to reducing voltage. In addition, the resistive switching device is tilted at a predetermined angle, which further increases the size of the resistive switching device, thereby further achieving the effect of reducing voltage.

[0071] Each pair of adjacent resistive switching devices 20 connected to the upper electrode 24 and the gripping oxide layer 23 constitutes a group of resistive switching devices. A second protective layer 62 and a third protective layer 63 surrounded by the second protective layer 62 are formed between the two adjacent groups of resistive switching devices. The material of the second protective layer 62 includes, but is not limited to, aluminum oxide, and the third protective layer 63 includes an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0072] In one embodiment, the semiconductor structure further includes: a contact layer 70 located on the resistive device 20 and a first metal layer 31 located on the contact layer 70 .

[0073] The material of the contact layer 70 includes but is not limited to titanium nitride. The material of the first metal layer 31 includes but is not limited to copper.

[0074] FIG3 is a schematic diagram of a semiconductor structure according to another embodiment of the present disclosure. As shown in FIG3 , the semiconductor structure further includes a first contact plug 41 located on the resistive switching device 20 , the first contact plug 41 connecting the resistive switching device 20 and the first metal layer 31 .

[0075] In this embodiment, the size of the first metal layer can be further increased by providing the first contact plug.

[0076] Specifically, a second dielectric layer 52 is formed on the resistive device 20 , and the first contact plug 41 is located in the second dielectric layer 52 .

[0077] The first contact plug 41 may have a double-layer structure, and the material of the first contact plug 41 may include titanium nitride in an outer layer and metal tungsten in an inner layer.

[0078] The material of the second dielectric layer 52 may include, for example, insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0079] The present disclosure also provides a method for preparing a semiconductor structure. For details, please refer to FIG. 4 . As shown in FIG. 4 , the method for preparing a semiconductor structure includes the following steps:

[0080] Step 401: providing a substrate;

[0081] Step 402: forming a plurality of resistive switching devices arranged in an array along a first direction and a second direction on the substrate, wherein the first direction and the second direction are parallel to the plane of the substrate and intersect with each other; wherein the resistive switching devices form a predetermined angle with the first direction;

[0082] Step 403: forming a plurality of first metal layers extending along the first direction on the resistive switching device.

[0083] The following is a further detailed description of the method for preparing the semiconductor structure provided by the embodiment of the present disclosure in conjunction with specific embodiments. Figures 5a to 5i are schematic diagrams of the semiconductor structure provided by the embodiment of the present disclosure during the preparation process.

[0084] First, referring to FIG. 5 a , step 401 is performed to provide a substrate 10 .

[0085] In one embodiment, the semiconductor structure further includes: a first dielectric layer 51 located on the substrate 10 . The material of the first dielectric layer 51 may include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0086] Next, referring to FIG5 a , the method further includes: forming a second metal layer 32 on the substrate 10 before forming the resistive switching device;

[0087] A second contact plug 42 is formed on the second metal layer 32 , wherein the second contact plug 42 connects the second metal layer 32 and the resistive switching device.

[0088] The material of the second metal layer 32 includes but is not limited to copper. The second contact plug 42 may have a double-layer structure, and the material of the second contact plug 42 may include titanium nitride in the outer layer and tungsten in the inner layer.

[0089] Next, a first dielectric layer 51 is formed to wrap the second metal layer 32 and the second contact plug 42. The material of the first dielectric layer 51 may include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0090] Next, referring to Figures 5b to 5g, step 402 is performed to form a plurality of resistive switching devices 20 arranged in an array along a first direction and a second direction on the substrate 10, wherein the first direction and the second direction are directions parallel to the plane of the substrate 10, and the first direction and the second direction intersect; wherein the resistive switching device 20 is at a preset angle to the first direction.

[0091] In one embodiment, the forming of the resistive switching device 20 includes: forming a lower electrode 21, a resistive switching layer 22, an oxide-capping layer 23 and an upper electrode 24 stacked in sequence;

[0092] Along the first direction, among the plurality of resistive devices 20 , the oxide-capping layers 23 and the upper electrodes 24 of every two adjacent resistive devices 20 are connected respectively.

[0093] Specifically, referring to FIG. 5 b , an initial lower electrode 21 ′, an initial first resistive switching layer 221 ′, and an initial second resistive switching layer 222 ′ are sequentially formed on the first dielectric layer 51 .

[0094] In actual operation, the initial lower electrode 21 ′, the initial first resistive layer 221 ′ and the initial second resistive layer 222 ′ formed on the first dielectric layer 51 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other deposition methods.

[0095] Next, referring to FIG. 5 c , the initial lower electrode 21 ′, the initial first resistive layer 221 ′, and the initial second resistive layer 222 ′ are etched to form a first through hole 81 .

[0096] In actual operation, the first through hole 81 may be formed by a dry etching process.

[0097] Next, referring to FIG. 5 d , an initial first protection layer 61 ′ is formed in the first through hole 81 , and the initial first protection layer 61 ′ covers the surface of the initial second resistive layer 222 ′.

[0098] In actual operation, the initial first protection layer 61 ′ can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other deposition methods.

[0099] Next, referring to FIG. 5 e , the initial first protection layer 61 ′ located on the surface of the initial second resistive layer 222 ′ is removed to form the first protection layer 61 located in the first through hole 81 .

[0100] In actual operation, the initial first protection layer 61 ′ located on the surface of the initial second resistive layer 222 ′ may be removed by a chemical mechanical polishing (CMP) process.

[0101] The material of the first protection layer 61 includes insulating materials such as silicon oxide, silicon nitride or silicon oxynitride.

[0102] Next, referring to FIG. 5 f , an initial oxide-grabbing layer 23 ′, an initial upper electrode 24 ′ and a mask layer 90 are sequentially formed on the initial second resistive layer 222 ′.

[0103] In actual operation, the initial oxide layer 23 ′, the initial upper electrode 24 ′ and the mask layer 90 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other deposition methods.

[0104] 5g, the mask layer 90 is used as a mask to etch the initial upper electrode 24', the initial oxide layer 23', the initial second resistive layer 222', the initial first resistive layer 221' and the initial lower electrode 21' to form a second through hole 82 and a resistive device 20.

[0105] Each of the resistive switching devices 20 includes a lower electrode 21, a resistive switching layer 22, an oxide-grabbing layer 23 and an upper electrode 24 stacked in sequence; along the first direction, among the multiple resistive switching devices 20, the oxide-grabbing layers 23 and the upper electrodes 24 of every two adjacent resistive switching devices 20 are connected respectively.

[0106] Specifically, as shown in FIG5g , the capping oxide layers 23 of each two adjacent resistive switching devices 20 are connected to each other, and the top electrodes 24 are connected to each other. The capping oxide layers and top electrodes of each two adjacent resistive switching devices are connected separately, which helps to increase the contact area between the top electrode and the capping oxide layer, thereby achieving the effect of reducing voltage.

[0107] In the prior art, the height of a resistive switching device is 1200 Å, so the distance between adjacent resistive switching devices cannot be too small. Otherwise, due to the large aspect ratio, voids will be left when filling the holes. However, in the disclosed embodiment, because the oxide-grabbing layer and the top electrode of each two adjacent resistive switching devices are interconnected, a first protective layer can be formed between the two adjacent resistive switching devices. The first protective layer has a small aspect ratio, so the distance between the two adjacent resistive switching devices can be reduced, thereby facilitating the increase in the area of ​​the resistive switching device. The increase in the area of ​​the entire resistive switching device is conducive to reducing voltage. In addition, the resistive switching device is tilted at a predetermined angle, which further increases the size of the resistive switching device, thereby further achieving the effect of reducing voltage.

[0108] The material of the lower electrode 21 includes, but is not limited to, titanium nitride. The resistive layer 22 includes a first resistive layer 221 and a second resistive layer 222 stacked in sequence. The material of the first resistive layer 221 includes, but is not limited to, hafnium oxide, and the material of the second resistive layer 222 includes, but is not limited to, aluminum oxide. The material of the grip oxide layer 23 may include, but is not limited to, at least one of aluminum, tantalum, tantalum nitride, titanium, and titanium nitride. In this embodiment, the material of the grip oxide layer 23 is, for example, titanium. The material of the upper electrode 24 includes, but is not limited to, titanium nitride.

[0109] As shown in Figure 2, the resistive device 20 forms a preset angle a with the first direction. The preset angle a ranges from 5° to 10°. Within this range, the size of the subsequently formed first metal layer can be expanded, thereby increasing the contact area between the resistive device and the first metal layer, thereby reducing the voltage. At the same time, because the distance between two adjacent first metal layers is at least 50nm, setting the preset angle within this range can also avoid affecting the distance between two adjacent first metal layers due to excessive inclination angles.

[0110] Specifically, because the resistive switching device 20 is arranged at an angle, the width h1 of a single resistive switching device can be increased from 135 nm in the prior art to 150 nm, thereby increasing the size of the resistive switching device and reducing the voltage.

[0111] At the same time, the inclined arrangement of the resistive switching device also increases the width h2 of the resistive switching device in the second direction, thereby increasing the size of the first metal layer. The width h3 of the first metal layer in the second direction is increased from 144nm in the prior art to 170nm.

[0112] Next, referring to FIG. 5 h , a second protection layer 62 and a third protection layer 63 surrounded by the second protection layer 62 are formed in the second through hole 82 .

[0113] The material of the second protective layer 62 includes but is not limited to aluminum oxide, and the third protective layer 63 includes insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0114] Next, referring to FIG. 5 i , step 403 is performed to form a plurality of first metal layers 31 extending along the first direction on the resistive device 20 .

[0115] Specifically, a contact layer 70 is first formed on the resistive device 20 , and then a first metal layer 31 is formed on the contact layer 70 .

[0116] In actual operation, the contact layer 70 and the first metal layer 31 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other deposition methods.

[0117] The material of the contact layer 70 includes but is not limited to titanium nitride. The material of the first metal layer 31 includes but is not limited to copper.

[0118] In another embodiment, as shown in FIG. 3 , the method further includes: before forming the first metal layer 31 , forming a first contact plug 41 on the resistive device 20 , wherein the first contact plug 41 connects the resistive device 20 and the first metal layer 31 .

[0119] In this embodiment, the size of the first metal layer can be further increased by providing the first contact plug.

[0120] Specifically, the second dielectric layer 52 may be formed on the resistive device 20 first, and then the second dielectric layer 52 may be etched to form a trench, and the first contact plug 41 may be formed in the trench.

[0121] The first contact plug 41 may have a double-layer structure, and the material of the first contact plug 41 may include titanium nitride in an outer layer and metal tungsten in an inner layer.

[0122] The material of the second dielectric layer 52 may include, for example, insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0123] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. This is not limited herein.

[0124] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0125] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A semiconductor structure, wherein: include: substrate; A plurality of resistive switching devices arranged in an array along a first direction and a second direction on the substrate, wherein the first direction and the second direction are directions parallel to the plane of the substrate, and the first direction and the second direction intersect; wherein the resistive switching devices form a preset angle with the first direction; A plurality of first metal layers are located on the resistive switching device and extend along the first direction.

2. The semiconductor structure according to claim 1, wherein: The preset angle ranges from 5° to 10°.

3. The semiconductor structure according to claim 1, wherein: Each of the resistive switching devices comprises a lower electrode, a resistive switching layer, an oxide-grabbing layer and an upper electrode stacked in sequence; Along the first direction, among the plurality of resistive switching devices, the oxide-grabbing layers and the upper electrodes of every two adjacent resistive switching devices are connected respectively.

4. The semiconductor structure according to claim 1, wherein: The semiconductor structure further comprises: A first contact plug is located on the resistive device, wherein the first contact plug connects the resistive device and the first metal layer.

5. The semiconductor structure according to claim 1, wherein: The semiconductor structure further comprises: a second metal layer located on the substrate; A second contact plug is located on the second metal layer; wherein the second contact plug connects the second metal layer and the resistive switching device.

6. A method for preparing a semiconductor structure, wherein: include: providing a substrate; A plurality of resistive switching devices are formed on the substrate and arranged in an array along a first direction and a second direction, wherein the first direction and the second direction are directions parallel to the plane of the substrate, and the first direction and the second direction intersect; wherein the resistive switching devices form a preset angle with the first direction; A plurality of first metal layers extending along the first direction are formed on the resistive switching device.

7. The method according to claim 6, wherein: The preset angle ranges from 5° to 10°.

8. The method according to claim 6, wherein: The forming of the resistive switching device comprises: forming a lower electrode, a resistive switching layer, an oxygen-grabbing layer and an upper electrode stacked in sequence; Along the first direction, among the plurality of resistive switching devices, the oxide-grabbing layers and the upper electrodes of every two adjacent resistive switching devices are connected respectively.

9. The method according to claim 6, wherein: The method further comprises: Before forming the first metal layer, a first contact plug is formed on the resistive device, wherein the first contact plug connects the resistive device and the first metal layer.

10. The method according to claim 6, wherein: The method further comprises: Before forming the resistive switching device, forming a second metal layer on the substrate; A second contact plug is formed on the second metal layer; wherein the second contact plug connects the second metal layer and the resistive device.

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